Merge tag 'v5.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

+30

Documentation/devicetree/bindings/arm/mediatek.yaml

··· 131 131 - enum: 132 132 - mediatek,mt8183-evb 133 133 - const: mediatek,mt8183 134 + - description: Google Hayato 135 + items: 136 + - const: google,hayato-rev1 137 + - const: google,hayato 138 + - const: mediatek,mt8192 139 + - description: Google Spherion (Acer Chromebook 514) 140 + items: 141 + - const: google,spherion-rev3 142 + - const: google,spherion-rev2 143 + - const: google,spherion-rev1 144 + - const: google,spherion-rev0 145 + - const: google,spherion 146 + - const: mediatek,mt8192 147 + - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) 148 + items: 149 + - enum: 150 + - google,tomato-rev2 151 + - google,tomato-rev1 152 + - const: google,tomato 153 + - const: mediatek,mt8195 154 + - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) 155 + items: 156 + - const: google,tomato-rev4 157 + - const: google,tomato-rev3 158 + - const: google,tomato 159 + - const: mediatek,mt8195 160 + - items: 161 + - enum: 162 + - mediatek,mt8186-evb 163 + - const: mediatek,mt8186 134 164 - items: 135 165 - enum: 136 166 - mediatek,mt8192-evb

+1

Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml

··· 26 26 - mediatek,mt8135-pericfg 27 27 - mediatek,mt8173-pericfg 28 28 - mediatek,mt8183-pericfg 29 + - mediatek,mt8186-pericfg 29 30 - mediatek,mt8195-pericfg 30 31 - mediatek,mt8516-pericfg 31 32 - const: syscon

+5

arch/arm64/boot/dts/mediatek/Makefile

··· 37 37 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb 38 38 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb 39 39 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb 40 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb 41 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb 40 42 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb 43 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb 44 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb 45 + dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb 41 46 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb 42 47 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb 43 48 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb

+1 -1

arch/arm64/boot/dts/mediatek/mt2712-evb.dts

··· 106 106 }; 107 107 108 108 &eth { 109 - phy-mode ="rgmii-rxid"; 109 + phy-mode = "rgmii-rxid"; 110 110 phy-handle = <&ethernet_phy0>; 111 111 mediatek,tx-delay-ps = <1530>; 112 112 snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;

+2

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

··· 329 329 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 330 330 clocks = <&infracfg CLK_INFRA_M4U>; 331 331 clock-names = "bclk"; 332 + mediatek,infracfg = <&infracfg>; 332 333 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 333 334 <&larb3>, <&larb6>; 334 335 #iommu-cells = <1>; ··· 347 346 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 348 347 clocks = <&infracfg CLK_INFRA_M4U>; 349 348 clock-names = "bclk"; 349 + mediatek,infracfg = <&infracfg>; 350 350 mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; 351 351 #iommu-cells = <1>; 352 352 };

+209 -59

arch/arm64/boot/dts/mediatek/mt6795.dtsi

··· 13 13 14 14 #include <dt-bindings/interrupt-controller/irq.h> 15 15 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 + #include <dt-bindings/pinctrl/mt6795-pinfunc.h> 16 17 17 18 / { 18 19 compatible = "mediatek,mt6795"; ··· 35 34 compatible = "arm,cortex-a53"; 36 35 enable-method = "psci"; 37 36 reg = <0x000>; 37 + cci-control-port = <&cci_control2>; 38 + next-level-cache = <&l2_0>; 38 39 }; 39 40 40 41 cpu1: cpu@1 { ··· 44 41 compatible = "arm,cortex-a53"; 45 42 enable-method = "psci"; 46 43 reg = <0x001>; 44 + cci-control-port = <&cci_control2>; 45 + next-level-cache = <&l2_0>; 47 46 }; 48 47 49 48 cpu2: cpu@2 { ··· 53 48 compatible = "arm,cortex-a53"; 54 49 enable-method = "psci"; 55 50 reg = <0x002>; 51 + cci-control-port = <&cci_control2>; 52 + next-level-cache = <&l2_0>; 56 53 }; 57 54 58 55 cpu3: cpu@3 { ··· 62 55 compatible = "arm,cortex-a53"; 63 56 enable-method = "psci"; 64 57 reg = <0x003>; 58 + cci-control-port = <&cci_control2>; 59 + next-level-cache = <&l2_0>; 65 60 }; 66 61 67 62 cpu4: cpu@100 { ··· 71 62 compatible = "arm,cortex-a53"; 72 63 enable-method = "psci"; 73 64 reg = <0x100>; 65 + cci-control-port = <&cci_control1>; 66 + next-level-cache = <&l2_1>; 74 67 }; 75 68 76 69 cpu5: cpu@101 { ··· 80 69 compatible = "arm,cortex-a53"; 81 70 enable-method = "psci"; 82 71 reg = <0x101>; 72 + cci-control-port = <&cci_control1>; 73 + next-level-cache = <&l2_1>; 83 74 }; 84 75 85 76 cpu6: cpu@102 { ··· 89 76 compatible = "arm,cortex-a53"; 90 77 enable-method = "psci"; 91 78 reg = <0x102>; 79 + cci-control-port = <&cci_control1>; 80 + next-level-cache = <&l2_1>; 92 81 }; 93 82 94 83 cpu7: cpu@103 { ··· 98 83 compatible = "arm,cortex-a53"; 99 84 enable-method = "psci"; 100 85 reg = <0x103>; 86 + cci-control-port = <&cci_control1>; 87 + next-level-cache = <&l2_1>; 101 88 }; 89 + 90 + cpu-map { 91 + cluster0 { 92 + core0 { 93 + cpu = <&cpu0>; 94 + }; 95 + 96 + core1 { 97 + cpu = <&cpu1>; 98 + }; 99 + 100 + core2 { 101 + cpu = <&cpu2>; 102 + }; 103 + 104 + core3 { 105 + cpu = <&cpu3>; 106 + }; 107 + }; 108 + 109 + cluster1 { 110 + core0 { 111 + cpu = <&cpu4>; 112 + }; 113 + 114 + core1 { 115 + cpu = <&cpu5>; 116 + }; 117 + 118 + core2 { 119 + cpu = <&cpu6>; 120 + }; 121 + 122 + core3 { 123 + cpu = <&cpu7>; 124 + }; 125 + }; 126 + }; 127 + 128 + l2_0: l2-cache0 { 129 + compatible = "cache"; 130 + cache-level = <2>; 131 + }; 132 + 133 + l2_1: l2-cache1 { 134 + compatible = "cache"; 135 + cache-level = <2>; 136 + }; 137 + }; 138 + 139 + clk26m: oscillator-26m { 140 + compatible = "fixed-clock"; 141 + #clock-cells = <0>; 142 + clock-frequency = <26000000>; 143 + clock-output-names = "clk26m"; 144 + }; 145 + 146 + clk32k: oscillator-32k { 147 + compatible = "fixed-clock"; 148 + #clock-cells = <0>; 149 + clock-frequency = <32000>; 150 + clock-output-names = "clk32k"; 102 151 }; 103 152 104 153 system_clk: dummy13m { ··· 171 92 #clock-cells = <0>; 172 93 }; 173 94 174 - rtc_clk: dummy32k { 175 - compatible = "fixed-clock"; 176 - clock-frequency = <32000>; 177 - #clock-cells = <0>; 178 - }; 179 - 180 - uart_clk: dummy26m { 181 - compatible = "fixed-clock"; 182 - clock-frequency = <26000000>; 183 - #clock-cells = <0>; 95 + pmu { 96 + compatible = "arm,cortex-a53-pmu"; 97 + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 98 + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 99 + <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 100 + <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 101 + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 184 102 }; 185 103 186 104 timer { ··· 193 117 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 194 118 }; 195 119 196 - sysirq: intpol-controller@10200620 { 197 - compatible = "mediatek,mt6795-sysirq", 198 - "mediatek,mt6577-sysirq"; 199 - interrupt-controller; 200 - #interrupt-cells = <3>; 201 - interrupt-parent = <&gic>; 202 - reg = <0 0x10200620 0 0x20>; 203 - }; 120 + soc { 121 + #address-cells = <2>; 122 + #size-cells = <2>; 123 + compatible = "simple-bus"; 124 + ranges; 204 125 205 - gic: interrupt-controller@10221000 { 206 - compatible = "arm,gic-400"; 207 - #interrupt-cells = <3>; 208 - interrupt-parent = <&gic>; 209 - interrupt-controller; 210 - reg = <0 0x10221000 0 0x1000>, 211 - <0 0x10222000 0 0x2000>, 212 - <0 0x10224000 0 0x2000>, 213 - <0 0x10226000 0 0x2000>; 214 - }; 126 + pio: pinctrl@10005000 { 127 + compatible = "mediatek,mt6795-pinctrl"; 128 + reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 129 + reg-names = "base", "eint"; 130 + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 131 + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 132 + gpio-controller; 133 + #gpio-cells = <2>; 134 + gpio-ranges = <&pio 0 0 196>; 135 + interrupt-controller; 136 + #interrupt-cells = <2>; 137 + }; 215 138 216 - uart0: serial@11002000 { 217 - compatible = "mediatek,mt6795-uart", 218 - "mediatek,mt6577-uart"; 219 - reg = <0 0x11002000 0 0x400>; 220 - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 221 - clocks = <&uart_clk>; 222 - status = "disabled"; 223 - }; 139 + watchdog: watchdog@10007000 { 140 + compatible = "mediatek,mt6795-wdt"; 141 + reg = <0 0x10007000 0 0x100>; 142 + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 143 + #reset-cells = <1>; 144 + timeout-sec = <20>; 145 + }; 224 146 225 - uart1: serial@11003000 { 226 - compatible = "mediatek,mt6795-uart", 227 - "mediatek,mt6577-uart"; 228 - reg = <0 0x11003000 0 0x400>; 229 - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 230 - clocks = <&uart_clk>; 231 - status = "disabled"; 232 - }; 147 + timer: timer@10008000 { 148 + compatible = "mediatek,mt6795-timer", 149 + "mediatek,mt6577-timer"; 150 + reg = <0 0x10008000 0 0x1000>; 151 + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 152 + clocks = <&system_clk>, <&clk32k>; 153 + }; 233 154 234 - uart2: serial@11004000 { 235 - compatible = "mediatek,mt6795-uart", 236 - "mediatek,mt6577-uart"; 237 - reg = <0 0x11004000 0 0x400>; 238 - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 239 - clocks = <&uart_clk>; 240 - status = "disabled"; 241 - }; 155 + sysirq: intpol-controller@10200620 { 156 + compatible = "mediatek,mt6795-sysirq", 157 + "mediatek,mt6577-sysirq"; 158 + interrupt-controller; 159 + #interrupt-cells = <3>; 160 + interrupt-parent = <&gic>; 161 + reg = <0 0x10200620 0 0x20>; 162 + }; 242 163 243 - uart3: serial@11005000 { 244 - compatible = "mediatek,mt6795-uart", 245 - "mediatek,mt6577-uart"; 246 - reg = <0 0x11005000 0 0x400>; 247 - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 248 - clocks = <&uart_clk>; 249 - status = "disabled"; 164 + gic: interrupt-controller@10221000 { 165 + compatible = "arm,gic-400"; 166 + #interrupt-cells = <3>; 167 + interrupt-parent = <&gic>; 168 + interrupt-controller; 169 + reg = <0 0x10221000 0 0x1000>, 170 + <0 0x10222000 0 0x2000>, 171 + <0 0x10224000 0 0x2000>, 172 + <0 0x10226000 0 0x2000>; 173 + interrupts = <GIC_PPI 9 174 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 175 + }; 176 + 177 + cci: cci@10390000 { 178 + compatible = "arm,cci-400"; 179 + #address-cells = <1>; 180 + #size-cells = <1>; 181 + reg = <0 0x10390000 0 0x1000>; 182 + ranges = <0 0 0x10390000 0x10000>; 183 + 184 + cci_control0: slave-if@1000 { 185 + compatible = "arm,cci-400-ctrl-if"; 186 + interface-type = "ace-lite"; 187 + reg = <0x1000 0x1000>; 188 + }; 189 + 190 + cci_control1: slave-if@4000 { 191 + compatible = "arm,cci-400-ctrl-if"; 192 + interface-type = "ace"; 193 + reg = <0x4000 0x1000>; 194 + }; 195 + 196 + cci_control2: slave-if@5000 { 197 + compatible = "arm,cci-400-ctrl-if"; 198 + interface-type = "ace"; 199 + reg = <0x5000 0x1000>; 200 + }; 201 + 202 + pmu@9000 { 203 + compatible = "arm,cci-400-pmu,r1"; 204 + reg = <0x9000 0x5000>; 205 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 206 + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 207 + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 208 + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 209 + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 210 + }; 211 + }; 212 + 213 + uart0: serial@11002000 { 214 + compatible = "mediatek,mt6795-uart", 215 + "mediatek,mt6577-uart"; 216 + reg = <0 0x11002000 0 0x400>; 217 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 218 + clocks = <&clk26m>; 219 + status = "disabled"; 220 + }; 221 + 222 + uart1: serial@11003000 { 223 + compatible = "mediatek,mt6795-uart", 224 + "mediatek,mt6577-uart"; 225 + reg = <0 0x11003000 0 0x400>; 226 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 227 + clocks = <&clk26m>; 228 + status = "disabled"; 229 + }; 230 + 231 + uart2: serial@11004000 { 232 + compatible = "mediatek,mt6795-uart", 233 + "mediatek,mt6577-uart"; 234 + reg = <0 0x11004000 0 0x400>; 235 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 236 + clocks = <&clk26m>; 237 + status = "disabled"; 238 + }; 239 + 240 + uart3: serial@11005000 { 241 + compatible = "mediatek,mt6795-uart", 242 + "mediatek,mt6577-uart"; 243 + reg = <0 0x11005000 0 0x400>; 244 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 245 + clocks = <&clk26m>; 246 + status = "disabled"; 247 + }; 250 248 }; 251 249 };

+12 -9

arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

··· 8 8 /dts-v1/; 9 9 #include <dt-bindings/input/input.h> 10 10 #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/leds/common.h> 11 12 12 13 #include "mt7622.dtsi" 13 14 #include "mt6380.dtsi" ··· 41 40 gpio-keys { 42 41 compatible = "gpio-keys"; 43 42 44 - factory { 43 + factory-key { 45 44 label = "factory"; 46 45 linux,code = <BTN_0>; 47 46 gpios = <&pio 0 GPIO_ACTIVE_HIGH>; 48 47 }; 49 48 50 - wps { 49 + wps-key { 51 50 label = "wps"; 52 51 linux,code = <KEY_WPS_BUTTON>; 53 - gpios = <&pio 102 GPIO_ACTIVE_HIGH>; 52 + gpios = <&pio 102 GPIO_ACTIVE_LOW>; 54 53 }; 55 54 }; 56 55 57 56 leds { 58 57 compatible = "gpio-leds"; 59 58 60 - green { 59 + led-0 { 61 60 label = "bpi-r64:pio:green"; 61 + color = <LED_COLOR_ID_GREEN>; 62 62 gpios = <&pio 89 GPIO_ACTIVE_HIGH>; 63 63 default-state = "off"; 64 64 }; 65 65 66 - red { 66 + led-1 { 67 67 label = "bpi-r64:pio:red"; 68 + color = <LED_COLOR_ID_RED>; 68 69 gpios = <&pio 88 GPIO_ACTIVE_HIGH>; 69 70 default-state = "off"; 70 71 }; ··· 339 336 i2c1_pins: i2c1-pins { 340 337 mux { 341 338 function = "i2c"; 342 - groups = "i2c1_0"; 339 + groups = "i2c1_0"; 343 340 }; 344 341 }; 345 342 346 343 i2c2_pins: i2c2-pins { 347 344 mux { 348 345 function = "i2c"; 349 - groups = "i2c2_0"; 346 + groups = "i2c2_0"; 350 347 }; 351 348 }; 352 349 ··· 369 366 irrx_pins: irrx-pins { 370 367 mux { 371 368 function = "ir"; 372 - groups = "ir_1_rx"; 369 + groups = "ir_1_rx"; 373 370 }; 374 371 }; 375 372 376 373 irtx_pins: irtx-pins { 377 374 mux { 378 375 function = "ir"; 379 - groups = "ir_1_tx"; 376 + groups = "ir_1_tx"; 380 377 }; 381 378 }; 382 379

+6 -7

arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

··· 40 40 41 41 gpio-keys { 42 42 compatible = "gpio-keys"; 43 - poll-interval = <100>; 44 43 45 - factory { 44 + key-factory { 46 45 label = "factory"; 47 46 linux,code = <BTN_0>; 48 47 gpios = <&pio 0 0>; 49 48 }; 50 49 51 - wps { 50 + key-wps { 52 51 label = "wps"; 53 52 linux,code = <KEY_WPS_BUTTON>; 54 53 gpios = <&pio 102 0>; ··· 297 298 i2c1_pins: i2c1-pins { 298 299 mux { 299 300 function = "i2c"; 300 - groups = "i2c1_0"; 301 + groups = "i2c1_0"; 301 302 }; 302 303 }; 303 304 304 305 i2c2_pins: i2c2-pins { 305 306 mux { 306 307 function = "i2c"; 307 - groups = "i2c2_0"; 308 + groups = "i2c2_0"; 308 309 }; 309 310 }; 310 311 ··· 327 328 irrx_pins: irrx-pins { 328 329 mux { 329 330 function = "ir"; 330 - groups = "ir_1_rx"; 331 + groups = "ir_1_rx"; 331 332 }; 332 333 }; 333 334 334 335 irtx_pins: irtx-pins { 335 336 mux { 336 337 function = "ir"; 337 - groups = "ir_1_tx"; 338 + groups = "ir_1_tx"; 338 339 }; 339 340 }; 340 341

+5 -5

arch/arm64/boot/dts/mediatek/mt7622.dtsi

··· 118 118 }; 119 119 120 120 psci { 121 - compatible = "arm,psci-0.2"; 122 - method = "smc"; 121 + compatible = "arm,psci-0.2"; 122 + method = "smc"; 123 123 }; 124 124 125 125 pmu { ··· 616 616 617 617 afe: audio-controller { 618 618 compatible = "mediatek,mt7622-audio"; 619 - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, 620 - <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 621 - interrupt-names = "afe", "asys"; 619 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, 620 + <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 621 + interrupt-names = "afe", "asys"; 622 622 623 623 clocks = <&infracfg CLK_INFRA_AUDIO_PD>, 624 624 <&topckgen CLK_TOP_AUD1_SEL>,

+2 -2

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

··· 57 57 }; 58 58 59 59 psci { 60 - compatible = "arm,psci-0.2"; 61 - method = "smc"; 60 + compatible = "arm,psci-0.2"; 61 + method = "smc"; 62 62 }; 63 63 64 64 reserved-memory {

+3 -3

arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts

··· 21 21 }; 22 22 23 23 &gpio_keys { 24 - /delete-node/tablet_mode; 25 - /delete-node/volume_down; 26 - /delete-node/volume_up; 24 + /delete-node/switch-tablet-mode; 25 + /delete-node/switch-volume-down; 26 + /delete-node/switch-volume-up; 27 27 };

+12 -12

arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi

··· 53 53 pinctrl-names = "default"; 54 54 pinctrl-0 = <&gpio_keys_pins>; 55 55 56 - lid { 56 + switch-lid { 57 57 label = "Lid"; 58 58 gpios = <&pio 69 GPIO_ACTIVE_LOW>; 59 59 linux,code = <SW_LID>; ··· 61 61 gpio-key,wakeup; 62 62 }; 63 63 64 - power { 64 + switch-power { 65 65 label = "Power"; 66 66 gpios = <&pio 14 GPIO_ACTIVE_HIGH>; 67 67 linux,code = <KEY_POWER>; ··· 69 69 gpio-key,wakeup; 70 70 }; 71 71 72 - tablet_mode { 72 + switch-tablet-mode { 73 73 label = "Tablet_mode"; 74 74 gpios = <&pio 121 GPIO_ACTIVE_HIGH>; 75 75 linux,code = <SW_TABLET_MODE>; ··· 77 77 gpio-key,wakeup; 78 78 }; 79 79 80 - volume_down { 80 + switch-volume-down { 81 81 label = "Volume_down"; 82 82 gpios = <&pio 123 GPIO_ACTIVE_LOW>; 83 83 linux,code = <KEY_VOLUMEDOWN>; 84 84 }; 85 85 86 - volume_up { 86 + switch-volume-up { 87 87 label = "Volume_up"; 88 88 gpios = <&pio 124 GPIO_ACTIVE_LOW>; 89 89 linux,code = <KEY_VOLUMEUP>; ··· 300 300 regulator-name = "VBUCKA"; 301 301 regulator-min-microvolt = < 700000>; 302 302 regulator-max-microvolt = <1310000>; 303 - regulator-min-microamp = <2000000>; 304 - regulator-max-microamp = <4400000>; 303 + regulator-min-microamp = <2000000>; 304 + regulator-max-microamp = <4400000>; 305 305 regulator-ramp-delay = <10000>; 306 306 regulator-always-on; 307 307 regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC ··· 312 312 regulator-name = "VBUCKB"; 313 313 regulator-min-microvolt = < 700000>; 314 314 regulator-max-microvolt = <1310000>; 315 - regulator-min-microamp = <2000000>; 316 - regulator-max-microamp = <3000000>; 315 + regulator-min-microamp = <2000000>; 316 + regulator-max-microamp = <3000000>; 317 317 regulator-ramp-delay = <10000>; 318 318 }; 319 319 }; ··· 374 374 mmc-hs400-1_8v; 375 375 cap-mmc-hw-reset; 376 376 hs400-ds-delay = <0x14015>; 377 - mediatek,hs200-cmd-int-delay=<30>; 378 - mediatek,hs400-cmd-int-delay=<14>; 377 + mediatek,hs200-cmd-int-delay = <30>; 378 + mediatek,hs400-cmd-int-delay = <14>; 379 379 mediatek,hs400-cmd-resp-sel-rising; 380 380 vmmc-supply = <&mt6397_vemc_3v3_reg>; 381 381 vqmmc-supply = <&mt6397_vio18_reg>; ··· 410 410 sd-uhs-sdr50; 411 411 sd-uhs-sdr104; 412 412 keep-power-in-suspend; 413 - enable-sdio-wakeup; 413 + wakeup-source; 414 414 cap-sdio-irq; 415 415 vmmc-supply = <&sdio_fixed_3v3>; 416 416 vqmmc-supply = <&mt6397_vgp3_reg>;

+6 -6

arch/arm64/boot/dts/mediatek/mt8173-evb.dts

··· 122 122 regulator-name = "VBUCKA"; 123 123 regulator-min-microvolt = < 700000>; 124 124 regulator-max-microvolt = <1310000>; 125 - regulator-min-microamp = <2000000>; 126 - regulator-max-microamp = <4400000>; 125 + regulator-min-microamp = <2000000>; 126 + regulator-max-microamp = <4400000>; 127 127 regulator-ramp-delay = <10000>; 128 128 regulator-always-on; 129 129 }; ··· 132 132 regulator-name = "VBUCKB"; 133 133 regulator-min-microvolt = < 700000>; 134 134 regulator-max-microvolt = <1310000>; 135 - regulator-min-microamp = <2000000>; 136 - regulator-max-microamp = <3000000>; 135 + regulator-min-microamp = <2000000>; 136 + regulator-max-microamp = <3000000>; 137 137 regulator-ramp-delay = <10000>; 138 138 }; 139 139 }; ··· 148 148 bus-width = <8>; 149 149 max-frequency = <50000000>; 150 150 cap-mmc-highspeed; 151 - mediatek,hs200-cmd-int-delay=<26>; 152 - mediatek,hs400-cmd-int-delay=<14>; 151 + mediatek,hs200-cmd-int-delay = <26>; 152 + mediatek,hs400-cmd-int-delay = <14>; 153 153 mediatek,hs400-cmd-resp-sel-rising; 154 154 vmmc-supply = <&mt6397_vemc_3v3_reg>; 155 155 vqmmc-supply = <&mt6397_vio18_reg>;

+10 -6

arch/arm64/boot/dts/mediatek/mt8173.dtsi

··· 246 246 psci { 247 247 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 248 248 method = "smc"; 249 - cpu_suspend = <0x84000001>; 250 - cpu_off = <0x84000002>; 251 - cpu_on = <0x84000003>; 249 + cpu_suspend = <0x84000001>; 250 + cpu_off = <0x84000002>; 251 + cpu_on = <0x84000003>; 252 252 }; 253 253 254 254 clk26m: oscillator0 { ··· 588 588 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 589 589 clocks = <&infracfg CLK_INFRA_M4U>; 590 590 clock-names = "bclk"; 591 + mediatek,infracfg = <&infracfg>; 591 592 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 592 593 <&larb3>, <&larb4>, <&larb5>; 593 594 #iommu-cells = <1>; ··· 791 790 nor_flash: spi@1100d000 { 792 791 compatible = "mediatek,mt8173-nor"; 793 792 reg = <0 0x1100d000 0 0xe0>; 793 + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; 794 + assigned-clock-parents = <&clk26m>; 794 795 clocks = <&pericfg CLK_PERI_SPI>, 795 - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 796 - clock-names = "spi", "sf"; 796 + <&topckgen CLK_TOP_SPINFI_IFR_SEL>, 797 + <&pericfg CLK_PERI_NFI>; 798 + clock-names = "spi", "sf", "axi"; 797 799 #address-cells = <1>; 798 800 #size-cells = <0>; 799 801 status = "disabled"; ··· 1509 1505 1510 1506 vcodec_enc_vp8: vcodec@19002000 { 1511 1507 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1512 - reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1508 + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1513 1509 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1514 1510 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1515 1511 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,

+37 -1

arch/arm64/boot/dts/mediatek/mt8183-evb.dts

··· 134 134 vmmc-supply = <&mt6358_vmch_reg>; 135 135 vqmmc-supply = <&mt6358_vmc_reg>; 136 136 keep-power-in-suspend; 137 - enable-sdio-wakeup; 137 + wakeup-source; 138 138 non-removable; 139 139 }; 140 140 ··· 410 410 mediatek,pad-select = <0>; 411 411 status = "okay"; 412 412 413 + }; 414 + 415 + &cci { 416 + proc-supply = <&mt6358_vproc12_reg>; 417 + }; 418 + 419 + &cpu0 { 420 + proc-supply = <&mt6358_vproc12_reg>; 421 + }; 422 + 423 + &cpu1 { 424 + proc-supply = <&mt6358_vproc12_reg>; 425 + }; 426 + 427 + &cpu2 { 428 + proc-supply = <&mt6358_vproc12_reg>; 429 + }; 430 + 431 + &cpu3 { 432 + proc-supply = <&mt6358_vproc12_reg>; 433 + }; 434 + 435 + &cpu4 { 436 + proc-supply = <&mt6358_vproc11_reg>; 437 + }; 438 + 439 + &cpu5 { 440 + proc-supply = <&mt6358_vproc11_reg>; 441 + }; 442 + 443 + &cpu6 { 444 + proc-supply = <&mt6358_vproc11_reg>; 445 + }; 446 + 447 + &cpu7 { 448 + proc-supply = <&mt6358_vproc11_reg>; 413 449 }; 414 450 415 451 &uart0 {

+2 -2

arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi

··· 73 73 pinctrl-names = "default"; 74 74 pinctrl-0 = <&volume_button_pins>; 75 75 76 - volume_down { 76 + button-volume-down { 77 77 label = "Volume Down"; 78 78 linux,code = <KEY_VOLUMEDOWN>; 79 79 debounce-interval = <100>; ··· 81 81 gpios = <&pio 6 GPIO_ACTIVE_LOW>; 82 82 }; 83 83 84 - volume_up { 84 + button-volume-up { 85 85 label = "Volume Up"; 86 86 linux,code = <KEY_VOLUMEUP>; 87 87 debounce-interval = <100>;

+1 -1

arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi

··· 45 45 pinctrl-names = "default"; 46 46 pinctrl-0 = <&pen_eject>; 47 47 48 - pen-insert { 48 + switch-pen-insert { 49 49 label = "Pen Insert"; 50 50 /* Insert = low, eject = high */ 51 51 gpios = <&pio 6 GPIO_ACTIVE_LOW>;

+11 -2

arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi

··· 144 144 pinctrl-names = "default"; 145 145 pinctrl-0 = <&wifi_pins_wakeup>; 146 146 147 - wowlan { 147 + button-wowlan { 148 148 label = "Wake on WiFi"; 149 149 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 150 150 linux,code = <KEY_WAKEUP>; ··· 230 230 status = "okay"; 231 231 }; 232 232 233 + &cci { 234 + proc-supply = <&mt6358_vproc12_reg>; 235 + }; 236 + 233 237 &cpu0 { 234 238 proc-supply = <&mt6358_vproc12_reg>; 235 239 }; ··· 280 276 avee-supply = <&ppvarp_lcd>; 281 277 pp1800-supply = <&pp1800_lcd>; 282 278 backlight = <&backlight_lcd0>; 279 + rotation = <270>; 283 280 port { 284 281 panel_in: endpoint { 285 282 remote-endpoint = <&dsi_out>; ··· 383 378 sd-uhs-sdr50; 384 379 sd-uhs-sdr104; 385 380 keep-power-in-suspend; 386 - enable-sdio-wakeup; 381 + wakeup-source; 387 382 cap-sdio-irq; 388 383 non-removable; 389 384 no-mmc; ··· 820 815 compatible = "google,cros-ec-rpmsg"; 821 816 mediatek,rpmsg-name = "cros-ec-rpmsg"; 822 817 }; 818 + }; 819 + 820 + &mfg_async { 821 + domain-supply = <&mt6358_vsram_gpu_reg>; 823 822 }; 824 823 825 824 &mfg {

+1 -1

arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts

··· 159 159 vmmc-supply = <&mt6358_vmch_reg>; 160 160 vqmmc-supply = <&mt6358_vmc_reg>; 161 161 keep-power-in-suspend; 162 - enable-sdio-wakeup; 162 + wakeup-source; 163 163 non-removable; 164 164 }; 165 165

+309 -6

arch/arm64/boot/dts/mediatek/mt8183.dtsi

··· 42 42 rdma1 = &rdma1; 43 43 }; 44 44 45 + cluster0_opp: opp-table-cluster0 { 46 + compatible = "operating-points-v2"; 47 + opp-shared; 48 + opp0-793000000 { 49 + opp-hz = /bits/ 64 <793000000>; 50 + opp-microvolt = <650000>; 51 + required-opps = <&opp2_00>; 52 + }; 53 + opp0-910000000 { 54 + opp-hz = /bits/ 64 <910000000>; 55 + opp-microvolt = <687500>; 56 + required-opps = <&opp2_01>; 57 + }; 58 + opp0-1014000000 { 59 + opp-hz = /bits/ 64 <1014000000>; 60 + opp-microvolt = <718750>; 61 + required-opps = <&opp2_02>; 62 + }; 63 + opp0-1131000000 { 64 + opp-hz = /bits/ 64 <1131000000>; 65 + opp-microvolt = <756250>; 66 + required-opps = <&opp2_03>; 67 + }; 68 + opp0-1248000000 { 69 + opp-hz = /bits/ 64 <1248000000>; 70 + opp-microvolt = <800000>; 71 + required-opps = <&opp2_04>; 72 + }; 73 + opp0-1326000000 { 74 + opp-hz = /bits/ 64 <1326000000>; 75 + opp-microvolt = <818750>; 76 + required-opps = <&opp2_05>; 77 + }; 78 + opp0-1417000000 { 79 + opp-hz = /bits/ 64 <1417000000>; 80 + opp-microvolt = <850000>; 81 + required-opps = <&opp2_06>; 82 + }; 83 + opp0-1508000000 { 84 + opp-hz = /bits/ 64 <1508000000>; 85 + opp-microvolt = <868750>; 86 + required-opps = <&opp2_07>; 87 + }; 88 + opp0-1586000000 { 89 + opp-hz = /bits/ 64 <1586000000>; 90 + opp-microvolt = <893750>; 91 + required-opps = <&opp2_08>; 92 + }; 93 + opp0-1625000000 { 94 + opp-hz = /bits/ 64 <1625000000>; 95 + opp-microvolt = <906250>; 96 + required-opps = <&opp2_09>; 97 + }; 98 + opp0-1677000000 { 99 + opp-hz = /bits/ 64 <1677000000>; 100 + opp-microvolt = <931250>; 101 + required-opps = <&opp2_10>; 102 + }; 103 + opp0-1716000000 { 104 + opp-hz = /bits/ 64 <1716000000>; 105 + opp-microvolt = <943750>; 106 + required-opps = <&opp2_11>; 107 + }; 108 + opp0-1781000000 { 109 + opp-hz = /bits/ 64 <1781000000>; 110 + opp-microvolt = <975000>; 111 + required-opps = <&opp2_12>; 112 + }; 113 + opp0-1846000000 { 114 + opp-hz = /bits/ 64 <1846000000>; 115 + opp-microvolt = <1000000>; 116 + required-opps = <&opp2_13>; 117 + }; 118 + opp0-1924000000 { 119 + opp-hz = /bits/ 64 <1924000000>; 120 + opp-microvolt = <1025000>; 121 + required-opps = <&opp2_14>; 122 + }; 123 + opp0-1989000000 { 124 + opp-hz = /bits/ 64 <1989000000>; 125 + opp-microvolt = <1050000>; 126 + required-opps = <&opp2_15>; 127 + }; }; 128 + 129 + cluster1_opp: opp-table-cluster1 { 130 + compatible = "operating-points-v2"; 131 + opp-shared; 132 + opp1-793000000 { 133 + opp-hz = /bits/ 64 <793000000>; 134 + opp-microvolt = <700000>; 135 + required-opps = <&opp2_00>; 136 + }; 137 + opp1-910000000 { 138 + opp-hz = /bits/ 64 <910000000>; 139 + opp-microvolt = <725000>; 140 + required-opps = <&opp2_01>; 141 + }; 142 + opp1-1014000000 { 143 + opp-hz = /bits/ 64 <1014000000>; 144 + opp-microvolt = <750000>; 145 + required-opps = <&opp2_02>; 146 + }; 147 + opp1-1131000000 { 148 + opp-hz = /bits/ 64 <1131000000>; 149 + opp-microvolt = <775000>; 150 + required-opps = <&opp2_03>; 151 + }; 152 + opp1-1248000000 { 153 + opp-hz = /bits/ 64 <1248000000>; 154 + opp-microvolt = <800000>; 155 + required-opps = <&opp2_04>; 156 + }; 157 + opp1-1326000000 { 158 + opp-hz = /bits/ 64 <1326000000>; 159 + opp-microvolt = <825000>; 160 + required-opps = <&opp2_05>; 161 + }; 162 + opp1-1417000000 { 163 + opp-hz = /bits/ 64 <1417000000>; 164 + opp-microvolt = <850000>; 165 + required-opps = <&opp2_06>; 166 + }; 167 + opp1-1508000000 { 168 + opp-hz = /bits/ 64 <1508000000>; 169 + opp-microvolt = <875000>; 170 + required-opps = <&opp2_07>; 171 + }; 172 + opp1-1586000000 { 173 + opp-hz = /bits/ 64 <1586000000>; 174 + opp-microvolt = <900000>; 175 + required-opps = <&opp2_08>; 176 + }; 177 + opp1-1625000000 { 178 + opp-hz = /bits/ 64 <1625000000>; 179 + opp-microvolt = <912500>; 180 + required-opps = <&opp2_09>; 181 + }; 182 + opp1-1677000000 { 183 + opp-hz = /bits/ 64 <1677000000>; 184 + opp-microvolt = <931250>; 185 + required-opps = <&opp2_10>; 186 + }; 187 + opp1-1716000000 { 188 + opp-hz = /bits/ 64 <1716000000>; 189 + opp-microvolt = <950000>; 190 + required-opps = <&opp2_11>; 191 + }; 192 + opp1-1781000000 { 193 + opp-hz = /bits/ 64 <1781000000>; 194 + opp-microvolt = <975000>; 195 + required-opps = <&opp2_12>; 196 + }; 197 + opp1-1846000000 { 198 + opp-hz = /bits/ 64 <1846000000>; 199 + opp-microvolt = <1000000>; 200 + required-opps = <&opp2_13>; 201 + }; 202 + opp1-1924000000 { 203 + opp-hz = /bits/ 64 <1924000000>; 204 + opp-microvolt = <1025000>; 205 + required-opps = <&opp2_14>; 206 + }; 207 + opp1-1989000000 { 208 + opp-hz = /bits/ 64 <1989000000>; 209 + opp-microvolt = <1050000>; 210 + required-opps = <&opp2_15>; 211 + }; 212 + }; 213 + 214 + cci_opp: opp-table-cci { 215 + compatible = "operating-points-v2"; 216 + opp-shared; 217 + opp2_00: opp-273000000 { 218 + opp-hz = /bits/ 64 <273000000>; 219 + opp-microvolt = <650000>; 220 + }; 221 + opp2_01: opp-338000000 { 222 + opp-hz = /bits/ 64 <338000000>; 223 + opp-microvolt = <687500>; 224 + }; 225 + opp2_02: opp-403000000 { 226 + opp-hz = /bits/ 64 <403000000>; 227 + opp-microvolt = <718750>; 228 + }; 229 + opp2_03: opp-463000000 { 230 + opp-hz = /bits/ 64 <463000000>; 231 + opp-microvolt = <756250>; 232 + }; 233 + opp2_04: opp-546000000 { 234 + opp-hz = /bits/ 64 <546000000>; 235 + opp-microvolt = <800000>; 236 + }; 237 + opp2_05: opp-624000000 { 238 + opp-hz = /bits/ 64 <624000000>; 239 + opp-microvolt = <818750>; 240 + }; 241 + opp2_06: opp-689000000 { 242 + opp-hz = /bits/ 64 <689000000>; 243 + opp-microvolt = <850000>; 244 + }; 245 + opp2_07: opp-767000000 { 246 + opp-hz = /bits/ 64 <767000000>; 247 + opp-microvolt = <868750>; 248 + }; 249 + opp2_08: opp-845000000 { 250 + opp-hz = /bits/ 64 <845000000>; 251 + opp-microvolt = <893750>; 252 + }; 253 + opp2_09: opp-871000000 { 254 + opp-hz = /bits/ 64 <871000000>; 255 + opp-microvolt = <906250>; 256 + }; 257 + opp2_10: opp-923000000 { 258 + opp-hz = /bits/ 64 <923000000>; 259 + opp-microvolt = <931250>; 260 + }; 261 + opp2_11: opp-962000000 { 262 + opp-hz = /bits/ 64 <962000000>; 263 + opp-microvolt = <943750>; 264 + }; 265 + opp2_12: opp-1027000000 { 266 + opp-hz = /bits/ 64 <1027000000>; 267 + opp-microvolt = <975000>; 268 + }; 269 + opp2_13: opp-1092000000 { 270 + opp-hz = /bits/ 64 <1092000000>; 271 + opp-microvolt = <1000000>; 272 + }; 273 + opp2_14: opp-1144000000 { 274 + opp-hz = /bits/ 64 <1144000000>; 275 + opp-microvolt = <1025000>; 276 + }; 277 + opp2_15: opp-1196000000 { 278 + opp-hz = /bits/ 64 <1196000000>; 279 + opp-microvolt = <1050000>; 280 + }; 281 + }; 282 + 283 + cci: cci { 284 + compatible = "mediatek,mt8183-cci"; 285 + clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 + clock-names = "cci", "intermediate"; 288 + operating-points-v2 = <&cci_opp>; 289 + }; 290 + 45 291 cpus { 46 292 #address-cells = <1>; 47 293 #size-cells = <0>; ··· 331 85 enable-method = "psci"; 332 86 capacity-dmips-mhz = <741>; 333 87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 88 + clocks = <&mcucfg CLK_MCU_MP0_SEL>, 89 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 90 + clock-names = "cpu", "intermediate"; 91 + operating-points-v2 = <&cluster0_opp>; 334 92 dynamic-power-coefficient = <84>; 335 93 #cooling-cells = <2>; 94 + mediatek,cci = <&cci>; 336 95 }; 337 96 338 97 cpu1: cpu@1 { ··· 347 96 enable-method = "psci"; 348 97 capacity-dmips-mhz = <741>; 349 98 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 99 + clocks = <&mcucfg CLK_MCU_MP0_SEL>, 100 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 101 + clock-names = "cpu", "intermediate"; 102 + operating-points-v2 = <&cluster0_opp>; 350 103 dynamic-power-coefficient = <84>; 351 104 #cooling-cells = <2>; 105 + mediatek,cci = <&cci>; 352 106 }; 353 107 354 108 cpu2: cpu@2 { ··· 363 107 enable-method = "psci"; 364 108 capacity-dmips-mhz = <741>; 365 109 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 110 + clocks = <&mcucfg CLK_MCU_MP0_SEL>, 111 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 112 + clock-names = "cpu", "intermediate"; 113 + operating-points-v2 = <&cluster0_opp>; 366 114 dynamic-power-coefficient = <84>; 367 115 #cooling-cells = <2>; 116 + mediatek,cci = <&cci>; 368 117 }; 369 118 370 119 cpu3: cpu@3 { ··· 379 118 enable-method = "psci"; 380 119 capacity-dmips-mhz = <741>; 381 120 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 121 + clocks = <&mcucfg CLK_MCU_MP0_SEL>, 122 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 123 + clock-names = "cpu", "intermediate"; 124 + operating-points-v2 = <&cluster0_opp>; 382 125 dynamic-power-coefficient = <84>; 383 126 #cooling-cells = <2>; 127 + mediatek,cci = <&cci>; 384 128 }; 385 129 386 130 cpu4: cpu@100 { ··· 395 129 enable-method = "psci"; 396 130 capacity-dmips-mhz = <1024>; 397 131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 132 + clocks = <&mcucfg CLK_MCU_MP2_SEL>, 133 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 134 + clock-names = "cpu", "intermediate"; 135 + operating-points-v2 = <&cluster1_opp>; 398 136 dynamic-power-coefficient = <211>; 399 137 #cooling-cells = <2>; 138 + mediatek,cci = <&cci>; 400 139 }; 401 140 402 141 cpu5: cpu@101 { ··· 411 140 enable-method = "psci"; 412 141 capacity-dmips-mhz = <1024>; 413 142 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 143 + clocks = <&mcucfg CLK_MCU_MP2_SEL>, 144 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 145 + clock-names = "cpu", "intermediate"; 146 + operating-points-v2 = <&cluster1_opp>; 414 147 dynamic-power-coefficient = <211>; 415 148 #cooling-cells = <2>; 149 + mediatek,cci = <&cci>; 416 150 }; 417 151 418 152 cpu6: cpu@102 { ··· 427 151 enable-method = "psci"; 428 152 capacity-dmips-mhz = <1024>; 429 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 154 + clocks = <&mcucfg CLK_MCU_MP2_SEL>, 155 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 156 + clock-names = "cpu", "intermediate"; 157 + operating-points-v2 = <&cluster1_opp>; 430 158 dynamic-power-coefficient = <211>; 431 159 #cooling-cells = <2>; 160 + mediatek,cci = <&cci>; 432 161 }; 433 162 434 163 cpu7: cpu@103 { ··· 443 162 enable-method = "psci"; 444 163 capacity-dmips-mhz = <1024>; 445 164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 165 + clocks = <&mcucfg CLK_MCU_MP2_SEL>, 166 + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 167 + clock-names = "cpu", "intermediate"; 168 + operating-points-v2 = <&cluster1_opp>; 446 169 dynamic-power-coefficient = <211>; 447 170 #cooling-cells = <2>; 171 + mediatek,cci = <&cci>; 448 172 }; 449 173 450 174 idle-states { ··· 581 295 }; 582 296 583 297 psci { 584 - compatible = "arm,psci-1.0"; 585 - method = "smc"; 298 + compatible = "arm,psci-1.0"; 299 + method = "smc"; 586 300 }; 587 301 588 302 clk26m: oscillator { ··· 607 321 compatible = "simple-bus"; 608 322 ranges; 609 323 610 - soc_data: soc_data@8000000 { 324 + soc_data: efuse@8000000 { 611 325 compatible = "mediatek,mt8183-efuse", 612 326 "mediatek,efuse"; 613 327 reg = <0 0x08000000 0 0x0010>; ··· 788 502 #power-domain-cells = <0>; 789 503 }; 790 504 791 - power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 505 + mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 792 506 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 793 - clocks = <&topckgen CLK_TOP_MUX_MFG>; 507 + clocks = <&topckgen CLK_TOP_MUX_MFG>; 794 508 clock-names = "mfg"; 795 509 #address-cells = <1>; 796 510 #size-cells = <0>; ··· 1091 805 <&infracfg CLK_INFRA_SPI0>; 1092 806 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1093 807 status = "disabled"; 808 + }; 809 + 810 + svs: svs@1100b000 { 811 + compatible = "mediatek,mt8183-svs"; 812 + reg = <0 0x1100b000 0 0x1000>; 813 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 814 + clocks = <&infracfg CLK_INFRA_THERM>; 815 + clock-names = "main"; 816 + nvmem-cells = <&svs_calibration>, 817 + <&thermal_calibration>; 818 + nvmem-cell-names = "svs-calibration-data", 819 + "t-calibration-data"; 1094 820 }; 1095 821 1096 822 thermal: thermal@1100b000 { ··· 1448 1150 }; 1449 1151 1450 1152 ssusb: usb@11201000 { 1451 - compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 1153 + compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; 1452 1154 reg = <0 0x11201000 0 0x2e00>, 1453 1155 <0 0x11203e00 0 0x0100>; 1454 1156 reg-names = "mac", "ippc"; ··· 1622 1324 1623 1325 mipi_tx_calibration: calib@190 { 1624 1326 reg = <0x190 0xc>; 1327 + }; 1328 + 1329 + svs_calibration: calib@580 { 1330 + reg = <0x580 0x64>; 1625 1331 }; 1626 1332 }; 1627 1333 ··· 1810 1508 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1811 1509 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1812 1510 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1511 + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1813 1512 }; 1814 1513 1815 1514 larb0: larb@14017000 {

+47

arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright 2020 Google LLC 4 + */ 5 + /dts-v1/; 6 + #include "mt8192-asurada.dtsi" 7 + 8 + / { 9 + model = "Google Hayato rev1"; 10 + compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; 11 + }; 12 + 13 + &keyboard_controller { 14 + function-row-physmap = < 15 + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 16 + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 17 + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 18 + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 19 + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 20 + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 21 + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 22 + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 23 + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 24 + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 25 + >; 26 + linux,keymap = < 27 + MATRIX_KEY(0x00, 0x02, KEY_BACK) 28 + MATRIX_KEY(0x03, 0x02, KEY_FORWARD) 29 + MATRIX_KEY(0x02, 0x02, KEY_REFRESH) 30 + MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN) 31 + MATRIX_KEY(0x03, 0x04, KEY_SCALE) 32 + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 33 + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 34 + MATRIX_KEY(0x02, 0x09, KEY_MUTE) 35 + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 36 + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 37 + 38 + CROS_STD_MAIN_KEYMAP 39 + >; 40 + }; 41 + 42 + &touchscreen { 43 + compatible = "hid-over-i2c"; 44 + post-power-on-delay-ms = <10>; 45 + hid-descr-addr = <0x0001>; 46 + vdd-supply = <&pp3300_u>; 47 + };

+62

arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright 2021 Google LLC 4 + */ 5 + /dts-v1/; 6 + #include "mt8192-asurada.dtsi" 7 + #include <dt-bindings/leds/common.h> 8 + 9 + / { 10 + model = "Google Spherion (rev0 - 3)"; 11 + compatible = "google,spherion-rev3", "google,spherion-rev2", 12 + "google,spherion-rev1", "google,spherion-rev0", 13 + "google,spherion", "mediatek,mt8192"; 14 + 15 + pwmleds { 16 + compatible = "pwm-leds"; 17 + 18 + led { 19 + function = LED_FUNCTION_KBD_BACKLIGHT; 20 + color = <LED_COLOR_ID_WHITE>; 21 + pwms = <&cros_ec_pwm 0>; 22 + max-brightness = <1023>; 23 + }; 24 + }; 25 + }; 26 + 27 + &cros_ec_pwm { 28 + status = "okay"; 29 + }; 30 + 31 + &keyboard_controller { 32 + function-row-physmap = < 33 + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 34 + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 35 + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 36 + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 37 + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 38 + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 39 + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 40 + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 41 + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 42 + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 43 + >; 44 + linux,keymap = < 45 + MATRIX_KEY(0x00, 0x02, KEY_BACK) 46 + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 47 + MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN) 48 + MATRIX_KEY(0x01, 0x02, KEY_SCALE) 49 + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 50 + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 51 + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 52 + MATRIX_KEY(0x02, 0x09, KEY_MUTE) 53 + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 54 + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 55 + 56 + CROS_STD_MAIN_KEYMAP 57 + >; 58 + }; 59 + 60 + &touchscreen { 61 + compatible = "elan,ekth3500"; 62 + };

+959

arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2020 MediaTek Inc. 4 + * Author: Seiya Wang <seiya.wang@mediatek.com> 5 + */ 6 + /dts-v1/; 7 + #include "mt8192.dtsi" 8 + #include "mt6359.dtsi" 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/spmi/spmi.h> 11 + 12 + / { 13 + aliases { 14 + serial0 = &uart0; 15 + }; 16 + 17 + chosen { 18 + stdout-path = "serial0:115200n8"; 19 + }; 20 + 21 + memory@40000000 { 22 + device_type = "memory"; 23 + reg = <0 0x40000000 0 0x80000000>; 24 + }; 25 + 26 + /* system wide LDO 1.8V power rail */ 27 + pp1800_ldo_g: regulator-1v8-g { 28 + compatible = "regulator-fixed"; 29 + regulator-name = "pp1800_ldo_g"; 30 + regulator-always-on; 31 + regulator-boot-on; 32 + regulator-min-microvolt = <1800000>; 33 + regulator-max-microvolt = <1800000>; 34 + vin-supply = <&pp3300_g>; 35 + }; 36 + 37 + /* system wide switching 3.3V power rail */ 38 + pp3300_g: regulator-3v3-g { 39 + compatible = "regulator-fixed"; 40 + regulator-name = "pp3300_g"; 41 + regulator-always-on; 42 + regulator-boot-on; 43 + regulator-min-microvolt = <3300000>; 44 + regulator-max-microvolt = <3300000>; 45 + vin-supply = <&ppvar_sys>; 46 + }; 47 + 48 + /* system wide LDO 3.3V power rail */ 49 + pp3300_ldo_z: regulator-3v3-z { 50 + compatible = "regulator-fixed"; 51 + regulator-name = "pp3300_ldo_z"; 52 + regulator-always-on; 53 + regulator-boot-on; 54 + regulator-min-microvolt = <3300000>; 55 + regulator-max-microvolt = <3300000>; 56 + vin-supply = <&ppvar_sys>; 57 + }; 58 + 59 + /* separately switched 3.3V power rail */ 60 + pp3300_u: regulator-3v3-u { 61 + compatible = "regulator-fixed"; 62 + regulator-name = "pp3300_u"; 63 + regulator-always-on; 64 + regulator-boot-on; 65 + regulator-min-microvolt = <3300000>; 66 + regulator-max-microvolt = <3300000>; 67 + /* enable pin wired to GPIO controlled by EC */ 68 + vin-supply = <&pp3300_g>; 69 + }; 70 + 71 + pp3300_wlan: regulator-3v3-wlan { 72 + compatible = "regulator-fixed"; 73 + regulator-name = "pp3300_wlan"; 74 + regulator-always-on; 75 + regulator-boot-on; 76 + regulator-min-microvolt = <3300000>; 77 + regulator-max-microvolt = <3300000>; 78 + pinctrl-names = "default"; 79 + pinctrl-0 = <&pp3300_wlan_pins>; 80 + enable-active-high; 81 + gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 82 + }; 83 + 84 + /* system wide switching 5.0V power rail */ 85 + pp5000_a: regulator-5v0-a { 86 + compatible = "regulator-fixed"; 87 + regulator-name = "pp5000_a"; 88 + regulator-always-on; 89 + regulator-boot-on; 90 + regulator-min-microvolt = <5000000>; 91 + regulator-max-microvolt = <5000000>; 92 + vin-supply = <&ppvar_sys>; 93 + }; 94 + 95 + /* system wide semi-regulated power rail from battery or USB */ 96 + ppvar_sys: regulator-var-sys { 97 + compatible = "regulator-fixed"; 98 + regulator-name = "ppvar_sys"; 99 + regulator-always-on; 100 + regulator-boot-on; 101 + }; 102 + 103 + reserved_memory: reserved-memory { 104 + #address-cells = <2>; 105 + #size-cells = <2>; 106 + ranges; 107 + 108 + scp_mem_reserved: scp@50000000 { 109 + compatible = "shared-dma-pool"; 110 + reg = <0 0x50000000 0 0x2900000>; 111 + no-map; 112 + }; 113 + 114 + wifi_restricted_dma_region: wifi@c0000000 { 115 + compatible = "restricted-dma-pool"; 116 + reg = <0 0xc0000000 0 0x4000000>; 117 + }; 118 + }; 119 + }; 120 + 121 + &i2c0 { 122 + status = "okay"; 123 + 124 + clock-frequency = <400000>; 125 + pinctrl-names = "default"; 126 + pinctrl-0 = <&i2c0_pins>; 127 + 128 + touchscreen: touchscreen@10 { 129 + reg = <0x10>; 130 + interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 131 + pinctrl-names = "default"; 132 + pinctrl-0 = <&touchscreen_pins>; 133 + }; 134 + }; 135 + 136 + &i2c1 { 137 + status = "okay"; 138 + 139 + clock-frequency = <400000>; 140 + pinctrl-names = "default"; 141 + pinctrl-0 = <&i2c1_pins>; 142 + }; 143 + 144 + &i2c2 { 145 + status = "okay"; 146 + 147 + clock-frequency = <400000>; 148 + clock-stretch-ns = <12600>; 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&i2c2_pins>; 151 + 152 + trackpad@15 { 153 + compatible = "elan,ekth3000"; 154 + reg = <0x15>; 155 + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 156 + pinctrl-names = "default"; 157 + pinctrl-0 = <&trackpad_pins>; 158 + vcc-supply = <&pp3300_u>; 159 + wakeup-source; 160 + }; 161 + }; 162 + 163 + &i2c3 { 164 + status = "okay"; 165 + 166 + clock-frequency = <400000>; 167 + pinctrl-names = "default"; 168 + pinctrl-0 = <&i2c3_pins>; 169 + }; 170 + 171 + &i2c7 { 172 + status = "okay"; 173 + 174 + clock-frequency = <400000>; 175 + pinctrl-names = "default"; 176 + pinctrl-0 = <&i2c7_pins>; 177 + }; 178 + 179 + &mmc0 { 180 + status = "okay"; 181 + 182 + pinctrl-names = "default", "state_uhs"; 183 + pinctrl-0 = <&mmc0_default_pins>; 184 + pinctrl-1 = <&mmc0_uhs_pins>; 185 + bus-width = <8>; 186 + max-frequency = <200000000>; 187 + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 188 + vqmmc-supply = <&mt6359_vufs_ldo_reg>; 189 + cap-mmc-highspeed; 190 + mmc-hs200-1_8v; 191 + mmc-hs400-1_8v; 192 + supports-cqe; 193 + cap-mmc-hw-reset; 194 + mmc-hs400-enhanced-strobe; 195 + hs400-ds-delay = <0x12814>; 196 + no-sdio; 197 + no-sd; 198 + non-removable; 199 + }; 200 + 201 + &mmc1 { 202 + status = "okay"; 203 + 204 + pinctrl-names = "default", "state_uhs"; 205 + pinctrl-0 = <&mmc1_default_pins>; 206 + pinctrl-1 = <&mmc1_uhs_pins>; 207 + bus-width = <4>; 208 + max-frequency = <200000000>; 209 + cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 210 + vmmc-supply = <&mt6360_ldo5_reg>; 211 + vqmmc-supply = <&mt6360_ldo3_reg>; 212 + cap-sd-highspeed; 213 + sd-uhs-sdr50; 214 + sd-uhs-sdr104; 215 + no-sdio; 216 + no-mmc; 217 + }; 218 + 219 + /* for CORE */ 220 + &mt6359_vgpu11_buck_reg { 221 + regulator-always-on; 222 + }; 223 + 224 + &mt6359_vgpu11_sshub_buck_reg { 225 + regulator-always-on; 226 + regulator-min-microvolt = <575000>; 227 + regulator-max-microvolt = <575000>; 228 + }; 229 + 230 + &mt6359_vrf12_ldo_reg { 231 + regulator-always-on; 232 + }; 233 + 234 + &mt6359_vufs_ldo_reg { 235 + regulator-always-on; 236 + }; 237 + 238 + &mt6359codec { 239 + mediatek,dmic-mode = <1>; /* one-wire */ 240 + mediatek,mic-type-0 = <2>; /* DMIC */ 241 + mediatek,mic-type-2 = <2>; /* DMIC */ 242 + }; 243 + 244 + &nor_flash { 245 + status = "okay"; 246 + 247 + pinctrl-names = "default"; 248 + pinctrl-0 = <&nor_flash_pins>; 249 + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 250 + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 251 + 252 + flash@0 { 253 + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 254 + reg = <0>; 255 + spi-max-frequency = <52000000>; 256 + spi-rx-bus-width = <2>; 257 + spi-tx-bus-width = <2>; 258 + }; 259 + }; 260 + 261 + &pcie { 262 + pinctrl-names = "default"; 263 + pinctrl-0 = <&pcie_pins>; 264 + 265 + pcie0: pcie@0,0 { 266 + device_type = "pci"; 267 + reg = <0x0000 0 0 0 0>; 268 + num-lanes = <1>; 269 + bus-range = <0x1 0x1>; 270 + 271 + #address-cells = <3>; 272 + #size-cells = <2>; 273 + ranges; 274 + 275 + wifi: wifi@0,0 { 276 + reg = <0x10000 0 0 0 0x100000>, 277 + <0x10000 0 0x100000 0 0x100000>; 278 + memory-region = <&wifi_restricted_dma_region>; 279 + }; 280 + }; 281 + }; 282 + 283 + &pio { 284 + /* 220 lines */ 285 + gpio-line-names = "I2S_DP_LRCK", 286 + "IS_DP_BCLK", 287 + "I2S_DP_MCLK", 288 + "I2S_DP_DATAOUT", 289 + "SAR0_INT_ODL", 290 + "EC_AP_INT_ODL", 291 + "EDPBRDG_INT_ODL", 292 + "DPBRDG_INT_ODL", 293 + "DPBRDG_PWREN", 294 + "DPBRDG_RST_ODL", 295 + "I2S_HP_MCLK", 296 + "I2S_HP_BCK", 297 + "I2S_HP_LRCK", 298 + "I2S_HP_DATAIN", 299 + /* 300 + * AP_FLASH_WP_L is crossystem ABI. Schematics 301 + * call it AP_FLASH_WP_ODL. 302 + */ 303 + "AP_FLASH_WP_L", 304 + "TRACKPAD_INT_ODL", 305 + "EC_AP_HPD_OD", 306 + "SD_CD_ODL", 307 + "HP_INT_ODL_ALC", 308 + "EN_PP1000_DPBRDG", 309 + "AP_GPIO20", 310 + "TOUCH_INT_L_1V8", 311 + "UART_BT_WAKE_ODL", 312 + "AP_GPIO23", 313 + "AP_SPI_FLASH_CS_L", 314 + "AP_SPI_FLASH_CLK", 315 + "EN_PP3300_DPBRDG_DX", 316 + "AP_SPI_FLASH_MOSI", 317 + "AP_SPI_FLASH_MISO", 318 + "I2S_HP_DATAOUT", 319 + "AP_GPIO30", 320 + "I2S_SPKR_MCLK", 321 + "I2S_SPKR_BCLK", 322 + "I2S_SPKR_LRCK", 323 + "I2S_SPKR_DATAIN", 324 + "I2S_SPKR_DATAOUT", 325 + "AP_SPI_H1_TPM_CLK", 326 + "AP_SPI_H1_TPM_CS_L", 327 + "AP_SPI_H1_TPM_MISO", 328 + "AP_SPI_H1_TPM_MOSI", 329 + "BL_PWM", 330 + "EDPBRDG_PWREN", 331 + "EDPBRDG_RST_ODL", 332 + "EN_PP3300_HUB", 333 + "HUB_RST_L", 334 + "", 335 + "", 336 + "", 337 + "", 338 + "", 339 + "", 340 + "SD_CLK", 341 + "SD_CMD", 342 + "SD_DATA3", 343 + "SD_DATA0", 344 + "SD_DATA2", 345 + "SD_DATA1", 346 + "", 347 + "", 348 + "", 349 + "", 350 + "", 351 + "", 352 + "PCIE_WAKE_ODL", 353 + "PCIE_RST_L", 354 + "PCIE_CLKREQ_ODL", 355 + "", 356 + "", 357 + "", 358 + "", 359 + "", 360 + "", 361 + "", 362 + "", 363 + "", 364 + "", 365 + "", 366 + "", 367 + "", 368 + "", 369 + "", 370 + "", 371 + "", 372 + "", 373 + "", 374 + "", 375 + "", 376 + "", 377 + "", 378 + "SPMI_SCL", 379 + "SPMI_SDA", 380 + "AP_GOOD", 381 + "UART_DBG_TX_AP_RX", 382 + "UART_AP_TX_DBG_RX", 383 + "UART_AP_TX_BT_RX", 384 + "UART_BT_TX_AP_RX", 385 + "MIPI_DPI_D0_R", 386 + "MIPI_DPI_D1_R", 387 + "MIPI_DPI_D2_R", 388 + "MIPI_DPI_D3_R", 389 + "MIPI_DPI_D4_R", 390 + "MIPI_DPI_D5_R", 391 + "MIPI_DPI_D6_R", 392 + "MIPI_DPI_D7_R", 393 + "MIPI_DPI_D8_R", 394 + "MIPI_DPI_D9_R", 395 + "MIPI_DPI_D10_R", 396 + "", 397 + "", 398 + "MIPI_DPI_DE_R", 399 + "MIPI_DPI_D11_R", 400 + "MIPI_DPI_VSYNC_R", 401 + "MIPI_DPI_CLK_R", 402 + "MIPI_DPI_HSYNC_R", 403 + "PCM_BT_DATAIN", 404 + "PCM_BT_SYNC", 405 + "PCM_BT_DATAOUT", 406 + "PCM_BT_CLK", 407 + "AP_I2C_AUDIO_SCL", 408 + "AP_I2C_AUDIO_SDA", 409 + "SCP_I2C_SCL", 410 + "SCP_I2C_SDA", 411 + "AP_I2C_WLAN_SCL", 412 + "AP_I2C_WLAN_SDA", 413 + "AP_I2C_DPBRDG_SCL", 414 + "AP_I2C_DPBRDG_SDA", 415 + "EN_PP1800_DPBRDG_DX", 416 + "EN_PP3300_EDP_DX", 417 + "EN_PP1800_EDPBRDG_DX", 418 + "EN_PP1000_EDPBRDG", 419 + "SCP_JTAG0_TDO", 420 + "SCP_JTAG0_TDI", 421 + "SCP_JTAG0_TMS", 422 + "SCP_JTAG0_TCK", 423 + "SCP_JTAG0_TRSTN", 424 + "EN_PP3000_VMC_PMU", 425 + "EN_PP3300_DISPLAY_DX", 426 + "TOUCH_RST_L_1V8", 427 + "TOUCH_REPORT_DISABLE", 428 + "", 429 + "", 430 + "AP_I2C_TRACKPAD_SCL_1V8", 431 + "AP_I2C_TRACKPAD_SDA_1V8", 432 + "EN_PP3300_WLAN", 433 + "BT_KILL_L", 434 + "WIFI_KILL_L", 435 + "SET_VMC_VOLT_AT_1V8", 436 + "EN_SPK", 437 + "AP_WARM_RST_REQ", 438 + "", 439 + "", 440 + "EN_PP3000_SD_S3", 441 + "AP_EDP_BKLTEN", 442 + "", 443 + "", 444 + "", 445 + "AP_SPI_EC_CLK", 446 + "AP_SPI_EC_CS_L", 447 + "AP_SPI_EC_MISO", 448 + "AP_SPI_EC_MOSI", 449 + "AP_I2C_EDPBRDG_SCL", 450 + "AP_I2C_EDPBRDG_SDA", 451 + "MT6315_PROC_INT", 452 + "MT6315_GPU_INT", 453 + "UART_SERVO_TX_SCP_RX", 454 + "UART_SCP_TX_SERVO_RX", 455 + "BT_RTS_AP_CTS", 456 + "AP_RTS_BT_CTS", 457 + "UART_AP_WAKE_BT_ODL", 458 + "WLAN_ALERT_ODL", 459 + "EC_IN_RW_ODL", 460 + "H1_AP_INT_ODL", 461 + "", 462 + "", 463 + "", 464 + "", 465 + "", 466 + "", 467 + "", 468 + "", 469 + "", 470 + "", 471 + "", 472 + "MSDC0_CMD", 473 + "MSDC0_DAT0", 474 + "MSDC0_DAT2", 475 + "MSDC0_DAT4", 476 + "MSDC0_DAT6", 477 + "MSDC0_DAT1", 478 + "MSDC0_DAT5", 479 + "MSDC0_DAT7", 480 + "MSDC0_DSL", 481 + "MSDC0_CLK", 482 + "MSDC0_DAT3", 483 + "MSDC0_RST_L", 484 + "SCP_VREQ_VAO", 485 + "AUD_DAT_MOSI2", 486 + "AUD_NLE_MOSI1", 487 + "AUD_NLE_MOSI0", 488 + "AUD_DAT_MISO2", 489 + "AP_I2C_SAR_SDA", 490 + "AP_I2C_SAR_SCL", 491 + "AP_I2C_PWR_SCL", 492 + "AP_I2C_PWR_SDA", 493 + "AP_I2C_TS_SCL_1V8", 494 + "AP_I2C_TS_SDA_1V8", 495 + "SRCLKENA0", 496 + "SRCLKENA1", 497 + "AP_EC_WATCHDOG_L", 498 + "PWRAP_SPI0_MI", 499 + "PWRAP_SPI0_CSN", 500 + "PWRAP_SPI0_MO", 501 + "PWRAP_SPI0_CK", 502 + "AP_RTC_CLK32K", 503 + "AUD_CLK_MOSI", 504 + "AUD_SYNC_MOSI", 505 + "AUD_DAT_MOSI0", 506 + "AUD_DAT_MOSI1", 507 + "AUD_DAT_MISO0", 508 + "AUD_DAT_MISO1"; 509 + 510 + cr50_int: cr50-irq-default-pins { 511 + pins-gsc-ap-int-odl { 512 + pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 513 + input-enable; 514 + }; 515 + }; 516 + 517 + cros_ec_int: cros-ec-irq-default-pins { 518 + pins-ec-ap-int-odl { 519 + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 520 + input-enable; 521 + bias-pull-up; 522 + }; 523 + }; 524 + 525 + i2c0_pins: i2c0-default-pins { 526 + pins-bus { 527 + pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 528 + <PINMUX_GPIO205__FUNC_SDA0>; 529 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 530 + drive-strength-microamp = <1000>; 531 + }; 532 + }; 533 + 534 + i2c1_pins: i2c1-default-pins { 535 + pins-bus { 536 + pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 537 + <PINMUX_GPIO119__FUNC_SDA1>; 538 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 539 + drive-strength-microamp = <1000>; 540 + }; 541 + }; 542 + 543 + i2c2_pins: i2c2-default-pins { 544 + pins-bus { 545 + pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 546 + <PINMUX_GPIO142__FUNC_SDA2>; 547 + bias-pull-up = <MTK_PULL_SET_RSEL_011>; 548 + }; 549 + }; 550 + 551 + i2c3_pins: i2c3-default-pins { 552 + pins-bus { 553 + pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 554 + <PINMUX_GPIO161__FUNC_SDA3>; 555 + bias-disable; 556 + drive-strength-microamp = <1000>; 557 + }; 558 + }; 559 + 560 + i2c7_pins: i2c7-default-pins { 561 + pins-bus { 562 + pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 563 + <PINMUX_GPIO125__FUNC_SDA7>; 564 + bias-disable; 565 + drive-strength-microamp = <1000>; 566 + }; 567 + }; 568 + 569 + mmc0_default_pins: mmc0-default-pins { 570 + pins-cmd-dat { 571 + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 572 + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 573 + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 574 + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 575 + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 576 + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 577 + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 578 + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 579 + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 580 + input-enable; 581 + drive-strength = <8>; 582 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 583 + }; 584 + 585 + pins-clk { 586 + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 587 + drive-strength = <8>; 588 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 589 + }; 590 + 591 + pins-rst { 592 + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 593 + drive-strength = <8>; 594 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 595 + }; 596 + }; 597 + 598 + mmc0_uhs_pins: mmc0-uhs-pins { 599 + pins-cmd-dat { 600 + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 601 + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 602 + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 603 + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 604 + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 605 + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 606 + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 607 + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 608 + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 609 + input-enable; 610 + drive-strength = <10>; 611 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 612 + }; 613 + 614 + pins-clk { 615 + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 616 + drive-strength = <10>; 617 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 618 + }; 619 + 620 + pins-rst { 621 + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 622 + drive-strength = <8>; 623 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 624 + }; 625 + 626 + pins-ds { 627 + pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 628 + drive-strength = <10>; 629 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 630 + }; 631 + }; 632 + 633 + mmc1_default_pins: mmc1-default-pins { 634 + pins-cmd-dat { 635 + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 636 + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 637 + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 638 + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 639 + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 640 + input-enable; 641 + drive-strength = <8>; 642 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 643 + }; 644 + 645 + pins-clk { 646 + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 647 + drive-strength = <8>; 648 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 649 + }; 650 + 651 + pins-insert { 652 + pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 653 + input-enable; 654 + bias-pull-up; 655 + }; 656 + }; 657 + 658 + mmc1_uhs_pins: mmc1-uhs-pins { 659 + pins-cmd-dat { 660 + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 661 + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 662 + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 663 + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 664 + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 665 + input-enable; 666 + drive-strength = <8>; 667 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 668 + }; 669 + 670 + pins-clk { 671 + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 672 + input-enable; 673 + drive-strength = <8>; 674 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 675 + }; 676 + }; 677 + 678 + nor_flash_pins: nor-flash-default-pins { 679 + pins-cs-io1 { 680 + pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 681 + <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 682 + input-enable; 683 + bias-pull-up; 684 + drive-strength = <10>; 685 + }; 686 + 687 + pins-io0 { 688 + pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 689 + bias-pull-up; 690 + drive-strength = <10>; 691 + }; 692 + 693 + pins-clk { 694 + pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 695 + input-enable; 696 + bias-pull-up; 697 + drive-strength = <10>; 698 + }; 699 + }; 700 + 701 + pcie_pins: pcie-default-pins { 702 + pins-pcie-wake { 703 + pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 704 + bias-pull-up; 705 + }; 706 + 707 + pins-pcie-pereset { 708 + pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 709 + }; 710 + 711 + pins-pcie-clkreq { 712 + pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 713 + bias-pull-up; 714 + }; 715 + 716 + pins-wifi-kill { 717 + pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 718 + output-high; 719 + }; 720 + }; 721 + 722 + pp3300_wlan_pins: pp3300-wlan-pins { 723 + pins-pcie-en-pp3300-wlan { 724 + pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 725 + output-high; 726 + }; 727 + }; 728 + 729 + scp_pins: scp-pins { 730 + pins-vreq-vao { 731 + pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 732 + }; 733 + }; 734 + 735 + spi1_pins: spi1-default-pins { 736 + pins-cs-mosi-clk { 737 + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 738 + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 739 + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 740 + bias-disable; 741 + }; 742 + 743 + pins-miso { 744 + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 745 + bias-pull-down; 746 + }; 747 + }; 748 + 749 + spi5_pins: spi5-default-pins { 750 + pins-bus { 751 + pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 752 + <PINMUX_GPIO37__FUNC_GPIO37>, 753 + <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 754 + <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 755 + bias-disable; 756 + }; 757 + }; 758 + 759 + trackpad_pins: trackpad-default-pins { 760 + pins-int-n { 761 + pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 762 + input-enable; 763 + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 764 + }; 765 + }; 766 + 767 + touchscreen_pins: touchscreen-default-pins { 768 + pins-irq { 769 + pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 770 + input-enable; 771 + bias-pull-up; 772 + }; 773 + 774 + pins-reset { 775 + pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 776 + output-high; 777 + }; 778 + 779 + pins-report-sw { 780 + pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 781 + output-low; 782 + }; 783 + }; 784 + }; 785 + 786 + &pmic { 787 + interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 788 + }; 789 + 790 + &scp { 791 + status = "okay"; 792 + 793 + firmware-name = "mediatek/mt8192/scp.img"; 794 + memory-region = <&scp_mem_reserved>; 795 + pinctrl-names = "default"; 796 + pinctrl-0 = <&scp_pins>; 797 + 798 + cros-ec { 799 + compatible = "google,cros-ec-rpmsg"; 800 + mediatek,rpmsg-name = "cros-ec-rpmsg"; 801 + }; 802 + }; 803 + 804 + &spi1 { 805 + status = "okay"; 806 + 807 + mediatek,pad-select = <0>; 808 + pinctrl-names = "default"; 809 + pinctrl-0 = <&spi1_pins>; 810 + 811 + cros_ec: ec@0 { 812 + compatible = "google,cros-ec-spi"; 813 + reg = <0>; 814 + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 815 + spi-max-frequency = <3000000>; 816 + pinctrl-names = "default"; 817 + pinctrl-0 = <&cros_ec_int>; 818 + 819 + #address-cells = <1>; 820 + #size-cells = <0>; 821 + 822 + base_detection: cbas { 823 + compatible = "google,cros-cbas"; 824 + }; 825 + 826 + cros_ec_pwm: pwm { 827 + compatible = "google,cros-ec-pwm"; 828 + #pwm-cells = <1>; 829 + 830 + status = "disabled"; 831 + }; 832 + 833 + i2c_tunnel: i2c-tunnel { 834 + compatible = "google,cros-ec-i2c-tunnel"; 835 + google,remote-bus = <0>; 836 + #address-cells = <1>; 837 + #size-cells = <0>; 838 + }; 839 + 840 + mt6360_ldo3_reg: regulator@0 { 841 + compatible = "google,cros-ec-regulator"; 842 + reg = <0>; 843 + regulator-min-microvolt = <1800000>; 844 + regulator-max-microvolt = <3300000>; 845 + }; 846 + 847 + mt6360_ldo5_reg: regulator@1 { 848 + compatible = "google,cros-ec-regulator"; 849 + reg = <1>; 850 + regulator-min-microvolt = <3300000>; 851 + regulator-max-microvolt = <3300000>; 852 + }; 853 + 854 + typec { 855 + compatible = "google,cros-ec-typec"; 856 + #address-cells = <1>; 857 + #size-cells = <0>; 858 + 859 + usb_c0: connector@0 { 860 + compatible = "usb-c-connector"; 861 + reg = <0>; 862 + label = "left"; 863 + power-role = "dual"; 864 + data-role = "host"; 865 + try-power-role = "source"; 866 + }; 867 + 868 + usb_c1: connector@1 { 869 + compatible = "usb-c-connector"; 870 + reg = <1>; 871 + label = "right"; 872 + power-role = "dual"; 873 + data-role = "host"; 874 + try-power-role = "source"; 875 + }; 876 + }; 877 + }; 878 + }; 879 + 880 + &spi5 { 881 + status = "okay"; 882 + 883 + cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 884 + mediatek,pad-select = <0>; 885 + pinctrl-names = "default"; 886 + pinctrl-0 = <&spi5_pins>; 887 + 888 + cr50@0 { 889 + compatible = "google,cr50"; 890 + reg = <0>; 891 + interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 892 + spi-max-frequency = <1000000>; 893 + pinctrl-names = "default"; 894 + pinctrl-0 = <&cr50_int>; 895 + }; 896 + }; 897 + 898 + &spmi { 899 + #address-cells = <2>; 900 + #size-cells = <0>; 901 + 902 + mt6315_6: pmic@6 { 903 + compatible = "mediatek,mt6315-regulator"; 904 + reg = <0x6 SPMI_USID>; 905 + 906 + regulators { 907 + mt6315_6_vbuck1: vbuck1 { 908 + regulator-compatible = "vbuck1"; 909 + regulator-name = "Vbcpu"; 910 + regulator-min-microvolt = <300000>; 911 + regulator-max-microvolt = <1193750>; 912 + regulator-enable-ramp-delay = <256>; 913 + regulator-allowed-modes = <0 1 2>; 914 + regulator-always-on; 915 + }; 916 + 917 + mt6315_6_vbuck3: vbuck3 { 918 + regulator-compatible = "vbuck3"; 919 + regulator-name = "Vlcpu"; 920 + regulator-min-microvolt = <300000>; 921 + regulator-max-microvolt = <1193750>; 922 + regulator-enable-ramp-delay = <256>; 923 + regulator-allowed-modes = <0 1 2>; 924 + regulator-always-on; 925 + }; 926 + }; 927 + }; 928 + 929 + mt6315_7: pmic@7 { 930 + compatible = "mediatek,mt6315-regulator"; 931 + reg = <0x7 SPMI_USID>; 932 + 933 + regulators { 934 + mt6315_7_vbuck1: vbuck1 { 935 + regulator-compatible = "vbuck1"; 936 + regulator-name = "Vgpu"; 937 + regulator-min-microvolt = <606250>; 938 + regulator-max-microvolt = <1193750>; 939 + regulator-enable-ramp-delay = <256>; 940 + regulator-allowed-modes = <0 1 2>; 941 + }; 942 + }; 943 + }; 944 + }; 945 + 946 + &uart0 { 947 + status = "okay"; 948 + }; 949 + 950 + &xhci { 951 + status = "okay"; 952 + 953 + wakeup-source; 954 + vusb33-supply = <&pp3300_g>; 955 + vbus-supply = <&pp5000_a>; 956 + }; 957 + 958 + #include <arm/cros-ec-keyboard.dtsi> 959 + #include <arm/cros-ec-sbs.dtsi>

+15 -14

arch/arm64/boot/dts/mediatek/mt8192.dtsi

··· 43 43 reg = <0x000>; 44 44 enable-method = "psci"; 45 45 clock-frequency = <1701000000>; 46 - cpu-idle-states = <&cpuoff_l &clusteroff_l>; 46 + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 47 47 next-level-cache = <&l2_0>; 48 48 capacity-dmips-mhz = <530>; 49 49 }; ··· 54 54 reg = <0x100>; 55 55 enable-method = "psci"; 56 56 clock-frequency = <1701000000>; 57 - cpu-idle-states = <&cpuoff_l &clusteroff_l>; 57 + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 58 58 next-level-cache = <&l2_0>; 59 59 capacity-dmips-mhz = <530>; 60 60 }; ··· 65 65 reg = <0x200>; 66 66 enable-method = "psci"; 67 67 clock-frequency = <1701000000>; 68 - cpu-idle-states = <&cpuoff_l &clusteroff_l>; 68 + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 69 69 next-level-cache = <&l2_0>; 70 70 capacity-dmips-mhz = <530>; 71 71 }; ··· 76 76 reg = <0x300>; 77 77 enable-method = "psci"; 78 78 clock-frequency = <1701000000>; 79 - cpu-idle-states = <&cpuoff_l &clusteroff_l>; 79 + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 80 80 next-level-cache = <&l2_0>; 81 81 capacity-dmips-mhz = <530>; 82 82 }; ··· 87 87 reg = <0x400>; 88 88 enable-method = "psci"; 89 89 clock-frequency = <2171000000>; 90 - cpu-idle-states = <&cpuoff_b &clusteroff_b>; 90 + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 91 91 next-level-cache = <&l2_1>; 92 92 capacity-dmips-mhz = <1024>; 93 93 }; ··· 98 98 reg = <0x500>; 99 99 enable-method = "psci"; 100 100 clock-frequency = <2171000000>; 101 - cpu-idle-states = <&cpuoff_b &clusteroff_b>; 101 + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 102 102 next-level-cache = <&l2_1>; 103 103 capacity-dmips-mhz = <1024>; 104 104 }; ··· 109 109 reg = <0x600>; 110 110 enable-method = "psci"; 111 111 clock-frequency = <2171000000>; 112 - cpu-idle-states = <&cpuoff_b &clusteroff_b>; 112 + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 113 113 next-level-cache = <&l2_1>; 114 114 capacity-dmips-mhz = <1024>; 115 115 }; ··· 120 120 reg = <0x700>; 121 121 enable-method = "psci"; 122 122 clock-frequency = <2171000000>; 123 - cpu-idle-states = <&cpuoff_b &clusteroff_b>; 123 + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 124 124 next-level-cache = <&l2_1>; 125 125 capacity-dmips-mhz = <1024>; 126 126 }; ··· 172 172 }; 173 173 174 174 idle-states { 175 - entry-method = "arm,psci"; 176 - cpuoff_l: cpuoff_l { 175 + entry-method = "psci"; 176 + cpu_sleep_l: cpu-sleep-l { 177 177 compatible = "arm,idle-state"; 178 178 arm,psci-suspend-param = <0x00010001>; 179 179 local-timer-stop; ··· 181 181 exit-latency-us = <140>; 182 182 min-residency-us = <780>; 183 183 }; 184 - cpuoff_b: cpuoff_b { 184 + cpu_sleep_b: cpu-sleep-b { 185 185 compatible = "arm,idle-state"; 186 186 arm,psci-suspend-param = <0x00010001>; 187 187 local-timer-stop; ··· 189 189 exit-latency-us = <145>; 190 190 min-residency-us = <720>; 191 191 }; 192 - clusteroff_l: clusteroff_l { 192 + cluster_sleep_l: cluster-sleep-l { 193 193 compatible = "arm,idle-state"; 194 194 arm,psci-suspend-param = <0x01010002>; 195 195 local-timer-stop; ··· 197 197 exit-latency-us = <155>; 198 198 min-residency-us = <860>; 199 199 }; 200 - clusteroff_b: clusteroff_b { 200 + cluster_sleep_b: cluster-sleep-b { 201 201 compatible = "arm,idle-state"; 202 202 arm,psci-suspend-param = <0x01010002>; 203 203 local-timer-stop; ··· 271 271 compatible = "mediatek,mt8192-infracfg", "syscon"; 272 272 reg = <0 0x10001000 0 0x1000>; 273 273 #clock-cells = <1>; 274 + #reset-cells = <1>; 274 275 }; 275 276 276 277 pericfg: syscon@10003000 { ··· 912 911 }; 913 912 914 913 efuse: efuse@11c10000 { 915 - compatible = "mediatek,efuse"; 914 + compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 916 915 reg = <0 0x11c10000 0 0x1000>; 917 916 #address-cells = <1>; 918 917 #size-cells = <1>;

+15

arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2021 MediaTek Inc. 4 + */ 5 + /dts-v1/; 6 + #include "mt8195-cherry.dtsi" 7 + 8 + / { 9 + model = "Acer Tomato (rev1) board"; 10 + compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195"; 11 + }; 12 + 13 + &ts_10 { 14 + status = "okay"; 15 + };

+35

arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2021 MediaTek Inc. 4 + */ 5 + /dts-v1/; 6 + #include "mt8195-cherry.dtsi" 7 + 8 + / { 9 + model = "Acer Tomato (rev2) board"; 10 + compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195"; 11 + }; 12 + 13 + &pio_default { 14 + pins-low-power-hdmi-disable { 15 + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, 16 + <PINMUX_GPIO32__FUNC_GPIO32>, 17 + <PINMUX_GPIO33__FUNC_GPIO33>, 18 + <PINMUX_GPIO34__FUNC_GPIO34>, 19 + <PINMUX_GPIO35__FUNC_GPIO35>; 20 + input-enable; 21 + bias-pull-down; 22 + }; 23 + 24 + pins-low-power-pcie0-disable { 25 + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>, 26 + <PINMUX_GPIO20__FUNC_GPIO20>, 27 + <PINMUX_GPIO21__FUNC_GPIO21>; 28 + input-enable; 29 + bias-pull-down; 30 + }; 31 + }; 32 + 33 + &ts_10 { 34 + status = "okay"; 35 + };

+36

arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2021 MediaTek Inc. 4 + */ 5 + /dts-v1/; 6 + #include "mt8195-cherry.dtsi" 7 + 8 + / { 9 + model = "Acer Tomato (rev3 - 4) board"; 10 + compatible = "google,tomato-rev4", "google,tomato-rev3", 11 + "google,tomato", "mediatek,mt8195"; 12 + }; 13 + 14 + &pio_default { 15 + pins-low-power-hdmi-disable { 16 + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, 17 + <PINMUX_GPIO32__FUNC_GPIO32>, 18 + <PINMUX_GPIO33__FUNC_GPIO33>, 19 + <PINMUX_GPIO34__FUNC_GPIO34>, 20 + <PINMUX_GPIO35__FUNC_GPIO35>; 21 + input-enable; 22 + bias-pull-down; 23 + }; 24 + 25 + pins-low-power-pcie0-disable { 26 + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>, 27 + <PINMUX_GPIO20__FUNC_GPIO20>, 28 + <PINMUX_GPIO21__FUNC_GPIO21>; 29 + input-enable; 30 + bias-pull-down; 31 + }; 32 + }; 33 + 34 + &ts_10 { 35 + status = "okay"; 36 + };

+702

arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi

··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2021 MediaTek Inc. 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include "mt8195.dtsi" 8 + #include "mt6359.dtsi" 9 + 10 + / { 11 + aliases { 12 + i2c0 = &i2c0; 13 + i2c1 = &i2c1; 14 + i2c2 = &i2c2; 15 + i2c3 = &i2c3; 16 + i2c4 = &i2c4; 17 + i2c5 = &i2c5; 18 + i2c7 = &i2c7; 19 + mmc0 = &mmc0; 20 + serial0 = &uart0; 21 + }; 22 + 23 + chosen { 24 + stdout-path = "serial0:115200n8"; 25 + }; 26 + 27 + memory@40000000 { 28 + device_type = "memory"; 29 + reg = <0 0x40000000 0 0x80000000>; 30 + }; 31 + 32 + /* system wide LDO 3.3V power rail */ 33 + pp3300_z5: regulator-pp3300-ldo-z5 { 34 + compatible = "regulator-fixed"; 35 + regulator-name = "pp3300_ldo_z5"; 36 + regulator-always-on; 37 + regulator-boot-on; 38 + regulator-min-microvolt = <3300000>; 39 + regulator-max-microvolt = <3300000>; 40 + vin-supply = <&ppvar_sys>; 41 + }; 42 + 43 + /* separately switched 3.3V power rail */ 44 + pp3300_s3: regulator-pp3300-s3 { 45 + compatible = "regulator-fixed"; 46 + regulator-name = "pp3300_s3"; 47 + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 48 + regulator-always-on; 49 + regulator-boot-on; 50 + regulator-min-microvolt = <3300000>; 51 + regulator-max-microvolt = <3300000>; 52 + vin-supply = <&pp3300_z2>; 53 + }; 54 + 55 + /* system wide 3.3V power rail */ 56 + pp3300_z2: regulator-pp3300-z2 { 57 + compatible = "regulator-fixed"; 58 + regulator-name = "pp3300_z2"; 59 + /* EN pin tied to pp4200_z2, which is controlled by EC */ 60 + regulator-always-on; 61 + regulator-boot-on; 62 + regulator-min-microvolt = <3300000>; 63 + regulator-max-microvolt = <3300000>; 64 + vin-supply = <&ppvar_sys>; 65 + }; 66 + 67 + /* system wide 4.2V power rail */ 68 + pp4200_z2: regulator-pp4200-z2 { 69 + compatible = "regulator-fixed"; 70 + regulator-name = "pp4200_z2"; 71 + /* controlled by EC */ 72 + regulator-always-on; 73 + regulator-boot-on; 74 + regulator-min-microvolt = <4200000>; 75 + regulator-max-microvolt = <4200000>; 76 + vin-supply = <&ppvar_sys>; 77 + }; 78 + 79 + /* system wide switching 5.0V power rail */ 80 + pp5000_s5: regulator-pp5000-s5 { 81 + compatible = "regulator-fixed"; 82 + regulator-name = "pp5000_s5"; 83 + /* controlled by EC */ 84 + regulator-always-on; 85 + regulator-boot-on; 86 + regulator-min-microvolt = <5000000>; 87 + regulator-max-microvolt = <5000000>; 88 + vin-supply = <&ppvar_sys>; 89 + }; 90 + 91 + /* system wide semi-regulated power rail from battery or USB */ 92 + ppvar_sys: regulator-ppvar-sys { 93 + compatible = "regulator-fixed"; 94 + regulator-name = "ppvar_sys"; 95 + regulator-always-on; 96 + regulator-boot-on; 97 + }; 98 + 99 + usb_vbus: regulator-5v0-usb-vbus { 100 + compatible = "regulator-fixed"; 101 + regulator-name = "usb-vbus"; 102 + regulator-min-microvolt = <5000000>; 103 + regulator-max-microvolt = <5000000>; 104 + enable-active-high; 105 + regulator-always-on; 106 + }; 107 + }; 108 + 109 + &i2c0 { 110 + status = "okay"; 111 + 112 + clock-frequency = <400000>; 113 + pinctrl-names = "default"; 114 + pinctrl-0 = <&i2c0_pins>; 115 + }; 116 + 117 + &i2c1 { 118 + status = "okay"; 119 + 120 + clock-frequency = <400000>; 121 + i2c-scl-internal-delay-ns = <12500>; 122 + pinctrl-names = "default"; 123 + pinctrl-0 = <&i2c1_pins>; 124 + }; 125 + 126 + &i2c2 { 127 + status = "okay"; 128 + 129 + clock-frequency = <400000>; 130 + pinctrl-names = "default"; 131 + pinctrl-0 = <&i2c2_pins>; 132 + }; 133 + 134 + &i2c3 { 135 + status = "okay"; 136 + 137 + clock-frequency = <400000>; 138 + pinctrl-names = "default"; 139 + pinctrl-0 = <&i2c3_pins>; 140 + }; 141 + 142 + &i2c4 { 143 + status = "okay"; 144 + 145 + clock-frequency = <400000>; 146 + pinctrl-names = "default"; 147 + pinctrl-0 = <&i2c4_pins>; 148 + 149 + ts_10: touchscreen@10 { 150 + compatible = "hid-over-i2c"; 151 + reg = <0x10>; 152 + hid-descr-addr = <0x0001>; 153 + interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 154 + pinctrl-names = "default"; 155 + pinctrl-0 = <&touchscreen_pins>; 156 + post-power-on-delay-ms = <10>; 157 + vdd-supply = <&pp3300_s3>; 158 + status = "disabled"; 159 + }; 160 + }; 161 + 162 + &i2c5 { 163 + status = "okay"; 164 + 165 + clock-frequency = <400000>; 166 + pinctrl-names = "default"; 167 + pinctrl-0 = <&i2c5_pins>; 168 + }; 169 + 170 + &i2c7 { 171 + status = "okay"; 172 + 173 + clock-frequency = <400000>; 174 + pinctrl-names = "default"; 175 + pinctrl-0 = <&i2c7_pins>; 176 + 177 + pmic@34 { 178 + #interrupt-cells = <1>; 179 + compatible = "mediatek,mt6360"; 180 + reg = <0x34>; 181 + interrupt-controller; 182 + interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 183 + interrupt-names = "IRQB"; 184 + pinctrl-names = "default"; 185 + pinctrl-0 = <&subpmic_default>; 186 + wakeup-source; 187 + }; 188 + }; 189 + 190 + &mmc0 { 191 + status = "okay"; 192 + 193 + bus-width = <8>; 194 + cap-mmc-highspeed; 195 + cap-mmc-hw-reset; 196 + hs400-ds-delay = <0x14c11>; 197 + max-frequency = <200000000>; 198 + mmc-hs200-1_8v; 199 + mmc-hs400-1_8v; 200 + no-sdio; 201 + no-sd; 202 + non-removable; 203 + pinctrl-names = "default", "state_uhs"; 204 + pinctrl-0 = <&mmc0_pins_default>; 205 + pinctrl-1 = <&mmc0_pins_uhs>; 206 + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 207 + vqmmc-supply = <&mt6359_vufs_ldo_reg>; 208 + }; 209 + 210 + /* for CPU-L */ 211 + &mt6359_vcore_buck_reg { 212 + regulator-always-on; 213 + }; 214 + 215 + /* for CORE */ 216 + &mt6359_vgpu11_buck_reg { 217 + regulator-always-on; 218 + }; 219 + 220 + &mt6359_vgpu11_sshub_buck_reg { 221 + regulator-always-on; 222 + regulator-min-microvolt = <550000>; 223 + regulator-max-microvolt = <550000>; 224 + }; 225 + 226 + /* for CORE SRAM */ 227 + &mt6359_vpu_buck_reg { 228 + regulator-always-on; 229 + }; 230 + 231 + &mt6359_vrf12_ldo_reg { 232 + regulator-always-on; 233 + }; 234 + 235 + /* for GPU SRAM */ 236 + &mt6359_vsram_others_ldo_reg { 237 + regulator-always-on; 238 + regulator-min-microvolt = <750000>; 239 + regulator-max-microvolt = <750000>; 240 + }; 241 + 242 + &mt6359_vufs_ldo_reg { 243 + regulator-always-on; 244 + }; 245 + 246 + &nor_flash { 247 + status = "okay"; 248 + 249 + pinctrl-names = "default"; 250 + pinctrl-0 = <&nor_pins_default>; 251 + 252 + flash@0 { 253 + compatible = "jedec,spi-nor"; 254 + reg = <0>; 255 + spi-max-frequency = <52000000>; 256 + spi-rx-bus-width = <2>; 257 + spi-tx-bus-width = <2>; 258 + }; 259 + }; 260 + 261 + &pio { 262 + mediatek,rsel-resistance-in-si-unit; 263 + pinctrl-names = "default"; 264 + pinctrl-0 = <&pio_default>; 265 + 266 + /* 144 lines */ 267 + gpio-line-names = 268 + "I2S_SPKR_MCLK", 269 + "I2S_SPKR_DATAIN", 270 + "I2S_SPKR_LRCK", 271 + "I2S_SPKR_BCLK", 272 + "EC_AP_INT_ODL", 273 + /* 274 + * AP_FLASH_WP_L is crossystem ABI. Schematics 275 + * call it AP_FLASH_WP_ODL. 276 + */ 277 + "AP_FLASH_WP_L", 278 + "TCHPAD_INT_ODL", 279 + "EDP_HPD_1V8", 280 + "AP_I2C_CAM_SDA", 281 + "AP_I2C_CAM_SCL", 282 + "AP_I2C_TCHPAD_SDA_1V8", 283 + "AP_I2C_TCHPAD_SCL_1V8", 284 + "AP_I2C_AUD_SDA", 285 + "AP_I2C_AUD_SCL", 286 + "AP_I2C_TPM_SDA_1V8", 287 + "AP_I2C_TPM_SCL_1V8", 288 + "AP_I2C_TCHSCR_SDA_1V8", 289 + "AP_I2C_TCHSCR_SCL_1V8", 290 + "EC_AP_HPD_OD", 291 + "", 292 + "PCIE_NVME_RST_L", 293 + "PCIE_NVME_CLKREQ_ODL", 294 + "PCIE_RST_1V8_L", 295 + "PCIE_CLKREQ_1V8_ODL", 296 + "PCIE_WAKE_1V8_ODL", 297 + "CLK_24M_CAM0", 298 + "CAM1_SEN_EN", 299 + "AP_I2C_PWR_SCL_1V8", 300 + "AP_I2C_PWR_SDA_1V8", 301 + "AP_I2C_MISC_SCL", 302 + "AP_I2C_MISC_SDA", 303 + "EN_PP5000_HDMI_X", 304 + "AP_HDMITX_HTPLG", 305 + "", 306 + "AP_HDMITX_SCL_1V8", 307 + "AP_HDMITX_SDA_1V8", 308 + "AP_RTC_CLK32K", 309 + "AP_EC_WATCHDOG_L", 310 + "SRCLKENA0", 311 + "SRCLKENA1", 312 + "PWRAP_SPI0_CS_L", 313 + "PWRAP_SPI0_CK", 314 + "PWRAP_SPI0_MOSI", 315 + "PWRAP_SPI0_MISO", 316 + "SPMI_SCL", 317 + "SPMI_SDA", 318 + "", 319 + "", 320 + "", 321 + "I2S_HP_DATAIN", 322 + "I2S_HP_MCLK", 323 + "I2S_HP_BCK", 324 + "I2S_HP_LRCK", 325 + "I2S_HP_DATAOUT", 326 + "SD_CD_ODL", 327 + "EN_PP3300_DISP_X", 328 + "TCHSCR_RST_1V8_L", 329 + "TCHSCR_REPORT_DISABLE", 330 + "EN_PP3300_WLAN_X", 331 + "BT_KILL_1V8_L", 332 + "I2S_SPKR_DATAOUT", 333 + "WIFI_KILL_1V8_L", 334 + "BEEP_ON", 335 + "SCP_I2C_SENSOR_SCL_1V8", 336 + "SCP_I2C_SENSOR_SDA_1V8", 337 + "", 338 + "", 339 + "", 340 + "", 341 + "AUD_CLK_MOSI", 342 + "AUD_SYNC_MOSI", 343 + "AUD_DAT_MOSI0", 344 + "AUD_DAT_MOSI1", 345 + "AUD_DAT_MISO0", 346 + "AUD_DAT_MISO1", 347 + "AUD_DAT_MISO2", 348 + "SCP_VREQ_VAO", 349 + "AP_SPI_GSC_TPM_CLK", 350 + "AP_SPI_GSC_TPM_MOSI", 351 + "AP_SPI_GSC_TPM_CS_L", 352 + "AP_SPI_GSC_TPM_MISO", 353 + "EN_PP1000_CAM_X", 354 + "AP_EDP_BKLTEN", 355 + "", 356 + "USB3_HUB_RST_L", 357 + "", 358 + "WLAN_ALERT_ODL", 359 + "EC_IN_RW_ODL", 360 + "GSC_AP_INT_ODL", 361 + "HP_INT_ODL", 362 + "CAM0_RST_L", 363 + "CAM1_RST_L", 364 + "TCHSCR_INT_1V8_L", 365 + "CAM1_DET_L", 366 + "RST_ALC1011_L", 367 + "", 368 + "", 369 + "BL_PWM_1V8", 370 + "UART_AP_TX_DBG_RX", 371 + "UART_DBG_TX_AP_RX", 372 + "EN_SPKR", 373 + "AP_EC_WARM_RST_REQ", 374 + "UART_SCP_TX_DBGCON_RX", 375 + "UART_DBGCON_TX_SCP_RX", 376 + "", 377 + "", 378 + "KPCOL0", 379 + "", 380 + "MT6315_GPU_INT", 381 + "MT6315_PROC_BC_INT", 382 + "SD_CMD", 383 + "SD_CLK", 384 + "SD_DAT0", 385 + "SD_DAT1", 386 + "SD_DAT2", 387 + "SD_DAT3", 388 + "EMMC_DAT7", 389 + "EMMC_DAT6", 390 + "EMMC_DAT5", 391 + "EMMC_DAT4", 392 + "EMMC_RSTB", 393 + "EMMC_CMD", 394 + "EMMC_CLK", 395 + "EMMC_DAT3", 396 + "EMMC_DAT2", 397 + "EMMC_DAT1", 398 + "EMMC_DAT0", 399 + "EMMC_DSL", 400 + "", 401 + "", 402 + "MT6360_INT_ODL", 403 + "SCP_JTAG0_TRSTN", 404 + "AP_SPI_EC_CS_L", 405 + "AP_SPI_EC_CLK", 406 + "AP_SPI_EC_MOSI", 407 + "AP_SPI_EC_MISO", 408 + "SCP_JTAG0_TMS", 409 + "SCP_JTAG0_TCK", 410 + "SCP_JTAG0_TDO", 411 + "SCP_JTAG0_TDI", 412 + "AP_SPI_FLASH_CS_L", 413 + "AP_SPI_FLASH_CLK", 414 + "AP_SPI_FLASH_MOSI", 415 + "AP_SPI_FLASH_MISO"; 416 + 417 + i2c0_pins: i2c0-default-pins { 418 + pins-bus { 419 + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 420 + <PINMUX_GPIO9__FUNC_SCL0>; 421 + bias-disable; 422 + drive-strength-microamp = <1000>; 423 + }; 424 + }; 425 + 426 + i2c1_pins: i2c1-default-pins { 427 + pins-bus { 428 + pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 429 + <PINMUX_GPIO11__FUNC_SCL1>; 430 + bias-pull-up = <1000>; 431 + drive-strength-microamp = <1000>; 432 + }; 433 + }; 434 + 435 + i2c2_pins: i2c2-default-pins { 436 + pins-bus { 437 + pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 438 + <PINMUX_GPIO13__FUNC_SCL2>; 439 + bias-disable; 440 + drive-strength-microamp = <1000>; 441 + }; 442 + }; 443 + 444 + i2c3_pins: i2c3-default-pins { 445 + pins-bus { 446 + pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 447 + <PINMUX_GPIO15__FUNC_SCL3>; 448 + bias-pull-up = <1000>; 449 + drive-strength-microamp = <1000>; 450 + }; 451 + }; 452 + 453 + i2c4_pins: i2c4-default-pins { 454 + pins-bus { 455 + pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 456 + <PINMUX_GPIO17__FUNC_SCL4>; 457 + bias-pull-up = <1000>; 458 + drive-strength = <4>; 459 + }; 460 + }; 461 + 462 + i2c5_pins: i2c5-default-pins { 463 + pins-bus { 464 + pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 465 + <PINMUX_GPIO30__FUNC_SDA5>; 466 + bias-disable; 467 + drive-strength-microamp = <1000>; 468 + }; 469 + }; 470 + 471 + i2c7_pins: i2c7-default-pins { 472 + pins-bus { 473 + pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 474 + <PINMUX_GPIO28__FUNC_SDA7>; 475 + bias-disable; 476 + }; 477 + }; 478 + 479 + mmc0_pins_default: mmc0-default-pins { 480 + pins-cmd-dat { 481 + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 482 + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 483 + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 484 + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 485 + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 486 + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 487 + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 488 + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 489 + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 490 + input-enable; 491 + drive-strength = <6>; 492 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 493 + }; 494 + 495 + pins-clk { 496 + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 497 + drive-strength = <6>; 498 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 499 + }; 500 + 501 + pins-rst { 502 + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 503 + drive-strength = <6>; 504 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 505 + }; 506 + }; 507 + 508 + mmc0_pins_uhs: mmc0-uhs-pins { 509 + pins-cmd-dat { 510 + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 511 + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 512 + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 513 + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 514 + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 515 + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 516 + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 517 + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 518 + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 519 + input-enable; 520 + drive-strength = <8>; 521 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 522 + }; 523 + 524 + pins-clk { 525 + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 526 + drive-strength = <8>; 527 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 528 + }; 529 + 530 + pins-ds { 531 + pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 532 + drive-strength = <8>; 533 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 534 + }; 535 + 536 + pins-rst { 537 + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 538 + drive-strength = <8>; 539 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 540 + }; 541 + }; 542 + 543 + nor_pins_default: nor-default-pins { 544 + pins-ck-io { 545 + pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 546 + <PINMUX_GPIO141__FUNC_SPINOR_CK>, 547 + <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 548 + drive-strength = <6>; 549 + bias-pull-down; 550 + }; 551 + 552 + pins-cs { 553 + pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 554 + drive-strength = <6>; 555 + bias-pull-up; 556 + }; 557 + }; 558 + 559 + pio_default: pio-default-pins { 560 + pins-wifi-enable { 561 + pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 562 + output-high; 563 + drive-strength = <14>; 564 + }; 565 + 566 + pins-low-power-pd { 567 + pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 568 + <PINMUX_GPIO26__FUNC_GPIO26>, 569 + <PINMUX_GPIO46__FUNC_GPIO46>, 570 + <PINMUX_GPIO47__FUNC_GPIO47>, 571 + <PINMUX_GPIO48__FUNC_GPIO48>, 572 + <PINMUX_GPIO65__FUNC_GPIO65>, 573 + <PINMUX_GPIO66__FUNC_GPIO66>, 574 + <PINMUX_GPIO67__FUNC_GPIO67>, 575 + <PINMUX_GPIO68__FUNC_GPIO68>, 576 + <PINMUX_GPIO128__FUNC_GPIO128>, 577 + <PINMUX_GPIO129__FUNC_GPIO129>; 578 + input-enable; 579 + bias-pull-down; 580 + }; 581 + 582 + pins-low-power-pupd { 583 + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 584 + <PINMUX_GPIO78__FUNC_GPIO78>, 585 + <PINMUX_GPIO79__FUNC_GPIO79>, 586 + <PINMUX_GPIO80__FUNC_GPIO80>, 587 + <PINMUX_GPIO83__FUNC_GPIO83>, 588 + <PINMUX_GPIO85__FUNC_GPIO85>, 589 + <PINMUX_GPIO90__FUNC_GPIO90>, 590 + <PINMUX_GPIO91__FUNC_GPIO91>, 591 + <PINMUX_GPIO93__FUNC_GPIO93>, 592 + <PINMUX_GPIO94__FUNC_GPIO94>, 593 + <PINMUX_GPIO95__FUNC_GPIO95>, 594 + <PINMUX_GPIO96__FUNC_GPIO96>, 595 + <PINMUX_GPIO104__FUNC_GPIO104>, 596 + <PINMUX_GPIO105__FUNC_GPIO105>, 597 + <PINMUX_GPIO107__FUNC_GPIO107>; 598 + input-enable; 599 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 600 + }; 601 + }; 602 + 603 + spi0_pins: spi0-default-pins { 604 + pins-cs-mosi-clk { 605 + pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 606 + <PINMUX_GPIO134__FUNC_SPIM0_MO>, 607 + <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 608 + bias-disable; 609 + }; 610 + 611 + pins-miso { 612 + pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 613 + bias-pull-down; 614 + }; 615 + }; 616 + 617 + subpmic_default: subpmic-default-pins { 618 + subpmic_pin_irq: pins-subpmic-int-n { 619 + pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 620 + input-enable; 621 + bias-pull-up; 622 + }; 623 + }; 624 + 625 + touchscreen_pins: touchscreen-default-pins { 626 + pins-int-n { 627 + pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 628 + input-enable; 629 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 630 + }; 631 + pins-rst { 632 + pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 633 + output-high; 634 + }; 635 + pins-report-sw { 636 + pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 637 + output-low; 638 + }; 639 + }; 640 + }; 641 + 642 + &pmic { 643 + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 644 + }; 645 + 646 + &spi0 { 647 + status = "okay"; 648 + 649 + pinctrl-names = "default"; 650 + pinctrl-0 = <&spi0_pins>; 651 + mediatek,pad-select = <0>; 652 + }; 653 + 654 + &u3phy0 { 655 + status = "okay"; 656 + }; 657 + 658 + &u3phy1 { 659 + status = "okay"; 660 + }; 661 + 662 + &u3phy2 { 663 + status = "okay"; 664 + }; 665 + 666 + &u3phy3 { 667 + status = "okay"; 668 + }; 669 + 670 + &uart0 { 671 + status = "okay"; 672 + }; 673 + 674 + &xhci0 { 675 + status = "okay"; 676 + 677 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 678 + vbus-supply = <&usb_vbus>; 679 + }; 680 + 681 + &xhci1 { 682 + status = "okay"; 683 + 684 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 685 + vbus-supply = <&usb_vbus>; 686 + }; 687 + 688 + &xhci2 { 689 + status = "okay"; 690 + 691 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 692 + vbus-supply = <&usb_vbus>; 693 + }; 694 + 695 + &xhci3 { 696 + status = "okay"; 697 + 698 + /* MT7921's USB Bluetooth has issues with USB2 LPM */ 699 + usb2-lpm-disable; 700 + vusb33-supply = <&mt6359_vusb_ldo_reg>; 701 + vbus-supply = <&usb_vbus>; 702 + };

+4 -4

arch/arm64/boot/dts/mediatek/mt8195-evb.dts

··· 139 139 }; 140 140 141 141 &u3phy0 { 142 - status="okay"; 142 + status = "okay"; 143 143 }; 144 144 145 145 &u3phy1 { 146 - status="okay"; 146 + status = "okay"; 147 147 }; 148 148 149 149 &u3phy2 { 150 - status="okay"; 150 + status = "okay"; 151 151 }; 152 152 153 153 &u3phy3 { 154 - status="okay"; 154 + status = "okay"; 155 155 }; 156 156 157 157 &uart0 {

+64 -12

arch/arm64/boot/dts/mediatek/mt8195.dtsi

··· 10 10 #include <dt-bindings/interrupt-controller/irq.h> 11 11 #include <dt-bindings/phy/phy.h> 12 12 #include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13 - #include <dt-bindings/reset/ti-syscon.h> 14 13 15 14 / { 16 15 compatible = "mediatek,mt8195"; ··· 294 295 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 295 296 reg = <0 0x10001000 0 0x1000>; 296 297 #clock-cells = <1>; 297 - 298 - infracfg_rst: reset-controller { 299 - compatible = "ti,syscon-reset"; 300 - #reset-cells = <1>; 301 - ti,reset-bits = < 302 - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ 303 - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ 304 - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ 305 - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ 306 - >; 307 - }; 298 + #reset-cells = <1>; 308 299 }; 309 300 310 301 pericfg: syscon@10003000 { ··· 562 573 <&apmixedsys CLK_APMIXED_USB1PLL>, 563 574 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 564 575 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 576 + mediatek,syscon-wakeup = <&pericfg 0x400 103>; 577 + wakeup-source; 565 578 status = "disabled"; 566 579 }; 567 580 ··· 627 636 <&apmixedsys CLK_APMIXED_USB1PLL>, 628 637 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 629 638 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 639 + mediatek,syscon-wakeup = <&pericfg 0x400 104>; 640 + wakeup-source; 630 641 status = "disabled"; 631 642 }; 632 643 ··· 648 655 <&topckgen CLK_TOP_SSUSB_P2_REF>, 649 656 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 650 657 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 658 + mediatek,syscon-wakeup = <&pericfg 0x400 105>; 659 + wakeup-source; 651 660 status = "disabled"; 652 661 }; 653 662 ··· 669 674 <&topckgen CLK_TOP_SSUSB_P3_REF>, 670 675 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 671 676 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 677 + mediatek,syscon-wakeup = <&pericfg 0x400 106>; 678 + wakeup-source; 672 679 status = "disabled"; 673 680 }; 674 681 ··· 686 689 #address-cells = <1>; 687 690 #size-cells = <0>; 688 691 status = "disabled"; 692 + }; 693 + 694 + efuse: efuse@11c10000 { 695 + compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 696 + reg = <0 0x11c10000 0 0x1000>; 697 + #address-cells = <1>; 698 + #size-cells = <1>; 699 + u3_tx_imp_p0: usb3-tx-imp@184,1 { 700 + reg = <0x184 0x1>; 701 + bits = <0 5>; 702 + }; 703 + u3_rx_imp_p0: usb3-rx-imp@184,2 { 704 + reg = <0x184 0x2>; 705 + bits = <5 5>; 706 + }; 707 + u3_intr_p0: usb3-intr@185 { 708 + reg = <0x185 0x1>; 709 + bits = <2 6>; 710 + }; 711 + comb_tx_imp_p1: usb3-tx-imp@186,1 { 712 + reg = <0x186 0x1>; 713 + bits = <0 5>; 714 + }; 715 + comb_rx_imp_p1: usb3-rx-imp@186,2 { 716 + reg = <0x186 0x2>; 717 + bits = <5 5>; 718 + }; 719 + comb_intr_p1: usb3-intr@187 { 720 + reg = <0x187 0x1>; 721 + bits = <2 6>; 722 + }; 723 + u2_intr_p0: usb2-intr-p0@188,1 { 724 + reg = <0x188 0x1>; 725 + bits = <0 5>; 726 + }; 727 + u2_intr_p1: usb2-intr-p1@188,2 { 728 + reg = <0x188 0x2>; 729 + bits = <5 5>; 730 + }; 731 + u2_intr_p2: usb2-intr-p2@189,1 { 732 + reg = <0x189 0x1>; 733 + bits = <2 5>; 734 + }; 735 + u2_intr_p3: usb2-intr-p3@189,2 { 736 + reg = <0x189 0x2>; 737 + bits = <7 5>; 738 + }; 689 739 }; 690 740 691 741 u3phy2: t-phy@11c40000 { ··· 917 873 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 918 874 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 919 875 clock-names = "ref", "da_ref"; 876 + nvmem-cells = <&comb_intr_p1>, 877 + <&comb_rx_imp_p1>, 878 + <&comb_tx_imp_p1>; 879 + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 920 880 #phy-cells = <1>; 921 881 }; 922 882 }; ··· 945 897 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 946 898 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 947 899 clock-names = "ref", "da_ref"; 900 + nvmem-cells = <&u3_intr_p0>, 901 + <&u3_rx_imp_p0>, 902 + <&u3_tx_imp_p0>; 903 + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 948 904 #phy-cells = <1>; 949 905 }; 950 906 };

+2 -2

arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi

··· 28 28 pinctrl-names = "default"; 29 29 pinctrl-0 = <&gpio_keys_default>; 30 30 31 - volume-up { 31 + key-volume-up { 32 32 gpios = <&pio 42 GPIO_ACTIVE_LOW>; 33 33 label = "volume_up"; 34 34 linux,code = <115>; ··· 36 36 debounce-interval = <15>; 37 37 }; 38 38 39 - volume-down { 39 + key-volume-down { 40 40 gpios = <&pio 43 GPIO_ACTIVE_LOW>; 41 41 label = "volume_down"; 42 42 linux,code = <114>;

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