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dt-bindings: dma: rz-dmac: Document clock-names and reset-names

Document clock-names and reset-names properties as we have multiple
clocks and resets.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230315064726.22739-1-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Biju Das and committed by
Vinod Koul
5aaf9079 d1e71a3a

+14
+14
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
··· 54 54 - description: DMA main clock 55 55 - description: DMA register access clock 56 56 57 + clock-names: 58 + items: 59 + - const: main 60 + - const: register 61 + 57 62 '#dma-cells': 58 63 const: 1 59 64 description: ··· 82 77 - description: Reset for DMA ARESETN reset terminal 83 78 - description: Reset for DMA RST_ASYNC reset terminal 84 79 80 + reset-names: 81 + items: 82 + - const: arst 83 + - const: rst_async 84 + 85 85 required: 86 86 - compatible 87 87 - reg 88 88 - interrupts 89 89 - interrupt-names 90 90 - clocks 91 + - clock-names 91 92 - '#dma-cells' 92 93 - dma-channels 93 94 - power-domains 94 95 - resets 96 + - reset-names 95 97 96 98 additionalProperties: false 97 99 ··· 136 124 "ch12", "ch13", "ch14", "ch15"; 137 125 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 138 126 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 127 + clock-names = "main", "register"; 139 128 power-domains = <&cpg>; 140 129 resets = <&cpg R9A07G044_DMAC_ARESETN>, 141 130 <&cpg R9A07G044_DMAC_RST_ASYNC>; 131 + reset-names = "arst", "rst_async"; 142 132 #dma-cells = <1>; 143 133 dma-channels = <16>; 144 134 };