Merge tag 'fpga-for-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next

Xu writes:

FPGA Manager changes for 6.17-rc1

- Matthew hands over the maintainership of Intel MAX10 BMC secure
update to Yilun.

- Fabio adds missing spi_device_id table for xilinx-spi

- Dihn updates link for Altera & AMD's dt-bindings.

- Andy uses pci_find_vsec_capability() instead of open-codes for
altera-cvp.

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: Xu Yilun <yilun.xu@intel.com>

* tag 'fpga-for-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
fpga: altera-cvp: Use pci_find_vsec_capability() when probing FPGA device
dt-bindings: fpga: update link for Altera's and AMD partial recon
fpga: xilinx-spi: Add missing spi_device_id table
MAINTAINERS: change maintainer for Intel MAX10 BMC secure updates

Greg Kroah-Hartman 6 months ago 5abeedad 41289b48

+15 -18

4 changed files

expand all

Documentation

devicetree

bindings

fpga

fpga-region.yaml

MAINTAINERS

drivers

fpga

altera-cvp.c

xilinx-spi.c

+2 -2

Documentation/devicetree/bindings/fpga/fpga-region.yaml

··· 215 215 FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. 216 216 217 217 -- 218 - [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf 218 + [1] https://www.intel.com/programmable/technical-pdfs/683404.pdf 219 219 [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf 220 - [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf 220 + [3] https://docs.amd.com/v/u/en-US/ug702 221 221 222 222 properties: 223 223 $nodename:

+1 -1

MAINTAINERS

··· 12741 12741 F: include/linux/mfd/intel-m10-bmc.h 12742 12742 12743 12743 INTEL MAX10 BMC SECURE UPDATES 12744 - M: Matthew Gerlach <matthew.gerlach@altera.com> 12744 + M: Xu Yilun <yilun.xu@intel.com> 12745 12745 L: linux-fpga@vger.kernel.org 12746 12746 S: Maintained 12747 12747 F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update

+5 -15

drivers/fpga/altera-cvp.c

··· 22 22 #define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */ 23 23 24 24 /* Vendor Specific Extended Capability Registers */ 25 - #define VSE_PCIE_EXT_CAP_ID 0x0 26 - #define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */ 27 - 28 25 #define VSE_CVP_STATUS 0x1c /* 32bit */ 29 26 #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */ 30 27 #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */ ··· 574 577 { 575 578 struct altera_cvp_conf *conf; 576 579 struct fpga_manager *mgr; 577 - int ret, offset; 578 - u16 cmd, val; 580 + u16 cmd, offset; 579 581 u32 regval; 580 - 581 - /* Discover the Vendor Specific Offset for this device */ 582 - offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR); 583 - if (!offset) { 584 - dev_err(&pdev->dev, "No Vendor Specific Offset.\n"); 585 - return -ENODEV; 586 - } 582 + int ret; 587 583 588 584 /* 589 585 * First check if this is the expected FPGA device. PCI config 590 586 * space access works without enabling the PCI device, memory 591 587 * space access is enabled further down. 592 588 */ 593 - pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val); 594 - if (val != VSE_PCIE_EXT_CAP_ID_VAL) { 595 - dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val); 589 + offset = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALTERA, 0x1172); 590 + if (!offset) { 591 + dev_err(&pdev->dev, "Wrong VSEC ID value\n"); 596 592 return -ENODEV; 597 593 } 598 594

drivers/fpga/xilinx-spi.c

··· 57 57 return xilinx_core_probe(core); 58 58 } 59 59 60 + static const struct spi_device_id xilinx_spi_ids[] = { 61 + { "fpga-slave-serial" }, 62 + { }, 63 + }; 64 + MODULE_DEVICE_TABLE(spi, xilinx_spi_ids); 65 + 60 66 #ifdef CONFIG_OF 61 67 static const struct of_device_id xlnx_spi_of_match[] = { 62 68 { ··· 79 73 .of_match_table = of_match_ptr(xlnx_spi_of_match), 80 74 }, 81 75 .probe = xilinx_spi_probe, 76 + .id_table = xilinx_spi_ids, 82 77 }; 83 78 84 79 module_spi_driver(xilinx_slave_spi_driver)

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