Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'net-6.11-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Pull networking fixes from Paolo Abeni:
"Including fixes from netfilter.
There is a recently notified BT regression with no fix yet. I do not
think a fix will land in the next week.
Current release - regressions:
- core: tighten bad gso csum offset check in virtio_net_hdr
- netfilter: move nf flowtable bpf initialization in
nf_flow_table_module_init()
- eth: ice: stop calling pci_disable_device() as we use pcim
- eth: fou: fix null-ptr-deref in GRO.
Current release - new code bugs:
- hsr: prevent NULL pointer dereference in hsr_proxy_announce()
Previous releases - regressions:
- hsr: remove seqnr_lock
- netfilter: nft_socket: fix sk refcount leaks
- mptcp: pm: fix uaf in __timer_delete_sync
- phy: dp83822: fix NULL pointer dereference on DP83825 devices
- eth: revert "virtio_net: rx enable premapped mode by default"
- eth: octeontx2-af: Modify SMQ flush sequence to drop packets
Previous releases - always broken:
- eth: mlx5: fix bridge mode operations when there are no VFs
- eth: igb: Always call igb_xdp_ring_update_tail() under Tx lock"
* tag 'net-6.11-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (36 commits)
net: netfilter: move nf flowtable bpf initialization in nf_flow_table_module_init()
net: tighten bad gso csum offset check in virtio_net_hdr
netlink: specs: mptcp: fix port endianness
net: dpaa: Pad packets to ETH_ZLEN
mptcp: pm: Fix uaf in __timer_delete_sync
net: libwx: fix number of Rx and Tx descriptors
net: dsa: felix: ignore pending status of TAS module when it's disabled
net: hsr: prevent NULL pointer dereference in hsr_proxy_announce()
selftests: mptcp: include net_helper.sh file
selftests: mptcp: include lib.sh file
selftests: mptcp: join: restrict fullmesh endp on 1st sf
netfilter: nft_socket: make cgroupsv2 matching work with namespaces
netfilter: nft_socket: fix sk refcount leaks
MAINTAINERS: Add ethtool pse-pd to PSE NETWORK DRIVER
dt-bindings: net: tja11xx: fix the broken binding
selftests: net: csum: Fix checksums for packets with non-zero padding
net: phy: dp83822: Fix NULL pointer dereference on DP83825 devices
virtio_net: disable premapped mode by default
Revert "virtio_net: big mode skip the unmap check"
Revert "virtio_net: rx remove premapped failover code"
...
+366
-192
+46
-16
Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
+46
-16
Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
···
14
14
description:
15
15
Bindings for NXP TJA11xx automotive PHYs
16
16
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- ethernet-phy-id0180.dc40
21
+
- ethernet-phy-id0180.dc41
22
+
- ethernet-phy-id0180.dc48
23
+
- ethernet-phy-id0180.dd00
24
+
- ethernet-phy-id0180.dd01
25
+
- ethernet-phy-id0180.dd02
26
+
- ethernet-phy-id0180.dc80
27
+
- ethernet-phy-id0180.dc82
28
+
- ethernet-phy-id001b.b010
29
+
- ethernet-phy-id001b.b013
30
+
- ethernet-phy-id001b.b030
31
+
- ethernet-phy-id001b.b031
32
+
17
33
allOf:
18
34
- $ref: ethernet-phy.yaml#
35
+
- if:
36
+
properties:
37
+
compatible:
38
+
contains:
39
+
enum:
40
+
- ethernet-phy-id0180.dc40
41
+
- ethernet-phy-id0180.dc41
42
+
- ethernet-phy-id0180.dc48
43
+
- ethernet-phy-id0180.dd00
44
+
- ethernet-phy-id0180.dd01
45
+
- ethernet-phy-id0180.dd02
46
+
47
+
then:
48
+
properties:
49
+
nxp,rmii-refclk-in:
50
+
type: boolean
51
+
description: |
52
+
The REF_CLK is provided for both transmitted and received data
53
+
in RMII mode. This clock signal is provided by the PHY and is
54
+
typically derived from an external 25MHz crystal. Alternatively,
55
+
a 50MHz clock signal generated by an external oscillator can be
56
+
connected to pin REF_CLK. A third option is to connect a 25MHz
57
+
clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
58
+
as input or output according to the actual circuit connection.
59
+
If present, indicates that the REF_CLK will be configured as
60
+
interface reference clock input when RMII mode enabled.
61
+
If not present, the REF_CLK will be configured as interface
62
+
reference clock output when RMII mode enabled.
63
+
Only supported on TJA1100 and TJA1101.
19
64
20
65
patternProperties:
21
66
"^ethernet-phy@[0-9a-f]+$":
···
77
32
description:
78
33
The ID number for the child PHY. Should be +1 of parent PHY.
79
34
80
-
nxp,rmii-refclk-in:
81
-
type: boolean
82
-
description: |
83
-
The REF_CLK is provided for both transmitted and received data
84
-
in RMII mode. This clock signal is provided by the PHY and is
85
-
typically derived from an external 25MHz crystal. Alternatively,
86
-
a 50MHz clock signal generated by an external oscillator can be
87
-
connected to pin REF_CLK. A third option is to connect a 25MHz
88
-
clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
89
-
as input or output according to the actual circuit connection.
90
-
If present, indicates that the REF_CLK will be configured as
91
-
interface reference clock input when RMII mode enabled.
92
-
If not present, the REF_CLK will be configured as interface
93
-
reference clock output when RMII mode enabled.
94
-
Only supported on TJA1100 and TJA1101.
95
-
96
35
required:
97
36
- reg
98
37
···
89
60
#size-cells = <0>;
90
61
91
62
tja1101_phy0: ethernet-phy@4 {
63
+
compatible = "ethernet-phy-id0180.dc40";
92
64
reg = <0x4>;
93
65
nxp,rmii-refclk-in;
94
66
};
-1
Documentation/netlink/specs/mptcp_pm.yaml
-1
Documentation/netlink/specs/mptcp_pm.yaml
+1
MAINTAINERS
+1
MAINTAINERS
+7
-4
drivers/net/dsa/ocelot/felix_vsc9959.c
+7
-4
drivers/net/dsa/ocelot/felix_vsc9959.c
···
1474
1474
/* Hardware errata - Admin config could not be overwritten if
1475
1475
* config is pending, need reset the TAS module
1476
1476
*/
1477
-
val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1478
-
if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1479
-
ret = -EBUSY;
1480
-
goto err_reset_tc;
1477
+
val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
1478
+
if (val & QSYS_TAG_CONFIG_ENABLE) {
1479
+
val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1480
+
if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1481
+
ret = -EBUSY;
1482
+
goto err_reset_tc;
1483
+
}
1481
1484
}
1482
1485
1483
1486
ocelot_rmw_rix(ocelot,
+1
-1
drivers/net/ethernet/faraday/ftgmac100.h
+1
-1
drivers/net/ethernet/faraday/ftgmac100.h
+8
-1
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+8
-1
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
···
2272
2272
dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2273
2273
{
2274
2274
const int queue_mapping = skb_get_queue_mapping(skb);
2275
-
bool nonlinear = skb_is_nonlinear(skb);
2276
2275
struct rtnl_link_stats64 *percpu_stats;
2277
2276
struct dpaa_percpu_priv *percpu_priv;
2278
2277
struct netdev_queue *txq;
2279
2278
struct dpaa_priv *priv;
2280
2279
struct qm_fd fd;
2280
+
bool nonlinear;
2281
2281
int offset = 0;
2282
2282
int err = 0;
2283
2283
···
2287
2287
2288
2288
qm_fd_clear_fd(&fd);
2289
2289
2290
+
/* Packet data is always read as 32-bit words, so zero out any part of
2291
+
* the skb which might be sent if we have to pad the packet
2292
+
*/
2293
+
if (__skb_put_padto(skb, ETH_ZLEN, false))
2294
+
goto enomem;
2295
+
2296
+
nonlinear = skb_is_nonlinear(skb);
2290
2297
if (!nonlinear) {
2291
2298
/* We're going to store the skb backpointer at the beginning
2292
2299
* of the data buffer, so we need a privately owned skb
+8
-7
drivers/net/ethernet/intel/ice/ice_lib.c
+8
-7
drivers/net/ethernet/intel/ice/ice_lib.c
···
2413
2413
struct ice_pf *pf = vsi->back;
2414
2414
int err;
2415
2415
2416
-
/* The Rx rule will only exist to remove if the LLDP FW
2417
-
* engine is currently stopped
2418
-
*/
2419
-
if (!ice_is_safe_mode(pf) && vsi->type == ICE_VSI_PF &&
2420
-
!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
2421
-
ice_cfg_sw_lldp(vsi, false, false);
2422
-
2423
2416
ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
2424
2417
err = ice_rm_vsi_rdma_cfg(vsi->port_info, vsi->idx);
2425
2418
if (err)
···
2757
2764
ice_rss_clean(vsi);
2758
2765
2759
2766
ice_vsi_close(vsi);
2767
+
2768
+
/* The Rx rule will only exist to remove if the LLDP FW
2769
+
* engine is currently stopped
2770
+
*/
2771
+
if (!ice_is_safe_mode(pf) && vsi->type == ICE_VSI_PF &&
2772
+
!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
2773
+
ice_cfg_sw_lldp(vsi, false, false);
2774
+
2760
2775
ice_vsi_decfg(vsi);
2761
2776
2762
2777
/* retain SW VSI data structure since it is needed to unregister and
-2
drivers/net/ethernet/intel/ice/ice_main.c
-2
drivers/net/ethernet/intel/ice/ice_main.c
···
5363
5363
ice_deinit(pf);
5364
5364
err_init:
5365
5365
ice_adapter_put(pdev);
5366
-
pci_disable_device(pdev);
5367
5366
return err;
5368
5367
}
5369
5368
···
5469
5470
ice_set_wake(pf);
5470
5471
5471
5472
ice_adapter_put(pdev);
5472
-
pci_disable_device(pdev);
5473
5473
}
5474
5474
5475
5475
/**
+2
-2
drivers/net/ethernet/intel/ice/ice_switch.c
+2
-2
drivers/net/ethernet/intel/ice/ice_switch.c
···
3194
3194
3195
3195
/* A rule already exists with the new VSI being added */
3196
3196
if (test_bit(vsi_handle, m_entry->vsi_list_info->vsi_map))
3197
-
return 0;
3197
+
return -EEXIST;
3198
3198
3199
3199
/* Update the previously created VSI list set with
3200
3200
* the new VSI ID passed in
···
3264
3264
3265
3265
list_head = &sw->recp_list[recp_id].filt_rules;
3266
3266
list_for_each_entry(list_itr, list_head, list_entry) {
3267
-
if (list_itr->vsi_list_info) {
3267
+
if (list_itr->vsi_count == 1 && list_itr->vsi_list_info) {
3268
3268
map_info = list_itr->vsi_list_info;
3269
3269
if (test_bit(vsi_handle, map_info->vsi_map)) {
3270
3270
*vsi_list_id = map_info->vsi_list_id;
+13
-4
drivers/net/ethernet/intel/igb/igb_main.c
+13
-4
drivers/net/ethernet/intel/igb/igb_main.c
···
33
33
#include <linux/bpf_trace.h>
34
34
#include <linux/pm_runtime.h>
35
35
#include <linux/etherdevice.h>
36
+
#include <linux/lockdep.h>
36
37
#ifdef CONFIG_IGB_DCA
37
38
#include <linux/dca.h>
38
39
#endif
···
2915
2914
}
2916
2915
}
2917
2916
2917
+
/* This function assumes __netif_tx_lock is held by the caller. */
2918
2918
static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2919
2919
{
2920
+
lockdep_assert_held(&txring_txq(ring)->_xmit_lock);
2921
+
2920
2922
/* Force memory writes to complete before letting h/w know there
2921
2923
* are new descriptors to fetch.
2922
2924
*/
···
3004
3000
nxmit++;
3005
3001
}
3006
3002
3007
-
__netif_tx_unlock(nq);
3008
-
3009
3003
if (unlikely(flags & XDP_XMIT_FLUSH))
3010
3004
igb_xdp_ring_update_tail(tx_ring);
3005
+
3006
+
__netif_tx_unlock(nq);
3011
3007
3012
3008
return nxmit;
3013
3009
}
···
8868
8864
8869
8865
static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8870
8866
{
8867
+
unsigned int total_bytes = 0, total_packets = 0;
8871
8868
struct igb_adapter *adapter = q_vector->adapter;
8872
8869
struct igb_ring *rx_ring = q_vector->rx.ring;
8873
-
struct sk_buff *skb = rx_ring->skb;
8874
-
unsigned int total_bytes = 0, total_packets = 0;
8875
8870
u16 cleaned_count = igb_desc_unused(rx_ring);
8871
+
struct sk_buff *skb = rx_ring->skb;
8872
+
int cpu = smp_processor_id();
8876
8873
unsigned int xdp_xmit = 0;
8874
+
struct netdev_queue *nq;
8877
8875
struct xdp_buff xdp;
8878
8876
u32 frame_sz = 0;
8879
8877
int rx_buf_pgcnt;
···
9003
8997
if (xdp_xmit & IGB_XDP_TX) {
9004
8998
struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
9005
8999
9000
+
nq = txring_txq(tx_ring);
9001
+
__netif_tx_lock(nq, cpu);
9006
9002
igb_xdp_ring_update_tail(tx_ring);
9003
+
__netif_tx_unlock(nq);
9007
9004
}
9008
9005
9009
9006
u64_stats_update_begin(&rx_ring->rx_syncp);
+1
-2
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+1
-2
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
···
319
319
320
320
/* smq(flush) to tl1 cir/pir info */
321
321
struct nix_smq_tree_ctx {
322
+
u16 schq;
322
323
u64 cir_off;
323
324
u64 cir_val;
324
325
u64 pir_off;
···
329
328
/* smq flush context */
330
329
struct nix_smq_flush_ctx {
331
330
int smq;
332
-
u16 tl1_schq;
333
-
u16 tl2_schq;
334
331
struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
335
332
};
336
333
+47
-12
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+47
-12
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
···
2259
2259
schq = smq;
2260
2260
for (lvl = NIX_TXSCH_LVL_SMQ; lvl <= NIX_TXSCH_LVL_TL1; lvl++) {
2261
2261
smq_tree_ctx = &smq_flush_ctx->smq_tree_ctx[lvl];
2262
+
smq_tree_ctx->schq = schq;
2262
2263
if (lvl == NIX_TXSCH_LVL_TL1) {
2263
-
smq_flush_ctx->tl1_schq = schq;
2264
2264
smq_tree_ctx->cir_off = NIX_AF_TL1X_CIR(schq);
2265
2265
smq_tree_ctx->pir_off = 0;
2266
2266
smq_tree_ctx->pir_val = 0;
2267
2267
parent_off = 0;
2268
2268
} else if (lvl == NIX_TXSCH_LVL_TL2) {
2269
-
smq_flush_ctx->tl2_schq = schq;
2270
2269
smq_tree_ctx->cir_off = NIX_AF_TL2X_CIR(schq);
2271
2270
smq_tree_ctx->pir_off = NIX_AF_TL2X_PIR(schq);
2272
2271
parent_off = NIX_AF_TL2X_PARENT(schq);
···
2300
2301
{
2301
2302
struct nix_txsch *txsch;
2302
2303
struct nix_hw *nix_hw;
2304
+
int tl2, tl2_schq;
2303
2305
u64 regoff;
2304
-
int tl2;
2305
2306
2306
2307
nix_hw = get_nix_hw(rvu->hw, blkaddr);
2307
2308
if (!nix_hw)
···
2309
2310
2310
2311
/* loop through all TL2s with matching PF_FUNC */
2311
2312
txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
2313
+
tl2_schq = smq_flush_ctx->smq_tree_ctx[NIX_TXSCH_LVL_TL2].schq;
2312
2314
for (tl2 = 0; tl2 < txsch->schq.max; tl2++) {
2313
2315
/* skip the smq(flush) TL2 */
2314
-
if (tl2 == smq_flush_ctx->tl2_schq)
2316
+
if (tl2 == tl2_schq)
2315
2317
continue;
2316
2318
/* skip unused TL2s */
2317
2319
if (TXSCH_MAP_FLAGS(txsch->pfvf_map[tl2]) & NIX_TXSCHQ_FREE)
2318
2320
continue;
2319
2321
/* skip if PF_FUNC doesn't match */
2320
2322
if ((TXSCH_MAP_FUNC(txsch->pfvf_map[tl2]) & ~RVU_PFVF_FUNC_MASK) !=
2321
-
(TXSCH_MAP_FUNC(txsch->pfvf_map[smq_flush_ctx->tl2_schq] &
2323
+
(TXSCH_MAP_FUNC(txsch->pfvf_map[tl2_schq] &
2322
2324
~RVU_PFVF_FUNC_MASK)))
2323
2325
continue;
2324
2326
/* enable/disable XOFF */
···
2361
2361
int smq, u16 pcifunc, int nixlf)
2362
2362
{
2363
2363
struct nix_smq_flush_ctx *smq_flush_ctx;
2364
+
int err, restore_tx_en = 0, i;
2364
2365
int pf = rvu_get_pf(pcifunc);
2365
2366
u8 cgx_id = 0, lmac_id = 0;
2366
-
int err, restore_tx_en = 0;
2367
-
u64 cfg;
2367
+
u16 tl2_tl3_link_schq;
2368
+
u8 link, link_level;
2369
+
u64 cfg, bmap = 0;
2368
2370
2369
2371
if (!is_rvu_otx2(rvu)) {
2370
2372
/* Skip SMQ flush if pkt count is zero */
···
2390
2388
nix_smq_flush_enadis_xoff(rvu, blkaddr, smq_flush_ctx, true);
2391
2389
nix_smq_flush_enadis_rate(rvu, blkaddr, smq_flush_ctx, false);
2392
2390
2393
-
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2394
-
/* Do SMQ flush and set enqueue xoff */
2395
-
cfg |= BIT_ULL(50) | BIT_ULL(49);
2396
-
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2397
-
2398
2391
/* Disable backpressure from physical link,
2399
2392
* otherwise SMQ flush may stall.
2400
2393
*/
2401
2394
rvu_cgx_enadis_rx_bp(rvu, pf, false);
2395
+
2396
+
link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?
2397
+
NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2;
2398
+
tl2_tl3_link_schq = smq_flush_ctx->smq_tree_ctx[link_level].schq;
2399
+
link = smq_flush_ctx->smq_tree_ctx[NIX_TXSCH_LVL_TL1].schq;
2400
+
2401
+
/* SMQ set enqueue xoff */
2402
+
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2403
+
cfg |= BIT_ULL(50);
2404
+
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2405
+
2406
+
/* Clear all NIX_AF_TL3_TL2_LINK_CFG[ENA] for the TL3/TL2 queue */
2407
+
for (i = 0; i < (rvu->hw->cgx_links + rvu->hw->lbk_links); i++) {
2408
+
cfg = rvu_read64(rvu, blkaddr,
2409
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link));
2410
+
if (!(cfg & BIT_ULL(12)))
2411
+
continue;
2412
+
bmap |= (1 << i);
2413
+
cfg &= ~BIT_ULL(12);
2414
+
rvu_write64(rvu, blkaddr,
2415
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link), cfg);
2416
+
}
2417
+
2418
+
/* Do SMQ flush and set enqueue xoff */
2419
+
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2420
+
cfg |= BIT_ULL(50) | BIT_ULL(49);
2421
+
rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2402
2422
2403
2423
/* Wait for flush to complete */
2404
2424
err = rvu_poll_reg(rvu, blkaddr,
···
2429
2405
dev_info(rvu->dev,
2430
2406
"NIXLF%d: SMQ%d flush failed, txlink might be busy\n",
2431
2407
nixlf, smq);
2408
+
2409
+
/* Set NIX_AF_TL3_TL2_LINKX_CFG[ENA] for the TL3/TL2 queue */
2410
+
for (i = 0; i < (rvu->hw->cgx_links + rvu->hw->lbk_links); i++) {
2411
+
if (!(bmap & (1 << i)))
2412
+
continue;
2413
+
cfg = rvu_read64(rvu, blkaddr,
2414
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link));
2415
+
cfg |= BIT_ULL(12);
2416
+
rvu_write64(rvu, blkaddr,
2417
+
NIX_AF_TL3_TL2X_LINKX_CFG(tl2_tl3_link_schq, link), cfg);
2418
+
}
2432
2419
2433
2420
/* clear XOFF on TL2s */
2434
2421
nix_smq_flush_enadis_rate(rvu, blkaddr, smq_flush_ctx, true);
+10
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+10
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
···
139
139
ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
140
140
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
141
141
ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
142
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy,
143
+
ETHTOOL_LINK_MODE_100baseT_Full_BIT);
144
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy,
145
+
ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
142
146
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
143
147
ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
144
148
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
···
208
204
ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
209
205
ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
210
206
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
207
+
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext,
208
+
ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
209
+
ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
210
+
ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
211
+
ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
212
+
ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT);
211
213
MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
212
214
ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
213
215
ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c
+2
-2
drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c
···
319
319
return -EPERM;
320
320
321
321
mutex_lock(&esw->state_lock);
322
-
if (esw->mode != MLX5_ESWITCH_LEGACY) {
322
+
if (esw->mode != MLX5_ESWITCH_LEGACY || !mlx5_esw_is_fdb_created(esw)) {
323
323
err = -EOPNOTSUPP;
324
324
goto out;
325
325
}
···
339
339
if (!mlx5_esw_allowed(esw))
340
340
return -EPERM;
341
341
342
-
if (esw->mode != MLX5_ESWITCH_LEGACY)
342
+
if (esw->mode != MLX5_ESWITCH_LEGACY || !mlx5_esw_is_fdb_created(esw))
343
343
return -EOPNOTSUPP;
344
344
345
345
*setting = esw->fdb_table.legacy.vepa_uplink_rule ? 1 : 0;
+31
-20
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
+31
-20
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
···
312
312
return err;
313
313
}
314
314
315
+
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
316
+
{
317
+
switch (type) {
318
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
319
+
return MLX5_CAP_QOS(dev, esw_element_type) &
320
+
ELEMENT_TYPE_CAP_MASK_TSAR;
321
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
322
+
return MLX5_CAP_QOS(dev, esw_element_type) &
323
+
ELEMENT_TYPE_CAP_MASK_VPORT;
324
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
325
+
return MLX5_CAP_QOS(dev, esw_element_type) &
326
+
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
327
+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
328
+
return MLX5_CAP_QOS(dev, esw_element_type) &
329
+
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
330
+
}
331
+
return false;
332
+
}
333
+
315
334
static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw,
316
335
struct mlx5_vport *vport,
317
336
u32 max_rate, u32 bw_share)
···
341
322
u32 parent_tsar_ix;
342
323
void *vport_elem;
343
324
int err;
325
+
326
+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT))
327
+
return -EOPNOTSUPP;
344
328
345
329
parent_tsar_ix = group ? group->tsar_ix : esw->qos.root_tsar_ix;
346
330
MLX5_SET(scheduling_context, sched_ctx, element_type,
···
443
421
{
444
422
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
445
423
struct mlx5_esw_rate_group *group;
424
+
__be32 *attr;
446
425
u32 divider;
447
426
int err;
448
427
449
428
group = kzalloc(sizeof(*group), GFP_KERNEL);
450
429
if (!group)
451
430
return ERR_PTR(-ENOMEM);
431
+
432
+
MLX5_SET(scheduling_context, tsar_ctx, element_type,
433
+
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
434
+
435
+
attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);
436
+
*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);
452
437
453
438
MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,
454
439
esw->qos.root_tsar_ix);
···
555
526
return err;
556
527
}
557
528
558
-
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
559
-
{
560
-
switch (type) {
561
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
562
-
return MLX5_CAP_QOS(dev, esw_element_type) &
563
-
ELEMENT_TYPE_CAP_MASK_TSAR;
564
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
565
-
return MLX5_CAP_QOS(dev, esw_element_type) &
566
-
ELEMENT_TYPE_CAP_MASK_VPORT;
567
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
568
-
return MLX5_CAP_QOS(dev, esw_element_type) &
569
-
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
570
-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
571
-
return MLX5_CAP_QOS(dev, esw_element_type) &
572
-
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
573
-
}
574
-
return false;
575
-
}
576
-
577
529
static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack)
578
530
{
579
531
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
···
565
555
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
566
556
return -EOPNOTSUPP;
567
557
568
-
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR))
558
+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR) ||
559
+
!(MLX5_CAP_QOS(dev, esw_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
569
560
return -EOPNOTSUPP;
570
561
571
562
MLX5_SET(scheduling_context, tsar_ctx, element_type,
+1
drivers/net/ethernet/mellanox/mlx5/core/main.c
+1
drivers/net/ethernet/mellanox/mlx5/core/main.c
···
2217
2217
{ PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2218
2218
{ PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2219
2219
{ PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2220
+
{ PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2220
2221
{ PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2221
2222
{ PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2222
2223
{ PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
+7
drivers/net/ethernet/mellanox/mlx5/core/qos.c
+7
drivers/net/ethernet/mellanox/mlx5/core/qos.c
···
28
28
{
29
29
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
30
30
31
+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP))
32
+
return -EOPNOTSUPP;
33
+
31
34
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
32
35
MLX5_SET(scheduling_context, sched_ctx, element_type,
33
36
SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP);
···
46
43
{
47
44
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
48
45
void *attr;
46
+
47
+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_TSAR) ||
48
+
!(MLX5_CAP_QOS(mdev, nic_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
49
+
return -EOPNOTSUPP;
49
50
50
51
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
51
52
MLX5_SET(scheduling_context, sched_ctx, element_type,
+3
-3
drivers/net/ethernet/wangxun/libwx/wx_type.h
+3
-3
drivers/net/ethernet/wangxun/libwx/wx_type.h
···
426
426
#define WX_MIN_RXD 128
427
427
#define WX_MIN_TXD 128
428
428
429
-
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
430
-
#define WX_REQ_RX_DESCRIPTOR_MULTIPLE 8
431
-
#define WX_REQ_TX_DESCRIPTOR_MULTIPLE 8
429
+
/* Number of Transmit and Receive Descriptors must be a multiple of 128 */
430
+
#define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
431
+
#define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
432
432
433
433
#define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
434
434
#define VMDQ_P(p) p
+22
-13
drivers/net/phy/dp83822.c
+22
-13
drivers/net/phy/dp83822.c
···
271
271
DP83822_ENERGY_DET_INT_EN |
272
272
DP83822_LINK_QUAL_INT_EN);
273
273
274
-
/* Private data pointer is NULL on DP83825 */
275
-
if (!dp83822 || !dp83822->fx_enabled)
274
+
if (!dp83822->fx_enabled)
276
275
misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
277
276
DP83822_DUP_MODE_CHANGE_INT_EN |
278
277
DP83822_SPEED_CHANGED_INT_EN;
···
291
292
DP83822_PAGE_RX_INT_EN |
292
293
DP83822_EEE_ERROR_CHANGE_INT_EN);
293
294
294
-
/* Private data pointer is NULL on DP83825 */
295
-
if (!dp83822 || !dp83822->fx_enabled)
295
+
if (!dp83822->fx_enabled)
296
296
misr_status |= DP83822_ANEG_ERR_INT_EN |
297
297
DP83822_WOL_PKT_INT_EN;
298
298
···
689
691
return 0;
690
692
}
691
693
692
-
static int dp83822_probe(struct phy_device *phydev)
694
+
static int dp8382x_probe(struct phy_device *phydev)
693
695
{
694
696
struct dp83822_private *dp83822;
695
-
int ret;
696
697
697
698
dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
698
699
GFP_KERNEL);
···
699
702
return -ENOMEM;
700
703
701
704
phydev->priv = dp83822;
705
+
706
+
return 0;
707
+
}
708
+
709
+
static int dp83822_probe(struct phy_device *phydev)
710
+
{
711
+
struct dp83822_private *dp83822;
712
+
int ret;
713
+
714
+
ret = dp8382x_probe(phydev);
715
+
if (ret)
716
+
return ret;
717
+
718
+
dp83822 = phydev->priv;
702
719
703
720
ret = dp83822_read_straps(phydev);
704
721
if (ret)
···
728
717
729
718
static int dp83826_probe(struct phy_device *phydev)
730
719
{
731
-
struct dp83822_private *dp83822;
720
+
int ret;
732
721
733
-
dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
734
-
GFP_KERNEL);
735
-
if (!dp83822)
736
-
return -ENOMEM;
737
-
738
-
phydev->priv = dp83822;
722
+
ret = dp8382x_probe(phydev);
723
+
if (ret)
724
+
return ret;
739
725
740
726
dp83826_of_init(phydev);
741
727
···
803
795
PHY_ID_MATCH_MODEL(_id), \
804
796
.name = (_name), \
805
797
/* PHY_BASIC_FEATURES */ \
798
+
.probe = dp8382x_probe, \
806
799
.soft_reset = dp83822_phy_reset, \
807
800
.config_init = dp8382x_config_init, \
808
801
.get_wol = dp83822_get_wol, \
+48
-51
drivers/net/virtio_net.c
+48
-51
drivers/net/virtio_net.c
···
356
356
struct xdp_rxq_info xsk_rxq_info;
357
357
358
358
struct xdp_buff **xsk_buffs;
359
+
360
+
/* Do dma by self */
361
+
bool do_dma;
359
362
};
360
363
361
364
/* This structure can contain rss message with maximum settings for indirection table and keysize
···
888
885
void *buf;
889
886
890
887
buf = virtqueue_get_buf_ctx(rq->vq, len, ctx);
891
-
if (buf)
888
+
if (buf && rq->do_dma)
892
889
virtnet_rq_unmap(rq, buf, *len);
893
890
894
891
return buf;
···
900
897
dma_addr_t addr;
901
898
u32 offset;
902
899
void *head;
900
+
901
+
if (!rq->do_dma) {
902
+
sg_init_one(rq->sg, buf, len);
903
+
return;
904
+
}
903
905
904
906
head = page_address(rq->alloc_frag.page);
905
907
···
931
923
932
924
head = page_address(alloc_frag->page);
933
925
934
-
dma = head;
926
+
if (rq->do_dma) {
927
+
dma = head;
935
928
936
-
/* new pages */
937
-
if (!alloc_frag->offset) {
938
-
if (rq->last_dma) {
939
-
/* Now, the new page is allocated, the last dma
940
-
* will not be used. So the dma can be unmapped
941
-
* if the ref is 0.
929
+
/* new pages */
930
+
if (!alloc_frag->offset) {
931
+
if (rq->last_dma) {
932
+
/* Now, the new page is allocated, the last dma
933
+
* will not be used. So the dma can be unmapped
934
+
* if the ref is 0.
935
+
*/
936
+
virtnet_rq_unmap(rq, rq->last_dma, 0);
937
+
rq->last_dma = NULL;
938
+
}
939
+
940
+
dma->len = alloc_frag->size - sizeof(*dma);
941
+
942
+
addr = virtqueue_dma_map_single_attrs(rq->vq, dma + 1,
943
+
dma->len, DMA_FROM_DEVICE, 0);
944
+
if (virtqueue_dma_mapping_error(rq->vq, addr))
945
+
return NULL;
946
+
947
+
dma->addr = addr;
948
+
dma->need_sync = virtqueue_dma_need_sync(rq->vq, addr);
949
+
950
+
/* Add a reference to dma to prevent the entire dma from
951
+
* being released during error handling. This reference
952
+
* will be freed after the pages are no longer used.
942
953
*/
943
-
virtnet_rq_unmap(rq, rq->last_dma, 0);
944
-
rq->last_dma = NULL;
954
+
get_page(alloc_frag->page);
955
+
dma->ref = 1;
956
+
alloc_frag->offset = sizeof(*dma);
957
+
958
+
rq->last_dma = dma;
945
959
}
946
960
947
-
dma->len = alloc_frag->size - sizeof(*dma);
948
-
949
-
addr = virtqueue_dma_map_single_attrs(rq->vq, dma + 1,
950
-
dma->len, DMA_FROM_DEVICE, 0);
951
-
if (virtqueue_dma_mapping_error(rq->vq, addr))
952
-
return NULL;
953
-
954
-
dma->addr = addr;
955
-
dma->need_sync = virtqueue_dma_need_sync(rq->vq, addr);
956
-
957
-
/* Add a reference to dma to prevent the entire dma from
958
-
* being released during error handling. This reference
959
-
* will be freed after the pages are no longer used.
960
-
*/
961
-
get_page(alloc_frag->page);
962
-
dma->ref = 1;
963
-
alloc_frag->offset = sizeof(*dma);
964
-
965
-
rq->last_dma = dma;
961
+
++dma->ref;
966
962
}
967
-
968
-
++dma->ref;
969
963
970
964
buf = head + alloc_frag->offset;
971
965
···
975
965
alloc_frag->offset += size;
976
966
977
967
return buf;
978
-
}
979
-
980
-
static void virtnet_rq_set_premapped(struct virtnet_info *vi)
981
-
{
982
-
int i;
983
-
984
-
/* disable for big mode */
985
-
if (!vi->mergeable_rx_bufs && vi->big_packets)
986
-
return;
987
-
988
-
for (i = 0; i < vi->max_queue_pairs; i++)
989
-
/* error should never happen */
990
-
BUG_ON(virtqueue_set_dma_premapped(vi->rq[i].vq));
991
968
}
992
969
993
970
static void virtnet_rq_unmap_free_buf(struct virtqueue *vq, void *buf)
···
990
993
return;
991
994
}
992
995
993
-
if (!vi->big_packets || vi->mergeable_rx_bufs)
996
+
if (rq->do_dma)
994
997
virtnet_rq_unmap(rq, buf, 0);
995
998
996
999
virtnet_rq_free_buf(vi, rq, buf);
···
2427
2430
2428
2431
err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
2429
2432
if (err < 0) {
2430
-
virtnet_rq_unmap(rq, buf, 0);
2433
+
if (rq->do_dma)
2434
+
virtnet_rq_unmap(rq, buf, 0);
2431
2435
put_page(virt_to_head_page(buf));
2432
2436
}
2433
2437
···
2542
2544
ctx = mergeable_len_to_ctx(len + room, headroom);
2543
2545
err = virtqueue_add_inbuf_ctx(rq->vq, rq->sg, 1, buf, ctx, gfp);
2544
2546
if (err < 0) {
2545
-
virtnet_rq_unmap(rq, buf, 0);
2547
+
if (rq->do_dma)
2548
+
virtnet_rq_unmap(rq, buf, 0);
2546
2549
put_page(virt_to_head_page(buf));
2547
2550
}
2548
2551
···
2700
2701
}
2701
2702
} else {
2702
2703
while (packets < budget &&
2703
-
(buf = virtqueue_get_buf(rq->vq, &len)) != NULL) {
2704
+
(buf = virtnet_rq_get_buf(rq, &len, NULL)) != NULL) {
2704
2705
receive_buf(vi, rq, buf, len, NULL, xdp_xmit, stats);
2705
2706
packets++;
2706
2707
}
···
5891
5892
int i;
5892
5893
for (i = 0; i < vi->max_queue_pairs; i++)
5893
5894
if (vi->rq[i].alloc_frag.page) {
5894
-
if (vi->rq[i].last_dma)
5895
+
if (vi->rq[i].do_dma && vi->rq[i].last_dma)
5895
5896
virtnet_rq_unmap(&vi->rq[i], vi->rq[i].last_dma, 0);
5896
5897
put_page(vi->rq[i].alloc_frag.page);
5897
5898
}
···
6088
6089
ret = virtnet_find_vqs(vi);
6089
6090
if (ret)
6090
6091
goto err_free;
6091
-
6092
-
virtnet_rq_set_premapped(vi);
6093
6092
6094
6093
cpus_read_lock();
6095
6094
virtnet_set_affinity(vi);
+9
-1
include/linux/mlx5/mlx5_ifc.h
+9
-1
include/linux/mlx5/mlx5_ifc.h
···
1027
1027
1028
1028
u8 max_tsar_bw_share[0x20];
1029
1029
1030
-
u8 reserved_at_100[0x20];
1030
+
u8 nic_element_type[0x10];
1031
+
u8 nic_tsar_type[0x10];
1031
1032
1032
1033
u8 reserved_at_120[0x3];
1033
1034
u8 log_meter_aso_granularity[0x5];
···
3967
3966
ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3968
3967
ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3969
3968
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3969
+
ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4,
3970
3970
};
3971
3971
3972
3972
struct mlx5_ifc_scheduling_context_bits {
···
4675
4673
TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4676
4674
TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4677
4675
TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4676
+
};
4677
+
4678
+
enum {
4679
+
TSAR_TYPE_CAP_MASK_DWRR = 1 << 0,
4680
+
TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1,
4681
+
TSAR_TYPE_CAP_MASK_ETS = 1 << 2,
4678
4682
};
4679
4683
4680
4684
struct mlx5_ifc_tsar_element_bits {
+2
-1
include/linux/virtio_net.h
+2
-1
include/linux/virtio_net.h
+14
-25
net/hsr/hsr_device.c
+14
-25
net/hsr/hsr_device.c
···
231
231
skb->dev = master->dev;
232
232
skb_reset_mac_header(skb);
233
233
skb_reset_mac_len(skb);
234
-
spin_lock_bh(&hsr->seqnr_lock);
235
234
hsr_forward_skb(skb, master);
236
-
spin_unlock_bh(&hsr->seqnr_lock);
237
235
} else {
238
236
dev_core_stats_tx_dropped_inc(dev);
239
237
dev_kfree_skb_any(skb);
···
312
314
set_hsr_stag_HSR_ver(hsr_stag, hsr->prot_version);
313
315
314
316
/* From HSRv1 on we have separate supervision sequence numbers. */
315
-
spin_lock_bh(&hsr->seqnr_lock);
316
-
if (hsr->prot_version > 0) {
317
-
hsr_stag->sequence_nr = htons(hsr->sup_sequence_nr);
318
-
hsr->sup_sequence_nr++;
319
-
} else {
320
-
hsr_stag->sequence_nr = htons(hsr->sequence_nr);
321
-
hsr->sequence_nr++;
322
-
}
317
+
if (hsr->prot_version > 0)
318
+
hsr_stag->sequence_nr = htons(atomic_inc_return(&hsr->sup_sequence_nr));
319
+
else
320
+
hsr_stag->sequence_nr = htons(atomic_inc_return(&hsr->sequence_nr));
323
321
324
322
hsr_stag->tlv.HSR_TLV_type = type;
325
323
/* TODO: Why 12 in HSRv0? */
···
337
343
ether_addr_copy(hsr_sp->macaddress_A, hsr->macaddress_redbox);
338
344
}
339
345
340
-
if (skb_put_padto(skb, ETH_ZLEN)) {
341
-
spin_unlock_bh(&hsr->seqnr_lock);
346
+
if (skb_put_padto(skb, ETH_ZLEN))
342
347
return;
343
-
}
344
348
345
349
hsr_forward_skb(skb, port);
346
-
spin_unlock_bh(&hsr->seqnr_lock);
350
+
347
351
return;
348
352
}
349
353
···
366
374
set_hsr_stag_HSR_ver(hsr_stag, (hsr->prot_version ? 1 : 0));
367
375
368
376
/* From HSRv1 on we have separate supervision sequence numbers. */
369
-
spin_lock_bh(&hsr->seqnr_lock);
370
-
hsr_stag->sequence_nr = htons(hsr->sup_sequence_nr);
371
-
hsr->sup_sequence_nr++;
377
+
hsr_stag->sequence_nr = htons(atomic_inc_return(&hsr->sup_sequence_nr));
372
378
hsr_stag->tlv.HSR_TLV_type = PRP_TLV_LIFE_CHECK_DD;
373
379
hsr_stag->tlv.HSR_TLV_length = sizeof(struct hsr_sup_payload);
374
380
···
374
384
hsr_sp = skb_put(skb, sizeof(struct hsr_sup_payload));
375
385
ether_addr_copy(hsr_sp->macaddress_A, master->dev->dev_addr);
376
386
377
-
if (skb_put_padto(skb, ETH_ZLEN)) {
378
-
spin_unlock_bh(&hsr->seqnr_lock);
387
+
if (skb_put_padto(skb, ETH_ZLEN))
379
388
return;
380
-
}
381
389
382
390
hsr_forward_skb(skb, master);
383
-
spin_unlock_bh(&hsr->seqnr_lock);
384
391
}
385
392
386
393
/* Announce (supervision frame) timer function
···
414
427
* of SAN nodes stored in ProxyNodeTable.
415
428
*/
416
429
interlink = hsr_port_get_hsr(hsr, HSR_PT_INTERLINK);
430
+
if (!interlink)
431
+
goto done;
432
+
417
433
list_for_each_entry_rcu(node, &hsr->proxy_node_db, mac_list) {
418
434
if (hsr_addr_is_redbox(hsr, node->macaddress_A))
419
435
continue;
···
431
441
mod_timer(&hsr->announce_proxy_timer, jiffies + interval);
432
442
}
433
443
444
+
done:
434
445
rcu_read_unlock();
435
446
}
436
447
···
612
621
if (res < 0)
613
622
return res;
614
623
615
-
spin_lock_init(&hsr->seqnr_lock);
616
624
/* Overflow soon to find bugs easier: */
617
-
hsr->sequence_nr = HSR_SEQNR_START;
618
-
hsr->sup_sequence_nr = HSR_SUP_SEQNR_START;
619
-
hsr->interlink_sequence_nr = HSR_SEQNR_START;
625
+
atomic_set(&hsr->sequence_nr, HSR_SEQNR_START);
626
+
atomic_set(&hsr->sup_sequence_nr, HSR_SUP_SEQNR_START);
620
627
621
628
timer_setup(&hsr->announce_timer, hsr_announce, 0);
622
629
timer_setup(&hsr->prune_timer, hsr_prune_nodes, 0);
+1
-3
net/hsr/hsr_forward.c
+1
-3
net/hsr/hsr_forward.c
···
599
599
if (port->type == HSR_PT_MASTER ||
600
600
port->type == HSR_PT_INTERLINK) {
601
601
/* Sequence nr for the master/interlink node */
602
-
lockdep_assert_held(&hsr->seqnr_lock);
603
-
frame->sequence_nr = hsr->sequence_nr;
604
-
hsr->sequence_nr++;
602
+
frame->sequence_nr = atomic_inc_return(&hsr->sequence_nr);
605
603
}
606
604
}
607
605
+2
-4
net/hsr/hsr_main.h
+2
-4
net/hsr/hsr_main.h
···
202
202
struct timer_list prune_timer;
203
203
struct timer_list prune_proxy_timer;
204
204
int announce_count;
205
-
u16 sequence_nr;
206
-
u16 interlink_sequence_nr; /* Interlink port seq_nr */
207
-
u16 sup_sequence_nr; /* For HSRv1 separate seq_nr for supervision */
205
+
atomic_t sequence_nr;
206
+
atomic_t sup_sequence_nr; /* For HSRv1 separate seq_nr for supervision */
208
207
enum hsr_version prot_version; /* Indicate if HSRv0, HSRv1 or PRPv1 */
209
-
spinlock_t seqnr_lock; /* locking for sequence_nr */
210
208
spinlock_t list_lock; /* locking for node list */
211
209
struct hsr_proto_ops *proto_ops;
212
210
#define PRP_LAN_ID 0x5 /* 0x1010 for A and 0x1011 for B. Bit 0 is set
+1
-1
net/hsr/hsr_netlink.c
+1
-1
net/hsr/hsr_netlink.c
···
163
163
164
164
if (nla_put(skb, IFLA_HSR_SUPERVISION_ADDR, ETH_ALEN,
165
165
hsr->sup_multicast_addr) ||
166
-
nla_put_u16(skb, IFLA_HSR_SEQ_NR, hsr->sequence_nr))
166
+
nla_put_u16(skb, IFLA_HSR_SEQ_NR, atomic_read(&hsr->sequence_nr)))
167
167
goto nla_put_failure;
168
168
if (hsr->prot_version == PRP_V1)
169
169
proto = HSR_PROTOCOL_PRP;
+2
-2
net/ipv4/fou_core.c
+2
-2
net/ipv4/fou_core.c
+9
-4
net/mptcp/pm_netlink.c
+9
-4
net/mptcp/pm_netlink.c
···
334
334
{
335
335
struct mptcp_pm_add_entry *entry;
336
336
struct sock *sk = (struct sock *)msk;
337
+
struct timer_list *add_timer = NULL;
337
338
338
339
spin_lock_bh(&msk->pm.lock);
339
340
entry = mptcp_lookup_anno_list_by_saddr(msk, addr);
340
-
if (entry && (!check_id || entry->addr.id == addr->id))
341
+
if (entry && (!check_id || entry->addr.id == addr->id)) {
341
342
entry->retrans_times = ADD_ADDR_RETRANS_MAX;
343
+
add_timer = &entry->add_timer;
344
+
}
345
+
if (!check_id && entry)
346
+
list_del(&entry->list);
342
347
spin_unlock_bh(&msk->pm.lock);
343
348
344
-
if (entry && (!check_id || entry->addr.id == addr->id))
345
-
sk_stop_timer_sync(sk, &entry->add_timer);
349
+
/* no lock, because sk_stop_timer_sync() is calling del_timer_sync() */
350
+
if (add_timer)
351
+
sk_stop_timer_sync(sk, add_timer);
346
352
347
353
return entry;
348
354
}
···
1468
1462
1469
1463
entry = mptcp_pm_del_add_timer(msk, addr, false);
1470
1464
if (entry) {
1471
-
list_del(&entry->list);
1472
1465
kfree(entry);
1473
1466
return true;
1474
1467
}
+6
net/netfilter/nf_flow_table_core.c
+6
net/netfilter/nf_flow_table_core.c
···
670
670
if (ret)
671
671
goto out_offload;
672
672
673
+
ret = nf_flow_register_bpf();
674
+
if (ret)
675
+
goto out_bpf;
676
+
673
677
return 0;
674
678
679
+
out_bpf:
680
+
nf_flow_table_offload_exit();
675
681
out_offload:
676
682
unregister_pernet_subsys(&nf_flow_table_net_ops);
677
683
return ret;
+1
-1
net/netfilter/nf_flow_table_inet.c
+1
-1
net/netfilter/nf_flow_table_inet.c
+42
-6
net/netfilter/nft_socket.c
+42
-6
net/netfilter/nft_socket.c
···
9
9
10
10
struct nft_socket {
11
11
enum nft_socket_keys key:8;
12
-
u8 level;
12
+
u8 level; /* cgroupv2 level to extract */
13
+
u8 level_user; /* cgroupv2 level provided by userspace */
13
14
u8 len;
14
15
union {
15
16
u8 dreg;
···
53
52
cgid = cgroup_id(cgrp);
54
53
memcpy(dest, &cgid, sizeof(u64));
55
54
return true;
55
+
}
56
+
57
+
/* process context only, uses current->nsproxy. */
58
+
static noinline int nft_socket_cgroup_subtree_level(void)
59
+
{
60
+
struct cgroup *cgrp = cgroup_get_from_path("/");
61
+
int level;
62
+
63
+
if (!cgrp)
64
+
return -ENOENT;
65
+
66
+
level = cgrp->level;
67
+
68
+
cgroup_put(cgrp);
69
+
70
+
if (WARN_ON_ONCE(level > 255))
71
+
return -ERANGE;
72
+
73
+
if (WARN_ON_ONCE(level < 0))
74
+
return -EINVAL;
75
+
76
+
return level;
56
77
}
57
78
#endif
58
79
···
133
110
*dest = READ_ONCE(sk->sk_mark);
134
111
} else {
135
112
regs->verdict.code = NFT_BREAK;
136
-
return;
113
+
goto out_put_sk;
137
114
}
138
115
break;
139
116
case NFT_SOCKET_WILDCARD:
140
117
if (!sk_fullsock(sk)) {
141
118
regs->verdict.code = NFT_BREAK;
142
-
return;
119
+
goto out_put_sk;
143
120
}
144
121
nft_socket_wildcard(pkt, regs, sk, dest);
145
122
break;
···
147
124
case NFT_SOCKET_CGROUPV2:
148
125
if (!nft_sock_get_eval_cgroupv2(dest, sk, pkt, priv->level)) {
149
126
regs->verdict.code = NFT_BREAK;
150
-
return;
127
+
goto out_put_sk;
151
128
}
152
129
break;
153
130
#endif
···
156
133
regs->verdict.code = NFT_BREAK;
157
134
}
158
135
136
+
out_put_sk:
159
137
if (sk != skb->sk)
160
138
sock_gen_put(sk);
161
139
}
···
197
173
case NFT_SOCKET_MARK:
198
174
len = sizeof(u32);
199
175
break;
200
-
#ifdef CONFIG_CGROUPS
176
+
#ifdef CONFIG_SOCK_CGROUP_DATA
201
177
case NFT_SOCKET_CGROUPV2: {
202
178
unsigned int level;
179
+
int err;
203
180
204
181
if (!tb[NFTA_SOCKET_LEVEL])
205
182
return -EINVAL;
206
183
207
184
level = ntohl(nla_get_be32(tb[NFTA_SOCKET_LEVEL]));
208
185
if (level > 255)
186
+
return -EOPNOTSUPP;
187
+
188
+
err = nft_socket_cgroup_subtree_level();
189
+
if (err < 0)
190
+
return err;
191
+
192
+
priv->level_user = level;
193
+
194
+
level += err;
195
+
/* Implies a giant cgroup tree */
196
+
if (WARN_ON_ONCE(level > 255))
209
197
return -EOPNOTSUPP;
210
198
211
199
priv->level = level;
···
244
208
if (nft_dump_register(skb, NFTA_SOCKET_DREG, priv->dreg))
245
209
return -1;
246
210
if (priv->key == NFT_SOCKET_CGROUPV2 &&
247
-
nla_put_be32(skb, NFTA_SOCKET_LEVEL, htonl(priv->level)))
211
+
nla_put_be32(skb, NFTA_SOCKET_LEVEL, htonl(priv->level_user)))
248
212
return -1;
249
213
return 0;
250
214
}
+14
-2
tools/testing/selftests/net/lib/csum.c
+14
-2
tools/testing/selftests/net/lib/csum.c
···
654
654
{
655
655
struct iphdr *iph = nh;
656
656
uint16_t proto = cfg_encap ? IPPROTO_UDP : cfg_proto;
657
+
uint16_t ip_len;
657
658
658
659
if (len < sizeof(*iph) || iph->protocol != proto)
659
660
return -1;
660
661
662
+
ip_len = ntohs(iph->tot_len);
663
+
if (ip_len > len || ip_len < sizeof(*iph))
664
+
return -1;
665
+
666
+
len = ip_len;
661
667
iph_addr_p = &iph->saddr;
662
668
if (proto == IPPROTO_TCP)
663
669
return recv_verify_packet_tcp(iph + 1, len - sizeof(*iph));
···
675
669
{
676
670
struct ipv6hdr *ip6h = nh;
677
671
uint16_t proto = cfg_encap ? IPPROTO_UDP : cfg_proto;
672
+
uint16_t ip_len;
678
673
679
674
if (len < sizeof(*ip6h) || ip6h->nexthdr != proto)
680
675
return -1;
681
676
677
+
ip_len = ntohs(ip6h->payload_len);
678
+
if (ip_len > len - sizeof(*ip6h))
679
+
return -1;
680
+
681
+
len = ip_len;
682
682
iph_addr_p = &ip6h->saddr;
683
683
684
684
if (proto == IPPROTO_TCP)
685
-
return recv_verify_packet_tcp(ip6h + 1, len - sizeof(*ip6h));
685
+
return recv_verify_packet_tcp(ip6h + 1, len);
686
686
else
687
-
return recv_verify_packet_udp(ip6h + 1, len - sizeof(*ip6h));
687
+
return recv_verify_packet_udp(ip6h + 1, len);
688
688
}
689
689
690
690
/* return whether auxdata includes TP_STATUS_CSUM_VALID */
+2
tools/testing/selftests/net/mptcp/Makefile
+2
tools/testing/selftests/net/mptcp/Makefile
+3
-1
tools/testing/selftests/net/mptcp/mptcp_join.sh
+3
-1
tools/testing/selftests/net/mptcp/mptcp_join.sh
···
3064
3064
pm_nl_set_limits $ns1 1 3
3065
3065
pm_nl_set_limits $ns2 1 3
3066
3066
pm_nl_add_endpoint $ns1 10.0.2.1 flags signal
3067
-
pm_nl_add_endpoint $ns2 10.0.1.2 flags subflow,fullmesh
3067
+
if mptcp_lib_kallsyms_has "mptcp_pm_subflow_check_next$"; then
3068
+
pm_nl_add_endpoint $ns2 10.0.1.2 flags subflow,fullmesh
3069
+
fi
3068
3070
fullmesh=1 speed=slow \
3069
3071
run_tests $ns1 $ns2 10.0.1.1
3070
3072
chk_join_nr 3 3 3