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arm64: dts: altera: Use lowercase hex

The DTS code coding style expects lowercase hex for values and unit
addresses.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Dinh Nguyen
5acb9254 1cb8486a

+31 -31
+1 -1
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
··· 382 382 383 383 pinctrl0: pinctrl@ffd13000 { 384 384 compatible = "pinctrl-single"; 385 - reg = <0xffd13000 0xA0>; 385 + reg = <0xffd13000 0xa0>; 386 386 #pinctrl-cells = <1>; 387 387 pinctrl-single,register-width = <32>; 388 388 pinctrl-single,function-mask = <0x0000000f>;
+1 -1
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
··· 192 192 193 193 root: partition@4200000 { 194 194 label = "Root Filesystem - UBIFS"; 195 - reg = <0x04200000 0x0BE00000>; 195 + reg = <0x04200000 0x0be00000>; 196 196 }; 197 197 }; 198 198 };
+2 -2
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
··· 174 174 175 175 qspi_boot: partition@0 { 176 176 label = "Boot and fpga data"; 177 - reg = <0x0 0x03FE0000>; 177 + reg = <0x0 0x03fe0000>; 178 178 }; 179 179 180 180 qspi_rootfs: partition@3fe0000 { 181 181 label = "Root Filesystem - JFFS2"; 182 - reg = <0x03FE0000 0x0C020000>; 182 + reg = <0x03fe0000 0x0c020000>; 183 183 }; 184 184 }; 185 185 };
+24 -24
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
··· 622 622 snps,dcb-algorithm; 623 623 }; 624 624 queue1 { 625 - snps,weight = <0x0A>; 625 + snps,weight = <0x0a>; 626 626 snps,dcb-algorithm; 627 627 }; 628 628 queue2 { 629 - snps,weight = <0x0B>; 629 + snps,weight = <0x0b>; 630 630 snps,coe-unsupported; 631 631 snps,dcb-algorithm; 632 632 }; 633 633 queue3 { 634 - snps,weight = <0x0C>; 634 + snps,weight = <0x0c>; 635 635 snps,coe-unsupported; 636 636 snps,dcb-algorithm; 637 637 }; 638 638 queue4 { 639 - snps,weight = <0x0D>; 639 + snps,weight = <0x0d>; 640 640 snps,coe-unsupported; 641 641 snps,dcb-algorithm; 642 642 }; 643 643 queue5 { 644 - snps,weight = <0x0E>; 644 + snps,weight = <0x0e>; 645 645 snps,coe-unsupported; 646 646 snps,dcb-algorithm; 647 647 }; 648 648 queue6 { 649 - snps,weight = <0x0F>; 649 + snps,weight = <0x0f>; 650 650 snps,coe-unsupported; 651 651 snps,dcb-algorithm; 652 652 }; ··· 735 735 snps,dcb-algorithm; 736 736 }; 737 737 queue1 { 738 - snps,weight = <0x0A>; 738 + snps,weight = <0x0a>; 739 739 snps,dcb-algorithm; 740 740 }; 741 741 queue2 { 742 - snps,weight = <0x0B>; 742 + snps,weight = <0x0b>; 743 743 snps,coe-unsupported; 744 744 snps,dcb-algorithm; 745 745 }; 746 746 queue3 { 747 - snps,weight = <0x0C>; 747 + snps,weight = <0x0c>; 748 748 snps,coe-unsupported; 749 749 snps,dcb-algorithm; 750 750 }; 751 751 queue4 { 752 - snps,weight = <0x0D>; 752 + snps,weight = <0x0d>; 753 753 snps,coe-unsupported; 754 754 snps,dcb-algorithm; 755 755 }; 756 756 queue5 { 757 - snps,weight = <0x0E>; 757 + snps,weight = <0x0e>; 758 758 snps,coe-unsupported; 759 759 snps,dcb-algorithm; 760 760 }; 761 761 queue6 { 762 - snps,weight = <0x0F>; 762 + snps,weight = <0x0f>; 763 763 snps,coe-unsupported; 764 764 snps,dcb-algorithm; 765 765 }; ··· 848 848 snps,dcb-algorithm; 849 849 }; 850 850 queue1 { 851 - snps,weight = <0x0A>; 851 + snps,weight = <0x0a>; 852 852 snps,dcb-algorithm; 853 853 }; 854 854 queue2 { 855 - snps,weight = <0x0B>; 855 + snps,weight = <0x0b>; 856 856 snps,coe-unsupported; 857 857 snps,dcb-algorithm; 858 858 }; 859 859 queue3 { 860 - snps,weight = <0x0C>; 860 + snps,weight = <0x0c>; 861 861 snps,coe-unsupported; 862 862 snps,dcb-algorithm; 863 863 }; 864 864 queue4 { 865 - snps,weight = <0x0D>; 865 + snps,weight = <0x0d>; 866 866 snps,coe-unsupported; 867 867 snps,dcb-algorithm; 868 868 }; 869 869 queue5 { 870 - snps,weight = <0x0E>; 870 + snps,weight = <0x0e>; 871 871 snps,coe-unsupported; 872 872 snps,dcb-algorithm; 873 873 }; 874 874 queue6 { 875 - snps,weight = <0x0F>; 875 + snps,weight = <0x0f>; 876 876 snps,coe-unsupported; 877 877 snps,dcb-algorithm; 878 878 }; ··· 918 918 919 919 pmu0_tbu3: pmu@160a2000 { 920 920 compatible = "arm,smmu-v3-pmcg"; 921 - reg = <0x160A2000 0x1000>, 922 - <0x160B2000 0x1000>; 921 + reg = <0x160a2000 0x1000>, 922 + <0x160b2000 0x1000>; 923 923 interrupt-parent = <&intc>; 924 924 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 925 925 }; 926 926 927 927 pmu0_tbu4: pmu@160c2000 { 928 928 compatible = "arm,smmu-v3-pmcg"; 929 - reg = <0x160C2000 0x1000>, 930 - <0x160D2000 0x1000>; 929 + reg = <0x160c2000 0x1000>, 930 + <0x160d2000 0x1000>; 931 931 interrupt-parent = <&intc>; 932 932 interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 933 933 }; 934 934 935 935 pmu0_tbu5: pmu@160e2000 { 936 936 compatible = "arm,smmu-v3-pmcg"; 937 - reg = <0x160E2000 0x1000>, 938 - <0x160F2000 0x1000>; 937 + reg = <0x160e2000 0x1000>, 938 + <0x160f2000 0x1000>; 939 939 interrupt-parent = <&intc>; 940 940 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 941 941 };
+1 -1
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
··· 131 131 132 132 root: partition@4200000 { 133 133 label = "Root Filesystem - UBIFS"; 134 - reg = <0x04200000 0x0BE00000>; 134 + reg = <0x04200000 0x0be00000>; 135 135 }; 136 136 }; 137 137 };
+2 -2
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
··· 103 103 104 104 qspi_boot: partition@0 { 105 105 label = "Boot and fpga data"; 106 - reg = <0x0 0x03FE0000>; 106 + reg = <0x0 0x03fe0000>; 107 107 }; 108 108 109 109 qspi_rootfs: partition@3fe0000 { 110 110 label = "Root Filesystem - JFFS2"; 111 - reg = <0x03FE0000 0x0C020000>; 111 + reg = <0x03fe0000 0x0c020000>; 112 112 }; 113 113 }; 114 114 };