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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
NTB: epf: Allow arbitrary BAR mapping
The NTB epf host driver assumes the BAR number associated with a memory
window is just incremented from the BAR number associated with MW1. This
seems to have been enough so far but this is not really how the endpoint
side work and the two could easily become mis-aligned.
ntb_epf_mw_to_bar() even assumes that the BAR number is the memory window
index + 2, which means the function only returns a proper result if BAR_2
is associated with MW1.
Instead, fully describe and allow arbitrary NTB BAR mapping.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
authored by
Jerome Brunet
and committed by
Jon Mason
5ad86586
3db835dd
+53
-50
+53
-50
drivers/ntb/hw/epf/ntb_hw_epf.c
+53
-50
drivers/ntb/hw/epf/ntb_hw_epf.c
···
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#define NTB_EPF_COMMAND_TIMEOUT 1000 /* 1 Sec */
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enum pci_barno {
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+
NO_BAR = -1,
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BAR_0,
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BAR_1,
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BAR_2,
···
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BAR_5,
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};
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+
enum epf_ntb_bar {
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BAR_CONFIG,
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BAR_PEER_SPAD,
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BAR_DB,
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BAR_MW1,
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BAR_MW2,
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BAR_MW3,
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BAR_MW4,
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NTB_BAR_NUM,
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};
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+
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#define NTB_EPF_MAX_MW_COUNT (NTB_BAR_NUM - BAR_MW1)
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struct ntb_epf_dev {
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struct ntb_dev ntb;
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struct device *dev;
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/* Mutex to protect providing commands to NTB EPF */
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struct mutex cmd_lock;
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-
enum pci_barno ctrl_reg_bar;
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enum pci_barno peer_spad_reg_bar;
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-
enum pci_barno db_reg_bar;
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-
enum pci_barno mw_bar;
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const enum pci_barno *barno_map;
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unsigned int mw_count;
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unsigned int spad_count;
···
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};
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#define ntb_ndev(__ntb) container_of(__ntb, struct ntb_epf_dev, ntb)
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-
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struct ntb_epf_data {
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/* BAR that contains both control region and self spad region */
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enum pci_barno ctrl_reg_bar;
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/* BAR that contains peer spad region */
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enum pci_barno peer_spad_reg_bar;
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/* BAR that contains Doorbell region and Memory window '1' */
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enum pci_barno db_reg_bar;
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/* BAR that contains memory windows*/
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enum pci_barno mw_bar;
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};
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static int ntb_epf_send_command(struct ntb_epf_dev *ndev, u32 command,
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u32 argument)
···
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return -EINVAL;
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}
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-
return idx + 2;
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return ndev->barno_map[BAR_MW1 + idx];
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}
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static int ntb_epf_mw_count(struct ntb_dev *ntb, int pidx)
···
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return -EINVAL;
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}
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-
bar = idx + ndev->mw_bar;
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bar = ntb_epf_mw_to_bar(ndev, idx);
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if (bar < 0)
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return bar;
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mw_size = pci_resource_len(ntb->pdev, bar);
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···
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if (idx == 0)
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offset = readl(ndev->ctrl_reg + NTB_EPF_MW1_OFFSET);
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-
bar = idx + ndev->mw_bar;
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bar = ntb_epf_mw_to_bar(ndev, idx);
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if (bar < 0)
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return bar;
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if (base)
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*base = pci_resource_start(ndev->ntb.pdev, bar) + offset;
···
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ndev->mw_count = readl(ndev->ctrl_reg + NTB_EPF_MW_COUNT);
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ndev->spad_count = readl(ndev->ctrl_reg + NTB_EPF_SPAD_COUNT);
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if (ndev->mw_count > NTB_EPF_MAX_MW_COUNT) {
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dev_err(dev, "Unsupported MW count: %u\n", ndev->mw_count);
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return -EINVAL;
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}
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return 0;
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}
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···
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dev_warn(&pdev->dev, "Cannot DMA highmem\n");
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}
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-
ndev->ctrl_reg = pci_iomap(pdev, ndev->ctrl_reg_bar, 0);
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ndev->ctrl_reg = pci_iomap(pdev, ndev->barno_map[BAR_CONFIG], 0);
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if (!ndev->ctrl_reg) {
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ret = -EIO;
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goto err_pci_regions;
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}
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-
if (ndev->peer_spad_reg_bar) {
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-
ndev->peer_spad_reg = pci_iomap(pdev, ndev->peer_spad_reg_bar, 0);
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if (ndev->barno_map[BAR_PEER_SPAD] != ndev->barno_map[BAR_CONFIG]) {
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ndev->peer_spad_reg = pci_iomap(pdev,
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ndev->barno_map[BAR_PEER_SPAD], 0);
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if (!ndev->peer_spad_reg) {
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ret = -EIO;
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goto err_pci_regions;
···
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ndev->peer_spad_reg = ndev->ctrl_reg + spad_off + spad_sz;
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}
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-
ndev->db_reg = pci_iomap(pdev, ndev->db_reg_bar, 0);
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ndev->db_reg = pci_iomap(pdev, ndev->barno_map[BAR_DB], 0);
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if (!ndev->db_reg) {
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ret = -EIO;
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goto err_pci_regions;
···
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static int ntb_epf_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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enum pci_barno peer_spad_reg_bar = BAR_1;
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enum pci_barno ctrl_reg_bar = BAR_0;
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enum pci_barno db_reg_bar = BAR_2;
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enum pci_barno mw_bar = BAR_2;
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struct device *dev = &pdev->dev;
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struct ntb_epf_data *data;
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struct ntb_epf_dev *ndev;
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int ret;
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···
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if (!ndev)
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return -ENOMEM;
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-
data = (struct ntb_epf_data *)id->driver_data;
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-
if (data) {
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peer_spad_reg_bar = data->peer_spad_reg_bar;
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ctrl_reg_bar = data->ctrl_reg_bar;
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db_reg_bar = data->db_reg_bar;
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mw_bar = data->mw_bar;
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-
}
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ndev->barno_map = (const enum pci_barno *)id->driver_data;
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if (!ndev->barno_map)
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return -EINVAL;
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-
ndev->peer_spad_reg_bar = peer_spad_reg_bar;
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ndev->ctrl_reg_bar = ctrl_reg_bar;
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ndev->db_reg_bar = db_reg_bar;
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ndev->mw_bar = mw_bar;
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ndev->dev = dev;
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ntb_epf_init_struct(ndev, pdev);
···
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ntb_epf_deinit_pci(ndev);
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731
}
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730
-
static const struct ntb_epf_data j721e_data = {
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.ctrl_reg_bar = BAR_0,
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.peer_spad_reg_bar = BAR_1,
733
-
.db_reg_bar = BAR_2,
734
-
.mw_bar = BAR_2,
733
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static const enum pci_barno j721e_map[NTB_BAR_NUM] = {
734
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[BAR_CONFIG] = BAR_0,
735
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[BAR_PEER_SPAD] = BAR_1,
736
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[BAR_DB] = BAR_2,
737
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[BAR_MW1] = BAR_2,
738
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[BAR_MW2] = BAR_3,
739
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[BAR_MW3] = BAR_4,
740
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[BAR_MW4] = BAR_5
735
741
};
736
742
737
-
static const struct ntb_epf_data mx8_data = {
738
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.ctrl_reg_bar = BAR_0,
739
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.peer_spad_reg_bar = BAR_0,
740
-
.db_reg_bar = BAR_2,
741
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.mw_bar = BAR_4,
743
+
static const enum pci_barno mx8_map[NTB_BAR_NUM] = {
744
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[BAR_CONFIG] = BAR_0,
745
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[BAR_PEER_SPAD] = BAR_0,
746
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[BAR_DB] = BAR_2,
747
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[BAR_MW1] = BAR_4,
748
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[BAR_MW2] = BAR_5,
749
+
[BAR_MW3] = NO_BAR,
750
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[BAR_MW4] = NO_BAR
742
751
};
743
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static const struct pci_device_id ntb_epf_pci_tbl[] = {
745
754
{
746
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PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
747
756
.class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,
748
-
.driver_data = (kernel_ulong_t)&j721e_data,
757
+
.driver_data = (kernel_ulong_t)j721e_map,
749
758
},
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{
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760
PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x0809),
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.class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,
753
-
.driver_data = (kernel_ulong_t)&mx8_data,
762
+
.driver_data = (kernel_ulong_t)mx8_map,
754
763
},
755
764
{ },
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765
};