Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mpfs-pinctrl-binding-base' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into devel
mpfs pinctrl binding base
The pinctrl binding patch for iomux0 mpfs adds a ref to itself to the
syscon/mfd mss-top-sysreg binding, and therefore needs that file to
exist.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+47
+47
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
+47
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
8
+
9
+
maintainers:
10
+
- Conor Dooley <conor.dooley@microchip.com>
11
+
12
+
description:
13
+
An wide assortment of registers that control elements of the MSS on PolarFire
14
+
SoC, including pinmuxing, resets and clocks among others.
15
+
16
+
properties:
17
+
compatible:
18
+
items:
19
+
- const: microchip,mpfs-mss-top-sysreg
20
+
- const: syscon
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
'#reset-cells':
26
+
description:
27
+
The AHB/AXI peripherals on the PolarFire SoC have reset support, so
28
+
from CLK_ENVM to CLK_CFM. The reset consumer should specify the
29
+
desired peripheral via the clock ID in its "resets" phandle cell.
30
+
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
31
+
of PolarFire clock/reset IDs.
32
+
const: 1
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
38
+
additionalProperties: false
39
+
40
+
examples:
41
+
- |
42
+
syscon@20002000 {
43
+
compatible = "microchip,mpfs-mss-top-sysreg", "syscon";
44
+
reg = <0x20002000 0x1000>;
45
+
#reset-cells = <1>;
46
+
};
47
+