Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_misc_for_6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull misc x86 updates from Dave Hansen:
"As usual for this branch, these are super random: a compile fix for
some newish LLVM checks and making sure a Kconfig text reference to
'RSB' matches the normal definition:
- Rework some CPU setup code to keep LLVM happy on 32-bit
- Correct RSB terminology in Kconfig text"
* tag 'x86_misc_for_6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/cpu: Make sure flag_is_changeable_p() is always being used
x86/bugs: Correct RSB terminology in Kconfig
+31
-33
+8
-9
arch/x86/Kconfig
+8
-9
arch/x86/Kconfig
···
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default y
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help
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Compile the kernel with call depth tracking to mitigate the Intel
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SKL Return-Speculation-Buffer (RSB) underflow issue. The
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mitigation is off by default and needs to be enabled on the
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kernel command line via the retbleed=stuff option. For
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non-affected systems the overhead of this option is marginal as
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the call depth tracking is using run-time generated call thunks
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in a compiler generated padding area and call patching. This
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increases text size by ~5%. For non affected systems this space
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is unused. On affected SKL systems this results in a significant
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performance gain over the IBRS mitigation.
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+
SKL Return-Stack-Buffer (RSB) underflow issue. The mitigation is off
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+
by default and needs to be enabled on the kernel command line via the
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+
retbleed=stuff option. For non-affected systems the overhead of this
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+
option is marginal as the call depth tracking is using run-time
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+
generated call thunks in a compiler generated padding area and call
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+
patching. This increases text size by ~5%. For non affected systems
2573
+
this space is unused. On affected SKL systems this results in a
2574
+
significant performance gain over the IBRS mitigation.
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config CALL_THUNKS_DEBUG
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bool "Enable call thunks and call depth tracking debugging"
+5
-3
arch/x86/include/asm/cpuid.h
+5
-3
arch/x86/include/asm/cpuid.h
···
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6
#ifndef _ASM_X86_CPUID_H
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#define _ASM_X86_CPUID_H
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+
#include <linux/types.h>
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+
9
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#include <asm/string.h>
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struct cpuid_regs {
···
22
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};
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#ifdef CONFIG_X86_32
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-
extern int have_cpuid_p(void);
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bool have_cpuid_p(void);
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#else
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static inline int have_cpuid_p(void)
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static inline bool have_cpuid_p(void)
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{
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return 1;
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return true;
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}
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#endif
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static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
+18
-21
arch/x86/kernel/cpu/common.c
+18
-21
arch/x86/kernel/cpu/common.c
···
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}
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early_param("noinvpcid", x86_noinvpcid_setup);
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-
#ifdef CONFIG_X86_32
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static int cachesize_override = -1;
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-
static int disable_x86_serial_nr = 1;
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static int __init cachesize_setup(char *str)
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{
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get_option(&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(u32 flag)
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static inline bool flag_is_changeable_p(unsigned long flag)
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{
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u32 f1, f2;
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unsigned long f1, f2;
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+
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if (!IS_ENABLED(CONFIG_X86_32))
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return true;
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/*
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* Cyrix and IDT cpus allow disabling of CPUID
···
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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return (f1 ^ f2) & flag;
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}
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#ifdef CONFIG_X86_32
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static int cachesize_override = -1;
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static int disable_x86_serial_nr = 1;
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+
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static int __init cachesize_setup(char *str)
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{
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get_option(&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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+
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/* Probe for the CPUID instruction */
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int have_cpuid_p(void)
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bool have_cpuid_p(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
···
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}
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__setup("serialnumber", x86_serial_nr_setup);
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#else
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static inline int flag_is_changeable_p(u32 flag)
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-
{
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return 1;
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-
}
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static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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}
···
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static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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int i;
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/*
···
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break;
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}
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1111
}
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-
#endif
1111
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}
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#define NO_SPECULATION BIT(0)