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dt-bindings: serial: Add bindings for nvidia,tegra264-utc

The Tegra UTC (UART Trace Controller) allows multiple clients within
the Tegra SoC to share a physical UART interface. It supports up to 16
clients. Each client operates as an independent UART endpoint with a
dedicated interrupt and 128-character TX/RX FIFOs.

Add device tree binding documentation for the Tegra UTC client.

Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250213125612.4705-2-kkartik@nvidia.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Kartik Rajput and committed by
Greg Kroah-Hartman 5b28371f a029a219

+73
+73
Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NVIDIA Tegra UTC (UART Trace Controller) client 8 + 9 + maintainers: 10 + - Kartik Rajput <kkartik@nvidia.com> 11 + - Thierry Reding <thierry.reding@gmail.com> 12 + - Jonathan Hunter <jonathanh@nvidia.com> 13 + 14 + description: 15 + Represents a client interface of the Tegra UTC (UART Trace Controller). The 16 + Tegra UTC allows multiple clients within the Tegra SoC to share a physical 17 + UART interface. It supports up to 16 clients. Each client operates as an 18 + independent UART endpoint with a dedicated interrupt and 128-character TX/RX 19 + FIFOs. 20 + 21 + The Tegra UTC clients use 8-N-1 configuration and operates on a baudrate 22 + configured by the bootloader at the controller level. 23 + 24 + allOf: 25 + - $ref: serial.yaml# 26 + 27 + properties: 28 + compatible: 29 + const: nvidia,tegra264-utc 30 + 31 + reg: 32 + items: 33 + - description: TX region. 34 + - description: RX region. 35 + 36 + reg-names: 37 + items: 38 + - const: tx 39 + - const: rx 40 + 41 + interrupts: 42 + maxItems: 1 43 + 44 + tx-threshold: 45 + minimum: 1 46 + maximum: 128 47 + 48 + rx-threshold: 49 + minimum: 1 50 + maximum: 128 51 + 52 + required: 53 + - compatible 54 + - reg 55 + - reg-names 56 + - interrupts 57 + - tx-threshold 58 + - rx-threshold 59 + 60 + additionalProperties: false 61 + 62 + examples: 63 + - | 64 + #include <dt-bindings/interrupt-controller/arm-gic.h> 65 + 66 + tegra_utc: serial@c4e0000 { 67 + compatible = "nvidia,tegra264-utc"; 68 + reg = <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; 69 + reg-names = "tx", "rx"; 70 + interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 71 + tx-threshold = <4>; 72 + rx-threshold = <4>; 73 + };