Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'memory-controller-drv-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
Memory controller drivers for v6.20
1. Mediatek SMI: Fix old struct device reference leaks during error
paths and device unbinding.
2. Memory Devicetree bindings: refactor existing LPDDR bindings and add
bindings for DDR4 SDRAM. These will be used for example in
stm32mp257f-ev1 DTS.
* tag 'memory-controller-drv-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
dt-bindings: memory: SDRAM channel: standardise node name
dt-bindings: memory: add DDR4 channel compatible
dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel
dt-bindings: memory: introduce DDR4
dt-bindings: memory: factorise LPDDR props into SDRAM props
memory: mtk-smi: clean up device link creation
memory: mtk-smi: fix device leak on larb probe
memory: mtk-smi: fix device leaks on common probe
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+181
-107
+34
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml
+34
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: DDR4 SDRAM compliant to JEDEC JESD79-4D
8
+
9
+
maintainers:
10
+
- Krzysztof Kozlowski <krzk@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: jedec,sdram-props.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,20}-[0-9a-f]{2}$"
19
+
- const: jedec,ddr4
20
+
21
+
required:
22
+
- compatible
23
+
- density
24
+
- io-width
25
+
26
+
unevaluatedProperties: false
27
+
28
+
examples:
29
+
- |
30
+
ddr {
31
+
compatible = "ddr4-00ff,azaz-ff", "jedec,ddr4";
32
+
density = <8192>;
33
+
io-width = <8>;
34
+
};
+27
-13
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml
+27
-13
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
4
+
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: LPDDR channel with chip/rank topology description
7
+
title: SDRAM channel with chip/rank topology description
8
8
9
9
description:
10
-
An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
11
-
CK, etc.) that connect one or more LPDDR chips to a host system. The main
12
-
purpose of this node is to overall LPDDR topology of the system, including the
13
-
amount of individual LPDDR chips and the ranks per chip.
10
+
A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
11
+
independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory
12
+
chips to a host system. The main purpose of this node is to overall memory
13
+
topology of the system, including the amount of individual memory chips and
14
+
the ranks per chip.
14
15
15
16
maintainers:
16
17
- Julius Werner <jwerner@chromium.org>
17
18
18
19
properties:
20
+
$nodename:
21
+
pattern: "sdram-channel-[0-9]+$"
22
+
19
23
compatible:
20
24
enum:
25
+
- jedec,ddr4-channel
21
26
- jedec,lpddr2-channel
22
27
- jedec,lpddr3-channel
23
28
- jedec,lpddr4-channel
···
31
26
io-width:
32
27
description:
33
28
The number of DQ pins in the channel. If this number is different
34
-
from (a multiple of) the io-width of the LPDDR chip, that means that
29
+
from (a multiple of) the io-width of the SDRAM chip, that means that
35
30
multiple instances of that type of chip are wired in parallel on this
36
31
channel (with the channel's DQ pins split up between the different
37
32
chips, and the CA, CS, etc. pins of the different chips all shorted
38
33
together). This means that the total physical memory controlled by a
39
34
channel is equal to the sum of the densities of each rank on the
40
-
connected LPDDR chip, times the io-width of the channel divided by
41
-
the io-width of the LPDDR chip.
35
+
connected SDRAM chip, times the io-width of the channel divided by
36
+
the io-width of the SDRAM chip.
42
37
enum:
43
38
- 8
44
39
- 16
···
56
51
"^rank@[0-9]+$":
57
52
type: object
58
53
description:
59
-
Each physical LPDDR chip may have one or more ranks. Ranks are
60
-
internal but fully independent sub-units of the chip. Each LPDDR bus
54
+
Each physical SDRAM chip may have one or more ranks. Ranks are
55
+
internal but fully independent sub-units of the chip. Each SDRAM bus
61
56
transaction on the channel targets exactly one rank, based on the
62
57
state of the CS pins. Different ranks may have different densities and
63
58
timing requirements.
···
65
60
- reg
66
61
67
62
allOf:
63
+
- if:
64
+
properties:
65
+
compatible:
66
+
contains:
67
+
const: jedec,ddr4-channel
68
+
then:
69
+
patternProperties:
70
+
"^rank@[0-9]+$":
71
+
$ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml#
68
72
- if:
69
73
properties:
70
74
compatible:
···
121
107
122
108
examples:
123
109
- |
124
-
lpddr-channel0 {
110
+
sdram-channel-0 {
125
111
#address-cells = <1>;
126
112
#size-cells = <0>;
127
113
compatible = "jedec,lpddr3-channel";
···
136
122
};
137
123
};
138
124
139
-
lpddr-channel1 {
125
+
sdram-channel-1 {
140
126
#address-cells = <1>;
141
127
#size-cells = <0>;
142
128
compatible = "jedec,lpddr4-channel";
-74
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml
-74
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Common properties for LPDDR types
8
-
9
-
description:
10
-
Different LPDDR types generally use the same properties and only differ in the
11
-
range of legal values for each. This file defines the common parts that can be
12
-
reused for each type. Nodes using this schema should generally be nested under
13
-
an LPDDR channel node.
14
-
15
-
maintainers:
16
-
- Krzysztof Kozlowski <krzk@kernel.org>
17
-
18
-
properties:
19
-
compatible:
20
-
description:
21
-
Compatible strings can be either explicit vendor names and part numbers
22
-
(e.g. elpida,ECB240ABACN), or generated strings of the form
23
-
lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
24
-
(from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
25
-
formatted in lower case hexadecimal representation with leading zeroes.
26
-
The latter form can be useful when LPDDR nodes are created at runtime by
27
-
boot firmware that doesn't have access to static part number information.
28
-
29
-
reg:
30
-
description:
31
-
The rank number of this LPDDR rank when used as a subnode to an LPDDR
32
-
channel.
33
-
minimum: 0
34
-
maximum: 3
35
-
36
-
revision-id:
37
-
$ref: /schemas/types.yaml#/definitions/uint32-array
38
-
description:
39
-
Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
40
-
maxItems: 2
41
-
items:
42
-
minimum: 0
43
-
maximum: 255
44
-
45
-
density:
46
-
$ref: /schemas/types.yaml#/definitions/uint32
47
-
description:
48
-
Density in megabits of SDRAM chip. Decoded from Mode Register 8.
49
-
enum:
50
-
- 64
51
-
- 128
52
-
- 256
53
-
- 512
54
-
- 1024
55
-
- 2048
56
-
- 3072
57
-
- 4096
58
-
- 6144
59
-
- 8192
60
-
- 12288
61
-
- 16384
62
-
- 24576
63
-
- 32768
64
-
65
-
io-width:
66
-
$ref: /schemas/types.yaml#/definitions/uint32
67
-
description:
68
-
IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
69
-
enum:
70
-
- 8
71
-
- 16
72
-
- 32
73
-
74
-
additionalProperties: true
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml
+1
-1
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml
+94
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml
+94
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Common properties for SDRAM types
8
+
9
+
description:
10
+
Different SDRAM types generally use the same properties and only differ in the
11
+
range of legal values for each. This file defines the common parts that can be
12
+
reused for each type. Nodes using this schema should generally be nested under
13
+
a SDRAM channel node.
14
+
15
+
maintainers:
16
+
- Krzysztof Kozlowski <krzk@kernel.org>
17
+
18
+
properties:
19
+
compatible:
20
+
description: |
21
+
Compatible strings can be either explicit vendor names and part numbers
22
+
(e.g. elpida,ECB240ABACN), or generated strings of the form
23
+
lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
24
+
hexadecimal with leading zeroes, and A is lowercase ASCII.
25
+
For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
26
+
For LPDDR SDRAM:
27
+
- YY is the manufacturer ID (from MR5), 1 byte
28
+
- ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
29
+
For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
30
+
- YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
31
+
- AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
32
+
without trailing spaces
33
+
- ZZ is the revision ID, 1 byte, from byte 349
34
+
The former form is useful when the SDRAM vendor and part number are
35
+
known, for example, when memory is soldered on the board. The latter
36
+
form is useful when SDRAM nodes are created at runtime by boot firmware
37
+
that doesn't have access to static part number information.
38
+
39
+
reg:
40
+
description:
41
+
The rank number of this memory rank when used as a subnode to an memory
42
+
channel.
43
+
minimum: 0
44
+
maximum: 3
45
+
46
+
revision-id:
47
+
$ref: /schemas/types.yaml#/definitions/uint32-array
48
+
description: |
49
+
SDRAM revision ID:
50
+
- LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
51
+
- DDR4 SDRAM, decoded from the SPD from byte 349 according to
52
+
JEDEC SPD4.1.2.L-6, always 1 byte.
53
+
One byte per uint32 cell (e.g., <MR6 MR7>).
54
+
maxItems: 2
55
+
items:
56
+
minimum: 0
57
+
maximum: 255
58
+
59
+
density:
60
+
$ref: /schemas/types.yaml#/definitions/uint32
61
+
description: |
62
+
Density of the SDRAM chip in megabits:
63
+
- LPDDR SDRAM, decoded from Mode Register 8.
64
+
- DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
65
+
JEDEC SPD4.1.2.L-6.
66
+
enum:
67
+
- 64
68
+
- 128
69
+
- 256
70
+
- 512
71
+
- 1024
72
+
- 2048
73
+
- 3072
74
+
- 4096
75
+
- 6144
76
+
- 8192
77
+
- 12288
78
+
- 16384
79
+
- 24576
80
+
- 32768
81
+
82
+
io-width:
83
+
$ref: /schemas/types.yaml#/definitions/uint32
84
+
description: |
85
+
I/O bus width in bits of the SDRAM chip:
86
+
- LPDDR SDRAM, decoded from Mode Register 8.
87
+
- DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
88
+
JEDEC SPD4.1.2.L-6.
89
+
enum:
90
+
- 8
91
+
- 16
92
+
- 32
93
+
94
+
additionalProperties: true
+22
-16
drivers/memory/mtk-smi.c
+22
-16
drivers/memory/mtk-smi.c
···
595
595
596
596
smi_com_pdev = of_find_device_by_node(smi_com_node);
597
597
of_node_put(smi_com_node);
598
-
if (smi_com_pdev) {
599
-
/* smi common is the supplier, Make sure it is ready before */
600
-
if (!platform_get_drvdata(smi_com_pdev)) {
601
-
put_device(&smi_com_pdev->dev);
602
-
return -EPROBE_DEFER;
603
-
}
604
-
smi_com_dev = &smi_com_pdev->dev;
605
-
link = device_link_add(dev, smi_com_dev,
606
-
DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
607
-
if (!link) {
608
-
dev_err(dev, "Unable to link smi-common dev\n");
609
-
put_device(&smi_com_pdev->dev);
610
-
return -ENODEV;
611
-
}
612
-
*com_dev = smi_com_dev;
613
-
} else {
598
+
if (!smi_com_pdev) {
614
599
dev_err(dev, "Failed to get the smi_common device\n");
615
600
return -EINVAL;
616
601
}
602
+
603
+
/* smi common is the supplier, Make sure it is ready before */
604
+
if (!platform_get_drvdata(smi_com_pdev)) {
605
+
put_device(&smi_com_pdev->dev);
606
+
return -EPROBE_DEFER;
607
+
}
608
+
609
+
smi_com_dev = &smi_com_pdev->dev;
610
+
link = device_link_add(dev, smi_com_dev,
611
+
DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
612
+
if (!link) {
613
+
dev_err(dev, "Unable to link smi-common dev\n");
614
+
put_device(&smi_com_pdev->dev);
615
+
return -ENODEV;
616
+
}
617
+
618
+
*com_dev = smi_com_dev;
619
+
617
620
return 0;
618
621
}
619
622
···
677
674
err_pm_disable:
678
675
pm_runtime_disable(dev);
679
676
device_link_remove(dev, larb->smi_common_dev);
677
+
put_device(larb->smi_common_dev);
680
678
return ret;
681
679
}
682
680
···
688
684
device_link_remove(&pdev->dev, larb->smi_common_dev);
689
685
pm_runtime_disable(&pdev->dev);
690
686
component_del(&pdev->dev, &mtk_smi_larb_component_ops);
687
+
put_device(larb->smi_common_dev);
691
688
}
692
689
693
690
static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
···
922
917
if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
923
918
device_link_remove(&pdev->dev, common->smi_common_dev);
924
919
pm_runtime_disable(&pdev->dev);
920
+
put_device(common->smi_common_dev);
925
921
}
926
922
927
923
static int __maybe_unused mtk_smi_common_resume(struct device *dev)