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net: dsa: mxl-gsw1xx: fix SerDes RX polarity

According to MaxLinear engineer Benny Weng the RX lane of the SerDes
port of the GSW1xx switches is inverted in hardware, and the
SGMII_PHY_RX0_CFG2_INVERT bit is set by default in order to compensate
for that. Hence also set the SGMII_PHY_RX0_CFG2_INVERT bit by default in
gsw1xx_pcs_reset().

Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
Reported-by: Rasmus Villemoes <ravi@prevas.dk>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://patch.msgid.link/ca10e9f780c0152ecf9ae8cbac5bf975802e8f99.1764668951.git.daniel@makrotopia.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Daniel Golle and committed by
Paolo Abeni 5b48f49e 4f0638b1

+7 -1
+7 -1
drivers/net/dsa/lantiq/mxl-gsw1xx.c
··· 255 255 FIELD_PREP(GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT, 256 256 GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF); 257 257 258 - /* TODO: Take care of inverted RX pair once generic property is 258 + /* RX lane seems to be inverted internally, so bit 259 + * GSW1XX_SGMII_PHY_RX0_CFG2_INVERT needs to be set for normal 260 + * (ie. non-inverted) operation. 261 + * 262 + * TODO: Take care of inverted RX pair once generic property is 259 263 * available 260 264 */ 265 + 266 + val |= GSW1XX_SGMII_PHY_RX0_CFG2_INVERT; 261 267 262 268 ret = regmap_write(priv->sgmii, GSW1XX_SGMII_PHY_RX0_CFG2, val); 263 269 if (ret < 0)