accel/ivpu: Update FW Boot API to version 3.29.4

+93 -118

1 changed file

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drivers

accel

ivpu

vpu_boot_api.h

+93 -118

drivers/accel/ivpu/vpu_boot_api.h

··· 1 1 /* SPDX-License-Identifier: MIT */ 2 2 /* 3 - * Copyright (c) 2020-2024, Intel Corporation. 3 + * Copyright (c) 2020-2025, Intel Corporation. 4 + */ 5 + 6 + /** 7 + * @addtogroup Boot 8 + * @{ 9 + */ 10 + 11 + /** 12 + * @file 13 + * @brief Boot API public header file. 4 14 */ 5 15 6 16 #ifndef VPU_BOOT_API_H 7 17 #define VPU_BOOT_API_H 8 18 9 - /* 19 + /** 10 20 * The below values will be used to construct the version info this way: 11 21 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) | 12 22 * VPU_BOOT_API_VER_MINOR; ··· 26 16 * partial info a build error will be generated. 27 17 */ 28 18 29 - /* 19 + /** 30 20 * Major version changes that break backward compatibility. 31 21 * Major version must start from 1 and can only be incremented. 32 22 */ 33 23 #define VPU_BOOT_API_VER_MAJOR 3 34 24 35 - /* 25 + /** 36 26 * Minor version changes when API backward compatibility is preserved. 37 27 * Resets to 0 if Major version is incremented. 38 28 */ 39 - #define VPU_BOOT_API_VER_MINOR 28 29 + #define VPU_BOOT_API_VER_MINOR 29 40 30 41 - /* 31 + /** 42 32 * API header changed (field names, documentation, formatting) but API itself has not been changed 43 33 */ 44 - #define VPU_BOOT_API_VER_PATCH 3 34 + #define VPU_BOOT_API_VER_PATCH 4 45 35 46 - /* 36 + /** 47 37 * Index in the API version table 48 38 * Must be unique for each API 49 39 */ ··· 51 41 52 42 #pragma pack(push, 4) 53 43 54 - /* 44 + /** 55 45 * Firmware image header format 56 46 */ 57 47 #define VPU_FW_HEADER_SIZE 4096 ··· 71 61 u32 firmware_version_size; 72 62 u64 boot_params_load_address; 73 63 u32 api_version[VPU_FW_API_VER_NUM]; 74 - /* Size of memory require for firmware execution */ 64 + /** Size of memory require for firmware execution */ 75 65 u32 runtime_size; 76 66 u32 shave_nn_fw_size; 77 - /* 67 + /** 78 68 * Size of primary preemption buffer, assuming a 2-job submission queue. 79 69 * NOTE: host driver is expected to adapt size accordingly to actual 80 70 * submission queue size and device capabilities. 81 71 */ 82 72 u32 preemption_buffer_1_size; 83 - /* 73 + /** 84 74 * Size of secondary preemption buffer, assuming a 2-job submission queue. 85 75 * NOTE: host driver is expected to adapt size accordingly to actual 86 76 * submission queue size and device capabilities. 87 77 */ 88 78 u32 preemption_buffer_2_size; 89 - /* 79 + /** 90 80 * Maximum preemption buffer size that the FW can use: no need for the host 91 81 * driver to allocate more space than that specified by these fields. 92 82 * A value of 0 means no declared limit. 93 83 */ 94 84 u32 preemption_buffer_1_max_size; 95 85 u32 preemption_buffer_2_max_size; 96 - /* Space reserved for future preemption-related fields. */ 86 + /** Space reserved for future preemption-related fields. */ 97 87 u32 preemption_reserved[4]; 98 - /* FW image read only section start address, 4KB aligned */ 88 + /** FW image read only section start address, 4KB aligned */ 99 89 u64 ro_section_start_address; 100 - /* FW image read only section size, 4KB aligned */ 90 + /** FW image read only section size, 4KB aligned */ 101 91 u32 ro_section_size; 102 92 u32 reserved; 103 93 }; 104 94 105 - /* 95 + /** 106 96 * Firmware boot parameters format 107 97 */ 108 - 109 - #define VPU_BOOT_PLL_COUNT 3 110 - #define VPU_BOOT_PLL_OUT_COUNT 4 111 98 112 99 /** Values for boot_type field */ 113 100 #define VPU_BOOT_TYPE_COLDBOOT 0 ··· 173 166 #define VPU_TRACE_PROC_BIT_ACT_SHV_3 22 174 167 #define VPU_TRACE_PROC_NO_OF_HW_DEVS 23 175 168 176 - /* VPU 30xx HW component IDs are sequential, so define first and last IDs. */ 169 + /** VPU 30xx HW component IDs are sequential, so define first and last IDs. */ 177 170 #define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT 178 171 #define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15 179 172 ··· 182 175 u8 cfg; 183 176 }; 184 177 185 - struct vpu_warm_boot_section { 186 - u32 src; 187 - u32 dst; 188 - u32 size; 189 - u32 core_id; 190 - u32 is_clear_op; 191 - }; 192 - 193 - /* 178 + /** 194 179 * When HW scheduling mode is enabled, a present period is defined. 195 180 * It will be used by VPU to swap between normal and focus priorities 196 181 * to prevent starving of normal priority band (when implemented). ··· 205 206 * Enum for dvfs_mode boot param. 206 207 */ 207 208 enum vpu_governor { 208 - VPU_GOV_DEFAULT = 0, /* Default Governor for the system */ 209 - VPU_GOV_MAX_PERFORMANCE = 1, /* Maximum performance governor */ 210 - VPU_GOV_ON_DEMAND = 2, /* On Demand frequency control governor */ 211 - VPU_GOV_POWER_SAVE = 3, /* Power save governor */ 212 - VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /* On Demand priority based governor */ 209 + VPU_GOV_DEFAULT = 0, /** Default Governor for the system */ 210 + VPU_GOV_MAX_PERFORMANCE = 1, /** Maximum performance governor */ 211 + VPU_GOV_ON_DEMAND = 2, /** On Demand frequency control governor */ 212 + VPU_GOV_POWER_SAVE = 3, /** Power save governor */ 213 + VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /** On Demand priority based governor */ 213 214 }; 214 215 215 216 struct vpu_boot_params { 216 217 u32 magic; 217 218 u32 vpu_id; 218 219 u32 vpu_count; 219 - u32 pad0[5]; 220 - /* Clock frequencies: 0x20 - 0xFF */ 220 + u32 reserved_0[5]; 221 + /** Clock frequencies: 0x20 - 0xFF */ 221 222 u32 frequency; 222 - u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT]; 223 + u32 reserved_1[12]; 223 224 u32 perf_clk_frequency; 224 - u32 pad1[42]; 225 - /* Memory regions: 0x100 - 0x1FF */ 225 + u32 reserved_2[42]; 226 + /** Memory regions: 0x100 - 0x1FF */ 226 227 u64 ipc_header_area_start; 227 228 u32 ipc_header_area_size; 228 229 u64 shared_region_base; ··· 233 234 u32 global_aliased_pio_size; 234 235 u32 autoconfig; 235 236 struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM]; 236 - u64 global_memory_allocator_base; 237 - u32 global_memory_allocator_size; 237 + u32 reserved_3[3]; 238 238 /** 239 239 * ShaveNN FW section VPU base address 240 240 * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base 241 241 */ 242 242 u64 shave_nn_fw_base; 243 - u64 save_restore_ret_address; /* stores the address of FW's restore entry point */ 244 - u32 pad2[43]; 245 - /* IRQ re-direct numbers: 0x200 - 0x2FF */ 243 + u64 save_restore_ret_address; /** stores the address of FW's restore entry point */ 244 + u32 reserved_4[43]; 245 + /** IRQ re-direct numbers: 0x200 - 0x2FF */ 246 246 s32 watchdog_irq_mss; 247 247 s32 watchdog_irq_nce; 248 - /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */ 248 + /** ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */ 249 249 u32 host_to_vpu_irq; 250 - /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */ 250 + /** VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */ 251 251 u32 job_done_irq; 252 - /* VPU -> ARM IRQ line to use to request MMU update. */ 253 - u32 mmu_update_request_irq; 254 - /* ARM -> VPU IRQ line to use to notify of MMU update completion. */ 255 - u32 mmu_update_done_irq; 256 - /* ARM -> VPU IRQ line to use to request power level change. */ 257 - u32 set_power_level_irq; 258 - /* VPU -> ARM IRQ line to use to notify of power level change completion. */ 259 - u32 set_power_level_done_irq; 260 - /* VPU -> ARM IRQ line to use to notify of VPU idle state change */ 261 - u32 set_vpu_idle_update_irq; 262 - /* VPU -> ARM IRQ line to use to request counter reset. */ 263 - u32 metric_query_event_irq; 264 - /* ARM -> VPU IRQ line to use to notify of counter reset completion. */ 265 - u32 metric_query_event_done_irq; 266 - /* VPU -> ARM IRQ line to use to notify of preemption completion. */ 267 - u32 preemption_done_irq; 268 - /* Padding. */ 269 - u32 pad3[52]; 270 - /* Silicon information: 0x300 - 0x3FF */ 252 + /** Padding. */ 253 + u32 reserved_5[60]; 254 + /** Silicon information: 0x300 - 0x3FF */ 271 255 u32 host_version_id; 272 256 u32 si_stepping; 273 257 u64 device_id; ··· 276 294 u32 crit_tracing_buff_size; 277 295 u64 verbose_tracing_buff_addr; 278 296 u32 verbose_tracing_buff_size; 279 - u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */ 297 + u64 verbose_tracing_sw_component_mask; /** TO BE REMOVED */ 280 298 /** 281 299 * Mask of destinations to which logging messages are delivered; bitwise OR 282 300 * of values defined in vpu_trace_destination enum. ··· 290 308 /** Mask of trace message formats supported by the driver */ 291 309 u64 tracing_buff_message_format_mask; 292 310 u64 trace_reserved_1[2]; 293 - /** 294 - * Period at which the VPU reads the temp sensor values into MMIO, on 295 - * platforms where that is necessary (in ms). 0 to disable reads. 296 - */ 297 - u32 temp_sensor_period_ms; 311 + u32 reserved_6; 298 312 /** PLL ratio for efficient clock frequency */ 299 313 u32 pn_freq_pll_ratio; 300 314 /** ··· 325 347 * 1: IPC message required to save state on D0i3 entry flow. 326 348 */ 327 349 u32 d0i3_delayed_entry; 328 - /* Time spent by VPU in D0i3 state */ 350 + /** Time spent by VPU in D0i3 state */ 329 351 u64 d0i3_residency_time_us; 330 - /* Value of VPU perf counter at the time of entering D0i3 state . */ 352 + /** Value of VPU perf counter at the time of entering D0i3 state . */ 331 353 u64 d0i3_entry_vpu_ts; 332 - /* 354 + /** 333 355 * The system time of the host operating system in microseconds. 334 356 * E.g the number of microseconds since 1st of January 1970, or whatever 335 357 * date the host operating system uses to maintain system time. ··· 337 359 * The KMD is required to update this value on every VPU reset. 338 360 */ 339 361 u64 system_time_us; 340 - u32 pad4[2]; 341 - /* 362 + u32 reserved_7[2]; 363 + /** 342 364 * The delta between device monotonic time and the current value of the 343 365 * HW timestamp register, in ticks. Written by the firmware during boot. 344 366 * Can be used by the KMD to calculate device time. 345 367 */ 346 368 u64 device_time_delta_ticks; 347 - u32 pad7[14]; 348 - /* Warm boot information: 0x400 - 0x43F */ 349 - u32 warm_boot_sections_count; 350 - u32 warm_boot_start_address_reference; 351 - u32 warm_boot_section_info_address_offset; 352 - u32 pad5[13]; 353 - /* Power States transitions timestamps: 0x440 - 0x46F*/ 354 - struct { 355 - /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */ 369 + u32 reserved_8[30]; 370 + /** Power States transitions timestamps: 0x440 - 0x46F*/ 371 + struct power_states_timestamps { 372 + /** VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */ 356 373 u64 vpu_active_state_requested; 357 - /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */ 374 + /** VPU_IDLE -> VPU_ACTIVE transition completed timestamp */ 358 375 u64 vpu_active_state_achieved; 359 - /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */ 376 + /** VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */ 360 377 u64 vpu_idle_state_requested; 361 - /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */ 378 + /** VPU_ACTIVE -> VPU_IDLE transition completed timestamp */ 362 379 u64 vpu_idle_state_achieved; 363 - /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */ 380 + /** VPU_IDLE -> VPU_STANDBY transition initiated timestamp */ 364 381 u64 vpu_standby_state_requested; 365 - /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */ 382 + /** VPU_IDLE -> VPU_STANDBY transition completed timestamp */ 366 383 u64 vpu_standby_state_achieved; 367 384 } power_states_timestamps; 368 - /* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */ 385 + /** VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */ 369 386 u32 vpu_scheduling_mode; 370 - /* Present call period in milliseconds. */ 387 + /** Present call period in milliseconds. */ 371 388 u32 vpu_focus_present_timer_ms; 372 - /* VPU ECC Signaling */ 389 + /** VPU ECC Signaling */ 373 390 u32 vpu_uses_ecc_mca_signal; 374 - /* Values defined by POWER_PROFILE* macros */ 391 + /** Values defined by POWER_PROFILE* macros */ 375 392 u32 power_profile; 376 - /* Microsecond value for DCT active cycle */ 393 + /** Microsecond value for DCT active cycle */ 377 394 u32 dct_active_us; 378 - /* Microsecond value for DCT inactive cycle */ 395 + /** Microsecond value for DCT inactive cycle */ 379 396 u32 dct_inactive_us; 380 - /* Unused/reserved: 0x488 - 0xFFF */ 381 - u32 pad6[734]; 397 + /** Unused/reserved: 0x488 - 0xFFF */ 398 + u32 reserved_9[734]; 382 399 }; 383 400 384 - /* Magic numbers set between host and vpu to detect corruption of tracing init */ 401 + /** Magic numbers set between host and vpu to detect corruption of tracing init */ 385 402 #define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE) 386 403 387 - /* Tracing buffer message format definitions */ 404 + /** Tracing buffer message format definitions */ 388 405 #define VPU_TRACING_FORMAT_STRING 0 389 406 #define VPU_TRACING_FORMAT_MIPI 2 390 - /* 407 + /** 391 408 * Header of the tracing buffer. 392 409 * The below defined header will be stored at the beginning of 393 410 * each allocated tracing buffer, followed by a series of 256b ··· 394 421 * @see VPU_TRACING_BUFFER_CANARY 395 422 */ 396 423 u32 host_canary_start; 397 - /* offset from start of buffer for trace entries */ 424 + /** offset from start of buffer for trace entries */ 398 425 u32 read_index; 399 - /* keeps track of wrapping on the reader side */ 426 + /** keeps track of wrapping on the reader side */ 400 427 u32 read_wrap_count; 401 428 u32 pad_to_cache_line_size_0[13]; 402 - /* End of first cache line */ 429 + /** End of first cache line */ 403 430 404 431 /** 405 432 * Magic number set by host to detect corruption 406 433 * @see VPU_TRACING_BUFFER_CANARY 407 434 */ 408 435 u32 vpu_canary_start; 409 - /* offset from start of buffer from write start */ 436 + /** offset from start of buffer from write start */ 410 437 u32 write_index; 411 - /* counter for buffer wrapping */ 438 + /** counter for buffer wrapping */ 412 439 u32 wrap_count; 413 - /* legacy field - do not use */ 440 + /** legacy field - do not use */ 414 441 u32 reserved_0; 415 442 /** 416 - * Size of the log buffer include this header (@header_size) and space 417 - * reserved for all messages. If @alignment` is greater that 0 the @Size 418 - * must be multiple of @Alignment. 443 + * Size of the log buffer including this header (`header_size`) and space 444 + * reserved for all messages. If `alignment` is greater than 0, the `size` 445 + * must be a multiple of `alignment`. 419 446 */ 420 447 u32 size; 421 - /* Header version */ 448 + /** Header version */ 422 449 u16 header_version; 423 - /* Header size */ 450 + /** Header size */ 424 451 u16 header_size; 425 - /* 452 + /** 426 453 * Format of the messages in the trace buffer 427 454 * 0 - null terminated string 428 455 * 1 - size + null terminated string 429 456 * 2 - MIPI-SysT encoding 430 457 */ 431 458 u32 format; 432 - /* 459 + /** 433 460 * Message alignment 434 461 * 0 - messages are place 1 after another 435 462 * n - every message starts and multiple on offset 436 463 */ 437 - u32 alignment; /* 64, 128, 256 */ 438 - /* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */ 464 + u32 alignment; /** 64, 128, 256 */ 465 + /** Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */ 439 466 char name[16]; 440 467 u32 pad_to_cache_line_size_1[4]; 441 - /* End of second cache line */ 468 + /** End of second cache line */ 442 469 }; 443 470 444 471 #pragma pack(pop) 445 472 446 473 #endif 474 + 475 + ///@}

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