Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
amd-xgbe: Add PPS periodic output support
Add support for hardware PPS (Pulse Per Second) output to the
AMD XGBE driver. The implementation enables flexible periodic
output mode, exposing it via the PTP per_out interface.
The driver supports configuring PPS output using the standard
PTP subsystem, allowing precise periodic signal generation for
time synchronization applications.
The feature has been verified using the testptp tool and
oscilloscope.
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20250909113143.1364477-1-Raju.Rangoju@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Raju Rangoju
and committed by
Jakub Kicinski
5b5ba63a
b957665d
+151
-4
+1
-1
drivers/net/ethernet/amd/xgbe/Makefile
+1
-1
drivers/net/ethernet/amd/xgbe/Makefile
+20
-2
drivers/net/ethernet/amd/xgbe/xgbe-common.h
+20
-2
drivers/net/ethernet/amd/xgbe/xgbe-common.h
···
227
227
#define MAC_TICSNR 0x0d5C
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#define MAC_TECNR 0x0d60
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#define MAC_TECSNR 0x0d64
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-
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+
#define MAC_PPSCR 0x0d70
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+
#define MAC_PPS0_TTSR 0x0d80
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+
#define MAC_PPS0_TTNSR 0x0d84
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+
#define MAC_PPS0_INTERVAL 0x0d88
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#define MAC_PPS0_WIDTH 0x0d8C
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#define MAC_QTFCR_INC 4
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#define MAC_MACA_INC 4
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#define MAC_HTR_INC 4
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#define MAC_RQC2_INC 4
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#define MAC_RQC2_Q_PER_REG 4
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+
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/* PPS helpers */
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#define PPSEN0 BIT(4)
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#define MAC_PPSx_TTSR(x) ((MAC_PPS0_TTSR) + ((x) * 0x10))
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#define MAC_PPSx_TTNSR(x) ((MAC_PPS0_TTNSR) + ((x) * 0x10))
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#define MAC_PPSx_INTERVAL(x) ((MAC_PPS0_INTERVAL) + ((x) * 0x10))
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#define MAC_PPSx_WIDTH(x) ((MAC_PPS0_WIDTH) + ((x) * 0x10))
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#define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1)
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+
#define PPS_MINIDX(x) ((x) * 8)
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#define XGBE_PPSCMD_STOP 0x5
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#define XGBE_PPSCMD_START 0x2
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#define XGBE_PPSTARGET_PULSE 0x2
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/* MAC register entry bit positions and sizes */
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#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
···
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#define MAC_VR_SNPSVER_WIDTH 8
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#define MAC_VR_USERVER_INDEX 16
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#define MAC_VR_USERVER_WIDTH 8
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+
#define MAC_PPSx_TTNSR_TRGTBUSY0_INDEX 31
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#define MAC_PPSx_TTNSR_TRGTBUSY0_WIDTH 1
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-
/* MMC register offsets */
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+
/* MMC register offsets */
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#define MMC_CR 0x0800
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#define MMC_RISR 0x0804
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#define MMC_TISR 0x0808
+15
drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+15
drivers/net/ethernet/amd/xgbe/xgbe-drv.c
···
691
691
hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
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hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
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+
/* Sanity check and warn if hardware reports more than supported */
695
+
if (hw_feat->pps_out_num > XGBE_MAX_PPS_OUT) {
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+
dev_warn(pdata->dev,
697
+
"Hardware reports %u PPS outputs, limiting to %u\n",
698
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hw_feat->pps_out_num, XGBE_MAX_PPS_OUT);
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hw_feat->pps_out_num = XGBE_MAX_PPS_OUT;
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}
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+
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if (hw_feat->aux_snap_num > XGBE_MAX_AUX_SNAP) {
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dev_warn(pdata->dev,
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"Hardware reports %u aux snapshot inputs, limiting to %u\n",
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hw_feat->aux_snap_num, XGBE_MAX_AUX_SNAP);
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+
hw_feat->aux_snap_num = XGBE_MAX_AUX_SNAP;
707
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}
708
+
694
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/* Translate the Hash Table size into actual number */
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switch (hw_feat->hash_table_size) {
696
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case 0:
+74
drivers/net/ethernet/amd/xgbe/xgbe-pps.c
+74
drivers/net/ethernet/amd/xgbe/xgbe-pps.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2
+
/*
3
+
* Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
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* Copyright (c) 2014, Synopsys, Inc.
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* All rights reserved
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*
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* Author: Raju Rangoju <Raju.Rangoju@amd.com>
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+
*/
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+
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#include "xgbe.h"
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#include "xgbe-common.h"
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+
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static u32 get_pps_mask(unsigned int x)
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+
{
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return GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x));
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}
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+
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static u32 get_pps_cmd(unsigned int x, u32 val)
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{
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return (val & GENMASK(3, 0)) << PPS_MINIDX(x);
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}
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+
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static u32 get_target_mode_sel(unsigned int x, u32 val)
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{
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return (val & GENMASK(1, 0)) << (PPS_MAXIDX(x) - 2);
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+
}
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+
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int xgbe_pps_config(struct xgbe_prv_data *pdata,
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struct xgbe_pps_config *cfg, int index, bool on)
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{
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unsigned int ppscr = 0;
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unsigned int tnsec;
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u64 period;
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+
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/* Check if target time register is busy */
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tnsec = XGMAC_IOREAD(pdata, MAC_PPSx_TTNSR(index));
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if (XGMAC_GET_BITS(tnsec, MAC_PPSx_TTNSR, TRGTBUSY0))
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return -EBUSY;
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+
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ppscr = XGMAC_IOREAD(pdata, MAC_PPSCR);
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ppscr &= ~get_pps_mask(index);
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+
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if (!on) {
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/* Disable PPS output */
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ppscr |= get_pps_cmd(index, XGBE_PPSCMD_STOP);
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ppscr |= PPSEN0;
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XGMAC_IOWRITE(pdata, MAC_PPSCR, ppscr);
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return 0;
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}
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/* Configure start time */
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XGMAC_IOWRITE(pdata, MAC_PPSx_TTSR(index), cfg->start.tv_sec);
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XGMAC_IOWRITE(pdata, MAC_PPSx_TTNSR(index), cfg->start.tv_nsec);
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+
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period = cfg->period.tv_sec * NSEC_PER_SEC + cfg->period.tv_nsec;
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period = div_u64(period, XGBE_V2_TSTAMP_SSINC);
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+
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if (period < 4)
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return -EINVAL;
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+
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/* Configure interval and pulse width (50% duty cycle) */
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XGMAC_IOWRITE(pdata, MAC_PPSx_INTERVAL(index), period - 1);
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XGMAC_IOWRITE(pdata, MAC_PPSx_WIDTH(index), (period >> 1) - 1);
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+
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/* Enable PPS with pulse train mode */
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ppscr |= get_pps_cmd(index, XGBE_PPSCMD_START);
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ppscr |= get_target_mode_sel(index, XGBE_PPSTARGET_PULSE);
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ppscr |= PPSEN0;
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XGMAC_IOWRITE(pdata, MAC_PPSCR, ppscr);
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return 0;
74
+
}
+25
-1
drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
+25
-1
drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
···
106
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static int xgbe_enable(struct ptp_clock_info *info,
107
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struct ptp_clock_request *request, int on)
108
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{
109
-
return -EOPNOTSUPP;
109
+
struct xgbe_prv_data *pdata = container_of(info, struct xgbe_prv_data,
110
+
ptp_clock_info);
111
+
struct xgbe_pps_config *pps_cfg;
112
+
unsigned long flags;
113
+
int ret;
114
+
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dev_dbg(pdata->dev, "rq->type %d on %d\n", request->type, on);
116
+
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if (request->type != PTP_CLK_REQ_PEROUT)
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return -EOPNOTSUPP;
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+
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pps_cfg = &pdata->pps[request->perout.index];
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+
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pps_cfg->start.tv_sec = request->perout.start.sec;
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pps_cfg->start.tv_nsec = request->perout.start.nsec;
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pps_cfg->period.tv_sec = request->perout.period.sec;
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pps_cfg->period.tv_nsec = request->perout.period.nsec;
126
+
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spin_lock_irqsave(&pdata->tstamp_lock, flags);
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+
ret = xgbe_pps_config(pdata, pps_cfg, request->perout.index, on);
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spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
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return ret;
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}
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void xgbe_ptp_register(struct xgbe_prv_data *pdata)
···
144
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info->adjtime = xgbe_adjtime;
145
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info->gettimex64 = xgbe_gettimex;
146
124
info->settime64 = xgbe_settime;
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info->n_per_out = pdata->hw_feat.pps_out_num;
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+
info->n_ext_ts = pdata->hw_feat.aux_snap_num;
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info->enable = xgbe_enable;
148
128
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clock = ptp_clock_register(info, pdata->dev);
+16
drivers/net/ethernet/amd/xgbe/xgbe.h
+16
drivers/net/ethernet/amd/xgbe/xgbe.h
···
142
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#define XGBE_V2_TSTAMP_SNSINC 0
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#define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000
144
144
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+
/* Define maximum supported values */
146
+
#define XGBE_MAX_PPS_OUT 4
147
+
#define XGBE_MAX_AUX_SNAP 4
148
+
145
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/* Driver PMT macros */
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#define XGMAC_DRIVER_CONTEXT 1
147
151
#define XGMAC_IOCTL_CONTEXT 2
···
677
673
u64 rx_vxlan_csum_errors;
678
674
};
679
675
676
+
struct xgbe_pps_config {
677
+
struct timespec64 start;
678
+
struct timespec64 period;
679
+
};
680
+
680
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struct xgbe_hw_if {
681
682
int (*tx_complete)(struct xgbe_ring_desc *);
682
683
···
1152
1143
struct sk_buff *tx_tstamp_skb;
1153
1144
u64 tx_tstamp;
1154
1145
1146
+
/* Pulse Per Second output */
1147
+
struct xgbe_pps_config pps[XGBE_MAX_PPS_OUT];
1148
+
1155
1149
/* DCB support */
1156
1150
struct ieee_ets *ets;
1157
1151
struct ieee_pfc *pfc;
···
1317
1305
int xgbe_init_ptp(struct xgbe_prv_data *pdata);
1318
1306
void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1319
1307
unsigned int nsec);
1308
+
1309
+
int xgbe_pps_config(struct xgbe_prv_data *pdata, struct xgbe_pps_config *cfg,
1310
+
int index, bool on);
1311
+
1320
1312
#ifdef CONFIG_DEBUG_FS
1321
1313
void xgbe_debugfs_init(struct xgbe_prv_data *);
1322
1314
void xgbe_debugfs_exit(struct xgbe_prv_data *);