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drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5

[Why]
On DCN20 & DCN30, the 6th DPP's & HUBP's are powered on permanently and
cannot be power gated. Thus, when dpp_reset() is invoked for the DPP5,
while it's still powered on, the cached cursor_state
(dpp_base->pos.cur0_ctl.bits.cur0_enable)
and the actual state (CUR0_ENABLE) bit are unsycned. This can cause a
double cursor in full screen with non-native scaling.

[How]
Force disable cursor on DPP5 on plane powerdown for ASICs w/ 6 DPPs/HUBPs.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4673
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 79b3c037f972dcb13e325a8eabfb8da835764e15)
Cc: stable@vger.kernel.org

authored by

Ivan Lipski and committed by
Alex Deucher 5bab4c89 c97da478

+8
+8
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
··· 614 614 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 615 615 * 1, 1000); 616 616 */ 617 + 618 + /* Force disable cursor on plane powerdown on DPP 5 using dpp_force_disable_cursor */ 619 + if (!power_on) { 620 + struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst]; 621 + if (dpp5 && dpp5->funcs->dpp_force_disable_cursor) 622 + dpp5->funcs->dpp_force_disable_cursor(dpp5); 623 + } 624 + 617 625 break; 618 626 default: 619 627 BREAK_TO_DEBUGGER();