Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Olof Johansson:
"Here's the first batch of fixes for this release cycle.
Main diffstat here is the re-deletion of netx. I messed up and most
likely didn't remove the files from the index when I test-merged this
and saw conflicts, and from there on out 'git rerere' remembered the
mistake and I missed checking it. Here it's done again as expected.
Besides that:
- A defconfig refresh + enabling of new drivers for u8500
- i.MX fixlets for i2c/SAI/pinmux
- sleep.S build fix for Davinci
- Broadcom devicetree build/warning fix"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: defconfig: u8500: Add new drivers
ARM: defconfig: u8500: Refresh defconfig
ARM: dts: bcm: bcm47094: add missing #cells for mdio-bus-mux
ARM: davinci: fix sleep.S build error on ARMv4
arm64: dts: imx8mq: fix SAI compatible
arm64: dts: imx8mm: Correct SAI3 RXC/TXFS pin's mux option #1
ARM: dts: imx6ul: fix clock frequency property name of I2C buses
ARM: Delete netx a second time
ARM: dts: imx7ulp: Fix usb-phy unit address format
+33
-1886
-5
arch/arm/Kconfig.debug
-5
arch/arm/Kconfig.debug
···
1535
1535
DEBUG_IMX7D_UART
1536
1536
default "debug/ks8695.S" if DEBUG_KS8695_UART
1537
1537
default "debug/msm.S" if DEBUG_QCOM_UARTDM
1538
-
default "debug/netx.S" if DEBUG_NETX_UART
1539
1538
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
1540
1539
default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
1541
1540
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
···
1574
1575
1575
1576
config DEBUG_UART_PHYS
1576
1577
hex "Physical base address of debug UART"
1577
-
default 0x00100a00 if DEBUG_NETX_UART
1578
1578
default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
1579
1579
default 0x01c28000 if DEBUG_SUNXI_UART0
1580
1580
default 0x01c28400 if DEBUG_SUNXI_UART1
···
1698
1700
DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1699
1701
DEBUG_LL_UART_EFM32 || \
1700
1702
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1701
-
DEBUG_NETX_UART || \
1702
1703
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
1703
1704
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
1704
1705
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
···
1714
1717
default 0xc881f000 if DEBUG_RV1108_UART2
1715
1718
default 0xc8821000 if DEBUG_RV1108_UART1
1716
1719
default 0xc8912000 if DEBUG_RV1108_UART0
1717
-
default 0xe0000a00 if DEBUG_NETX_UART
1718
1720
default 0xe0010fe0 if ARCH_RPC
1719
1721
default 0xf0000be0 if ARCH_EBSA110
1720
1722
default 0xf0010000 if DEBUG_ASM9260_UART
···
1818
1822
default DEBUG_UART_PHYS if !MMU
1819
1823
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1820
1824
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
1821
-
DEBUG_NETX_UART || \
1822
1825
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
1823
1826
DEBUG_S3C64XX_UART || \
1824
1827
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
+3
arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+3
arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+1
-1
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+1
-1
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+1
-1
arch/arm/boot/dts/imx6ul-geam.dts
+1
-1
arch/arm/boot/dts/imx6ul-geam.dts
+1
-1
arch/arm/boot/dts/imx6ul-isiot.dtsi
+1
-1
arch/arm/boot/dts/imx6ul-isiot.dtsi
+1
-1
arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+1
-1
arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+2
-2
arch/arm/boot/dts/imx6ul-pico-pi.dts
+2
-2
arch/arm/boot/dts/imx6ul-pico-pi.dts
···
43
43
};
44
44
45
45
&i2c2 {
46
-
clock_frequency = <100000>;
46
+
clock-frequency = <100000>;
47
47
pinctrl-names = "default";
48
48
pinctrl-0 = <&pinctrl_i2c2>;
49
49
status = "okay";
···
58
58
};
59
59
60
60
&i2c3 {
61
-
clock_frequency = <100000>;
61
+
clock-frequency = <100000>;
62
62
pinctrl-names = "default";
63
63
pinctrl-0 = <&pinctrl_i2c3>;
64
64
status = "okay";
+1
-1
arch/arm/boot/dts/imx7ulp.dtsi
+1
-1
arch/arm/boot/dts/imx7ulp.dtsi
+19
-15
arch/arm/configs/u8500_defconfig
+19
-15
arch/arm/configs/u8500_defconfig
···
4
4
CONFIG_HIGH_RES_TIMERS=y
5
5
CONFIG_BLK_DEV_INITRD=y
6
6
CONFIG_KALLSYMS_ALL=y
7
-
CONFIG_MODULES=y
8
-
CONFIG_MODULE_UNLOAD=y
9
-
# CONFIG_BLK_DEV_BSG is not set
10
-
CONFIG_PARTITION_ADVANCED=y
11
7
CONFIG_ARCH_U8500=y
12
-
CONFIG_MACH_HREFV60=y
13
-
CONFIG_MACH_SNOWBALL=y
14
8
CONFIG_SMP=y
15
9
CONFIG_NR_CPUS=2
16
-
CONFIG_PREEMPT=y
17
-
CONFIG_AEABI=y
18
10
CONFIG_HIGHMEM=y
19
11
CONFIG_ARM_APPENDED_DTB=y
20
12
CONFIG_ARM_ATAG_DTB_COMPAT=y
···
17
25
CONFIG_ARM_U8500_CPUIDLE=y
18
26
CONFIG_VFP=y
19
27
CONFIG_NEON=y
28
+
CONFIG_MODULES=y
29
+
CONFIG_MODULE_UNLOAD=y
30
+
# CONFIG_BLK_DEV_BSG is not set
31
+
CONFIG_PARTITION_ADVANCED=y
32
+
CONFIG_CMA=y
20
33
CONFIG_NET=y
21
34
CONFIG_PACKET=y
22
35
CONFIG_UNIX=y
···
44
47
CONFIG_SMSC_PHY=y
45
48
CONFIG_CW1200=y
46
49
CONFIG_CW1200_WLAN_SDIO=y
47
-
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
48
50
CONFIG_INPUT_EVDEV=y
49
51
# CONFIG_KEYBOARD_ATKBD is not set
50
52
CONFIG_KEYBOARD_GPIO=y
···
59
63
CONFIG_RMI4_I2C=y
60
64
CONFIG_RMI4_F11=y
61
65
# CONFIG_SERIO is not set
62
-
CONFIG_VT_HW_CONSOLE_BINDING=y
63
66
# CONFIG_LEGACY_PTYS is not set
64
67
CONFIG_SERIAL_AMBA_PL011=y
65
68
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
···
67
72
CONFIG_SPI_PL022=y
68
73
CONFIG_GPIO_STMPE=y
69
74
CONFIG_GPIO_TC3589X=y
75
+
CONFIG_SENSORS_IIO_HWMON=y
70
76
CONFIG_THERMAL=y
71
77
CONFIG_CPU_THERMAL=y
72
78
CONFIG_WATCHDOG=y
···
75
79
CONFIG_MFD_TC3589X=y
76
80
CONFIG_REGULATOR_AB8500=y
77
81
CONFIG_REGULATOR_GPIO=y
82
+
CONFIG_DRM=y
83
+
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
84
+
CONFIG_DRM_LIMA=y
85
+
CONFIG_DRM_MCDE=y
86
+
CONFIG_BACKLIGHT_CLASS_DEVICE=y
87
+
CONFIG_BACKLIGHT_GENERIC=m
88
+
CONFIG_LOGO=y
78
89
CONFIG_SOUND=y
79
90
CONFIG_SND=y
80
91
CONFIG_SND_SOC=y
···
90
87
CONFIG_USB=y
91
88
CONFIG_USB_MUSB_HDRC=y
92
89
CONFIG_USB_MUSB_UX500=y
90
+
CONFIG_MUSB_PIO_ONLY=y
93
91
CONFIG_AB8500_USB=y
94
92
CONFIG_USB_GADGET=y
95
93
CONFIG_USB_ETH=m
···
107
103
CONFIG_RTC_DRV_PL031=y
108
104
CONFIG_DMADEVICES=y
109
105
CONFIG_STE_DMA40=y
106
+
CONFIG_HWSPINLOCK=y
110
107
CONFIG_HSEM_U8500=y
111
108
CONFIG_IIO=y
112
109
CONFIG_IIO_SW_TRIGGER=y
···
131
126
CONFIG_ROOT_NFS=y
132
127
CONFIG_NLS_CODEPAGE_437=y
133
128
CONFIG_NLS_ISO8859_1=y
129
+
CONFIG_CRYPTO_DEV_UX500=y
130
+
CONFIG_CRYPTO_DEV_UX500_CRYP=y
131
+
CONFIG_CRYPTO_DEV_UX500_HASH=y
132
+
CONFIG_CRYPTO_DEV_UX500_DEBUG=y
134
133
CONFIG_PRINTK_TIME=y
135
134
CONFIG_DEBUG_INFO=y
136
135
CONFIG_DEBUG_FS=y
137
136
CONFIG_MAGIC_SYSRQ=y
138
137
CONFIG_DEBUG_KERNEL=y
139
138
# CONFIG_SCHED_DEBUG is not set
140
-
# CONFIG_DEBUG_PREEMPT is not set
141
139
# CONFIG_FTRACE is not set
142
140
CONFIG_DEBUG_USER=y
143
141
CONFIG_CORESIGHT=y
144
142
CONFIG_CORESIGHT_SINK_TPIU=y
145
143
CONFIG_CORESIGHT_SINK_ETBV10=y
146
144
CONFIG_CORESIGHT_SOURCE_ETM3X=y
147
-
CONFIG_CRYPTO_DEV_UX500=y
148
-
CONFIG_CRYPTO_DEV_UX500_CRYP=y
149
-
CONFIG_CRYPTO_DEV_UX500_HASH=y
150
-
CONFIG_CRYPTO_DEV_UX500_DEBUG=y
+1
arch/arm/mach-davinci/sleep.S
+1
arch/arm/mach-davinci/sleep.S
-22
arch/arm/mach-netx/Kconfig
-22
arch/arm/mach-netx/Kconfig
···
1
-
# SPDX-License-Identifier: GPL-2.0-only
2
-
menu "NetX Implementations"
3
-
depends on ARCH_NETX
4
-
5
-
config MACH_NXDKN
6
-
bool "Enable Hilscher nxdkn Eval Board support"
7
-
help
8
-
Board support for the Hilscher NetX Eval Board
9
-
10
-
config MACH_NXDB500
11
-
bool "Enable Hilscher nxdb500 Eval Board support"
12
-
select ARM_AMBA
13
-
help
14
-
Board support for the Hilscher nxdb500 Eval Board
15
-
16
-
config MACH_NXEB500HMI
17
-
bool "Enable Hilscher nxeb500hmi Eval Board support"
18
-
select ARM_AMBA
19
-
help
20
-
Board support for the Hilscher nxeb500hmi Eval Board
21
-
22
-
endmenu
-13
arch/arm/mach-netx/Makefile
-13
arch/arm/mach-netx/Makefile
···
1
-
# SPDX-License-Identifier: GPL-2.0-only
2
-
#
3
-
# Makefile for the linux kernel.
4
-
#
5
-
6
-
# Object file lists.
7
-
8
-
obj-y += time.o generic.o pfifo.o xc.o
9
-
10
-
# Specific board support
11
-
obj-$(CONFIG_MACH_NXDKN) += nxdkn.o
12
-
obj-$(CONFIG_MACH_NXDB500) += nxdb500.o fb.o
13
-
obj-$(CONFIG_MACH_NXEB500HMI) += nxeb500hmi.o fb.o
-3
arch/arm/mach-netx/Makefile.boot
-3
arch/arm/mach-netx/Makefile.boot
-65
arch/arm/mach-netx/fb.c
-65
arch/arm/mach-netx/fb.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/fb.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/device.h>
9
-
#include <linux/init.h>
10
-
#include <linux/dma-mapping.h>
11
-
#include <linux/amba/bus.h>
12
-
#include <linux/amba/clcd.h>
13
-
#include <linux/err.h>
14
-
#include <linux/gfp.h>
15
-
16
-
#include <asm/irq.h>
17
-
18
-
#include <mach/netx-regs.h>
19
-
#include <mach/hardware.h>
20
-
21
-
static struct clcd_panel *netx_panel;
22
-
23
-
void netx_clcd_enable(struct clcd_fb *fb)
24
-
{
25
-
}
26
-
27
-
int netx_clcd_setup(struct clcd_fb *fb)
28
-
{
29
-
dma_addr_t dma;
30
-
31
-
fb->panel = netx_panel;
32
-
33
-
fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, 1024 * 1024, &dma,
34
-
GFP_KERNEL);
35
-
if (!fb->fb.screen_base) {
36
-
printk(KERN_ERR "CLCD: unable to map framebuffer\n");
37
-
return -ENOMEM;
38
-
}
39
-
40
-
fb->fb.fix.smem_start = dma;
41
-
fb->fb.fix.smem_len = 1024*1024;
42
-
43
-
return 0;
44
-
}
45
-
46
-
int netx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
47
-
{
48
-
return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
49
-
fb->fb.fix.smem_start, fb->fb.fix.smem_len);
50
-
}
51
-
52
-
void netx_clcd_remove(struct clcd_fb *fb)
53
-
{
54
-
dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base,
55
-
fb->fb.fix.smem_start);
56
-
}
57
-
58
-
static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
59
-
60
-
int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
61
-
{
62
-
netx_panel = panel;
63
-
fb_device.dev.platform_data = board;
64
-
return amba_device_register(&fb_device, &iomem_resource);
65
-
}
-12
arch/arm/mach-netx/fb.h
-12
arch/arm/mach-netx/fb.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/fb.h
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
void netx_clcd_enable(struct clcd_fb *fb);
9
-
int netx_clcd_setup(struct clcd_fb *fb);
10
-
int netx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
11
-
void netx_clcd_remove(struct clcd_fb *fb);
12
-
int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel);
-182
arch/arm/mach-netx/generic.c
-182
arch/arm/mach-netx/generic.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/generic.c
4
-
*
5
-
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/device.h>
9
-
#include <linux/init.h>
10
-
#include <linux/kernel.h>
11
-
#include <linux/module.h>
12
-
#include <linux/platform_device.h>
13
-
#include <linux/io.h>
14
-
#include <linux/irqchip/arm-vic.h>
15
-
#include <linux/reboot.h>
16
-
#include <mach/hardware.h>
17
-
#include <asm/mach/map.h>
18
-
#include <mach/netx-regs.h>
19
-
#include <asm/mach/irq.h>
20
-
21
-
static struct map_desc netx_io_desc[] __initdata = {
22
-
{
23
-
.virtual = NETX_IO_VIRT,
24
-
.pfn = __phys_to_pfn(NETX_IO_PHYS),
25
-
.length = NETX_IO_SIZE,
26
-
.type = MT_DEVICE
27
-
}
28
-
};
29
-
30
-
void __init netx_map_io(void)
31
-
{
32
-
iotable_init(netx_io_desc, ARRAY_SIZE(netx_io_desc));
33
-
}
34
-
35
-
static struct resource netx_rtc_resources[] = {
36
-
[0] = {
37
-
.start = 0x00101200,
38
-
.end = 0x00101220,
39
-
.flags = IORESOURCE_MEM,
40
-
},
41
-
};
42
-
43
-
static struct platform_device netx_rtc_device = {
44
-
.name = "netx-rtc",
45
-
.id = 0,
46
-
.num_resources = ARRAY_SIZE(netx_rtc_resources),
47
-
.resource = netx_rtc_resources,
48
-
};
49
-
50
-
static struct platform_device *devices[] __initdata = {
51
-
&netx_rtc_device,
52
-
};
53
-
54
-
#if 0
55
-
#define DEBUG_IRQ(fmt...) printk(fmt)
56
-
#else
57
-
#define DEBUG_IRQ(fmt...) while (0) {}
58
-
#endif
59
-
60
-
static void netx_hif_demux_handler(struct irq_desc *desc)
61
-
{
62
-
unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
63
-
unsigned int stat;
64
-
65
-
stat = ((readl(NETX_DPMAS_INT_EN) &
66
-
readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f;
67
-
68
-
while (stat) {
69
-
if (stat & 1) {
70
-
DEBUG_IRQ("handling irq %d\n", irq);
71
-
generic_handle_irq(irq);
72
-
}
73
-
irq++;
74
-
stat >>= 1;
75
-
}
76
-
}
77
-
78
-
static int
79
-
netx_hif_irq_type(struct irq_data *d, unsigned int type)
80
-
{
81
-
unsigned int val, irq;
82
-
83
-
val = readl(NETX_DPMAS_IF_CONF1);
84
-
85
-
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
86
-
87
-
if (type & IRQ_TYPE_EDGE_RISING) {
88
-
DEBUG_IRQ("rising edges\n");
89
-
val |= (1 << 26) << irq;
90
-
}
91
-
if (type & IRQ_TYPE_EDGE_FALLING) {
92
-
DEBUG_IRQ("falling edges\n");
93
-
val &= ~((1 << 26) << irq);
94
-
}
95
-
if (type & IRQ_TYPE_LEVEL_LOW) {
96
-
DEBUG_IRQ("low level\n");
97
-
val &= ~((1 << 26) << irq);
98
-
}
99
-
if (type & IRQ_TYPE_LEVEL_HIGH) {
100
-
DEBUG_IRQ("high level\n");
101
-
val |= (1 << 26) << irq;
102
-
}
103
-
104
-
writel(val, NETX_DPMAS_IF_CONF1);
105
-
106
-
return 0;
107
-
}
108
-
109
-
static void
110
-
netx_hif_ack_irq(struct irq_data *d)
111
-
{
112
-
unsigned int val, irq;
113
-
114
-
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
115
-
writel((1 << 24) << irq, NETX_DPMAS_INT_STAT);
116
-
117
-
val = readl(NETX_DPMAS_INT_EN);
118
-
val &= ~((1 << 24) << irq);
119
-
writel(val, NETX_DPMAS_INT_EN);
120
-
121
-
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
122
-
}
123
-
124
-
static void
125
-
netx_hif_mask_irq(struct irq_data *d)
126
-
{
127
-
unsigned int val, irq;
128
-
129
-
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
130
-
val = readl(NETX_DPMAS_INT_EN);
131
-
val &= ~((1 << 24) << irq);
132
-
writel(val, NETX_DPMAS_INT_EN);
133
-
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
134
-
}
135
-
136
-
static void
137
-
netx_hif_unmask_irq(struct irq_data *d)
138
-
{
139
-
unsigned int val, irq;
140
-
141
-
irq = d->irq - NETX_IRQ_HIF_CHAINED(0);
142
-
val = readl(NETX_DPMAS_INT_EN);
143
-
val |= (1 << 24) << irq;
144
-
writel(val, NETX_DPMAS_INT_EN);
145
-
DEBUG_IRQ("%s: irq %d\n", __func__, d->irq);
146
-
}
147
-
148
-
static struct irq_chip netx_hif_chip = {
149
-
.irq_ack = netx_hif_ack_irq,
150
-
.irq_mask = netx_hif_mask_irq,
151
-
.irq_unmask = netx_hif_unmask_irq,
152
-
.irq_set_type = netx_hif_irq_type,
153
-
};
154
-
155
-
void __init netx_init_irq(void)
156
-
{
157
-
int irq;
158
-
159
-
vic_init(io_p2v(NETX_PA_VIC), NETX_IRQ_VIC_START, ~0, 0);
160
-
161
-
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
162
-
irq_set_chip_and_handler(irq, &netx_hif_chip,
163
-
handle_level_irq);
164
-
irq_clear_status_flags(irq, IRQ_NOREQUEST);
165
-
}
166
-
167
-
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
168
-
irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
169
-
}
170
-
171
-
static int __init netx_init(void)
172
-
{
173
-
return platform_add_devices(devices, ARRAY_SIZE(devices));
174
-
}
175
-
176
-
subsys_initcall(netx_init);
177
-
178
-
void netx_restart(enum reboot_mode mode, const char *cmd)
179
-
{
180
-
writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
181
-
NETX_SYSTEM_RES_CR);
182
-
}
-14
arch/arm/mach-netx/generic.h
-14
arch/arm/mach-netx/generic.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/generic.h
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/reboot.h>
9
-
10
-
extern void __init netx_map_io(void);
11
-
extern void __init netx_init_irq(void);
12
-
extern void netx_restart(enum reboot_mode, const char *);
13
-
14
-
extern void netx_timer_init(void);
-27
arch/arm/mach-netx/include/mach/hardware.h
-27
arch/arm/mach-netx/include/mach/hardware.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/include/mach/hardware.h
4
-
*
5
-
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
#ifndef __ASM_ARCH_HARDWARE_H
8
-
#define __ASM_ARCH_HARDWARE_H
9
-
10
-
#define NETX_IO_PHYS 0x00100000
11
-
#define NETX_IO_VIRT 0xe0000000
12
-
#define NETX_IO_SIZE 0x00100000
13
-
14
-
#define SRAM_INTERNAL_PHYS_0 0x00000
15
-
#define SRAM_INTERNAL_PHYS_1 0x08000
16
-
#define SRAM_INTERNAL_PHYS_2 0x10000
17
-
#define SRAM_INTERNAL_PHYS_3 0x18000
18
-
#define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000)
19
-
20
-
#define XPEC_MEM_SIZE 0x4000
21
-
#define XMAC_MEM_SIZE 0x1000
22
-
#define SRAM_MEM_SIZE 0x8000
23
-
24
-
#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
25
-
#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
26
-
27
-
#endif
-58
arch/arm/mach-netx/include/mach/irqs.h
-58
arch/arm/mach-netx/include/mach/irqs.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/include/mach/irqs.h
4
-
*
5
-
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#define NETX_IRQ_VIC_START 64
9
-
#define NETX_IRQ_SOFTINT (NETX_IRQ_VIC_START + 0)
10
-
#define NETX_IRQ_TIMER0 (NETX_IRQ_VIC_START + 1)
11
-
#define NETX_IRQ_TIMER1 (NETX_IRQ_VIC_START + 2)
12
-
#define NETX_IRQ_TIMER2 (NETX_IRQ_VIC_START + 3)
13
-
#define NETX_IRQ_SYSTIME_NS (NETX_IRQ_VIC_START + 4)
14
-
#define NETX_IRQ_SYSTIME_S (NETX_IRQ_VIC_START + 5)
15
-
#define NETX_IRQ_GPIO_15 (NETX_IRQ_VIC_START + 6)
16
-
#define NETX_IRQ_WATCHDOG (NETX_IRQ_VIC_START + 7)
17
-
#define NETX_IRQ_UART0 (NETX_IRQ_VIC_START + 8)
18
-
#define NETX_IRQ_UART1 (NETX_IRQ_VIC_START + 9)
19
-
#define NETX_IRQ_UART2 (NETX_IRQ_VIC_START + 10)
20
-
#define NETX_IRQ_USB (NETX_IRQ_VIC_START + 11)
21
-
#define NETX_IRQ_SPI (NETX_IRQ_VIC_START + 12)
22
-
#define NETX_IRQ_I2C (NETX_IRQ_VIC_START + 13)
23
-
#define NETX_IRQ_LCD (NETX_IRQ_VIC_START + 14)
24
-
#define NETX_IRQ_HIF (NETX_IRQ_VIC_START + 15)
25
-
#define NETX_IRQ_GPIO_0_14 (NETX_IRQ_VIC_START + 16)
26
-
#define NETX_IRQ_XPEC0 (NETX_IRQ_VIC_START + 17)
27
-
#define NETX_IRQ_XPEC1 (NETX_IRQ_VIC_START + 18)
28
-
#define NETX_IRQ_XPEC2 (NETX_IRQ_VIC_START + 19)
29
-
#define NETX_IRQ_XPEC3 (NETX_IRQ_VIC_START + 20)
30
-
#define NETX_IRQ_XPEC(no) (NETX_IRQ_VIC_START + 17 + (no))
31
-
#define NETX_IRQ_MSYNC0 (NETX_IRQ_VIC_START + 21)
32
-
#define NETX_IRQ_MSYNC1 (NETX_IRQ_VIC_START + 22)
33
-
#define NETX_IRQ_MSYNC2 (NETX_IRQ_VIC_START + 23)
34
-
#define NETX_IRQ_MSYNC3 (NETX_IRQ_VIC_START + 24)
35
-
#define NETX_IRQ_IRQ_PHY (NETX_IRQ_VIC_START + 25)
36
-
#define NETX_IRQ_ISO_AREA (NETX_IRQ_VIC_START + 26)
37
-
/* int 27 is reserved */
38
-
/* int 28 is reserved */
39
-
#define NETX_IRQ_TIMER3 (NETX_IRQ_VIC_START + 29)
40
-
#define NETX_IRQ_TIMER4 (NETX_IRQ_VIC_START + 30)
41
-
/* int 31 is reserved */
42
-
43
-
#define NETX_IRQS (NETX_IRQ_VIC_START + 32)
44
-
45
-
/* for multiplexed irqs on gpio 0..14 */
46
-
#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
47
-
#define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14)
48
-
49
-
/* Host interface interrupts */
50
-
#define NETX_IRQ_HIF_CHAINED(x) (NETX_IRQ_GPIO_LAST + 1 + (x))
51
-
#define NETX_IRQ_HIF_PIO35 NETX_IRQ_HIF_CHAINED(0)
52
-
#define NETX_IRQ_HIF_PIO36 NETX_IRQ_HIF_CHAINED(1)
53
-
#define NETX_IRQ_HIF_PIO40 NETX_IRQ_HIF_CHAINED(2)
54
-
#define NETX_IRQ_HIF_PIO47 NETX_IRQ_HIF_CHAINED(3)
55
-
#define NETX_IRQ_HIF_PIO72 NETX_IRQ_HIF_CHAINED(4)
56
-
#define NETX_IRQ_HIF_LAST NETX_IRQ_HIF_CHAINED(4)
57
-
58
-
#define NR_IRQS (NETX_IRQ_HIF_LAST + 1)
-420
arch/arm/mach-netx/include/mach/netx-regs.h
-420
arch/arm/mach-netx/include/mach/netx-regs.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/include/mach/netx-regs.h
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#ifndef __ASM_ARCH_NETX_REGS_H
9
-
#define __ASM_ARCH_NETX_REGS_H
10
-
11
-
/* offsets relative to the beginning of the io space */
12
-
#define NETX_OFS_SYSTEM 0x00000
13
-
#define NETX_OFS_MEMCR 0x00100
14
-
#define NETX_OFS_DPMAS 0x03000
15
-
#define NETX_OFS_GPIO 0x00800
16
-
#define NETX_OFS_PIO 0x00900
17
-
#define NETX_OFS_UART0 0x00a00
18
-
#define NETX_OFS_UART1 0x00a40
19
-
#define NETX_OFS_UART2 0x00a80
20
-
#define NETX_OF_MIIMU 0x00b00
21
-
#define NETX_OFS_SPI 0x00c00
22
-
#define NETX_OFS_I2C 0x00d00
23
-
#define NETX_OFS_SYSTIME 0x01100
24
-
#define NETX_OFS_RTC 0x01200
25
-
#define NETX_OFS_EXTBUS 0x03600
26
-
#define NETX_OFS_LCD 0x04000
27
-
#define NETX_OFS_USB 0x20000
28
-
#define NETX_OFS_XMAC0 0x60000
29
-
#define NETX_OFS_XMAC1 0x61000
30
-
#define NETX_OFS_XMAC2 0x62000
31
-
#define NETX_OFS_XMAC3 0x63000
32
-
#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
33
-
#define NETX_OFS_PFIFO 0x64000
34
-
#define NETX_OFS_XPEC0 0x70000
35
-
#define NETX_OFS_XPEC1 0x74000
36
-
#define NETX_OFS_XPEC2 0x78000
37
-
#define NETX_OFS_XPEC3 0x7c000
38
-
#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
39
-
#define NETX_OFS_VIC 0xff000
40
-
41
-
/* physical addresses */
42
-
#define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM)
43
-
#define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR)
44
-
#define NETX_PA_DPMAS (NETX_IO_PHYS + NETX_OFS_DPMAS)
45
-
#define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO)
46
-
#define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO)
47
-
#define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0)
48
-
#define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1)
49
-
#define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2)
50
-
#define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU)
51
-
#define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI)
52
-
#define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C)
53
-
#define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME)
54
-
#define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC)
55
-
#define NETX_PA_EXTBUS (NETX_IO_PHYS + NETX_OFS_EXTBUS)
56
-
#define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD)
57
-
#define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB)
58
-
#define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0)
59
-
#define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1)
60
-
#define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2)
61
-
#define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3)
62
-
#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no))
63
-
#define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO)
64
-
#define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0)
65
-
#define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1)
66
-
#define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2)
67
-
#define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3)
68
-
#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no))
69
-
#define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC)
70
-
71
-
/* virtual addresses */
72
-
#define NETX_VA_SYSTEM (NETX_IO_VIRT + NETX_OFS_SYSTEM)
73
-
#define NETX_VA_MEMCR (NETX_IO_VIRT + NETX_OFS_MEMCR)
74
-
#define NETX_VA_DPMAS (NETX_IO_VIRT + NETX_OFS_DPMAS)
75
-
#define NETX_VA_GPIO (NETX_IO_VIRT + NETX_OFS_GPIO)
76
-
#define NETX_VA_PIO (NETX_IO_VIRT + NETX_OFS_PIO)
77
-
#define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0)
78
-
#define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1)
79
-
#define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2)
80
-
#define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU)
81
-
#define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI)
82
-
#define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C)
83
-
#define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME)
84
-
#define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC)
85
-
#define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS)
86
-
#define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD)
87
-
#define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB)
88
-
#define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0)
89
-
#define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1)
90
-
#define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2)
91
-
#define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3)
92
-
#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
93
-
#define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO)
94
-
#define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0)
95
-
#define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1)
96
-
#define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2)
97
-
#define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3)
98
-
#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
99
-
#define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC)
100
-
101
-
/*********************************
102
-
* System functions *
103
-
*********************************/
104
-
105
-
/* Registers */
106
-
#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
107
-
#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
108
-
#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
109
-
#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
110
-
111
-
/* FIXME: Docs are not consistent */
112
-
/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */
113
-
#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c)
114
-
115
-
#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
116
-
#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
117
-
#define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70)
118
-
#define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200)
119
-
#define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204)
120
-
#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
121
-
#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
122
-
123
-
/* Bits */
124
-
#define NETX_SYSTEM_RES_CR_RSTIN (1<<0)
125
-
#define NETX_SYSTEM_RES_CR_WDG_RES (1<<1)
126
-
#define NETX_SYSTEM_RES_CR_HOST_RES (1<<2)
127
-
#define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3)
128
-
#define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4)
129
-
#define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5)
130
-
#define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6)
131
-
#define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7)
132
-
#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
133
-
#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
134
-
#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
135
-
#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
136
-
#define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20)
137
-
#define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21)
138
-
#define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22)
139
-
#define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23)
140
-
#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24)
141
-
#define NETX_SYSTEM_RES_CR_RSTOUT (1<<25)
142
-
#define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26)
143
-
144
-
#define PHY_CONTROL_RESET (1<<31)
145
-
#define PHY_CONTROL_SIM_BYP (1<<30)
146
-
#define PHY_CONTROL_CLK_XLATIN (1<<29)
147
-
#define PHY_CONTROL_PHY1_EN (1<<21)
148
-
#define PHY_CONTROL_PHY1_NP_MSG_CODE
149
-
#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17)
150
-
#define PHY_CONTROL_PHY1_FIXMODE (1<<16)
151
-
#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13)
152
-
#define PHY_CONTROL_PHY0_EN (1<<12)
153
-
#define PHY_CONTROL_PHY0_NP_MSG_CODE
154
-
#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8)
155
-
#define PHY_CONTROL_PHY0_FIXMODE (1<<7)
156
-
#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4)
157
-
#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
158
-
159
-
#define PHY_MODE_10BASE_T_HALF 0
160
-
#define PHY_MODE_10BASE_T_FULL 1
161
-
#define PHY_MODE_100BASE_TX_FX_FULL 2
162
-
#define PHY_MODE_100BASE_TX_FX_HALF 3
163
-
#define PHY_MODE_100BASE_TX_HALF 4
164
-
#define PHY_MODE_REPEATER 5
165
-
#define PHY_MODE_POWER_DOWN 6
166
-
#define PHY_MODE_ALL 7
167
-
168
-
/* Bits */
169
-
#define VECT_CNTL_ENABLE (1 << 5)
170
-
171
-
/*******************************
172
-
* GPIO and timer module *
173
-
*******************************/
174
-
175
-
/* Registers */
176
-
#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
177
-
#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
178
-
#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
179
-
#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
180
-
#define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2))
181
-
#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
182
-
#define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc)
183
-
#define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0)
184
-
#define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4)
185
-
#define NETX_GPIO_LINE NETX_GPIO_REG(0xc8)
186
-
#define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0)
187
-
188
-
/* Bits */
189
-
#define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0)
190
-
#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1)
191
-
#define NETX_GPIO_CFG_IOCFG_GP_UART (0x2)
192
-
#define NETX_GPIO_CFG_INV (1<<2)
193
-
#define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3)
194
-
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
195
-
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
196
-
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3)
197
-
#define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5)
198
-
#define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5)
199
-
#define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5)
200
-
#define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5)
201
-
#define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5)
202
-
#define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5)
203
-
204
-
#define NETX_GPIO_COUNTER_CTRL_RUN (1<<0)
205
-
#define NETX_GPIO_COUNTER_CTRL_SYM (1<<1)
206
-
#define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2)
207
-
#define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3)
208
-
#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4)
209
-
#define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5)
210
-
#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6)
211
-
#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
212
-
213
-
#define GPIO_BIT(gpio) (1<<(gpio))
214
-
#define COUNTER_BIT(counter) ((1<<16)<<(counter))
215
-
216
-
/*******************************
217
-
* PIO *
218
-
*******************************/
219
-
220
-
/* Registers */
221
-
#define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
222
-
#define NETX_PIO_INPIO NETX_PIO_REG(0x0)
223
-
#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
224
-
#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
225
-
226
-
/*******************************
227
-
* MII Unit *
228
-
*******************************/
229
-
230
-
/* Registers */
231
-
#define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
232
-
233
-
/* Bits */
234
-
#define MIIMU_SNRDY (1<<0)
235
-
#define MIIMU_PREAMBLE (1<<1)
236
-
#define MIIMU_OPMODE_WRITE (1<<2)
237
-
#define MIIMU_MDC_PERIOD (1<<3)
238
-
#define MIIMU_PHY_NRES (1<<4)
239
-
#define MIIMU_RTA (1<<5)
240
-
#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
241
-
#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
242
-
#define MIIMU_DATA(data) (((data) & 0xffff) << 16)
243
-
244
-
/*******************************
245
-
* xmac / xpec *
246
-
*******************************/
247
-
248
-
/* XPEC register offsets relative to NETX_VA_XPEC(no) */
249
-
#define NETX_XPEC_R0_OFS 0x00
250
-
#define NETX_XPEC_R1_OFS 0x04
251
-
#define NETX_XPEC_R2_OFS 0x08
252
-
#define NETX_XPEC_R3_OFS 0x0c
253
-
#define NETX_XPEC_R4_OFS 0x10
254
-
#define NETX_XPEC_R5_OFS 0x14
255
-
#define NETX_XPEC_R6_OFS 0x18
256
-
#define NETX_XPEC_R7_OFS 0x1c
257
-
#define NETX_XPEC_RANGE01_OFS 0x20
258
-
#define NETX_XPEC_RANGE23_OFS 0x24
259
-
#define NETX_XPEC_RANGE45_OFS 0x28
260
-
#define NETX_XPEC_RANGE67_OFS 0x2c
261
-
#define NETX_XPEC_PC_OFS 0x48
262
-
#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
263
-
#define NETX_XPEC_IRQ_OFS 0x8c
264
-
#define NETX_XPEC_SYSTIME_NS_OFS 0x90
265
-
#define NETX_XPEC_FIFO_DATA_OFS 0x94
266
-
#define NETX_XPEC_SYSTIME_S_OFS 0x98
267
-
#define NETX_XPEC_ADC_OFS 0x9c
268
-
#define NETX_XPEC_URX_COUNT_OFS 0x40
269
-
#define NETX_XPEC_UTX_COUNT_OFS 0x44
270
-
#define NETX_XPEC_PC_OFS 0x48
271
-
#define NETX_XPEC_ZERO_OFS 0x4c
272
-
#define NETX_XPEC_STATCFG_OFS 0x50
273
-
#define NETX_XPEC_EC_MASKA_OFS 0x54
274
-
#define NETX_XPEC_EC_MASKB_OFS 0x58
275
-
#define NETX_XPEC_EC_MASK0_OFS 0x5c
276
-
#define NETX_XPEC_EC_MASK8_OFS 0x7c
277
-
#define NETX_XPEC_EC_MASK9_OFS 0x80
278
-
#define NETX_XPEC_XPU_HOLD_PC_OFS 0x100
279
-
#define NETX_XPEC_RAM_START_OFS 0x2000
280
-
281
-
/* Bits */
282
-
#define XPU_HOLD_PC (1<<0)
283
-
284
-
/* XMAC register offsets relative to NETX_VA_XMAC(no) */
285
-
#define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000
286
-
#define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff
287
-
#define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400
288
-
#define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff
289
-
#define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00
290
-
#define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04
291
-
#define NETX_XMAC_STATUS_SHARED0_OFS 0x840
292
-
#define NETX_XMAC_CONFIG_SHARED0_OFS 0x844
293
-
#define NETX_XMAC_STATUS_SHARED1_OFS 0x848
294
-
#define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c
295
-
#define NETX_XMAC_STATUS_SHARED2_OFS 0x850
296
-
#define NETX_XMAC_CONFIG_SHARED2_OFS 0x854
297
-
#define NETX_XMAC_STATUS_SHARED3_OFS 0x858
298
-
#define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c
299
-
300
-
#define RPU_HOLD_PC (1<<15)
301
-
#define TPU_HOLD_PC (1<<15)
302
-
303
-
/*******************************
304
-
* Pointer FIFO *
305
-
*******************************/
306
-
307
-
/* Registers */
308
-
#define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
309
-
#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
310
-
#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
311
-
#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
312
-
#define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104)
313
-
#define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108)
314
-
#define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c)
315
-
#define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110)
316
-
#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
317
-
#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))
318
-
319
-
320
-
/*******************************
321
-
* Memory Controller *
322
-
*******************************/
323
-
324
-
/* Registers */
325
-
#define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
326
-
#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
327
-
#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
328
-
#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
329
-
#define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48)
330
-
#define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c)
331
-
#define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80)
332
-
#define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84)
333
-
334
-
/* Bits */
335
-
#define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24)
336
-
#define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16)
337
-
#define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8)
338
-
#define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0)
339
-
340
-
341
-
/*******************************
342
-
* Dual Port Memory *
343
-
*******************************/
344
-
345
-
/* Registers */
346
-
#define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
347
-
#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
348
-
#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
349
-
#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
350
-
#define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608)
351
-
#define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c)
352
-
#define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs))
353
-
#define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */
354
-
#define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624)
355
-
#define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628)
356
-
#define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */
357
-
#define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634)
358
-
#define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638)
359
-
360
-
/* Bits */
361
-
#define NETX_DPMAS_INT_EN_GLB_EN (1<<31)
362
-
#define NETX_DPMAS_INT_EN_MEM_LCK (1<<30)
363
-
#define NETX_DPMAS_INT_EN_WDG (1<<29)
364
-
#define NETX_DPMAS_INT_EN_PIO72 (1<<28)
365
-
#define NETX_DPMAS_INT_EN_PIO47 (1<<27)
366
-
#define NETX_DPMAS_INT_EN_PIO40 (1<<26)
367
-
#define NETX_DPMAS_INT_EN_PIO36 (1<<25)
368
-
#define NETX_DPMAS_INT_EN_PIO35 (1<<24)
369
-
370
-
#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
371
-
#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28)
372
-
#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28)
373
-
#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)
374
-
#define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28)
375
-
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14)
376
-
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14)
377
-
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)
378
-
379
-
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)
380
-
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)
381
-
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)
382
-
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)
383
-
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)
384
-
385
-
#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
386
-
#define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26)
387
-
#define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23)
388
-
#define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20)
389
-
#define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17)
390
-
#define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12)
391
-
#define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7)
392
-
#define NETX_EXT_CONFIG_WAIT_POL (1<<6)
393
-
#define NETX_EXT_CONFIG_WAIT_EN (1<<5)
394
-
#define NETX_EXT_CONFIG_NRD_MODE (1<<4)
395
-
#define NETX_EXT_CONFIG_DS_MODE (1<<3)
396
-
#define NETX_EXT_CONFIG_NWR_MODE (1<<2)
397
-
#define NETX_EXT_CONFIG_16BIT (1<<1)
398
-
#define NETX_EXT_CONFIG_CS_ENABLE (1<<0)
399
-
400
-
#define NETX_DPMAS_IO_MODE0_WRL (1<<13)
401
-
#define NETX_DPMAS_IO_MODE0_WAIT (1<<14)
402
-
#define NETX_DPMAS_IO_MODE0_READY (1<<15)
403
-
#define NETX_DPMAS_IO_MODE0_CS0 (1<<19)
404
-
#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)
405
-
406
-
#define NETX_DPMAS_IO_MODE1_CS2 (1<<15)
407
-
#define NETX_DPMAS_IO_MODE1_CS1 (1<<16)
408
-
#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30)
409
-
#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)
410
-
#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)
411
-
#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30)
412
-
413
-
/*******************************
414
-
* I2C *
415
-
*******************************/
416
-
#define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
417
-
#define NETX_I2C_CTRL NETX_I2C_REG(0x0)
418
-
#define NETX_I2C_DATA NETX_I2C_REG(0x4)
419
-
420
-
#endif /* __ASM_ARCH_NETX_REGS_H */
-42
arch/arm/mach-netx/include/mach/pfifo.h
-42
arch/arm/mach-netx/include/mach/pfifo.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/include/mach/pfifo.h
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
9
-
#ifndef ASM_ARCH_PFIFO_H
10
-
#define ASM_ARCH_PFIFO_H
11
-
12
-
static inline int pfifo_push(int no, unsigned int pointer)
13
-
{
14
-
writel(pointer, NETX_PFIFO_BASE(no));
15
-
return 0;
16
-
}
17
-
18
-
static inline unsigned int pfifo_pop(int no)
19
-
{
20
-
return readl(NETX_PFIFO_BASE(no));
21
-
}
22
-
23
-
static inline int pfifo_fill_level(int no)
24
-
{
25
-
26
-
return readl(NETX_PFIFO_FILL_LEVEL(no));
27
-
}
28
-
29
-
static inline int pfifo_full(int no)
30
-
{
31
-
return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0;
32
-
}
33
-
34
-
static inline int pfifo_empty(int no)
35
-
{
36
-
return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0;
37
-
}
38
-
39
-
int pfifo_request(unsigned int pfifo_mask);
40
-
void pfifo_free(unsigned int pfifo_mask);
41
-
42
-
#endif /* ASM_ARCH_PFIFO_H */
-63
arch/arm/mach-netx/include/mach/uncompress.h
-63
arch/arm/mach-netx/include/mach/uncompress.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/include/mach/uncompress.h
4
-
*
5
-
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
/*
9
-
* The following code assumes the serial port has already been
10
-
* initialized by the bootloader. We search for the first enabled
11
-
* port in the most probable order. If you didn't setup a port in
12
-
* your bootloader then nothing will appear (which might be desired).
13
-
*
14
-
* This does not append a newline
15
-
*/
16
-
17
-
#define REG(x) (*(volatile unsigned long *)(x))
18
-
19
-
#define UART1_BASE 0x100a00
20
-
#define UART2_BASE 0x100a80
21
-
22
-
#define UART_DR 0x0
23
-
24
-
#define UART_CR 0x14
25
-
#define CR_UART_EN (1<<0)
26
-
27
-
#define UART_FR 0x18
28
-
#define FR_BUSY (1<<3)
29
-
#define FR_TXFF (1<<5)
30
-
31
-
static inline void putc(char c)
32
-
{
33
-
unsigned long base;
34
-
35
-
if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
36
-
base = UART1_BASE;
37
-
else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
38
-
base = UART2_BASE;
39
-
else
40
-
return;
41
-
42
-
while (REG(base + UART_FR) & FR_TXFF);
43
-
REG(base + UART_DR) = c;
44
-
}
45
-
46
-
static inline void flush(void)
47
-
{
48
-
unsigned long base;
49
-
50
-
if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
51
-
base = UART1_BASE;
52
-
else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
53
-
base = UART2_BASE;
54
-
else
55
-
return;
56
-
57
-
while (REG(base + UART_FR) & FR_BUSY);
58
-
}
59
-
60
-
/*
61
-
* nothing to do
62
-
*/
63
-
#define arch_decomp_setup()
-30
arch/arm/mach-netx/include/mach/xc.h
-30
arch/arm/mach-netx/include/mach/xc.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* arch/arm/mach-netx/include/mach/xc.h
4
-
*
5
-
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#ifndef __ASM_ARCH_XC_H
9
-
#define __ASM_ARCH_XC_H
10
-
11
-
struct xc {
12
-
int no;
13
-
unsigned int type;
14
-
unsigned int version;
15
-
void __iomem *xpec_base;
16
-
void __iomem *xmac_base;
17
-
void __iomem *sram_base;
18
-
int irq;
19
-
struct device *dev;
20
-
};
21
-
22
-
int xc_reset(struct xc *x);
23
-
int xc_stop(struct xc* x);
24
-
int xc_start(struct xc *x);
25
-
int xc_running(struct xc *x);
26
-
int xc_request_firmware(struct xc* x);
27
-
struct xc* request_xc(int xcno, struct device *dev);
28
-
void free_xc(struct xc *x);
29
-
30
-
#endif /* __ASM_ARCH_XC_H */
-197
arch/arm/mach-netx/nxdb500.c
-197
arch/arm/mach-netx/nxdb500.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/nxdb500.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/dma-mapping.h>
9
-
#include <linux/init.h>
10
-
#include <linux/interrupt.h>
11
-
#include <linux/mtd/plat-ram.h>
12
-
#include <linux/platform_device.h>
13
-
#include <linux/amba/bus.h>
14
-
#include <linux/amba/clcd.h>
15
-
16
-
#include <mach/hardware.h>
17
-
#include <asm/mach-types.h>
18
-
#include <asm/mach/arch.h>
19
-
#include <mach/netx-regs.h>
20
-
#include <linux/platform_data/eth-netx.h>
21
-
22
-
#include "generic.h"
23
-
#include "fb.h"
24
-
25
-
static struct clcd_panel qvga = {
26
-
.mode = {
27
-
.name = "QVGA",
28
-
.refresh = 60,
29
-
.xres = 240,
30
-
.yres = 320,
31
-
.pixclock = 187617,
32
-
.left_margin = 6,
33
-
.right_margin = 26,
34
-
.upper_margin = 0,
35
-
.lower_margin = 6,
36
-
.hsync_len = 6,
37
-
.vsync_len = 1,
38
-
.sync = 0,
39
-
.vmode = FB_VMODE_NONINTERLACED,
40
-
},
41
-
.width = -1,
42
-
.height = -1,
43
-
.tim2 = 16,
44
-
.cntl = CNTL_LCDTFT | CNTL_BGR,
45
-
.bpp = 16,
46
-
.grayscale = 0,
47
-
};
48
-
49
-
static inline int nxdb500_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
50
-
{
51
-
var->green.length = 5;
52
-
var->green.msb_right = 0;
53
-
54
-
return clcdfb_check(fb, var);
55
-
}
56
-
57
-
static int nxdb500_clcd_setup(struct clcd_fb *fb)
58
-
{
59
-
unsigned int val;
60
-
61
-
fb->fb.var.green.length = 5;
62
-
fb->fb.var.green.msb_right = 0;
63
-
64
-
/* enable asic control */
65
-
val = readl(NETX_SYSTEM_IOC_ACCESS_KEY);
66
-
writel(val, NETX_SYSTEM_IOC_ACCESS_KEY);
67
-
68
-
writel(3, NETX_SYSTEM_IOC_CR);
69
-
70
-
val = readl(NETX_PIO_OUTPIO);
71
-
writel(val | 1, NETX_PIO_OUTPIO);
72
-
73
-
val = readl(NETX_PIO_OEPIO);
74
-
writel(val | 1, NETX_PIO_OEPIO);
75
-
return netx_clcd_setup(fb);
76
-
}
77
-
78
-
static struct clcd_board clcd_data = {
79
-
.name = "netX",
80
-
.check = nxdb500_check,
81
-
.decode = clcdfb_decode,
82
-
.enable = netx_clcd_enable,
83
-
.setup = nxdb500_clcd_setup,
84
-
.mmap = netx_clcd_mmap,
85
-
.remove = netx_clcd_remove,
86
-
};
87
-
88
-
static struct netxeth_platform_data eth0_platform_data = {
89
-
.xcno = 0,
90
-
};
91
-
92
-
static struct platform_device netx_eth0_device = {
93
-
.name = "netx-eth",
94
-
.id = 0,
95
-
.num_resources = 0,
96
-
.resource = NULL,
97
-
.dev = {
98
-
.platform_data = ð0_platform_data,
99
-
}
100
-
};
101
-
102
-
static struct netxeth_platform_data eth1_platform_data = {
103
-
.xcno = 1,
104
-
};
105
-
106
-
static struct platform_device netx_eth1_device = {
107
-
.name = "netx-eth",
108
-
.id = 1,
109
-
.num_resources = 0,
110
-
.resource = NULL,
111
-
.dev = {
112
-
.platform_data = ð1_platform_data,
113
-
}
114
-
};
115
-
116
-
static struct resource netx_uart0_resources[] = {
117
-
[0] = {
118
-
.start = 0x00100A00,
119
-
.end = 0x00100A3F,
120
-
.flags = IORESOURCE_MEM,
121
-
},
122
-
[1] = {
123
-
.start = (NETX_IRQ_UART0),
124
-
.end = (NETX_IRQ_UART0),
125
-
.flags = IORESOURCE_IRQ,
126
-
},
127
-
};
128
-
129
-
static struct platform_device netx_uart0_device = {
130
-
.name = "netx-uart",
131
-
.id = 0,
132
-
.num_resources = ARRAY_SIZE(netx_uart0_resources),
133
-
.resource = netx_uart0_resources,
134
-
};
135
-
136
-
static struct resource netx_uart1_resources[] = {
137
-
[0] = {
138
-
.start = 0x00100A40,
139
-
.end = 0x00100A7F,
140
-
.flags = IORESOURCE_MEM,
141
-
},
142
-
[1] = {
143
-
.start = (NETX_IRQ_UART1),
144
-
.end = (NETX_IRQ_UART1),
145
-
.flags = IORESOURCE_IRQ,
146
-
},
147
-
};
148
-
149
-
static struct platform_device netx_uart1_device = {
150
-
.name = "netx-uart",
151
-
.id = 1,
152
-
.num_resources = ARRAY_SIZE(netx_uart1_resources),
153
-
.resource = netx_uart1_resources,
154
-
};
155
-
156
-
static struct resource netx_uart2_resources[] = {
157
-
[0] = {
158
-
.start = 0x00100A80,
159
-
.end = 0x00100ABF,
160
-
.flags = IORESOURCE_MEM,
161
-
},
162
-
[1] = {
163
-
.start = (NETX_IRQ_UART2),
164
-
.end = (NETX_IRQ_UART2),
165
-
.flags = IORESOURCE_IRQ,
166
-
},
167
-
};
168
-
169
-
static struct platform_device netx_uart2_device = {
170
-
.name = "netx-uart",
171
-
.id = 2,
172
-
.num_resources = ARRAY_SIZE(netx_uart2_resources),
173
-
.resource = netx_uart2_resources,
174
-
};
175
-
176
-
static struct platform_device *devices[] __initdata = {
177
-
&netx_eth0_device,
178
-
&netx_eth1_device,
179
-
&netx_uart0_device,
180
-
&netx_uart1_device,
181
-
&netx_uart2_device,
182
-
};
183
-
184
-
static void __init nxdb500_init(void)
185
-
{
186
-
netx_fb_init(&clcd_data, &qvga);
187
-
platform_add_devices(devices, ARRAY_SIZE(devices));
188
-
}
189
-
190
-
MACHINE_START(NXDB500, "Hilscher nxdb500")
191
-
.atag_offset = 0x100,
192
-
.map_io = netx_map_io,
193
-
.init_irq = netx_init_irq,
194
-
.init_time = netx_timer_init,
195
-
.init_machine = nxdb500_init,
196
-
.restart = netx_restart,
197
-
MACHINE_END
-90
arch/arm/mach-netx/nxdkn.c
-90
arch/arm/mach-netx/nxdkn.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/nxdkn.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/dma-mapping.h>
9
-
#include <linux/init.h>
10
-
#include <linux/interrupt.h>
11
-
#include <linux/mtd/plat-ram.h>
12
-
#include <linux/platform_device.h>
13
-
#include <linux/amba/bus.h>
14
-
#include <linux/amba/clcd.h>
15
-
16
-
#include <mach/hardware.h>
17
-
#include <asm/mach-types.h>
18
-
#include <asm/mach/arch.h>
19
-
#include <mach/netx-regs.h>
20
-
#include <linux/platform_data/eth-netx.h>
21
-
22
-
#include "generic.h"
23
-
24
-
static struct netxeth_platform_data eth0_platform_data = {
25
-
.xcno = 0,
26
-
};
27
-
28
-
static struct platform_device nxdkn_eth0_device = {
29
-
.name = "netx-eth",
30
-
.id = 0,
31
-
.num_resources = 0,
32
-
.resource = NULL,
33
-
.dev = {
34
-
.platform_data = ð0_platform_data,
35
-
}
36
-
};
37
-
38
-
static struct netxeth_platform_data eth1_platform_data = {
39
-
.xcno = 1,
40
-
};
41
-
42
-
static struct platform_device nxdkn_eth1_device = {
43
-
.name = "netx-eth",
44
-
.id = 1,
45
-
.num_resources = 0,
46
-
.resource = NULL,
47
-
.dev = {
48
-
.platform_data = ð1_platform_data,
49
-
}
50
-
};
51
-
52
-
static struct resource netx_uart0_resources[] = {
53
-
[0] = {
54
-
.start = 0x00100A00,
55
-
.end = 0x00100A3F,
56
-
.flags = IORESOURCE_MEM,
57
-
},
58
-
[1] = {
59
-
.start = (NETX_IRQ_UART0),
60
-
.end = (NETX_IRQ_UART0),
61
-
.flags = IORESOURCE_IRQ,
62
-
},
63
-
};
64
-
65
-
static struct platform_device netx_uart0_device = {
66
-
.name = "netx-uart",
67
-
.id = 0,
68
-
.num_resources = ARRAY_SIZE(netx_uart0_resources),
69
-
.resource = netx_uart0_resources,
70
-
};
71
-
72
-
static struct platform_device *devices[] __initdata = {
73
-
&nxdkn_eth0_device,
74
-
&nxdkn_eth1_device,
75
-
&netx_uart0_device,
76
-
};
77
-
78
-
static void __init nxdkn_init(void)
79
-
{
80
-
platform_add_devices(devices, ARRAY_SIZE(devices));
81
-
}
82
-
83
-
MACHINE_START(NXDKN, "Hilscher nxdkn")
84
-
.atag_offset = 0x100,
85
-
.map_io = netx_map_io,
86
-
.init_irq = netx_init_irq,
87
-
.init_time = netx_timer_init,
88
-
.init_machine = nxdkn_init,
89
-
.restart = netx_restart,
90
-
MACHINE_END
-174
arch/arm/mach-netx/nxeb500hmi.c
-174
arch/arm/mach-netx/nxeb500hmi.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/nxeb500hmi.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/dma-mapping.h>
9
-
#include <linux/init.h>
10
-
#include <linux/interrupt.h>
11
-
#include <linux/mtd/plat-ram.h>
12
-
#include <linux/platform_device.h>
13
-
#include <linux/amba/bus.h>
14
-
#include <linux/amba/clcd.h>
15
-
16
-
#include <mach/hardware.h>
17
-
#include <asm/mach-types.h>
18
-
#include <asm/mach/arch.h>
19
-
#include <mach/netx-regs.h>
20
-
#include <linux/platform_data/eth-netx.h>
21
-
22
-
#include "generic.h"
23
-
#include "fb.h"
24
-
25
-
static struct clcd_panel qvga = {
26
-
.mode = {
27
-
.name = "QVGA",
28
-
.refresh = 60,
29
-
.xres = 240,
30
-
.yres = 320,
31
-
.pixclock = 187617,
32
-
.left_margin = 6,
33
-
.right_margin = 26,
34
-
.upper_margin = 0,
35
-
.lower_margin = 6,
36
-
.hsync_len = 6,
37
-
.vsync_len = 1,
38
-
.sync = 0,
39
-
.vmode = FB_VMODE_NONINTERLACED,
40
-
},
41
-
.width = -1,
42
-
.height = -1,
43
-
.tim2 = 16,
44
-
.cntl = CNTL_LCDTFT | CNTL_BGR,
45
-
.bpp = 16,
46
-
.grayscale = 0,
47
-
};
48
-
49
-
static inline int nxeb500hmi_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
50
-
{
51
-
var->green.length = 5;
52
-
var->green.msb_right = 0;
53
-
54
-
return clcdfb_check(fb, var);
55
-
}
56
-
57
-
static int nxeb500hmi_clcd_setup(struct clcd_fb *fb)
58
-
{
59
-
unsigned int val;
60
-
61
-
fb->fb.var.green.length = 5;
62
-
fb->fb.var.green.msb_right = 0;
63
-
64
-
/* enable asic control */
65
-
val = readl(NETX_SYSTEM_IOC_ACCESS_KEY);
66
-
writel(val, NETX_SYSTEM_IOC_ACCESS_KEY);
67
-
68
-
writel(3, NETX_SYSTEM_IOC_CR);
69
-
70
-
/* GPIO 14 is used for display enable on newer boards */
71
-
writel(9, NETX_GPIO_CFG(14));
72
-
73
-
val = readl(NETX_PIO_OUTPIO);
74
-
writel(val | 1, NETX_PIO_OUTPIO);
75
-
76
-
val = readl(NETX_PIO_OEPIO);
77
-
writel(val | 1, NETX_PIO_OEPIO);
78
-
return netx_clcd_setup(fb);
79
-
}
80
-
81
-
static struct clcd_board clcd_data = {
82
-
.name = "netX",
83
-
.check = nxeb500hmi_check,
84
-
.decode = clcdfb_decode,
85
-
.enable = netx_clcd_enable,
86
-
.setup = nxeb500hmi_clcd_setup,
87
-
.mmap = netx_clcd_mmap,
88
-
.remove = netx_clcd_remove,
89
-
};
90
-
91
-
static struct netxeth_platform_data eth0_platform_data = {
92
-
.xcno = 0,
93
-
};
94
-
95
-
static struct platform_device netx_eth0_device = {
96
-
.name = "netx-eth",
97
-
.id = 0,
98
-
.num_resources = 0,
99
-
.resource = NULL,
100
-
.dev = {
101
-
.platform_data = ð0_platform_data,
102
-
}
103
-
};
104
-
105
-
static struct netxeth_platform_data eth1_platform_data = {
106
-
.xcno = 1,
107
-
};
108
-
109
-
static struct platform_device netx_eth1_device = {
110
-
.name = "netx-eth",
111
-
.id = 1,
112
-
.num_resources = 0,
113
-
.resource = NULL,
114
-
.dev = {
115
-
.platform_data = ð1_platform_data,
116
-
}
117
-
};
118
-
119
-
static struct resource netx_cf_resources[] = {
120
-
[0] = {
121
-
.start = 0x20000000,
122
-
.end = 0x25ffffff,
123
-
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
124
-
},
125
-
};
126
-
127
-
static struct platform_device netx_cf_device = {
128
-
.name = "netx-cf",
129
-
.id = 0,
130
-
.resource = netx_cf_resources,
131
-
.num_resources = ARRAY_SIZE(netx_cf_resources),
132
-
};
133
-
134
-
static struct resource netx_uart0_resources[] = {
135
-
[0] = {
136
-
.start = 0x00100A00,
137
-
.end = 0x00100A3F,
138
-
.flags = IORESOURCE_MEM,
139
-
},
140
-
[1] = {
141
-
.start = (NETX_IRQ_UART0),
142
-
.end = (NETX_IRQ_UART0),
143
-
.flags = IORESOURCE_IRQ,
144
-
},
145
-
};
146
-
147
-
static struct platform_device netx_uart0_device = {
148
-
.name = "netx-uart",
149
-
.id = 0,
150
-
.num_resources = ARRAY_SIZE(netx_uart0_resources),
151
-
.resource = netx_uart0_resources,
152
-
};
153
-
154
-
static struct platform_device *devices[] __initdata = {
155
-
&netx_eth0_device,
156
-
&netx_eth1_device,
157
-
&netx_cf_device,
158
-
&netx_uart0_device,
159
-
};
160
-
161
-
static void __init nxeb500hmi_init(void)
162
-
{
163
-
netx_fb_init(&clcd_data, &qvga);
164
-
platform_add_devices(devices, ARRAY_SIZE(devices));
165
-
}
166
-
167
-
MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
168
-
.atag_offset = 0x100,
169
-
.map_io = netx_map_io,
170
-
.init_irq = netx_init_irq,
171
-
.init_time = netx_timer_init,
172
-
.init_machine = nxeb500hmi_init,
173
-
.restart = netx_restart,
174
-
MACHINE_END
-56
arch/arm/mach-netx/pfifo.c
-56
arch/arm/mach-netx/pfifo.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/pfifo.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/init.h>
9
-
#include <linux/module.h>
10
-
#include <linux/mutex.h>
11
-
#include <linux/io.h>
12
-
13
-
#include <mach/hardware.h>
14
-
#include <mach/netx-regs.h>
15
-
#include <mach/pfifo.h>
16
-
17
-
static DEFINE_MUTEX(pfifo_lock);
18
-
19
-
static unsigned int pfifo_used = 0;
20
-
21
-
int pfifo_request(unsigned int pfifo_mask)
22
-
{
23
-
int err = 0;
24
-
unsigned int val;
25
-
26
-
mutex_lock(&pfifo_lock);
27
-
28
-
if (pfifo_mask & pfifo_used) {
29
-
err = -EBUSY;
30
-
goto out;
31
-
}
32
-
33
-
pfifo_used |= pfifo_mask;
34
-
35
-
val = readl(NETX_PFIFO_RESET);
36
-
writel(val | pfifo_mask, NETX_PFIFO_RESET);
37
-
writel(val, NETX_PFIFO_RESET);
38
-
39
-
out:
40
-
mutex_unlock(&pfifo_lock);
41
-
return err;
42
-
}
43
-
44
-
void pfifo_free(unsigned int pfifo_mask)
45
-
{
46
-
mutex_lock(&pfifo_lock);
47
-
pfifo_used &= ~pfifo_mask;
48
-
mutex_unlock(&pfifo_lock);
49
-
}
50
-
51
-
EXPORT_SYMBOL(pfifo_push);
52
-
EXPORT_SYMBOL(pfifo_pop);
53
-
EXPORT_SYMBOL(pfifo_fill_level);
54
-
EXPORT_SYMBOL(pfifo_empty);
55
-
EXPORT_SYMBOL(pfifo_request);
56
-
EXPORT_SYMBOL(pfifo_free);
-141
arch/arm/mach-netx/time.c
-141
arch/arm/mach-netx/time.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/time.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/init.h>
9
-
#include <linux/interrupt.h>
10
-
#include <linux/irq.h>
11
-
#include <linux/clocksource.h>
12
-
#include <linux/clockchips.h>
13
-
#include <linux/io.h>
14
-
15
-
#include <mach/hardware.h>
16
-
#include <asm/mach/time.h>
17
-
#include <mach/netx-regs.h>
18
-
19
-
#define NETX_CLOCK_FREQ 100000000
20
-
#define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ)
21
-
22
-
#define TIMER_CLOCKEVENT 0
23
-
#define TIMER_CLOCKSOURCE 1
24
-
25
-
static inline void timer_shutdown(struct clock_event_device *evt)
26
-
{
27
-
/* disable timer */
28
-
writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
29
-
}
30
-
31
-
static int netx_shutdown(struct clock_event_device *evt)
32
-
{
33
-
timer_shutdown(evt);
34
-
35
-
return 0;
36
-
}
37
-
38
-
static int netx_set_oneshot(struct clock_event_device *evt)
39
-
{
40
-
u32 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
41
-
42
-
timer_shutdown(evt);
43
-
writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
44
-
writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
45
-
46
-
return 0;
47
-
}
48
-
49
-
static int netx_set_periodic(struct clock_event_device *evt)
50
-
{
51
-
u32 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
52
-
NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
53
-
54
-
timer_shutdown(evt);
55
-
writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
56
-
writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
57
-
58
-
return 0;
59
-
}
60
-
61
-
static int netx_set_next_event(unsigned long evt,
62
-
struct clock_event_device *clk)
63
-
{
64
-
writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
65
-
return 0;
66
-
}
67
-
68
-
static struct clock_event_device netx_clockevent = {
69
-
.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
70
-
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
71
-
.set_next_event = netx_set_next_event,
72
-
.set_state_shutdown = netx_shutdown,
73
-
.set_state_periodic = netx_set_periodic,
74
-
.set_state_oneshot = netx_set_oneshot,
75
-
.tick_resume = netx_shutdown,
76
-
};
77
-
78
-
/*
79
-
* IRQ handler for the timer
80
-
*/
81
-
static irqreturn_t
82
-
netx_timer_interrupt(int irq, void *dev_id)
83
-
{
84
-
struct clock_event_device *evt = &netx_clockevent;
85
-
86
-
/* acknowledge interrupt */
87
-
writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
88
-
89
-
evt->event_handler(evt);
90
-
91
-
return IRQ_HANDLED;
92
-
}
93
-
94
-
static struct irqaction netx_timer_irq = {
95
-
.name = "NetX Timer Tick",
96
-
.flags = IRQF_TIMER | IRQF_IRQPOLL,
97
-
.handler = netx_timer_interrupt,
98
-
};
99
-
100
-
/*
101
-
* Set up timer interrupt
102
-
*/
103
-
void __init netx_timer_init(void)
104
-
{
105
-
/* disable timer initially */
106
-
writel(0, NETX_GPIO_COUNTER_CTRL(0));
107
-
108
-
/* Reset the timer value to zero */
109
-
writel(0, NETX_GPIO_COUNTER_CURRENT(0));
110
-
111
-
writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0));
112
-
113
-
/* acknowledge interrupt */
114
-
writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
115
-
116
-
/* Enable the interrupt in the specific timer
117
-
* register and start timer
118
-
*/
119
-
writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
120
-
writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
121
-
NETX_GPIO_COUNTER_CTRL(0));
122
-
123
-
setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
124
-
125
-
/* Setup timer one for clocksource */
126
-
writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
127
-
writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
128
-
writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
129
-
130
-
writel(NETX_GPIO_COUNTER_CTRL_RUN,
131
-
NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
132
-
133
-
clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
134
-
"netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up);
135
-
136
-
/* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
137
-
* Adding some safety ... */
138
-
netx_clockevent.cpumask = cpumask_of(0);
139
-
clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ,
140
-
0xa00, 0xfffffffe);
141
-
}
-246
arch/arm/mach-netx/xc.c
-246
arch/arm/mach-netx/xc.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* arch/arm/mach-netx/xc.c
4
-
*
5
-
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6
-
*/
7
-
8
-
#include <linux/init.h>
9
-
#include <linux/device.h>
10
-
#include <linux/firmware.h>
11
-
#include <linux/mutex.h>
12
-
#include <linux/slab.h>
13
-
#include <linux/io.h>
14
-
#include <linux/export.h>
15
-
16
-
#include <mach/hardware.h>
17
-
#include <mach/irqs.h>
18
-
#include <mach/netx-regs.h>
19
-
20
-
#include <mach/xc.h>
21
-
22
-
static DEFINE_MUTEX(xc_lock);
23
-
24
-
static int xc_in_use = 0;
25
-
26
-
struct fw_desc {
27
-
unsigned int ofs;
28
-
unsigned int size;
29
-
unsigned int patch_ofs;
30
-
unsigned int patch_entries;
31
-
};
32
-
33
-
struct fw_header {
34
-
unsigned int magic;
35
-
unsigned int type;
36
-
unsigned int version;
37
-
unsigned int reserved[5];
38
-
struct fw_desc fw_desc[3];
39
-
} __attribute__ ((packed));
40
-
41
-
int xc_stop(struct xc *x)
42
-
{
43
-
writel(RPU_HOLD_PC, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS);
44
-
writel(TPU_HOLD_PC, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS);
45
-
writel(XPU_HOLD_PC, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS);
46
-
return 0;
47
-
}
48
-
49
-
int xc_start(struct xc *x)
50
-
{
51
-
writel(0, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS);
52
-
writel(0, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS);
53
-
writel(0, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS);
54
-
return 0;
55
-
}
56
-
57
-
int xc_running(struct xc *x)
58
-
{
59
-
return (readl(x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS) & RPU_HOLD_PC)
60
-
|| (readl(x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS) & TPU_HOLD_PC)
61
-
|| (readl(x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS) & XPU_HOLD_PC) ?
62
-
0 : 1;
63
-
}
64
-
65
-
int xc_reset(struct xc *x)
66
-
{
67
-
writel(0, x->xpec_base + NETX_XPEC_PC_OFS);
68
-
return 0;
69
-
}
70
-
71
-
static int xc_check_ptr(struct xc *x, unsigned long adr, unsigned int size)
72
-
{
73
-
if (adr >= NETX_PA_XMAC(x->no) &&
74
-
adr + size < NETX_PA_XMAC(x->no) + XMAC_MEM_SIZE)
75
-
return 0;
76
-
77
-
if (adr >= NETX_PA_XPEC(x->no) &&
78
-
adr + size < NETX_PA_XPEC(x->no) + XPEC_MEM_SIZE)
79
-
return 0;
80
-
81
-
dev_err(x->dev, "Illegal pointer in firmware found. aborting\n");
82
-
83
-
return -1;
84
-
}
85
-
86
-
static int xc_patch(struct xc *x, const void *patch, int count)
87
-
{
88
-
unsigned int val, adr;
89
-
const unsigned int *data = patch;
90
-
91
-
int i;
92
-
for (i = 0; i < count; i++) {
93
-
adr = *data++;
94
-
val = *data++;
95
-
if (xc_check_ptr(x, adr, 4) < 0)
96
-
return -EINVAL;
97
-
98
-
writel(val, (void __iomem *)io_p2v(adr));
99
-
}
100
-
return 0;
101
-
}
102
-
103
-
int xc_request_firmware(struct xc *x)
104
-
{
105
-
int ret;
106
-
char name[16];
107
-
const struct firmware *fw;
108
-
struct fw_header *head;
109
-
unsigned int size;
110
-
int i;
111
-
const void *src;
112
-
unsigned long dst;
113
-
114
-
sprintf(name, "xc%d.bin", x->no);
115
-
116
-
ret = request_firmware(&fw, name, x->dev);
117
-
118
-
if (ret < 0) {
119
-
dev_err(x->dev, "request_firmware failed\n");
120
-
return ret;
121
-
}
122
-
123
-
head = (struct fw_header *)fw->data;
124
-
if (head->magic != 0x4e657458) {
125
-
if (head->magic == 0x5874654e) {
126
-
dev_err(x->dev,
127
-
"firmware magic is 'XteN'. Endianness problems?\n");
128
-
ret = -ENODEV;
129
-
goto exit_release_firmware;
130
-
}
131
-
dev_err(x->dev, "unrecognized firmware magic 0x%08x\n",
132
-
head->magic);
133
-
ret = -ENODEV;
134
-
goto exit_release_firmware;
135
-
}
136
-
137
-
x->type = head->type;
138
-
x->version = head->version;
139
-
140
-
ret = -EINVAL;
141
-
142
-
for (i = 0; i < 3; i++) {
143
-
src = fw->data + head->fw_desc[i].ofs;
144
-
dst = *(unsigned int *)src;
145
-
src += sizeof (unsigned int);
146
-
size = head->fw_desc[i].size - sizeof (unsigned int);
147
-
148
-
if (xc_check_ptr(x, dst, size))
149
-
goto exit_release_firmware;
150
-
151
-
memcpy((void *)io_p2v(dst), src, size);
152
-
153
-
src = fw->data + head->fw_desc[i].patch_ofs;
154
-
size = head->fw_desc[i].patch_entries;
155
-
ret = xc_patch(x, src, size);
156
-
if (ret < 0)
157
-
goto exit_release_firmware;
158
-
}
159
-
160
-
ret = 0;
161
-
162
-
exit_release_firmware:
163
-
release_firmware(fw);
164
-
165
-
return ret;
166
-
}
167
-
168
-
struct xc *request_xc(int xcno, struct device *dev)
169
-
{
170
-
struct xc *x = NULL;
171
-
172
-
mutex_lock(&xc_lock);
173
-
174
-
if (xcno > 3)
175
-
goto exit;
176
-
if (xc_in_use & (1 << xcno))
177
-
goto exit;
178
-
179
-
x = kmalloc(sizeof (struct xc), GFP_KERNEL);
180
-
if (!x)
181
-
goto exit;
182
-
183
-
if (!request_mem_region
184
-
(NETX_PA_XPEC(xcno), XPEC_MEM_SIZE, kobject_name(&dev->kobj)))
185
-
goto exit_free;
186
-
187
-
if (!request_mem_region
188
-
(NETX_PA_XMAC(xcno), XMAC_MEM_SIZE, kobject_name(&dev->kobj)))
189
-
goto exit_release_1;
190
-
191
-
if (!request_mem_region
192
-
(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE, kobject_name(&dev->kobj)))
193
-
goto exit_release_2;
194
-
195
-
x->xpec_base = (void * __iomem)io_p2v(NETX_PA_XPEC(xcno));
196
-
x->xmac_base = (void * __iomem)io_p2v(NETX_PA_XMAC(xcno));
197
-
x->sram_base = ioremap(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE);
198
-
if (!x->sram_base)
199
-
goto exit_release_3;
200
-
201
-
x->irq = NETX_IRQ_XPEC(xcno);
202
-
203
-
x->no = xcno;
204
-
x->dev = dev;
205
-
206
-
xc_in_use |= (1 << xcno);
207
-
208
-
goto exit;
209
-
210
-
exit_release_3:
211
-
release_mem_region(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE);
212
-
exit_release_2:
213
-
release_mem_region(NETX_PA_XMAC(xcno), XMAC_MEM_SIZE);
214
-
exit_release_1:
215
-
release_mem_region(NETX_PA_XPEC(xcno), XPEC_MEM_SIZE);
216
-
exit_free:
217
-
kfree(x);
218
-
x = NULL;
219
-
exit:
220
-
mutex_unlock(&xc_lock);
221
-
return x;
222
-
}
223
-
224
-
void free_xc(struct xc *x)
225
-
{
226
-
int xcno = x->no;
227
-
228
-
mutex_lock(&xc_lock);
229
-
230
-
iounmap(x->sram_base);
231
-
release_mem_region(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE);
232
-
release_mem_region(NETX_PA_XMAC(xcno), XMAC_MEM_SIZE);
233
-
release_mem_region(NETX_PA_XPEC(xcno), XPEC_MEM_SIZE);
234
-
xc_in_use &= ~(1 << x->no);
235
-
kfree(x);
236
-
237
-
mutex_unlock(&xc_lock);
238
-
}
239
-
240
-
EXPORT_SYMBOL(free_xc);
241
-
EXPORT_SYMBOL(request_xc);
242
-
EXPORT_SYMBOL(xc_request_firmware);
243
-
EXPORT_SYMBOL(xc_reset);
244
-
EXPORT_SYMBOL(xc_running);
245
-
EXPORT_SYMBOL(xc_start);
246
-
EXPORT_SYMBOL(xc_stop);
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
···
462
462
#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
463
463
#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
464
464
#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
465
-
#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
465
+
#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0
466
466
#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
467
467
#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
468
468
#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
···
472
472
#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
473
473
#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
474
474
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
475
-
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
475
+
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
476
476
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
477
477
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
478
478
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
+1
-2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
+1
-2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
···
715
715
716
716
sai2: sai@308b0000 {
717
717
#sound-dai-cells = <0>;
718
-
compatible = "fsl,imx8mq-sai",
719
-
"fsl,imx6sx-sai";
718
+
compatible = "fsl,imx8mq-sai";
720
719
reg = <0x308b0000 0x10000>;
721
720
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
722
721
clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,