Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2021-04-23' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Just some small i915 and amdgpu fixes this week, should be all until
you open the merge window.
amdgpu:
- Fix gpuvm page table update issue
- Modifier fixes
- Register fix for dimgrey cavefish
i915:
- GVT's BDW regression fix for cmd parser
- Fix modesetting in case of unexpected AUX timeouts"
* tag 'drm-fixes-2021-04-23' of git://anongit.freedesktop.org/drm/drm:
drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish
amd/display: allow non-linear multi-planar formats
drm/amd/display: Update modifier list for gfx10_3
drm/amdgpu: reserve fence slot to update page table
drm/i915: Fix modesetting in case of unexpected AUX timeouts
drm/i915/gvt: Fix BDW command parser regression
+30
-19
+8
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+8
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
3300
3300
struct amdgpu_bo *root;
3301
3301
uint64_t value, flags;
3302
3302
struct amdgpu_vm *vm;
3303
-
long r;
3303
+
int r;
3304
3304
3305
3305
spin_lock(&adev->vm_manager.pasid_lock);
3306
3306
vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
···
3349
3349
value = 0;
3350
3350
}
3351
3351
3352
+
r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3353
+
if (r) {
3354
+
pr_debug("failed %d to reserve fence slot\n", r);
3355
+
goto error_unlock;
3356
+
}
3357
+
3352
3358
r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3353
3359
addr, flags, value, NULL, NULL,
3354
3360
NULL);
···
3366
3360
error_unlock:
3367
3361
amdgpu_bo_unreserve(root);
3368
3362
if (r < 0)
3369
-
DRM_ERROR("Can't handle page fault (%ld)\n", r);
3363
+
DRM_ERROR("Can't handle page fault (%d)\n", r);
3370
3364
3371
3365
error_unref:
3372
3366
amdgpu_bo_unref(&root);
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
3280
3280
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3281
3281
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3282
3282
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3283
-
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3283
+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3284
3284
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3285
3285
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3286
3286
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+6
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+6
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
4072
4072
return true;
4073
4073
4074
4074
/*
4075
-
* The arbitrary tiling support for multiplane formats has not been hooked
4076
-
* up.
4077
-
*/
4078
-
if (info->num_planes > 1)
4079
-
return false;
4080
-
4081
-
/*
4082
4075
* For D swizzle the canonical modifier depends on the bpp, so check
4083
4076
* it here.
4084
4077
*/
···
4088
4095
if (modifier_has_dcc(modifier)) {
4089
4096
/* Per radeonsi comments 16/64 bpp are more complicated. */
4090
4097
if (info->cpp[0] != 4)
4098
+
return false;
4099
+
/* We support multi-planar formats, but not when combined with
4100
+
* additional DCC metadata planes. */
4101
+
if (info->num_planes > 1)
4091
4102
return false;
4092
4103
}
4093
4104
···
4293
4296
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4294
4297
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4295
4298
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4296
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
4299
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4297
4300
4298
4301
add_modifier(mods, size, capacity, AMD_FMT_MOD |
4299
4302
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
···
4305
4308
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4306
4309
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4307
4310
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4308
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
4311
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4309
4312
4310
4313
add_modifier(mods, size, capacity, AMD_FMT_MOD |
4311
4314
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+2
-1
drivers/gpu/drm/i915/display/intel_dp_link_training.c
+2
-1
drivers/gpu/drm/i915/display/intel_dp_link_training.c
···
848
848
int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
849
849
850
850
if (lttpr_count < 0)
851
-
return;
851
+
/* Still continue with enabling the port and link training. */
852
+
lttpr_count = 0;
852
853
853
854
if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
854
855
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+13
-6
drivers/gpu/drm/i915/gvt/cmd_parser.c
+13
-6
drivers/gpu/drm/i915/gvt/cmd_parser.c
···
916
916
917
917
if (!strncmp(cmd, "srm", 3) ||
918
918
!strncmp(cmd, "lrm", 3)) {
919
-
if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
920
-
offset != 0x21f0) {
919
+
if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
920
+
offset == 0x21f0 ||
921
+
(IS_BROADWELL(gvt->gt->i915) &&
922
+
offset == i915_mmio_reg_offset(INSTPM)))
923
+
return 0;
924
+
else {
921
925
gvt_vgpu_err("%s access to register (%x)\n",
922
926
cmd, offset);
923
927
return -EPERM;
924
-
} else
925
-
return 0;
928
+
}
926
929
}
927
930
928
931
if (!strncmp(cmd, "lrr-src", 7) ||
929
932
!strncmp(cmd, "lrr-dst", 7)) {
930
-
gvt_vgpu_err("not allowed cmd %s\n", cmd);
931
-
return -EPERM;
933
+
if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
934
+
return 0;
935
+
else {
936
+
gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
937
+
return -EPERM;
938
+
}
932
939
}
933
940
934
941
if (!strncmp(cmd, "pipe_ctrl", 9)) {