tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"All is about drivers, no core business going on.

- Fix a host of runtime problems with the Intel Cherryview driver:
suspend/resume needs to be marshalled properly, and strange effects
from BIOS interaction during suspend/resume need to be dealt with.

- A single bit was being set wrong in the Aspeed driver.

- Fix an iProc probe ordering fallout resulting from v4.9
refactorings for bus population.

- Do not specify a default trigger in the ST Micro cascaded GPIO IRQ
controller: the kernel will moan.

- Make IRQs optional altogether on the STM32 driver, it turns out not
all systems have them or want them.

- Fix a re-probe bug in the i.MX driver, it will eventually crash if
probed repeatedly, not good"

* tag 'pinctrl-v4.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl-aspeed-g5: Never set SCU90[6]
pinctrl: cherryview: Prevent possible interrupt storm on resume
pinctrl: cherryview: Serialize register access in suspend/resume
pinctrl: imx: reset group index on probe
pinctrl: stm32: move gpio irqs binding to optional
pinctrl: stm32: remove dependency with interrupt controller
pinctrl: st: don't specify default interrupt trigger
pinctrl: iproc: Fix iProc and NSP GPIO support

Linus Torvalds 5c03b53c 015ed943

+29 -15
+5 -5
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
··· 14 14 - #size-cells : The value of this property must be 1 15 15 - ranges : defines mapping between pin controller node (parent) to 16 16 gpio-bank node (children). 17 - - interrupt-parent: phandle of the interrupt parent to which the external 18 - GPIO interrupts are forwarded to. 19 - - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node 20 - which includes IRQ mux selection register, and the offset of the IRQ mux 21 - selection register. 22 17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to 23 18 specify pins. 24 19 ··· 32 37 33 38 Optional properties: 34 39 - reset: : Reference to the reset controller 40 + - interrupt-parent: phandle of the interrupt parent to which the external 41 + GPIO interrupts are forwarded to. 42 + - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node 43 + which includes IRQ mux selection register, and the offset of the IRQ mux 44 + selection register. 35 45 36 46 Example: 37 47 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+1 -1
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
··· 26 26 27 27 #define ASPEED_G5_NR_PINS 228 28 28 29 - #define COND1 SIG_DESC_BIT(SCU90, 6, 0) 29 + #define COND1 { SCU90, BIT(6), 0, 0 } 30 30 #define COND2 { SCU94, GENMASK(1, 0), 0, 0 } 31 31 32 32 #define B14 0
+1 -1
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
··· 844 844 845 845 static int __init iproc_gpio_init(void) 846 846 { 847 - return platform_driver_probe(&iproc_gpio_driver, iproc_gpio_probe); 847 + return platform_driver_register(&iproc_gpio_driver); 848 848 } 849 849 arch_initcall_sync(iproc_gpio_init);
+1 -1
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
··· 741 741 742 742 static int __init nsp_gpio_init(void) 743 743 { 744 - return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe); 744 + return platform_driver_register(&nsp_gpio_driver); 745 745 } 746 746 arch_initcall_sync(nsp_gpio_init);
+1
drivers/pinctrl/freescale/pinctrl-imx.c
··· 687 687 if (!info->functions) 688 688 return -ENOMEM; 689 689 690 + info->group_index = 0; 690 691 if (flat_funcs) { 691 692 info->ngroups = of_get_child_count(np); 692 693 } else {
+14 -3
drivers/pinctrl/intel/pinctrl-cherryview.c
··· 1652 1652 } 1653 1653 1654 1654 #ifdef CONFIG_PM_SLEEP 1655 - static int chv_pinctrl_suspend(struct device *dev) 1655 + static int chv_pinctrl_suspend_noirq(struct device *dev) 1656 1656 { 1657 1657 struct platform_device *pdev = to_platform_device(dev); 1658 1658 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1659 + unsigned long flags; 1659 1660 int i; 1661 + 1662 + raw_spin_lock_irqsave(&chv_lock, flags); 1660 1663 1661 1664 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 1662 1665 ··· 1681 1678 ctx->padctrl1 = readl(reg); 1682 1679 } 1683 1680 1681 + raw_spin_unlock_irqrestore(&chv_lock, flags); 1682 + 1684 1683 return 0; 1685 1684 } 1686 1685 1687 - static int chv_pinctrl_resume(struct device *dev) 1686 + static int chv_pinctrl_resume_noirq(struct device *dev) 1688 1687 { 1689 1688 struct platform_device *pdev = to_platform_device(dev); 1690 1689 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1690 + unsigned long flags; 1691 1691 int i; 1692 + 1693 + raw_spin_lock_irqsave(&chv_lock, flags); 1692 1694 1693 1695 /* 1694 1696 * Mask all interrupts before restoring per-pin configuration ··· 1739 1731 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1740 1732 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 1741 1733 1734 + raw_spin_unlock_irqrestore(&chv_lock, flags); 1735 + 1742 1736 return 0; 1743 1737 } 1744 1738 #endif 1745 1739 1746 1740 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1747 - SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) 1741 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1742 + chv_pinctrl_resume_noirq) 1748 1743 }; 1749 1744 1750 1745 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
+1 -1
drivers/pinctrl/pinctrl-st.c
··· 1512 1512 if (info->irqmux_base || gpio_irq > 0) { 1513 1513 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, 1514 1514 0, handle_simple_irq, 1515 - IRQ_TYPE_LEVEL_LOW); 1515 + IRQ_TYPE_NONE); 1516 1516 if (err) { 1517 1517 gpiochip_remove(&bank->gpio_chip); 1518 1518 dev_info(dev, "could not add irqchip\n");
+5 -3
drivers/pinctrl/stm32/pinctrl-stm32.c
··· 1092 1092 return -EINVAL; 1093 1093 } 1094 1094 1095 - ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1096 - if (ret) 1097 - return ret; 1095 + if (of_find_property(np, "interrupt-parent", NULL)) { 1096 + ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1097 + if (ret) 1098 + return ret; 1099 + } 1098 1100 1099 1101 for_each_child_of_node(np, child) 1100 1102 if (of_property_read_bool(child, "gpio-controller"))