Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm fixes from Paolo Bonzini:
"x86 guest:
- Avoid false positive for check that only matters on AMD processors
x86:
- Give a hint when Win2016 might fail to boot due to XSAVES &&
!XSAVEC configuration
- Do not allow creating an in-kernel PIT unless an IOAPIC already
exists
RISC-V:
- Allow ISA extensions that were enabled for bare metal in 6.8 (Zbc,
scalar and vector crypto, Zfh[min], Zihintntl, Zvfh[min], Zfa)
S390:
- fix CC for successful PQAP instruction
- fix a race when creating a shadow page"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
x86/coco: Define cc_vendor without CONFIG_ARCH_HAS_CC_PLATFORM
x86/kvm: Fix SEV check in sev_map_percpu_data()
KVM: x86: Give a hint when Win2016 might fail to boot due to XSAVES erratum
KVM: x86: Check irqchip mode before create PIT
KVM: riscv: selftests: Add Zfa extension to get-reg-list test
RISC-V: KVM: Allow Zfa extension for Guest/VM
KVM: riscv: selftests: Add Zvfh[min] extensions to get-reg-list test
RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VM
KVM: riscv: selftests: Add Zihintntl extension to get-reg-list test
RISC-V: KVM: Allow Zihintntl extension for Guest/VM
KVM: riscv: selftests: Add Zfh[min] extensions to get-reg-list test
RISC-V: KVM: Allow Zfh[min] extensions for Guest/VM
KVM: riscv: selftests: Add vector crypto extensions to get-reg-list test
RISC-V: KVM: Allow vector crypto extensions for Guest/VM
KVM: riscv: selftests: Add scaler crypto extensions to get-reg-list test
RISC-V: KVM: Allow scalar crypto extensions for Guest/VM
KVM: riscv: selftests: Add Zbc extension to get-reg-list test
RISC-V: KVM: Allow Zbc extension for Guest/VM
KVM: s390: fix cc for successful PQAP
KVM: s390: vsie: fix race during shadow creation
+263
-6
+27
arch/riscv/include/uapi/asm/kvm.h
+27
arch/riscv/include/uapi/asm/kvm.h
···
139
139
KVM_RISCV_ISA_EXT_ZIHPM,
140
140
KVM_RISCV_ISA_EXT_SMSTATEEN,
141
141
KVM_RISCV_ISA_EXT_ZICOND,
142
+
KVM_RISCV_ISA_EXT_ZBC,
143
+
KVM_RISCV_ISA_EXT_ZBKB,
144
+
KVM_RISCV_ISA_EXT_ZBKC,
145
+
KVM_RISCV_ISA_EXT_ZBKX,
146
+
KVM_RISCV_ISA_EXT_ZKND,
147
+
KVM_RISCV_ISA_EXT_ZKNE,
148
+
KVM_RISCV_ISA_EXT_ZKNH,
149
+
KVM_RISCV_ISA_EXT_ZKR,
150
+
KVM_RISCV_ISA_EXT_ZKSED,
151
+
KVM_RISCV_ISA_EXT_ZKSH,
152
+
KVM_RISCV_ISA_EXT_ZKT,
153
+
KVM_RISCV_ISA_EXT_ZVBB,
154
+
KVM_RISCV_ISA_EXT_ZVBC,
155
+
KVM_RISCV_ISA_EXT_ZVKB,
156
+
KVM_RISCV_ISA_EXT_ZVKG,
157
+
KVM_RISCV_ISA_EXT_ZVKNED,
158
+
KVM_RISCV_ISA_EXT_ZVKNHA,
159
+
KVM_RISCV_ISA_EXT_ZVKNHB,
160
+
KVM_RISCV_ISA_EXT_ZVKSED,
161
+
KVM_RISCV_ISA_EXT_ZVKSH,
162
+
KVM_RISCV_ISA_EXT_ZVKT,
163
+
KVM_RISCV_ISA_EXT_ZFH,
164
+
KVM_RISCV_ISA_EXT_ZFHMIN,
165
+
KVM_RISCV_ISA_EXT_ZIHINTNTL,
166
+
KVM_RISCV_ISA_EXT_ZVFH,
167
+
KVM_RISCV_ISA_EXT_ZVFHMIN,
168
+
KVM_RISCV_ISA_EXT_ZFA,
142
169
KVM_RISCV_ISA_EXT_MAX,
143
170
};
144
171
+54
arch/riscv/kvm/vcpu_onereg.c
+54
arch/riscv/kvm/vcpu_onereg.c
···
42
42
KVM_ISA_EXT_ARR(SVPBMT),
43
43
KVM_ISA_EXT_ARR(ZBA),
44
44
KVM_ISA_EXT_ARR(ZBB),
45
+
KVM_ISA_EXT_ARR(ZBC),
46
+
KVM_ISA_EXT_ARR(ZBKB),
47
+
KVM_ISA_EXT_ARR(ZBKC),
48
+
KVM_ISA_EXT_ARR(ZBKX),
45
49
KVM_ISA_EXT_ARR(ZBS),
50
+
KVM_ISA_EXT_ARR(ZFA),
51
+
KVM_ISA_EXT_ARR(ZFH),
52
+
KVM_ISA_EXT_ARR(ZFHMIN),
46
53
KVM_ISA_EXT_ARR(ZICBOM),
47
54
KVM_ISA_EXT_ARR(ZICBOZ),
48
55
KVM_ISA_EXT_ARR(ZICNTR),
49
56
KVM_ISA_EXT_ARR(ZICOND),
50
57
KVM_ISA_EXT_ARR(ZICSR),
51
58
KVM_ISA_EXT_ARR(ZIFENCEI),
59
+
KVM_ISA_EXT_ARR(ZIHINTNTL),
52
60
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
53
61
KVM_ISA_EXT_ARR(ZIHPM),
62
+
KVM_ISA_EXT_ARR(ZKND),
63
+
KVM_ISA_EXT_ARR(ZKNE),
64
+
KVM_ISA_EXT_ARR(ZKNH),
65
+
KVM_ISA_EXT_ARR(ZKR),
66
+
KVM_ISA_EXT_ARR(ZKSED),
67
+
KVM_ISA_EXT_ARR(ZKSH),
68
+
KVM_ISA_EXT_ARR(ZKT),
69
+
KVM_ISA_EXT_ARR(ZVBB),
70
+
KVM_ISA_EXT_ARR(ZVBC),
71
+
KVM_ISA_EXT_ARR(ZVFH),
72
+
KVM_ISA_EXT_ARR(ZVFHMIN),
73
+
KVM_ISA_EXT_ARR(ZVKB),
74
+
KVM_ISA_EXT_ARR(ZVKG),
75
+
KVM_ISA_EXT_ARR(ZVKNED),
76
+
KVM_ISA_EXT_ARR(ZVKNHA),
77
+
KVM_ISA_EXT_ARR(ZVKNHB),
78
+
KVM_ISA_EXT_ARR(ZVKSED),
79
+
KVM_ISA_EXT_ARR(ZVKSH),
80
+
KVM_ISA_EXT_ARR(ZVKT),
54
81
};
55
82
56
83
static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
···
119
92
case KVM_RISCV_ISA_EXT_SVNAPOT:
120
93
case KVM_RISCV_ISA_EXT_ZBA:
121
94
case KVM_RISCV_ISA_EXT_ZBB:
95
+
case KVM_RISCV_ISA_EXT_ZBC:
96
+
case KVM_RISCV_ISA_EXT_ZBKB:
97
+
case KVM_RISCV_ISA_EXT_ZBKC:
98
+
case KVM_RISCV_ISA_EXT_ZBKX:
122
99
case KVM_RISCV_ISA_EXT_ZBS:
100
+
case KVM_RISCV_ISA_EXT_ZFA:
101
+
case KVM_RISCV_ISA_EXT_ZFH:
102
+
case KVM_RISCV_ISA_EXT_ZFHMIN:
123
103
case KVM_RISCV_ISA_EXT_ZICNTR:
124
104
case KVM_RISCV_ISA_EXT_ZICOND:
125
105
case KVM_RISCV_ISA_EXT_ZICSR:
126
106
case KVM_RISCV_ISA_EXT_ZIFENCEI:
107
+
case KVM_RISCV_ISA_EXT_ZIHINTNTL:
127
108
case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
128
109
case KVM_RISCV_ISA_EXT_ZIHPM:
110
+
case KVM_RISCV_ISA_EXT_ZKND:
111
+
case KVM_RISCV_ISA_EXT_ZKNE:
112
+
case KVM_RISCV_ISA_EXT_ZKNH:
113
+
case KVM_RISCV_ISA_EXT_ZKR:
114
+
case KVM_RISCV_ISA_EXT_ZKSED:
115
+
case KVM_RISCV_ISA_EXT_ZKSH:
116
+
case KVM_RISCV_ISA_EXT_ZKT:
117
+
case KVM_RISCV_ISA_EXT_ZVBB:
118
+
case KVM_RISCV_ISA_EXT_ZVBC:
119
+
case KVM_RISCV_ISA_EXT_ZVFH:
120
+
case KVM_RISCV_ISA_EXT_ZVFHMIN:
121
+
case KVM_RISCV_ISA_EXT_ZVKB:
122
+
case KVM_RISCV_ISA_EXT_ZVKG:
123
+
case KVM_RISCV_ISA_EXT_ZVKNED:
124
+
case KVM_RISCV_ISA_EXT_ZVKNHA:
125
+
case KVM_RISCV_ISA_EXT_ZVKNHB:
126
+
case KVM_RISCV_ISA_EXT_ZVKSED:
127
+
case KVM_RISCV_ISA_EXT_ZVKSH:
128
+
case KVM_RISCV_ISA_EXT_ZVKT:
129
129
return false;
130
130
/* Extensions which can be disabled using Smstateen */
131
131
case KVM_RISCV_ISA_EXT_SSAIA:
+6
-2
arch/s390/kvm/priv.c
+6
-2
arch/s390/kvm/priv.c
···
676
676
if (vcpu->kvm->arch.crypto.pqap_hook) {
677
677
pqap_hook = *vcpu->kvm->arch.crypto.pqap_hook;
678
678
ret = pqap_hook(vcpu);
679
-
if (!ret && vcpu->run->s.regs.gprs[1] & 0x00ff0000)
680
-
kvm_s390_set_psw_cc(vcpu, 3);
679
+
if (!ret) {
680
+
if (vcpu->run->s.regs.gprs[1] & 0x00ff0000)
681
+
kvm_s390_set_psw_cc(vcpu, 3);
682
+
else
683
+
kvm_s390_set_psw_cc(vcpu, 0);
684
+
}
681
685
up_read(&vcpu->kvm->arch.crypto.pqap_hook_rwsem);
682
686
return ret;
683
687
}
-1
arch/s390/kvm/vsie.c
-1
arch/s390/kvm/vsie.c
+1
arch/s390/mm/gmap.c
+1
arch/s390/mm/gmap.c
+3
-2
arch/x86/include/asm/coco.h
+3
-2
arch/x86/include/asm/coco.h
···
10
10
CC_VENDOR_INTEL,
11
11
};
12
12
13
-
extern enum cc_vendor cc_vendor;
14
-
15
13
#ifdef CONFIG_ARCH_HAS_CC_PLATFORM
14
+
extern enum cc_vendor cc_vendor;
16
15
void cc_set_mask(u64 mask);
17
16
u64 cc_mkenc(u64 val);
18
17
u64 cc_mkdec(u64 val);
19
18
#else
19
+
#define cc_vendor (CC_VENDOR_NONE)
20
+
20
21
static inline u64 cc_mkenc(u64 val)
21
22
{
22
23
return val;
+2
arch/x86/include/asm/kvm_host.h
+2
arch/x86/include/asm/kvm_host.h
+2
-1
arch/x86/kernel/kvm.c
+2
-1
arch/x86/kernel/kvm.c
+50
arch/x86/kvm/hyperv.c
+50
arch/x86/kvm/hyperv.c
···
1322
1322
return false;
1323
1323
}
1324
1324
1325
+
#define KVM_HV_WIN2016_GUEST_ID 0x1040a00003839
1326
+
#define KVM_HV_WIN2016_GUEST_ID_MASK (~GENMASK_ULL(23, 16)) /* mask out the service version */
1327
+
1328
+
/*
1329
+
* Hyper-V enabled Windows Server 2016 SMP VMs fail to boot in !XSAVES && XSAVEC
1330
+
* configuration.
1331
+
* Such configuration can result from, for example, AMD Erratum 1386 workaround.
1332
+
*
1333
+
* Print a notice so users aren't left wondering what's suddenly gone wrong.
1334
+
*/
1335
+
static void __kvm_hv_xsaves_xsavec_maybe_warn(struct kvm_vcpu *vcpu)
1336
+
{
1337
+
struct kvm *kvm = vcpu->kvm;
1338
+
struct kvm_hv *hv = to_kvm_hv(kvm);
1339
+
1340
+
/* Check again under the hv_lock. */
1341
+
if (hv->xsaves_xsavec_checked)
1342
+
return;
1343
+
1344
+
if ((hv->hv_guest_os_id & KVM_HV_WIN2016_GUEST_ID_MASK) !=
1345
+
KVM_HV_WIN2016_GUEST_ID)
1346
+
return;
1347
+
1348
+
hv->xsaves_xsavec_checked = true;
1349
+
1350
+
/* UP configurations aren't affected */
1351
+
if (atomic_read(&kvm->online_vcpus) < 2)
1352
+
return;
1353
+
1354
+
if (guest_cpuid_has(vcpu, X86_FEATURE_XSAVES) ||
1355
+
!guest_cpuid_has(vcpu, X86_FEATURE_XSAVEC))
1356
+
return;
1357
+
1358
+
pr_notice_ratelimited("Booting SMP Windows KVM VM with !XSAVES && XSAVEC. "
1359
+
"If it fails to boot try disabling XSAVEC in the VM config.\n");
1360
+
}
1361
+
1362
+
void kvm_hv_xsaves_xsavec_maybe_warn(struct kvm_vcpu *vcpu)
1363
+
{
1364
+
struct kvm_hv *hv = to_kvm_hv(vcpu->kvm);
1365
+
1366
+
if (!vcpu->arch.hyperv_enabled ||
1367
+
hv->xsaves_xsavec_checked)
1368
+
return;
1369
+
1370
+
mutex_lock(&hv->hv_lock);
1371
+
__kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
1372
+
mutex_unlock(&hv->hv_lock);
1373
+
}
1374
+
1325
1375
static int kvm_hv_set_msr_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data,
1326
1376
bool host)
1327
1377
{
+3
arch/x86/kvm/hyperv.h
+3
arch/x86/kvm/hyperv.h
···
182
182
struct pvclock_vcpu_time_info *hv_clock);
183
183
void kvm_hv_request_tsc_page_update(struct kvm *kvm);
184
184
185
+
void kvm_hv_xsaves_xsavec_maybe_warn(struct kvm_vcpu *vcpu);
186
+
185
187
void kvm_hv_init_vm(struct kvm *kvm);
186
188
void kvm_hv_destroy_vm(struct kvm *kvm);
187
189
int kvm_hv_vcpu_init(struct kvm_vcpu *vcpu);
···
269
267
static inline void kvm_hv_setup_tsc_page(struct kvm *kvm,
270
268
struct pvclock_vcpu_time_info *hv_clock) {}
271
269
static inline void kvm_hv_request_tsc_page_update(struct kvm *kvm) {}
270
+
static inline void kvm_hv_xsaves_xsavec_maybe_warn(struct kvm_vcpu *vcpu) {}
272
271
static inline void kvm_hv_init_vm(struct kvm *kvm) {}
273
272
static inline void kvm_hv_destroy_vm(struct kvm *kvm) {}
274
273
static inline int kvm_hv_vcpu_init(struct kvm_vcpu *vcpu)
+7
arch/x86/kvm/x86.c
+7
arch/x86/kvm/x86.c
···
1782
1782
if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1783
1783
kvm_mmu_reset_context(vcpu);
1784
1784
1785
+
if (!static_cpu_has(X86_FEATURE_XSAVES) &&
1786
+
(efer & EFER_SVME))
1787
+
kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
1788
+
1785
1789
return 0;
1786
1790
}
1787
1791
···
7019
7015
mutex_lock(&kvm->lock);
7020
7016
r = -EEXIST;
7021
7017
if (kvm->arch.vpit)
7018
+
goto create_pit_unlock;
7019
+
r = -ENOENT;
7020
+
if (!pic_in_kernel(kvm))
7022
7021
goto create_pit_unlock;
7023
7022
r = -ENOMEM;
7024
7023
kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
+108
tools/testing/selftests/kvm/riscv/get-reg-list.c
+108
tools/testing/selftests/kvm/riscv/get-reg-list.c
···
49
49
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
50
50
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
51
51
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB:
52
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC:
53
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB:
54
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC:
55
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX:
52
56
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS:
57
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
58
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
59
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
53
60
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
54
61
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
55
62
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
56
63
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
57
64
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
58
65
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI:
66
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL:
59
67
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
60
68
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM:
69
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND:
70
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE:
71
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH:
72
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR:
73
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:
74
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:
75
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:
76
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
77
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
78
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:
79
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:
80
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
81
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:
82
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:
83
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:
84
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:
85
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:
86
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:
87
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:
61
88
/*
62
89
* Like ISA_EXT registers, SBI_EXT registers are only visible when the
63
90
* host supports them and disabling them does not affect the visibility
···
421
394
KVM_ISA_EXT_ARR(SVPBMT),
422
395
KVM_ISA_EXT_ARR(ZBA),
423
396
KVM_ISA_EXT_ARR(ZBB),
397
+
KVM_ISA_EXT_ARR(ZBC),
398
+
KVM_ISA_EXT_ARR(ZBKB),
399
+
KVM_ISA_EXT_ARR(ZBKC),
400
+
KVM_ISA_EXT_ARR(ZBKX),
424
401
KVM_ISA_EXT_ARR(ZBS),
402
+
KVM_ISA_EXT_ARR(ZFA),
403
+
KVM_ISA_EXT_ARR(ZFH),
404
+
KVM_ISA_EXT_ARR(ZFHMIN),
425
405
KVM_ISA_EXT_ARR(ZICBOM),
426
406
KVM_ISA_EXT_ARR(ZICBOZ),
427
407
KVM_ISA_EXT_ARR(ZICNTR),
428
408
KVM_ISA_EXT_ARR(ZICOND),
429
409
KVM_ISA_EXT_ARR(ZICSR),
430
410
KVM_ISA_EXT_ARR(ZIFENCEI),
411
+
KVM_ISA_EXT_ARR(ZIHINTNTL),
431
412
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
432
413
KVM_ISA_EXT_ARR(ZIHPM),
414
+
KVM_ISA_EXT_ARR(ZKND),
415
+
KVM_ISA_EXT_ARR(ZKNE),
416
+
KVM_ISA_EXT_ARR(ZKNH),
417
+
KVM_ISA_EXT_ARR(ZKR),
418
+
KVM_ISA_EXT_ARR(ZKSED),
419
+
KVM_ISA_EXT_ARR(ZKSH),
420
+
KVM_ISA_EXT_ARR(ZKT),
421
+
KVM_ISA_EXT_ARR(ZVBB),
422
+
KVM_ISA_EXT_ARR(ZVBC),
423
+
KVM_ISA_EXT_ARR(ZVFH),
424
+
KVM_ISA_EXT_ARR(ZVFHMIN),
425
+
KVM_ISA_EXT_ARR(ZVKB),
426
+
KVM_ISA_EXT_ARR(ZVKG),
427
+
KVM_ISA_EXT_ARR(ZVKNED),
428
+
KVM_ISA_EXT_ARR(ZVKNHA),
429
+
KVM_ISA_EXT_ARR(ZVKNHB),
430
+
KVM_ISA_EXT_ARR(ZVKSED),
431
+
KVM_ISA_EXT_ARR(ZVKSH),
432
+
KVM_ISA_EXT_ARR(ZVKT),
433
433
};
434
434
435
435
if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
···
942
888
KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
943
889
KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
944
890
KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);
891
+
KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC);
892
+
KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);
893
+
KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);
894
+
KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);
945
895
KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
896
+
KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
897
+
KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
898
+
KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
946
899
KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
947
900
KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
948
901
KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
949
902
KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
950
903
KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
951
904
KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);
905
+
KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL);
952
906
KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);
953
907
KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
908
+
KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND);
909
+
KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE);
910
+
KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH);
911
+
KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR);
912
+
KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);
913
+
KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);
914
+
KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
915
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
916
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
917
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);
918
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);
919
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
920
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);
921
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);
922
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);
923
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);
924
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);
925
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);
926
+
KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);
954
927
955
928
struct vcpu_reg_list *vcpu_configs[] = {
956
929
&config_sbi_base,
···
995
914
&config_svpbmt,
996
915
&config_zba,
997
916
&config_zbb,
917
+
&config_zbc,
918
+
&config_zbkb,
919
+
&config_zbkc,
920
+
&config_zbkx,
998
921
&config_zbs,
922
+
&config_zfa,
923
+
&config_zfh,
924
+
&config_zfhmin,
999
925
&config_zicbom,
1000
926
&config_zicboz,
1001
927
&config_zicntr,
1002
928
&config_zicond,
1003
929
&config_zicsr,
1004
930
&config_zifencei,
931
+
&config_zihintntl,
1005
932
&config_zihintpause,
1006
933
&config_zihpm,
934
+
&config_zknd,
935
+
&config_zkne,
936
+
&config_zknh,
937
+
&config_zkr,
938
+
&config_zksed,
939
+
&config_zksh,
940
+
&config_zkt,
941
+
&config_zvbb,
942
+
&config_zvbc,
943
+
&config_zvfh,
944
+
&config_zvfhmin,
945
+
&config_zvkb,
946
+
&config_zvkg,
947
+
&config_zvkned,
948
+
&config_zvknha,
949
+
&config_zvknhb,
950
+
&config_zvksed,
951
+
&config_zvksh,
952
+
&config_zvkt,
1007
953
};
1008
954
int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);