Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf jevents: If the long_desc and desc are identical then drop the long_desc
If the short and long descriptions are the same then save space and
don't store both of them. When storing the desc in the perf_pmu_alias,
don't duplicate the desc into the long_desc.
By avoiding storing the duplicate the size of the events string in the
binary on x86 is reduced by 29,840 bytes.
Fix tests that expect a duplicated description.
Signed-off-by: Ian Rogers <irogers@google.com>
Link: https://lore.kernel.org/r/20250710235126.1086011-9-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
authored by
Ian Rogers
and committed by
Namhyung Kim
5c255832
3787cdaf
+68
-88
+64
-64
tools/perf/pmu-events/empty-pmu-events.c
+64
-64
tools/perf/pmu-events/empty-pmu-events.c
···
40
40
/* offset=1475 */ "dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\000\000\000\000"
41
41
/* offset=1608 */ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\000\000\000\000"
42
42
/* offset=1726 */ "hisi_sccl,ddrc\000"
43
-
/* offset=1741 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\000\000\000DDRC write commands\000"
44
-
/* offset=1830 */ "uncore_cbox\000"
45
-
/* offset=1842 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000\000\000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000"
46
-
/* offset=2076 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000\000\000\000UNC_CBO_HYPHEN\000"
47
-
/* offset=2144 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000\000\000\000UNC_CBO_TWO_HYPH\000"
48
-
/* offset=2218 */ "hisi_sccl,l3c\000"
49
-
/* offset=2232 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000\000\000\000Total read hits\000"
50
-
/* offset=2315 */ "uncore_imc_free_running\000"
51
-
/* offset=2339 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000\000\000\000Total cache misses\000"
52
-
/* offset=2437 */ "uncore_imc\000"
53
-
/* offset=2448 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000\000\000\000Total cache hits\000"
54
-
/* offset=2529 */ "uncore_sys_ddr_pmu\000"
55
-
/* offset=2548 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000\000\000"
56
-
/* offset=2624 */ "uncore_sys_ccn_pmu\000"
57
-
/* offset=2643 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000\000\000"
58
-
/* offset=2720 */ "uncore_sys_cmn_pmu\000"
59
-
/* offset=2739 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000\000\000"
60
-
/* offset=2882 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000"
61
-
/* offset=2904 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000"
62
-
/* offset=2967 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000"
63
-
/* offset=3133 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000"
64
-
/* offset=3197 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000"
65
-
/* offset=3264 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000"
66
-
/* offset=3335 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000"
67
-
/* offset=3429 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000"
68
-
/* offset=3563 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000"
69
-
/* offset=3627 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000"
70
-
/* offset=3695 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000"
71
-
/* offset=3765 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000"
72
-
/* offset=3787 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000"
73
-
/* offset=3809 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000"
74
-
/* offset=3829 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000"
43
+
/* offset=1741 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\000\000\000\000"
44
+
/* offset=1811 */ "uncore_cbox\000"
45
+
/* offset=1823 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000\000\000\000\000"
46
+
/* offset=1977 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000\000\000\000\000"
47
+
/* offset=2031 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000\000\000\000\000"
48
+
/* offset=2089 */ "hisi_sccl,l3c\000"
49
+
/* offset=2103 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000\000\000\000\000"
50
+
/* offset=2171 */ "uncore_imc_free_running\000"
51
+
/* offset=2195 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000\000\000\000\000"
52
+
/* offset=2275 */ "uncore_imc\000"
53
+
/* offset=2286 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000\000\000\000\000"
54
+
/* offset=2351 */ "uncore_sys_ddr_pmu\000"
55
+
/* offset=2370 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000\000\000"
56
+
/* offset=2446 */ "uncore_sys_ccn_pmu\000"
57
+
/* offset=2465 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000\000\000"
58
+
/* offset=2542 */ "uncore_sys_cmn_pmu\000"
59
+
/* offset=2561 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000\000\000"
60
+
/* offset=2704 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000"
61
+
/* offset=2726 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000"
62
+
/* offset=2789 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000"
63
+
/* offset=2955 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000"
64
+
/* offset=3019 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000"
65
+
/* offset=3086 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000"
66
+
/* offset=3157 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000"
67
+
/* offset=3251 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000"
68
+
/* offset=3385 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000"
69
+
/* offset=3449 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000"
70
+
/* offset=3517 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000"
71
+
/* offset=3587 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000"
72
+
/* offset=3609 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000"
73
+
/* offset=3631 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000"
74
+
/* offset=3651 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000"
75
75
;
76
76
77
77
static const struct compact_pmu_event pmu_events__common_tool[] = {
···
107
107
{ 1373 }, /* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\000\000\000\000 */
108
108
};
109
109
static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_ddrc[] = {
110
-
{ 1741 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\000\000\000DDRC write commands\000 */
110
+
{ 1741 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\000\000\000\000 */
111
111
};
112
112
static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l3c[] = {
113
-
{ 2232 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000\000\000\000Total read hits\000 */
113
+
{ 2103 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000\000\000\000\000 */
114
114
};
115
115
static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox[] = {
116
-
{ 2076 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000\000\000\000UNC_CBO_HYPHEN\000 */
117
-
{ 2144 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000\000\000\000UNC_CBO_TWO_HYPH\000 */
118
-
{ 1842 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000\000\000\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000 */
116
+
{ 1977 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000\000\000\000\000 */
117
+
{ 2031 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000\000\000\000\000 */
118
+
{ 1823 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000\000\000\000\000 */
119
119
};
120
120
static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[] = {
121
-
{ 2448 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000\000\000\000Total cache hits\000 */
121
+
{ 2286 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000\000\000\000\000 */
122
122
};
123
123
static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_free_running[] = {
124
-
{ 2339 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000\000\000\000Total cache misses\000 */
124
+
{ 2195 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000\000\000\000\000 */
125
125
126
126
};
127
127
···
139
139
{
140
140
.entries = pmu_events__test_soc_cpu_hisi_sccl_l3c,
141
141
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c),
142
-
.pmu_name = { 2218 /* hisi_sccl,l3c\000 */ },
142
+
.pmu_name = { 2089 /* hisi_sccl,l3c\000 */ },
143
143
},
144
144
{
145
145
.entries = pmu_events__test_soc_cpu_uncore_cbox,
146
146
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox),
147
-
.pmu_name = { 1830 /* uncore_cbox\000 */ },
147
+
.pmu_name = { 1811 /* uncore_cbox\000 */ },
148
148
},
149
149
{
150
150
.entries = pmu_events__test_soc_cpu_uncore_imc,
151
151
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc),
152
-
.pmu_name = { 2437 /* uncore_imc\000 */ },
152
+
.pmu_name = { 2275 /* uncore_imc\000 */ },
153
153
},
154
154
{
155
155
.entries = pmu_events__test_soc_cpu_uncore_imc_free_running,
156
156
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_running),
157
-
.pmu_name = { 2315 /* uncore_imc_free_running\000 */ },
157
+
.pmu_name = { 2171 /* uncore_imc_free_running\000 */ },
158
158
},
159
159
};
160
160
161
161
static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_core[] = {
162
-
{ 2882 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */
163
-
{ 3563 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000 */
164
-
{ 3335 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */
165
-
{ 3429 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000 */
166
-
{ 3627 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000 */
167
-
{ 3695 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000 */
168
-
{ 2967 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */
169
-
{ 2904 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000 */
170
-
{ 3829 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000 */
171
-
{ 3765 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */
172
-
{ 3787 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */
173
-
{ 3809 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */
174
-
{ 3264 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000 */
175
-
{ 3133 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */
176
-
{ 3197 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */
162
+
{ 2704 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */
163
+
{ 3385 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\00000 */
164
+
{ 3157 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */
165
+
{ 3251 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\00000 */
166
+
{ 3449 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\00000 */
167
+
{ 3517 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\00000 */
168
+
{ 2789 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */
169
+
{ 2726 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\00000 */
170
+
{ 3651 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\00000 */
171
+
{ 3587 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */
172
+
{ 3609 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */
173
+
{ 3631 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */
174
+
{ 3086 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\00000 */
175
+
{ 2955 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */
176
+
{ 3019 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\00000 */
177
177
178
178
};
179
179
···
186
186
};
187
187
188
188
static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ccn_pmu[] = {
189
-
{ 2643 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000\000\000 */
189
+
{ 2465 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000\000\000 */
190
190
};
191
191
static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_cmn_pmu[] = {
192
-
{ 2739 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000\000\000 */
192
+
{ 2561 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000\000\000 */
193
193
};
194
194
static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ddr_pmu[] = {
195
-
{ 2548 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000\000\000 */
195
+
{ 2370 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000\000\000 */
196
196
197
197
};
198
198
···
200
200
{
201
201
.entries = pmu_events__test_soc_sys_uncore_sys_ccn_pmu,
202
202
.num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_pmu),
203
-
.pmu_name = { 2624 /* uncore_sys_ccn_pmu\000 */ },
203
+
.pmu_name = { 2446 /* uncore_sys_ccn_pmu\000 */ },
204
204
},
205
205
{
206
206
.entries = pmu_events__test_soc_sys_uncore_sys_cmn_pmu,
207
207
.num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_pmu),
208
-
.pmu_name = { 2720 /* uncore_sys_cmn_pmu\000 */ },
208
+
.pmu_name = { 2542 /* uncore_sys_cmn_pmu\000 */ },
209
209
},
210
210
{
211
211
.entries = pmu_events__test_soc_sys_uncore_sys_ddr_pmu,
212
212
.num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_pmu),
213
-
.pmu_name = { 2529 /* uncore_sys_ddr_pmu\000 */ },
213
+
.pmu_name = { 2351 /* uncore_sys_ddr_pmu\000 */ },
214
214
},
215
215
};
216
216
+3
tools/perf/pmu-events/jevents.py
+3
tools/perf/pmu-events/jevents.py
···
397
397
self.desc += extra_desc
398
398
if self.long_desc and extra_desc:
399
399
self.long_desc += extra_desc
400
+
if self.desc and self.long_desc and self.desc == self.long_desc:
401
+
# Avoid duplicated descriptions.
402
+
self.long_desc = None
400
403
if arch_std:
401
404
if arch_std.lower() in _arch_std_events:
402
405
event = _arch_std_events[arch_std.lower()].event
-22
tools/perf/tests/pmu-events.c
-22
tools/perf/tests/pmu-events.c
···
53
53
.topic = "branch",
54
54
},
55
55
.alias_str = "event=0x8a",
56
-
.alias_long_desc = "L1 BTB Correction",
57
56
};
58
57
59
58
static const struct perf_pmu_test_event bp_l2_btb_correct = {
···
64
65
.topic = "branch",
65
66
},
66
67
.alias_str = "event=0x8b",
67
-
.alias_long_desc = "L2 BTB Correction",
68
68
};
69
69
70
70
static const struct perf_pmu_test_event segment_reg_loads_any = {
···
75
77
.topic = "other",
76
78
},
77
79
.alias_str = "event=0x6,period=0x30d40,umask=0x80",
78
-
.alias_long_desc = "Number of segment register loads",
79
80
};
80
81
81
82
static const struct perf_pmu_test_event dispatch_blocked_any = {
···
86
89
.topic = "other",
87
90
},
88
91
.alias_str = "event=0x9,period=0x30d40,umask=0x20",
89
-
.alias_long_desc = "Memory cluster signals to block micro-op dispatch for any reason",
90
92
};
91
93
92
94
static const struct perf_pmu_test_event eist_trans = {
···
97
101
.topic = "other",
98
102
},
99
103
.alias_str = "event=0x3a,period=0x30d40",
100
-
.alias_long_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
101
104
};
102
105
103
106
static const struct perf_pmu_test_event l3_cache_rd = {
···
128
133
.event = "event=2",
129
134
.desc = "DDRC write commands",
130
135
.topic = "uncore",
131
-
.long_desc = "DDRC write commands",
132
136
.pmu = "hisi_sccl,ddrc",
133
137
},
134
138
.alias_str = "event=0x2",
135
-
.alias_long_desc = "DDRC write commands",
136
139
.matching_pmu = "hisi_sccl1_ddrc2",
137
140
};
138
141
···
140
147
.event = "event=0x22,umask=0x81",
141
148
.desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
142
149
.topic = "uncore",
143
-
.long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
144
150
.pmu = "uncore_cbox",
145
151
},
146
152
.alias_str = "event=0x22,umask=0x81",
147
-
.alias_long_desc = "A cross-core snoop resulted from L3 Eviction which misses in some processor core",
148
153
.matching_pmu = "uncore_cbox_0",
149
154
};
150
155
···
152
161
.event = "event=0xe0",
153
162
.desc = "UNC_CBO_HYPHEN",
154
163
.topic = "uncore",
155
-
.long_desc = "UNC_CBO_HYPHEN",
156
164
.pmu = "uncore_cbox",
157
165
},
158
166
.alias_str = "event=0xe0",
159
-
.alias_long_desc = "UNC_CBO_HYPHEN",
160
167
.matching_pmu = "uncore_cbox_0",
161
168
};
162
169
···
164
175
.event = "event=0xc0",
165
176
.desc = "UNC_CBO_TWO_HYPH",
166
177
.topic = "uncore",
167
-
.long_desc = "UNC_CBO_TWO_HYPH",
168
178
.pmu = "uncore_cbox",
169
179
},
170
180
.alias_str = "event=0xc0",
171
-
.alias_long_desc = "UNC_CBO_TWO_HYPH",
172
181
.matching_pmu = "uncore_cbox_0",
173
182
};
174
183
···
176
189
.event = "event=7",
177
190
.desc = "Total read hits",
178
191
.topic = "uncore",
179
-
.long_desc = "Total read hits",
180
192
.pmu = "hisi_sccl,l3c",
181
193
},
182
194
.alias_str = "event=0x7",
183
-
.alias_long_desc = "Total read hits",
184
195
.matching_pmu = "hisi_sccl3_l3c7",
185
196
};
186
197
···
188
203
.event = "event=0x12",
189
204
.desc = "Total cache misses",
190
205
.topic = "uncore",
191
-
.long_desc = "Total cache misses",
192
206
.pmu = "uncore_imc_free_running",
193
207
},
194
208
.alias_str = "event=0x12",
195
-
.alias_long_desc = "Total cache misses",
196
209
.matching_pmu = "uncore_imc_free_running_0",
197
210
};
198
211
···
200
217
.event = "event=0x34",
201
218
.desc = "Total cache hits",
202
219
.topic = "uncore",
203
-
.long_desc = "Total cache hits",
204
220
.pmu = "uncore_imc",
205
221
},
206
222
.alias_str = "event=0x34",
207
-
.alias_long_desc = "Total cache hits",
208
223
.matching_pmu = "uncore_imc_0",
209
224
};
210
225
···
227
246
.compat = "v8",
228
247
},
229
248
.alias_str = "event=0x2b",
230
-
.alias_long_desc = "ddr write-cycles event",
231
249
.matching_pmu = "uncore_sys_ddr_pmu0",
232
250
};
233
251
···
240
260
.compat = "0x01",
241
261
},
242
262
.alias_str = "config=0x2c",
243
-
.alias_long_desc = "ccn read-cycles event",
244
263
.matching_pmu = "uncore_sys_ccn_pmu4",
245
264
};
246
265
···
253
274
.compat = "(434|436|43c|43a).*",
254
275
},
255
276
.alias_str = "eventid=0x1,type=0x5",
256
-
.alias_long_desc = "Counts total cache misses in first lookup result (high priority)",
257
277
.matching_pmu = "uncore_sys_cmn_pmu0",
258
278
};
259
279
+1
-2
tools/perf/util/pmu.c
+1
-2
tools/perf/util/pmu.c
···
623
623
624
624
alias->name = strdup(name);
625
625
alias->desc = desc ? strdup(desc) : NULL;
626
-
alias->long_desc = long_desc ? strdup(long_desc) :
627
-
desc ? strdup(desc) : NULL;
626
+
alias->long_desc = long_desc ? strdup(long_desc) : NULL;
628
627
alias->topic = topic ? strdup(topic) : NULL;
629
628
alias->pmu_name = pmu_name ? strdup(pmu_name) : NULL;
630
629
if (unit) {