tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm-soc-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC/dt fixes from Arnd Bergmann:
"This round of fixes is almost exclusively device tree changes, with
trivial defconfig fixes and one compiler warning fix added in.

A number of patches are to fix dtc warnings, in particular on Amlogic,
i.MX and Rockchips.

Other notable changes include:

Renesas:
- Fix a wrong clock configuration on R-Mobile A1
- Fix IOMMU support on R-Car V3H

Allwinner
- Multiple audio fixes

Qualcomm
- Use a safe CPU voltage on MSM8996
- Fixes to match a late audio driver change

Rockchip:
- Some fixes for the newly added Pinebook Pro

NXP i.MX:
- Fix I2C1 pinctrl configuration for i.MX27 phytec-phycard board
- Fix imx6dl-yapp4-ursa board Ethernet connection

OMAP:
- A regression fix for non-existing can device on am534x-idk
- Fix flakey wlan on droid4 where some devices would not connect at
all because of internal pull being used with an external pull
- Fix occasional missed wake-up events on droid4 modem uart"

* tag 'arm-soc-fixes-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (51 commits)
ARM: dts: iwg20d-q7-dbcm-ca: Remove unneeded properties in hdmi@39
ARM: dts: renesas: Make hdmi encoder nodes compliant with DT bindings
arm64: dts: renesas: Make hdmi encoder nodes compliant with DT bindings
arm64: defconfig: add MEDIA_PLATFORM_SUPPORT
arm64: defconfig: ARCH_R8A7795: follow changed config symbol name
arm64: defconfig: add DRM_DISPLAY_CONNECTOR
arm64: defconfig: DRM_DUMB_VGA_DAC: follow changed config symbol name
ARM: oxnas: make ox820_boot_secondary static
ARM: dts: r8a7740: Add missing extal2 to CPG node
ARM: dts: omap4-droid4: Fix occasional lost wakeirq for uart1
ARM: dts: omap4-droid4: Fix flakey wlan by disabling internal pull for gpio
arm64: dts: allwinner: a64: Remove unused SPDIF sound card
arm64: dts: allwinner: a64: pinetab: Fix cpvdd supply name
arm64: dts: meson-g12: remove spurious blank line
arm64: dts: meson-g12b-khadas-vim3: add missing frddr_a status property
arm64: dts: meson-g12-common: fix dwc2 clock names
arm64: dts: meson-g12b-ugoos-am6: fix usb vbus-supply
arm64: dts: freescale: imx8mp: update input_val for AUDIOMIX_BIT_STREAM
ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes
ARM: dts: rockchip: fix pinctrl sub nodename for spi in rk322x.dtsi
...

Linus Torvalds 5c33696f 3d1c1e59

+168 -171
+2 -1
Documentation/devicetree/bindings/dma/fsl-edma.txt
··· 10 10 - compatible : 11 11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC 12 12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp 13 - - "fsl,fsl,ls1028a-edma" for eDMA used similar to that on Vybrid vf610 SoC 13 + - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the 14 + LS1028A SoC. 14 15 - reg : Specifies base physical address(s) and size of the eDMA registers. 15 16 The 1st region is eDMA control register's address and size. 16 17 The 2nd and the 3rd regions are programmable channel multiplexing
+4
arch/arm/boot/dts/am574x-idk.dts
··· 40 40 status = "okay"; 41 41 dual_emac; 42 42 }; 43 + 44 + &m_can0 { 45 + status = "disabled"; 46 + };
+2 -2
arch/arm/boot/dts/dra7.dtsi
··· 172 172 #address-cells = <1>; 173 173 ranges = <0x51000000 0x51000000 0x3000 174 174 0x0 0x20000000 0x10000000>; 175 + dma-ranges; 175 176 /** 176 177 * To enable PCI endpoint mode, disable the pcie1_rc 177 178 * node and enable pcie1_ep mode. ··· 186 185 device_type = "pci"; 187 186 ranges = <0x81000000 0 0 0x03000 0 0x00010000 188 187 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 189 - dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; 190 188 bus-range = <0x00 0xff>; 191 189 #interrupt-cells = <1>; 192 190 num-lanes = <1>; ··· 230 230 #address-cells = <1>; 231 231 ranges = <0x51800000 0x51800000 0x3000 232 232 0x0 0x30000000 0x10000000>; 233 + dma-ranges; 233 234 status = "disabled"; 234 235 pcie2_rc: pcie@51800000 { 235 236 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; ··· 241 240 device_type = "pci"; 242 241 ranges = <0x81000000 0 0 0x03000 0 0x00010000 243 242 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 244 - dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; 245 243 bus-range = <0x00 0xff>; 246 244 #interrupt-cells = <1>; 247 245 num-lanes = <1>;
+2 -2
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
··· 75 75 imx27-phycard-s-rdk { 76 76 pinctrl_i2c1: i2c1grp { 77 77 fsl,pins = < 78 - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 79 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 78 + MX27_PAD_I2C_DATA__I2C_DATA 0x0 79 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 80 80 >; 81 81 }; 82 82
+1 -1
arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
··· 38 38 }; 39 39 40 40 &switch_ports { 41 - /delete-node/ port@2; 41 + /delete-node/ port@3; 42 42 }; 43 43 44 44 &touchscreen {
-2
arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
··· 72 72 adi,input-depth = <8>; 73 73 adi,input-colorspace = "rgb"; 74 74 adi,input-clock = "1x"; 75 - adi,input-style = <1>; 76 - adi,input-justification = "evenly"; 77 75 78 76 ports { 79 77 #address-cells = <1>;
+40 -3
arch/arm/boot/dts/motorola-mapphone-common.dtsi
··· 367 367 }; 368 368 369 369 &mmc3 { 370 + pinctrl-names = "default"; 371 + pinctrl-0 = <&mmc3_pins>; 370 372 vmmc-supply = <&wl12xx_vmmc>; 371 373 /* uart2_tx.sdmmc3_dat1 pad as wakeirq */ 372 374 interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH ··· 471 469 OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) 472 470 OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) 473 471 OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) 472 + >; 473 + }; 474 + 475 + /* 476 + * Android uses PIN_OFF_INPUT_PULLDOWN | PIN_INPUT_PULLUP | MUX_MODE3 477 + * for gpio_100, but the internal pull makes wlan flakey on some 478 + * devices. Off mode value should be tested if we have off mode working 479 + * later on. 480 + */ 481 + mmc3_pins: pinmux_mmc3_pins { 482 + pinctrl-single,pins = < 483 + /* 0x4a10008e gpmc_wait2.gpio_100 d23 */ 484 + OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3) 485 + 486 + /* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */ 487 + OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP | MUX_MODE1) 488 + 489 + /* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */ 490 + OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP | MUX_MODE1) 491 + 492 + /* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */ 493 + OMAP4_IOPAD(0x118, PIN_INPUT | MUX_MODE1) 494 + 495 + /* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */ 496 + OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE1) 497 + 498 + /* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */ 499 + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE1) 500 + 501 + /* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */ 502 + OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1) 474 503 >; 475 504 }; 476 505 ··· 723 690 }; 724 691 725 692 /* 726 - * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for 727 - * uart1 wakeirq. 693 + * The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149 694 + * for wake-up events for both the USB PHY and the UART. We can use gpio_149 695 + * pad as the shared wakeirq for the UART rather than the RX or CTS pad as we 696 + * have gpio_149 trigger before the UART transfer starts. 728 697 */ 729 698 &uart1 { 730 699 pinctrl-names = "default"; 731 700 pinctrl-0 = <&uart1_pins>; 732 701 interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH 733 - &omap4_pmx_core 0xfc>; 702 + &omap4_pmx_core 0x110>; 703 + uart-has-rtscts; 704 + current-speed = <115200>; 734 705 }; 735 706 736 707 &uart3 {
-3
arch/arm/boot/dts/r7s9210.dtsi
··· 304 304 reg = <0xe803b000 0x30>; 305 305 interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 306 306 clocks = <&cpg CPG_MOD 36>; 307 - clock-names = "ostm0"; 308 307 power-domains = <&cpg>; 309 308 status = "disabled"; 310 309 }; ··· 313 314 reg = <0xe803c000 0x30>; 314 315 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 315 316 clocks = <&cpg CPG_MOD 35>; 316 - clock-names = "ostm1"; 317 317 power-domains = <&cpg>; 318 318 status = "disabled"; 319 319 }; ··· 322 324 reg = <0xe803d000 0x30>; 323 325 interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>; 324 326 clocks = <&cpg CPG_MOD 34>; 325 - clock-names = "ostm2"; 326 327 power-domains = <&cpg>; 327 328 status = "disabled"; 328 329 };
+8 -1
arch/arm/boot/dts/r8a73a4.dtsi
··· 131 131 cmt1: timer@e6130000 { 132 132 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; 133 133 reg = <0 0xe6130000 0 0x1004>; 134 - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 134 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 135 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 136 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 137 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 138 + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 139 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 140 + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 141 + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 135 142 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 136 143 clock-names = "fck"; 137 144 power-domains = <&pd_c5>;
+1 -1
arch/arm/boot/dts/r8a7740.dtsi
··· 479 479 cpg_clocks: cpg_clocks@e6150000 { 480 480 compatible = "renesas,r8a7740-cpg-clocks"; 481 481 reg = <0xe6150000 0x10000>; 482 - clocks = <&extal1_clk>, <&extalr_clk>; 482 + clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; 483 483 #clock-cells = <1>; 484 484 clock-output-names = "system", "pllc0", "pllc1", 485 485 "pllc2", "r",
-2
arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
··· 84 84 adi,input-depth = <8>; 85 85 adi,input-colorspace = "rgb"; 86 86 adi,input-clock = "1x"; 87 - adi,input-style = <1>; 88 - adi,input-justification = "evenly"; 89 87 90 88 ports { 91 89 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7790-lager.dts
··· 364 364 adi,input-depth = <8>; 365 365 adi,input-colorspace = "rgb"; 366 366 adi,input-clock = "1x"; 367 - adi,input-style = <1>; 368 - adi,input-justification = "evenly"; 369 367 370 368 ports { 371 369 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7790-stout.dts
··· 297 297 adi,input-depth = <8>; 298 298 adi,input-colorspace = "rgb"; 299 299 adi,input-clock = "1x"; 300 - adi,input-style = <1>; 301 - adi,input-justification = "evenly"; 302 300 303 301 ports { 304 302 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7791-koelsch.dts
··· 387 387 adi,input-depth = <8>; 388 388 adi,input-colorspace = "rgb"; 389 389 adi,input-clock = "1x"; 390 - adi,input-style = <1>; 391 - adi,input-justification = "evenly"; 392 390 393 391 ports { 394 392 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7791-porter.dts
··· 181 181 adi,input-depth = <8>; 182 182 adi,input-colorspace = "rgb"; 183 183 adi,input-clock = "1x"; 184 - adi,input-style = <1>; 185 - adi,input-justification = "evenly"; 186 184 187 185 ports { 188 186 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7792-blanche.dts
··· 289 289 adi,input-depth = <8>; 290 290 adi,input-colorspace = "rgb"; 291 291 adi,input-clock = "1x"; 292 - adi,input-style = <1>; 293 - adi,input-justification = "evenly"; 294 292 295 293 ports { 296 294 #address-cells = <1>;
+4 -8
arch/arm/boot/dts/r8a7792-wheat.dts
··· 249 249 */ 250 250 hdmi@3d { 251 251 compatible = "adi,adv7513"; 252 - reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; 253 - reg-names = "main", "cec", "edid", "packet"; 252 + reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; 253 + reg-names = "main", "edid", "cec", "packet"; 254 254 255 255 adi,input-depth = <8>; 256 256 adi,input-colorspace = "rgb"; 257 257 adi,input-clock = "1x"; 258 - adi,input-style = <1>; 259 - adi,input-justification = "evenly"; 260 258 261 259 ports { 262 260 #address-cells = <1>; ··· 278 280 279 281 hdmi@39 { 280 282 compatible = "adi,adv7513"; 281 - reg = <0x39>, <0x29>, <0x49>, <0x59>; 282 - reg-names = "main", "cec", "edid", "packet"; 283 + reg = <0x39>, <0x49>, <0x29>, <0x59>; 284 + reg-names = "main", "edid", "cec", "packet"; 283 285 284 286 adi,input-depth = <8>; 285 287 adi,input-colorspace = "rgb"; 286 288 adi,input-clock = "1x"; 287 - adi,input-style = <1>; 288 - adi,input-justification = "evenly"; 289 289 290 290 ports { 291 291 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7793-gose.dts
··· 366 366 adi,input-depth = <8>; 367 367 adi,input-colorspace = "rgb"; 368 368 adi,input-clock = "1x"; 369 - adi,input-style = <1>; 370 - adi,input-justification = "evenly"; 371 369 372 370 ports { 373 371 #address-cells = <1>;
-2
arch/arm/boot/dts/r8a7794-silk.dts
··· 255 255 adi,input-depth = <8>; 256 256 adi,input-colorspace = "rgb"; 257 257 adi,input-clock = "1x"; 258 - adi,input-style = <1>; 259 - adi,input-justification = "evenly"; 260 258 261 259 ports { 262 260 #address-cells = <1>;
+1 -1
arch/arm/boot/dts/rk3036.dtsi
··· 128 128 assigned-clocks = <&cru SCLK_GPU>; 129 129 assigned-clock-rates = <100000000>; 130 130 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 131 - clock-names = "core", "bus"; 131 + clock-names = "bus", "core"; 132 132 resets = <&cru SRST_GPU>; 133 133 status = "disabled"; 134 134 };
+1 -1
arch/arm/boot/dts/rk3228-evb.dts
··· 46 46 #address-cells = <1>; 47 47 #size-cells = <0>; 48 48 49 - phy: phy@0 { 49 + phy: ethernet-phy@0 { 50 50 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 51 51 reg = <0>; 52 52 clocks = <&cru SCLK_MAC_PHY>;
+1 -1
arch/arm/boot/dts/rk3229-xms6.dts
··· 150 150 #address-cells = <1>; 151 151 #size-cells = <0>; 152 152 153 - phy: phy@0 { 153 + phy: ethernet-phy@0 { 154 154 compatible = "ethernet-phy-id1234.d400", 155 155 "ethernet-phy-ieee802.3-c22"; 156 156 reg = <0>;
+3 -3
arch/arm/boot/dts/rk322x.dtsi
··· 555 555 "pp1", 556 556 "ppmmu1"; 557 557 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 558 - clock-names = "core", "bus"; 558 + clock-names = "bus", "core"; 559 559 resets = <&cru SRST_GPU_A>; 560 560 status = "disabled"; 561 561 }; ··· 1020 1020 }; 1021 1021 }; 1022 1022 1023 - spi-0 { 1023 + spi0 { 1024 1024 spi0_clk: spi0-clk { 1025 1025 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; 1026 1026 }; ··· 1038 1038 }; 1039 1039 }; 1040 1040 1041 - spi-1 { 1041 + spi1 { 1042 1042 spi1_clk: spi1-clk { 1043 1043 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; 1044 1044 };
+1 -1
arch/arm/boot/dts/rk3xxx.dtsi
··· 84 84 compatible = "arm,mali-400"; 85 85 reg = <0x10090000 0x10000>; 86 86 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 87 - clock-names = "core", "bus"; 87 + clock-names = "bus", "core"; 88 88 assigned-clocks = <&cru ACLK_GPU>; 89 89 assigned-clock-rates = <100000000>; 90 90 resets = <&cru SRST_GPU>;
+2 -1
arch/arm/mach-oxnas/platsmp.c
··· 27 27 #define GIC_CPU_CTRL 0x00 28 28 #define GIC_CPU_CTRL_ENABLE 1 29 29 30 - int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle) 30 + static int __init ox820_boot_secondary(unsigned int cpu, 31 + struct task_struct *idle) 31 32 { 32 33 /* 33 34 * Write the address of secondary startup into the
+1 -1
arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
··· 98 98 }; 99 99 100 100 &codec_analog { 101 - hpvcc-supply = <&reg_eldo1>; 101 + cpvdd-supply = <&reg_eldo1>; 102 102 status = "okay"; 103 103 }; 104 104
-18
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
··· 154 154 }; 155 155 }; 156 156 157 - sound_spdif { 158 - compatible = "simple-audio-card"; 159 - simple-audio-card,name = "On-board SPDIF"; 160 - 161 - simple-audio-card,cpu { 162 - sound-dai = <&spdif>; 163 - }; 164 - 165 - simple-audio-card,codec { 166 - sound-dai = <&spdif_out>; 167 - }; 168 - }; 169 - 170 - spdif_out: spdif-out { 171 - #sound-dai-cells = <0>; 172 - compatible = "linux,spdif-dit"; 173 - }; 174 - 175 157 timer { 176 158 compatible = "arm,armv8-timer"; 177 159 allwinner,erratum-unknown1;
+1 -1
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
··· 2319 2319 reg = <0x0 0xff400000 0x0 0x40000>; 2320 2320 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2321 2321 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2322 - clock-names = "ddr"; 2322 + clock-names = "otg"; 2323 2323 phys = <&usb2_phy1>; 2324 2324 phy-names = "usb2-phy"; 2325 2325 dr_mode = "peripheral";
-1
arch/arm64/boot/dts/amlogic/meson-g12.dtsi
··· 1 - 2 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 2 /* 4 3 * Copyright (c) 2019 BayLibre, SAS
+4
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
··· 154 154 clock-latency = <50000>; 155 155 }; 156 156 157 + &frddr_a { 158 + status = "okay"; 159 + }; 160 + 157 161 &frddr_b { 158 162 status = "okay"; 159 163 };
+1 -1
arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts
··· 545 545 &usb { 546 546 status = "okay"; 547 547 dr_mode = "host"; 548 - vbus-regulator = <&usb_pwr_en>; 548 + vbus-supply = <&usb_pwr_en>; 549 549 }; 550 550 551 551 &usb2_phy0 {
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
··· 447 447 448 448 edma0: dma-controller@22c0000 { 449 449 #dma-cells = <2>; 450 - compatible = "fsl,ls1028a-edma"; 450 + compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 451 451 reg = <0x0 0x22c0000 0x0 0x10000>, 452 452 <0x0 0x22d0000 0x0 0x10000>, 453 453 <0x0 0x22e0000 0x0 0x10000>;
+4 -4
arch/arm64/boot/dts/freescale/imx8mm.dtsi
··· 264 264 265 265 aips1: bus@30000000 { 266 266 compatible = "fsl,aips-bus", "simple-bus"; 267 - reg = <0x301f0000 0x10000>; 267 + reg = <0x30000000 0x400000>; 268 268 #address-cells = <1>; 269 269 #size-cells = <1>; 270 270 ranges = <0x30000000 0x30000000 0x400000>; ··· 543 543 544 544 aips2: bus@30400000 { 545 545 compatible = "fsl,aips-bus", "simple-bus"; 546 - reg = <0x305f0000 0x10000>; 546 + reg = <0x30400000 0x400000>; 547 547 #address-cells = <1>; 548 548 #size-cells = <1>; 549 549 ranges = <0x30400000 0x30400000 0x400000>; ··· 603 603 604 604 aips3: bus@30800000 { 605 605 compatible = "fsl,aips-bus", "simple-bus"; 606 - reg = <0x309f0000 0x10000>; 606 + reg = <0x30800000 0x400000>; 607 607 #address-cells = <1>; 608 608 #size-cells = <1>; 609 609 ranges = <0x30800000 0x30800000 0x400000>, ··· 863 863 864 864 aips4: bus@32c00000 { 865 865 compatible = "fsl,aips-bus", "simple-bus"; 866 - reg = <0x32df0000 0x10000>; 866 + reg = <0x32c00000 0x400000>; 867 867 #address-cells = <1>; 868 868 #size-cells = <1>; 869 869 ranges = <0x32c00000 0x32c00000 0x400000>;
+5 -5
arch/arm64/boot/dts/freescale/imx8mn.dtsi
··· 241 241 242 242 aips1: bus@30000000 { 243 243 compatible = "fsl,aips-bus", "simple-bus"; 244 - reg = <0x301f0000 0x10000>; 244 + reg = <0x30000000 0x400000>; 245 245 #address-cells = <1>; 246 246 #size-cells = <1>; 247 247 ranges; ··· 448 448 449 449 aips2: bus@30400000 { 450 450 compatible = "fsl,aips-bus", "simple-bus"; 451 - reg = <0x305f0000 0x10000>; 451 + reg = <0x30400000 0x400000>; 452 452 #address-cells = <1>; 453 453 #size-cells = <1>; 454 454 ranges; ··· 508 508 509 509 aips3: bus@30800000 { 510 510 compatible = "fsl,aips-bus", "simple-bus"; 511 - reg = <0x309f0000 0x10000>; 511 + reg = <0x30800000 0x400000>; 512 512 #address-cells = <1>; 513 513 #size-cells = <1>; 514 514 ranges; ··· 718 718 reg = <0x30bd0000 0x10000>; 719 719 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 720 720 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 721 - <&clk IMX8MN_CLK_SDMA1_ROOT>; 721 + <&clk IMX8MN_CLK_AHB>; 722 722 clock-names = "ipg", "ahb"; 723 723 #dma-cells = <3>; 724 724 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; ··· 754 754 755 755 aips4: bus@32c00000 { 756 756 compatible = "fsl,aips-bus", "simple-bus"; 757 - reg = <0x32df0000 0x10000>; 757 + reg = <0x32c00000 0x400000>; 758 758 #address-cells = <1>; 759 759 #size-cells = <1>; 760 760 ranges;
+23 -23
arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
··· 151 151 #define MX8MP_IOMUXC_ENET_TXC__SIM_M_HADDR22 0x070 0x2D0 0x000 0x7 0x0 152 152 #define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 153 153 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 154 - #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x0 154 + #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 155 155 #define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 156 156 #define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 157 157 #define MX8MP_IOMUXC_ENET_RX_CTL__SIM_M_HADDR23 0x074 0x2D4 0x000 0x7 0x0 158 158 #define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 159 159 #define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 160 160 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 161 - #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x0 161 + #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 162 162 #define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 163 163 #define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 164 164 #define MX8MP_IOMUXC_ENET_RXC__SIM_M_HADDR24 0x078 0x2D8 0x000 0x7 0x0 165 165 #define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 166 166 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 167 - #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x0 167 + #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 168 168 #define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 169 169 #define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 170 170 #define MX8MP_IOMUXC_ENET_RD0__SIM_M_HADDR25 0x07C 0x2DC 0x000 0x7 0x0 171 171 #define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 172 172 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 173 - #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x0 173 + #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 174 174 #define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 175 175 #define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 176 176 #define MX8MP_IOMUXC_ENET_RD1__SIM_M_HADDR26 0x080 0x2E0 0x000 0x7 0x0 ··· 291 291 #define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 292 292 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 293 293 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 294 - #define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x1 294 + #define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 295 295 #define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 296 296 #define MX8MP_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x0C8 0x328 0x000 0x6 0x0 297 297 #define MX8MP_IOMUXC_SD2_DATA0__OBSERVE_MUX_OUT02 0x0C8 0x328 0x000 0x7 0x0 ··· 313 313 #define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 314 314 #define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 315 315 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF_IN 0x0D4 0x334 0x544 0x3 0x1 316 - #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x1 316 + #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 317 317 #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 318 318 #define MX8MP_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 319 319 #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 ··· 487 487 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 488 488 #define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 489 489 #define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 490 - #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x2 490 + #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 491 491 #define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 492 492 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 493 493 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 494 494 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 495 495 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 496 - #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x2 496 + #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 497 497 #define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 498 498 #define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 499 499 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 500 500 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 501 501 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 502 502 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 503 - #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x2 503 + #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 504 504 #define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 505 505 #define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 506 506 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 507 507 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 508 508 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 509 509 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 510 - #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x2 510 + #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 511 511 #define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 512 512 #define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 513 513 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 ··· 528 528 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 529 529 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x150 0x3B0 0x4F8 0x1 0x1 530 530 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 531 - #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x3 531 + #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 532 532 #define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 533 533 #define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 534 534 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 535 535 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x154 0x3B4 0x4FC 0x1 0x1 536 - #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x3 536 + #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 537 537 #define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 538 538 #define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 539 539 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 540 540 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x158 0x3B8 0x500 0x1 0x1 541 - #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x3 541 + #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 542 542 #define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 543 543 #define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 544 544 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 545 545 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x15C 0x3BC 0x504 0x1 0x1 546 - #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x3 546 + #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 547 547 #define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 548 548 #define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 549 549 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 ··· 624 624 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 625 625 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 626 626 #define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 627 - #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x4 627 + #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 628 628 #define MX8MP_IOMUXC_SAI2_RXFS__SIM_M_HSIZE00 0x19C 0x3FC 0x000 0x7 0x0 629 629 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 630 630 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 ··· 632 632 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 633 633 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 634 634 #define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 635 - #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x4 635 + #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 636 636 #define MX8MP_IOMUXC_SAI2_RXC__SIM_M_HSIZE01 0x1A0 0x400 0x000 0x7 0x0 637 637 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 638 638 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 ··· 641 641 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 642 642 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 643 643 #define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 644 - #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x4 644 + #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 645 645 #define MX8MP_IOMUXC_SAI2_RXD0__SIM_M_HSIZE02 0x1A4 0x404 0x000 0x7 0x0 646 646 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 647 647 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 ··· 650 650 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 651 651 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 652 652 #define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 653 - #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x5 653 + #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 654 654 #define MX8MP_IOMUXC_SAI2_TXFS__SIM_M_HWRITE 0x1A8 0x408 0x000 0x7 0x0 655 655 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 656 656 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 657 657 #define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 658 658 #define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 659 - #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x5 659 + #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 660 660 #define MX8MP_IOMUXC_SAI2_TXC__SIM_M_HREADYOUT 0x1AC 0x40C 0x000 0x7 0x0 661 661 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 662 662 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 ··· 680 680 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 681 681 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF_IN 0x1B8 0x418 0x544 0x4 0x2 682 682 #define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 683 - #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x4 683 + #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 684 684 #define MX8MP_IOMUXC_SAI3_RXFS__TPSMP_HTRANS00 0x1B8 0x418 0x000 0x7 0x0 685 685 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 686 686 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 ··· 697 697 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 698 698 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 699 699 #define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 700 - #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x6 700 + #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 701 701 #define MX8MP_IOMUXC_SAI3_RXD__TPSMP_HDATA00 0x1C0 0x420 0x000 0x7 0x0 702 702 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 703 703 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 ··· 706 706 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 707 707 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 708 708 #define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 709 - #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x5 709 + #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 710 710 #define MX8MP_IOMUXC_SAI3_TXFS__TPSMP_HDATA01 0x1C4 0x424 0x000 0x7 0x0 711 711 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 712 712 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 ··· 715 715 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 716 716 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 717 717 #define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 718 - #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x6 718 + #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 719 719 #define MX8MP_IOMUXC_SAI3_TXC__TPSMP_HDATA02 0x1C8 0x428 0x000 0x7 0x0 720 720 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 721 721 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0
+3 -3
arch/arm64/boot/dts/freescale/imx8mp.dtsi
··· 145 145 146 146 aips1: bus@30000000 { 147 147 compatible = "fsl,aips-bus", "simple-bus"; 148 - reg = <0x301f0000 0x10000>; 148 + reg = <0x30000000 0x400000>; 149 149 #address-cells = <1>; 150 150 #size-cells = <1>; 151 151 ranges; ··· 318 318 319 319 aips2: bus@30400000 { 320 320 compatible = "fsl,aips-bus", "simple-bus"; 321 - reg = <0x305f0000 0x400000>; 321 + reg = <0x30400000 0x400000>; 322 322 #address-cells = <1>; 323 323 #size-cells = <1>; 324 324 ranges; ··· 378 378 379 379 aips3: bus@30800000 { 380 380 compatible = "fsl,aips-bus", "simple-bus"; 381 - reg = <0x309f0000 0x400000>; 381 + reg = <0x30800000 0x400000>; 382 382 #address-cells = <1>; 383 383 #size-cells = <1>; 384 384 ranges;
+4 -4
arch/arm64/boot/dts/freescale/imx8mq.dtsi
··· 291 291 292 292 bus@30000000 { /* AIPS1 */ 293 293 compatible = "fsl,aips-bus", "simple-bus"; 294 - reg = <0x301f0000 0x10000>; 294 + reg = <0x30000000 0x400000>; 295 295 #address-cells = <1>; 296 296 #size-cells = <1>; 297 297 ranges = <0x30000000 0x30000000 0x400000>; ··· 696 696 697 697 bus@30400000 { /* AIPS2 */ 698 698 compatible = "fsl,aips-bus", "simple-bus"; 699 - reg = <0x305f0000 0x10000>; 699 + reg = <0x30400000 0x400000>; 700 700 #address-cells = <1>; 701 701 #size-cells = <1>; 702 702 ranges = <0x30400000 0x30400000 0x400000>; ··· 756 756 757 757 bus@30800000 { /* AIPS3 */ 758 758 compatible = "fsl,aips-bus", "simple-bus"; 759 - reg = <0x309f0000 0x10000>; 759 + reg = <0x30800000 0x400000>; 760 760 #address-cells = <1>; 761 761 #size-cells = <1>; 762 762 ranges = <0x30800000 0x30800000 0x400000>, ··· 1029 1029 1030 1030 bus@32c00000 { /* AIPS4 */ 1031 1031 compatible = "fsl,aips-bus", "simple-bus"; 1032 - reg = <0x32df0000 0x10000>; 1032 + reg = <0x32c00000 0x400000>; 1033 1033 #address-cells = <1>; 1034 1034 #size-cells = <1>; 1035 1035 ranges = <0x32c00000 0x32c00000 0x400000>;
+20 -3
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
··· 658 658 s11 { 659 659 qcom,saw-leader; 660 660 regulator-always-on; 661 - regulator-min-microvolt = <1230000>; 662 - regulator-max-microvolt = <1230000>; 661 + regulator-min-microvolt = <980000>; 662 + regulator-max-microvolt = <980000>; 663 663 }; 664 664 }; 665 665 ··· 908 908 status = "okay"; 909 909 }; 910 910 911 + &q6asmdai { 912 + dai@0 { 913 + reg = <0>; 914 + }; 915 + 916 + dai@1 { 917 + reg = <1>; 918 + }; 919 + 920 + dai@2 { 921 + reg = <2>; 922 + }; 923 + }; 924 + 911 925 &sound { 912 926 compatible = "qcom,apq8096-sndcard"; 913 927 model = "DB820c"; 914 - audio-routing = "RX_BIAS", "MCLK"; 928 + audio-routing = "RX_BIAS", "MCLK", 929 + "MM_DL1", "MultiMedia1 Playback", 930 + "MM_DL2", "MultiMedia2 Playback", 931 + "MultiMedia3 Capture", "MM_UL3"; 915 932 916 933 mm1-dai-link { 917 934 link-name = "MultiMedia1";
+2
arch/arm64/boot/dts/qcom/msm8996.dtsi
··· 2066 2066 reg = <APR_SVC_ASM>; 2067 2067 q6asmdai: dais { 2068 2068 compatible = "qcom,q6asm-dais"; 2069 + #address-cells = <1>; 2070 + #size-cells = <0>; 2069 2071 #sound-dai-cells = <1>; 2070 2072 iommus = <&lpass_q6_smmu 1>; 2071 2073 };
-3
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
··· 442 442 &q6asmdai { 443 443 dai@0 { 444 444 reg = <0>; 445 - direction = <2>; 446 445 }; 447 446 448 447 dai@1 { 449 448 reg = <1>; 450 - direction = <2>; 451 449 }; 452 450 453 451 dai@2 { 454 452 reg = <2>; 455 - direction = <1>; 456 453 }; 457 454 458 455 dai@3 {
-2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
··· 359 359 &q6asmdai { 360 360 dai@0 { 361 361 reg = <0>; 362 - direction = <2>; 363 362 }; 364 363 365 364 dai@1 { 366 365 reg = <1>; 367 - direction = <1>; 368 366 }; 369 367 }; 370 368
-2
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
··· 137 137 adi,input-depth = <8>; 138 138 adi,input-colorspace = "rgb"; 139 139 adi,input-clock = "1x"; 140 - adi,input-style = <1>; 141 - adi,input-justification = "evenly"; 142 140 143 141 ports { 144 142 #address-cells = <1>;
-2
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
··· 150 150 adi,input-depth = <8>; 151 151 adi,input-colorspace = "rgb"; 152 152 adi,input-clock = "1x"; 153 - adi,input-style = <1>; 154 - adi,input-justification = "evenly"; 155 153 156 154 ports { 157 155 #address-cells = <1>;
-2
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
··· 174 174 adi,input-depth = <8>; 175 175 adi,input-colorspace = "rgb"; 176 176 adi,input-clock = "1x"; 177 - adi,input-style = <1>; 178 - adi,input-justification = "evenly"; 179 177 180 178 ports { 181 179 #address-cells = <1>;
-2
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
··· 141 141 adi,input-depth = <8>; 142 142 adi,input-colorspace = "rgb"; 143 143 adi,input-clock = "1x"; 144 - adi,input-style = <1>; 145 - adi,input-justification = "evenly"; 146 144 147 145 ports { 148 146 #address-cells = <1>;
+2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
··· 1318 1318 ipmmu_vip0: mmu@e7b00000 { 1319 1319 compatible = "renesas,ipmmu-r8a77980"; 1320 1320 reg = <0 0xe7b00000 0 0x1000>; 1321 + renesas,ipmmu-main = <&ipmmu_mm 4>; 1321 1322 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1322 1323 #iommu-cells = <1>; 1323 1324 }; ··· 1326 1325 ipmmu_vip1: mmu@e7960000 { 1327 1326 compatible = "renesas,ipmmu-r8a77980"; 1328 1327 reg = <0 0xe7960000 0 0x1000>; 1328 + renesas,ipmmu-main = <&ipmmu_mm 11>; 1329 1329 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1330 1330 #iommu-cells = <1>; 1331 1331 };
-2
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
··· 360 360 adi,input-depth = <8>; 361 361 adi,input-colorspace = "rgb"; 362 362 adi,input-clock = "1x"; 363 - adi,input-style = <1>; 364 - adi,input-justification = "evenly"; 365 363 366 364 ports { 367 365 #address-cells = <1>;
+2 -4
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
··· 272 272 273 273 hdmi-encoder@39 { 274 274 compatible = "adi,adv7511w"; 275 - reg = <0x39>, <0x3f>, <0x38>, <0x3c>; 276 - reg-names = "main", "edid", "packet", "cec"; 275 + reg = <0x39>, <0x3f>, <0x3c>, <0x38>; 276 + reg-names = "main", "edid", "cec", "packet"; 277 277 interrupt-parent = <&gpio1>; 278 278 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 279 279 ··· 284 284 adi,input-depth = <8>; 285 285 adi,input-colorspace = "rgb"; 286 286 adi,input-clock = "1x"; 287 - adi,input-style = <1>; 288 - adi,input-justification = "evenly"; 289 287 290 288 ports { 291 289 #address-cells = <1>;
+1 -1
arch/arm64/boot/dts/rockchip/px30.dtsi
··· 143 143 }; 144 144 145 145 arm-pmu { 146 - compatible = "arm,cortex-a53-pmu"; 146 + compatible = "arm,cortex-a35-pmu"; 147 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+1 -1
arch/arm64/boot/dts/rockchip/rk3308.dtsi
··· 127 127 }; 128 128 129 129 arm-pmu { 130 - compatible = "arm,cortex-a53-pmu"; 130 + compatible = "arm,cortex-a35-pmu"; 131 131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+2 -3
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
··· 82 82 &gmac2phy { 83 83 phy-supply = <&vcc_phy>; 84 84 clock_in_out = "output"; 85 - assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; 86 85 assigned-clock-rate = <50000000>; 87 86 assigned-clocks = <&cru SCLK_MAC2PHY>; 88 87 assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; 89 - 88 + status = "okay"; 90 89 }; 91 90 92 91 &i2c1 { 93 92 status = "okay"; 94 93 95 - rk805: rk805@18 { 94 + rk805: pmic@18 { 96 95 compatible = "rockchip,rk805"; 97 96 reg = <0x18>; 98 97 interrupt-parent = <&gpio2>;
+1 -1
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
··· 170 170 &i2c1 { 171 171 status = "okay"; 172 172 173 - rk805: rk805@18 { 173 + rk805: pmic@18 { 174 174 compatible = "rockchip,rk805"; 175 175 reg = <0x18>; 176 176 interrupt-parent = <&gpio2>;
-18
arch/arm64/boot/dts/rockchip/rk3328.dtsi
··· 299 299 grf: syscon@ff100000 { 300 300 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 301 301 reg = <0x0 0xff100000 0x0 0x1000>; 302 - #address-cells = <1>; 303 - #size-cells = <1>; 304 302 305 303 io_domains: io-domains { 306 304 compatible = "rockchip,rk3328-io-voltage-domain"; ··· 1792 1794 }; 1793 1795 1794 1796 gmac2phy { 1795 - fephyled_speed100: fephyled-speed100 { 1796 - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1797 - }; 1798 - 1799 1797 fephyled_speed10: fephyled-speed10 { 1800 1798 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1801 1799 }; 1802 1800 1803 1801 fephyled_duplex: fephyled-duplex { 1804 1802 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1805 - }; 1806 - 1807 - fephyled_rxm0: fephyled-rxm0 { 1808 - rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1809 - }; 1810 - 1811 - fephyled_txm0: fephyled-txm0 { 1812 - rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1813 - }; 1814 - 1815 - fephyled_linkm0: fephyled-linkm0 { 1816 - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1817 1803 }; 1818 1804 1819 1805 fephyled_rxm1: fephyled-rxm1 {
+5 -4
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
··· 147 147 "Speaker", "Speaker Amplifier OUTL", 148 148 "Speaker", "Speaker Amplifier OUTR"; 149 149 150 - simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; 150 + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 151 151 simple-audio-card,aux-devs = <&speaker_amp>; 152 152 simple-audio-card,pin-switches = "Speaker"; 153 153 ··· 690 690 fusb0: fusb30x@22 { 691 691 compatible = "fcs,fusb302"; 692 692 reg = <0x22>; 693 - fcs,int_n = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; 693 + interrupt-parent = <&gpio1>; 694 + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; 694 695 pinctrl-names = "default"; 695 696 pinctrl-0 = <&fusb0_int_gpio>; 696 697 vbus-supply = <&vbus_typec>; ··· 789 788 790 789 dc-charger { 791 790 dc_det_gpio: dc-det-gpio { 792 - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 791 + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; 793 792 }; 794 793 }; 795 794 796 795 es8316 { 797 796 hp_det_gpio: hp-det-gpio { 798 - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; 797 + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 799 798 }; 800 799 }; 801 800
+6 -8
arch/arm64/boot/dts/rockchip/rk3399.dtsi
··· 403 403 reset-names = "usb3-otg"; 404 404 status = "disabled"; 405 405 406 - usbdrd_dwc3_0: dwc3 { 406 + usbdrd_dwc3_0: usb@fe800000 { 407 407 compatible = "snps,dwc3"; 408 408 reg = <0x0 0xfe800000 0x0 0x100000>; 409 409 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; ··· 439 439 reset-names = "usb3-otg"; 440 440 status = "disabled"; 441 441 442 - usbdrd_dwc3_1: dwc3 { 442 + usbdrd_dwc3_1: usb@fe900000 { 443 443 compatible = "snps,dwc3"; 444 444 reg = <0x0 0xfe900000 0x0 0x100000>; 445 445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; ··· 1124 1124 pmugrf: syscon@ff320000 { 1125 1125 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1126 1126 reg = <0x0 0xff320000 0x0 0x1000>; 1127 - #address-cells = <1>; 1128 - #size-cells = <1>; 1129 1127 1130 1128 pmu_io_domains: io-domains { 1131 1129 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; ··· 1881 1883 gpu: gpu@ff9a0000 { 1882 1884 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1883 1885 reg = <0x0 0xff9a0000 0x0 0x10000>; 1884 - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1885 - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1886 - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1887 - interrupt-names = "gpu", "job", "mmu"; 1886 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1887 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1888 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1889 + interrupt-names = "job", "mmu", "gpu"; 1888 1890 clocks = <&cru ACLK_GPU>; 1889 1891 #cooling-cells = <2>; 1890 1892 power-domains = <&power RK3399_PD_GPU>;
+6 -3
arch/arm64/configs/defconfig
··· 208 208 CONFIG_PCIE_ARMADA_8K=y 209 209 CONFIG_PCIE_KIRIN=y 210 210 CONFIG_PCIE_HISI_STB=y 211 - CONFIG_PCIE_TEGRA194=m 211 + CONFIG_PCIE_TEGRA194_HOST=m 212 212 CONFIG_DEVTMPFS=y 213 213 CONFIG_DEVTMPFS_MOUNT=y 214 214 CONFIG_FW_LOADER_USER_HELPER=y ··· 567 567 CONFIG_MEDIA_SDR_SUPPORT=y 568 568 CONFIG_MEDIA_CONTROLLER=y 569 569 CONFIG_VIDEO_V4L2_SUBDEV_API=y 570 + CONFIG_MEDIA_PLATFORM_SUPPORT=y 570 571 # CONFIG_DVB_NET is not set 571 572 CONFIG_MEDIA_USB_SUPPORT=y 572 573 CONFIG_USB_VIDEO_CLASS=m ··· 611 610 CONFIG_DRM_TEGRA=m 612 611 CONFIG_DRM_PANEL_LVDS=m 613 612 CONFIG_DRM_PANEL_SIMPLE=m 614 - CONFIG_DRM_DUMB_VGA_DAC=m 613 + CONFIG_DRM_SIMPLE_BRIDGE=m 615 614 CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m 615 + CONFIG_DRM_DISPLAY_CONNECTOR=m 616 616 CONFIG_DRM_SII902X=m 617 617 CONFIG_DRM_THINE_THC63LVD1024=m 618 618 CONFIG_DRM_TI_SN65DSI86=m ··· 850 848 CONFIG_ARCH_R8A774A1=y 851 849 CONFIG_ARCH_R8A774B1=y 852 850 CONFIG_ARCH_R8A774C0=y 853 - CONFIG_ARCH_R8A7795=y 851 + CONFIG_ARCH_R8A77950=y 852 + CONFIG_ARCH_R8A77951=y 854 853 CONFIG_ARCH_R8A77960=y 855 854 CONFIG_ARCH_R8A77961=y 856 855 CONFIG_ARCH_R8A77965=y