Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King.
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
ARM: 7611/1: VIC: fix bug in VIC irqdomain code
ARM: 7610/1: versatile: bump IRQ numbers
ARM: 7609/1: disable errata work-arounds which access secure registers
ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
+40
-22
+6
arch/arm/Kconfig
+6
arch/arm/Kconfig
···
1229
1229
config ARM_ERRATA_458693
1230
1230
bool "ARM errata: Processor deadlock when a false hazard is created"
1231
1231
depends on CPU_V7
1232
+
depends on !ARCH_MULTIPLATFORM
1232
1233
help
1233
1234
This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1234
1235
erratum. For very specific sequences of memory operations, it is
···
1243
1242
config ARM_ERRATA_460075
1244
1243
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1245
1244
depends on CPU_V7
1245
+
depends on !ARCH_MULTIPLATFORM
1246
1246
help
1247
1247
This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1248
1248
erratum. Any asynchronous access to the L2 cache may encounter a
···
1256
1254
config ARM_ERRATA_742230
1257
1255
bool "ARM errata: DMB operation may be faulty"
1258
1256
depends on CPU_V7 && SMP
1257
+
depends on !ARCH_MULTIPLATFORM
1259
1258
help
1260
1259
This option enables the workaround for the 742230 Cortex-A9
1261
1260
(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
···
1269
1266
config ARM_ERRATA_742231
1270
1267
bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1271
1268
depends on CPU_V7 && SMP
1269
+
depends on !ARCH_MULTIPLATFORM
1272
1270
help
1273
1271
This option enables the workaround for the 742231 Cortex-A9
1274
1272
(r2p0..r2p2) erratum. Under certain conditions, specific to the
···
1320
1316
config ARM_ERRATA_743622
1321
1317
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1322
1318
depends on CPU_V7
1319
+
depends on !ARCH_MULTIPLATFORM
1323
1320
help
1324
1321
This option enables the workaround for the 743622 Cortex-A9
1325
1322
(r2p*) erratum. Under very rare conditions, a faulty
···
1334
1329
config ARM_ERRATA_751472
1335
1330
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1336
1331
depends on CPU_V7
1332
+
depends on !ARCH_MULTIPLATFORM
1337
1333
help
1338
1334
This option enables the workaround for the 751472 Cortex-A9 (prior
1339
1335
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
+7
-2
arch/arm/common/vic.c
+7
-2
arch/arm/common/vic.c
···
206
206
struct device_node *node)
207
207
{
208
208
struct vic_device *v;
209
+
int i;
209
210
210
211
if (vic_id >= ARRAY_SIZE(vic_devices)) {
211
212
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
···
221
220
vic_id++;
222
221
v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
223
222
&vic_irqdomain_ops, v);
223
+
/* create an IRQ mapping for each valid IRQ */
224
+
for (i = 0; i < fls(valid_sources); i++)
225
+
if (valid_sources & (1 << i))
226
+
irq_create_mapping(v->domain, i);
224
227
}
225
228
226
229
static void vic_ack_irq(struct irq_data *d)
···
421
416
return -EIO;
422
417
423
418
/*
424
-
* Passing -1 as first IRQ makes the simple domain allocate descriptors
419
+
* Passing 0 as first IRQ makes the simple domain allocate descriptors
425
420
*/
426
-
__vic_init(regs, -1, ~0, ~0, node);
421
+
__vic_init(regs, 0, ~0, ~0, node);
427
422
428
423
return 0;
429
424
}
-2
arch/arm/mach-imx/Kconfig
-2
arch/arm/mach-imx/Kconfig
+3
-3
arch/arm/mach-versatile/include/mach/irqs.h
+3
-3
arch/arm/mach-versatile/include/mach/irqs.h
···
25
25
* IRQ interrupts definitions are the same as the INT definitions
26
26
* held within platform.h
27
27
*/
28
-
#define IRQ_VIC_START 0
28
+
#define IRQ_VIC_START 32
29
29
#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
30
30
#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
31
31
#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
···
100
100
/*
101
101
* Secondary interrupt controller
102
102
*/
103
-
#define IRQ_SIC_START 32
103
+
#define IRQ_SIC_START 64
104
104
#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
105
105
#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
106
106
#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
···
120
120
#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
121
121
#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
122
122
#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
123
-
#define IRQ_SIC_END 63
123
+
#define IRQ_SIC_END 95
124
124
125
125
#define IRQ_GPIO0_START (IRQ_SIC_END + 1)
126
126
#define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)
-1
arch/arm/mach-vexpress/Kconfig
-1
arch/arm/mach-vexpress/Kconfig
+21
-13
arch/arm/mm/cache-l2x0.c
+21
-13
arch/arm/mm/cache-l2x0.c
···
352
352
/* Unmapped register. */
353
353
sync_reg_offset = L2X0_DUMMY_REG;
354
354
#endif
355
-
outer_cache.set_debug = pl310_set_debug;
355
+
if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
356
+
outer_cache.set_debug = pl310_set_debug;
356
357
break;
357
358
case L2X0_CACHE_ID_PART_L210:
358
359
ways = (aux >> 13) & 0xf;
···
460
459
unsigned long flags;
461
460
462
461
raw_spin_lock_irqsave(&l2x0_lock, flags);
463
-
writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
464
-
writel(end, l2x0_base + offset);
462
+
writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
463
+
writel_relaxed(end, l2x0_base + offset);
465
464
raw_spin_unlock_irqrestore(&l2x0_lock, flags);
466
465
467
466
cache_sync();
···
506
505
507
506
static void aurora_flush_range(unsigned long start, unsigned long end)
508
507
{
509
-
if (!l2_wt_override) {
510
-
start &= ~(CACHE_LINE_SIZE - 1);
511
-
end = ALIGN(end, CACHE_LINE_SIZE);
512
-
while (start != end) {
513
-
unsigned long range_end = calc_range_end(start, end);
508
+
start &= ~(CACHE_LINE_SIZE - 1);
509
+
end = ALIGN(end, CACHE_LINE_SIZE);
510
+
while (start != end) {
511
+
unsigned long range_end = calc_range_end(start, end);
512
+
/*
513
+
* If L2 is forced to WT, the L2 will always be clean and we
514
+
* just need to invalidate.
515
+
*/
516
+
if (l2_wt_override)
514
517
aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
515
-
AURORA_FLUSH_RANGE_REG);
516
-
start = range_end;
517
-
}
518
+
AURORA_INVAL_RANGE_REG);
519
+
else
520
+
aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
521
+
AURORA_FLUSH_RANGE_REG);
522
+
start = range_end;
518
523
}
519
524
}
520
525
···
675
668
static void aurora_resume(void)
676
669
{
677
670
if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
678
-
writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL);
679
-
writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
671
+
writel_relaxed(l2x0_saved_regs.aux_ctrl,
672
+
l2x0_base + L2X0_AUX_CTRL);
673
+
writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
680
674
}
681
675
}
682
676
+3
-1
arch/arm/mm/proc-v7.S
+3
-1
arch/arm/mm/proc-v7.S
···
169
169
orreq r0, r0, r10 @ Enable CPU-specific SMP bits
170
170
mcreq p15, 0, r0, c1, c0, 1
171
171
#endif
172
+
b __v7_setup
172
173
173
174
__v7_pj4b_setup:
174
175
#ifdef CONFIG_CPU_PJ4B
···
246
245
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
247
246
teq r0, r10
248
247
bne 2f
249
-
#ifdef CONFIG_ARM_ERRATA_430973
248
+
#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
249
+
250
250
teq r5, #0x00100000 @ only present in r1p*
251
251
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
252
252
orreq r10, r10, #(1 << 6) @ set IBE to 1