Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - add support for AF to CPT PF uplink mbox
This patch adds support for AF -> CPT PF uplink mailbox messages
and adds a mailbox handler to submit a CPT instruction from AF as
current architecture doesn't allow AF to submit CPT instruction
directly to HW.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Srujana Challa
and committed by
Herbert Xu
5c553114
dee3590c
+98
-2
+4
drivers/crypto/marvell/octeontx2/otx2_cptpf.h
+4
drivers/crypto/marvell/octeontx2/otx2_cptpf.h
···
40
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struct work_struct afpf_mbox_work;
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struct workqueue_struct *afpf_mbox_wq;
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+
struct otx2_mbox afpf_mbox_up;
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+
struct work_struct afpf_mbox_up_work;
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+
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/* VF <=> PF mbox */
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struct otx2_mbox vfpf_mbox;
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struct workqueue_struct *vfpf_mbox_wq;
···
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irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);
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void otx2_cptpf_afpf_mbox_handler(struct work_struct *work);
64
+
void otx2_cptpf_afpf_mbox_up_handler(struct work_struct *work);
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irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg);
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void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work);
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67
+10
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+10
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
···
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473
if (err)
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goto error;
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+
err = otx2_mbox_init(&cptpf->afpf_mbox_up, cptpf->afpf_mbox_base,
477
+
pdev, cptpf->reg_base, MBOX_DIR_PFAF_UP, 1);
478
+
if (err)
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+
goto mbox_cleanup;
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+
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INIT_WORK(&cptpf->afpf_mbox_work, otx2_cptpf_afpf_mbox_handler);
482
+
INIT_WORK(&cptpf->afpf_mbox_up_work, otx2_cptpf_afpf_mbox_up_handler);
477
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mutex_init(&cptpf->lock);
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+
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return 0;
479
486
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+
mbox_cleanup:
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otx2_mbox_destroy(&cptpf->afpf_mbox);
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error:
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destroy_workqueue(cptpf->afpf_mbox_wq);
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return err;
···
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486
{
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destroy_workqueue(cptpf->afpf_mbox_wq);
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otx2_mbox_destroy(&cptpf->afpf_mbox);
489
+
otx2_mbox_destroy(&cptpf->afpf_mbox_up);
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}
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static ssize_t kvf_limits_show(struct device *dev,
+84
-2
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+84
-2
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
···
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irqreturn_t otx2_cptpf_afpf_mbox_intr(int __always_unused irq, void *arg)
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{
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struct otx2_cptpf_dev *cptpf = arg;
227
+
struct otx2_mbox_dev *mdev;
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+
struct otx2_mbox *mbox;
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+
struct mbox_hdr *hdr;
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u64 intr;
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/* Read the interrupt bits */
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intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT);
231
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if (intr & 0x1ULL) {
233
-
/* Schedule work queue function to process the MBOX request */
234
-
queue_work(cptpf->afpf_mbox_wq, &cptpf->afpf_mbox_work);
236
+
mbox = &cptpf->afpf_mbox;
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+
mdev = &mbox->dev[0];
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+
hdr = mdev->mbase + mbox->rx_start;
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+
if (hdr->num_msgs)
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+
/* Schedule work queue function to process the MBOX request */
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+
queue_work(cptpf->afpf_mbox_wq, &cptpf->afpf_mbox_work);
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+
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+
mbox = &cptpf->afpf_mbox_up;
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+
mdev = &mbox->dev[0];
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+
hdr = mdev->mbase + mbox->rx_start;
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+
if (hdr->num_msgs)
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+
/* Schedule work queue function to process the MBOX request */
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+
queue_work(cptpf->afpf_mbox_wq, &cptpf->afpf_mbox_up_work);
235
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/* Clear and ack the interrupt */
236
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otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT,
237
251
0x1ULL);
···
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mdev->msgs_acked++;
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}
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otx2_mbox_reset(afpf_mbox, 0);
369
+
}
370
+
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+
static void handle_msg_cpt_inst_lmtst(struct otx2_cptpf_dev *cptpf,
372
+
struct mbox_msghdr *msg)
373
+
{
374
+
struct cpt_inst_lmtst_req *req = (struct cpt_inst_lmtst_req *)msg;
375
+
struct otx2_cptlfs_info *lfs = &cptpf->lfs;
376
+
struct msg_rsp *rsp;
377
+
378
+
if (cptpf->lfs.lfs_num)
379
+
lfs->ops->send_cmd((union otx2_cpt_inst_s *)req->inst, 1,
380
+
&lfs->lf[0]);
381
+
382
+
rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(&cptpf->afpf_mbox_up, 0,
383
+
sizeof(*rsp));
384
+
if (!rsp)
385
+
return;
386
+
387
+
rsp->hdr.id = msg->id;
388
+
rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
389
+
rsp->hdr.pcifunc = 0;
390
+
rsp->hdr.rc = 0;
391
+
}
392
+
393
+
static void process_afpf_mbox_up_msg(struct otx2_cptpf_dev *cptpf,
394
+
struct mbox_msghdr *msg)
395
+
{
396
+
if (msg->id >= MBOX_MSG_MAX) {
397
+
dev_err(&cptpf->pdev->dev,
398
+
"MBOX msg with unknown ID %d\n", msg->id);
399
+
return;
400
+
}
401
+
402
+
switch (msg->id) {
403
+
case MBOX_MSG_CPT_INST_LMTST:
404
+
handle_msg_cpt_inst_lmtst(cptpf, msg);
405
+
break;
406
+
default:
407
+
otx2_reply_invalid_msg(&cptpf->afpf_mbox_up, 0, 0, msg->id);
408
+
}
409
+
}
410
+
411
+
void otx2_cptpf_afpf_mbox_up_handler(struct work_struct *work)
412
+
{
413
+
struct otx2_cptpf_dev *cptpf;
414
+
struct otx2_mbox_dev *mdev;
415
+
struct mbox_hdr *rsp_hdr;
416
+
struct mbox_msghdr *msg;
417
+
struct otx2_mbox *mbox;
418
+
int offset, i;
419
+
420
+
cptpf = container_of(work, struct otx2_cptpf_dev, afpf_mbox_up_work);
421
+
mbox = &cptpf->afpf_mbox_up;
422
+
mdev = &mbox->dev[0];
423
+
/* Sync mbox data into memory */
424
+
smp_wmb();
425
+
426
+
rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
427
+
offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
428
+
429
+
for (i = 0; i < rsp_hdr->num_msgs; i++) {
430
+
msg = (struct mbox_msghdr *)(mdev->mbase + offset);
431
+
432
+
process_afpf_mbox_up_msg(cptpf, msg);
433
+
434
+
offset = mbox->rx_start + msg->next_msgoff;
435
+
}
436
+
otx2_mbox_msg_send(mbox, 0);
383
437
}