Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: rewrite VLV IOSF SB unit specific read/write functions
Rewrite the VLV IOSF SB unit specific helpers in terms of the new
generic read/write functions. They become even simpler than they were.
The DPIO get/put helpers need to get/put both DPIO units.
v2: get/put both DPIO units
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
Link: https://lore.kernel.org/r/df97dafa0f7b665e2078c392f0dc3edc59655b0a.1747061743.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+22
-55
+20
-53
drivers/gpu/drm/i915/vlv_iosf_sb.c
+20
-53
drivers/gpu/drm/i915/vlv_iosf_sb.c
···
198
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u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
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{
201
-
u32 val = 0;
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-
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
204
-
SB_CRRDDA_NP, addr, &val);
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-
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-
return val;
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+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, addr);
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}
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int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
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{
211
-
return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
212
-
SB_CRWRDA_NP, addr, &val);
206
+
return vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, addr, val);
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}
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u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
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{
217
-
u32 val = 0;
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-
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRRDDA_NP, reg, &val);
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-
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-
return val;
211
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_BUNIT, reg);
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}
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void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
226
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{
227
-
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
228
-
SB_CRWRDA_NP, reg, &val);
216
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_BUNIT, reg, val);
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}
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u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
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{
233
-
u32 val = 0;
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-
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
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-
SB_CRRDDA_NP, addr, &val);
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-
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-
return val;
221
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, addr);
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222
}
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u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
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{
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-
u32 val = 0;
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-
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRRDDA_NP, reg, &val);
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-
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-
return val;
226
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCK, reg);
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227
}
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void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
252
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{
253
-
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
254
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SB_CRWRDA_NP, reg, &val);
231
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_CCK, reg, val);
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}
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u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
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{
259
-
u32 val = 0;
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-
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRRDDA_NP, reg, &val);
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-
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-
return val;
236
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCU, reg);
265
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}
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void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
269
-
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
270
-
SB_CRWRDA_NP, reg, &val);
241
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_CCU, reg, val);
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}
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-
static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
244
+
static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct drm_i915_private *i915,
245
+
enum dpio_phy phy)
274
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{
275
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/*
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* IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
277
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* IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
278
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*/
279
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if (IS_CHERRYVIEW(i915))
280
-
return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO;
252
+
return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO;
281
253
else
282
-
return IOSF_PORT_DPIO;
254
+
return VLV_IOSF_SB_DPIO;
283
255
}
284
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u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg)
286
258
{
287
-
u32 port = vlv_dpio_phy_iosf_port(i915, phy);
288
-
u32 val = 0;
259
+
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(i915, phy);
260
+
u32 val;
289
261
290
-
vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
262
+
val = vlv_iosf_sb_read(i915, unit, reg);
291
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292
264
/*
293
265
* FIXME: There might be some registers where all 1's is a valid value,
···
275
303
void vlv_dpio_write(struct drm_i915_private *i915,
276
304
enum dpio_phy phy, int reg, u32 val)
277
305
{
278
-
u32 port = vlv_dpio_phy_iosf_port(i915, phy);
306
+
enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(i915, phy);
279
307
280
-
vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
308
+
vlv_iosf_sb_write(i915, unit, reg, val);
281
309
}
282
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283
311
u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
284
312
{
285
-
u32 val = 0;
286
-
287
-
vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
288
-
reg, &val);
289
-
return val;
313
+
return vlv_iosf_sb_read(i915, VLV_IOSF_SB_FLISDSI, reg);
290
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}
291
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292
316
void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
293
317
{
294
-
vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
295
-
reg, &val);
318
+
vlv_iosf_sb_write(i915, VLV_IOSF_SB_FLISDSI, reg, val);
296
319
}
297
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298
321
void vlv_iosf_sb_init(struct drm_i915_private *i915)
+2
-2
drivers/gpu/drm/i915/vlv_iosf_sb.h
+2
-2
drivers/gpu/drm/i915/vlv_iosf_sb.h
···
76
76
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77
static inline void vlv_dpio_get(struct drm_i915_private *i915)
78
78
{
79
-
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
79
+
vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
80
80
}
81
81
82
82
u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg);
···
85
85
86
86
static inline void vlv_dpio_put(struct drm_i915_private *i915)
87
87
{
88
-
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
88
+
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2));
89
89
}
90
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91
static inline void vlv_flisdsi_get(struct drm_i915_private *i915)