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dt-bindings: mfd: Convert lpc1850-creg-clk, pc1850-dmamux and phy-lpc18xx-usb-otg to YAML format
Combine the following separate plain text based bindings to YAML:
lpc1850-creg-clk.txt
pc1850-dmamux.txt
phy-lpc18xx-usb-otg.txt
Additional changes:
- remove label in example.
- remove dmamux consumer in example.
- remove clock consumer in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250602143612.943516-1-Frank.Li@nxp.com
Signed-off-by: Lee Jones <lee@kernel.org>
+148
-132
-52
Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt
-52
Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt
···
1
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* NXP LPC1850 CREG clocks
2
-
3
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The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
4
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control registers for two low speed clocks. One of the clocks is a
5
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32 kHz oscillator driver with power up/down and clock gating. Next
6
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is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
7
-
8
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These clocks are used by the RTC and the Event Router peripherals.
9
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The 32 kHz can also be routed to other peripherals to enable low
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power modes.
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-
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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-
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Required properties:
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- compatible:
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Should be "nxp,lpc1850-creg-clk"
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- #clock-cells:
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Shall have value <1>.
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- clocks:
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Shall contain a phandle to the fixed 32 kHz crystal.
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-
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The creg-clk node must be a child of the creg syscon node.
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-
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The following clocks are available from the clock node.
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Clock ID Name
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0 1 kHz clock
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1 32 kHz Oscillator
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Example:
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soc {
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creg: syscon@40043000 {
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compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
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reg = <0x40043000 0x1000>;
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-
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creg_clk: clock-controller {
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compatible = "nxp,lpc1850-creg-clk";
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clocks = <&xtal32>;
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#clock-cells = <1>;
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};
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-
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...
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};
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-
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rtc: rtc@40046000 {
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...
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clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
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clock-names = "rtc", "reg";
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...
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};
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};
-54
Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt
-54
Documentation/devicetree/bindings/dma/lpc1850-dmamux.txt
···
1
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NXP LPC18xx/43xx DMA MUX (DMA request router)
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3
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Required properties:
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- compatible: "nxp,lpc1850-dmamux"
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- reg: Memory map for accessing module
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- #dma-cells: Should be set to <3>.
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* 1st cell contain the master dma request signal
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* 2nd cell contain the mux value (0-3) for the peripheral
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* 3rd cell contain either 1 or 2 depending on the AHB
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master used.
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- dma-requests: Number of DMA requests for the mux
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- dma-masters: phandle pointing to the DMA controller
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-
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The DMA controller node need to have the following poroperties:
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- dma-requests: Number of DMA requests the controller can handle
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Example:
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dmac: dma@40002000 {
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compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
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arm,primecell-periphid = <0x00041080>;
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reg = <0x40002000 0x1000>;
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interrupts = <2>;
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clocks = <&ccu1 CLK_CPU_DMA>;
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clock-names = "apb_pclk";
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#dma-cells = <2>;
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dma-channels = <8>;
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dma-requests = <16>;
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lli-bus-interface-ahb1;
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lli-bus-interface-ahb2;
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mem-bus-interface-ahb1;
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mem-bus-interface-ahb2;
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memcpy-burst-size = <256>;
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memcpy-bus-width = <32>;
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};
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-
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dmamux: dma-mux {
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compatible = "nxp,lpc1850-dmamux";
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#dma-cells = <3>;
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dma-requests = <64>;
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dma-masters = <&dmac>;
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};
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-
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uart0: serial@40081000 {
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compatible = "nxp,lpc1850-uart", "ns16550a";
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reg = <0x40081000 0x1000>;
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reg-shift = <2>;
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interrupts = <24>;
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clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
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clock-names = "uartclk", "reg";
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dmas = <&dmamux 1 1 2
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&dmamux 2 1 2>;
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dma-names = "tx", "rx";
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};
+148
Documentation/devicetree/bindings/mfd/nxp,lpc1850-creg.yaml
+148
Documentation/devicetree/bindings/mfd/nxp,lpc1850-creg.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/nxp,lpc1850-creg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: The NXP LPC18xx/43xx CREG (Configuration Registers) block
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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items:
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- enum:
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- nxp,lpc1850-creg
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- const: syscon
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- const: simple-mfd
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+
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reg:
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maxItems: 1
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+
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clocks:
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maxItems: 1
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+
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resets:
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maxItems: 1
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+
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clock-controller:
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type: object
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description:
32
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The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
33
+
control registers for two low speed clocks. One of the clocks is a
34
+
32 kHz oscillator driver with power up/down and clock gating. Next
35
+
is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
36
+
37
+
These clocks are used by the RTC and the Event Router peripherals.
38
+
The 32 kHz can also be routed to other peripherals to enable low
39
+
power modes.
40
+
41
+
properties:
42
+
compatible:
43
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const: nxp,lpc1850-creg-clk
44
+
45
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clocks:
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maxItems: 1
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+
48
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'#clock-cells':
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const: 1
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description: |
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0 1 kHz clock
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1 32 kHz Oscillator
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+
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required:
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- compatible
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- clocks
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- '#clock-cells'
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+
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additionalProperties: false
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+
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phy:
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type: object
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description: the internal USB OTG PHY in NXP LPC18xx and LPC43xx SoCs
64
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properties:
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compatible:
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const: nxp,lpc1850-usb-otg-phy
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+
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clocks:
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maxItems: 1
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+
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'#phy-cells':
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const: 0
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+
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required:
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- compatible
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- clocks
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- '#phy-cells'
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+
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additionalProperties: false
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+
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dma-mux:
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type: object
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description: NXP LPC18xx/43xx DMA MUX (DMA request router)
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properties:
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compatible:
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const: nxp,lpc1850-dmamux
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+
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'#dma-cells':
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const: 3
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description: |
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Should be set to <3>.
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* 1st cell contain the master dma request signal
93
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* 2nd cell contain the mux value (0-3) for the peripheral
94
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* 3rd cell contain either 1 or 2 depending on the AHB master used.
95
+
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dma-requests:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 64
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description: Number of DMA requests the controller can handle
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dma-masters:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle pointing to the DMA controller
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required:
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- compatible
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- '#dma-cells'
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- dma-masters
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- resets
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+
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additionalProperties: false
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+
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examples:
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- |
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#include <dt-bindings/clock/lpc18xx-ccu.h>
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+
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syscon@40043000 {
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compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
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reg = <0x40043000 0x1000>;
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clocks = <&ccu1 CLK_CPU_CREG>;
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resets = <&rgu 5>;
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+
130
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clock-controller {
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compatible = "nxp,lpc1850-creg-clk";
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clocks = <&xtal32>;
133
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#clock-cells = <1>;
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};
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+
136
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phy {
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compatible = "nxp,lpc1850-usb-otg-phy";
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clocks = <&ccu1 CLK_USB0>;
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#phy-cells = <0>;
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};
141
+
142
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dma-mux {
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compatible = "nxp,lpc1850-dmamux";
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#dma-cells = <3>;
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+
dma-requests = <64>;
146
+
dma-masters = <&dmac>;
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};
148
+
};
-26
Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt
-26
Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt
···
1
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NXP LPC18xx/43xx internal USB OTG PHY binding
2
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---------------------------------------------
3
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4
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This file contains documentation for the internal USB OTG PHY found
5
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in NXP LPC18xx and LPC43xx SoCs.
6
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7
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Required properties:
8
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- compatible : must be "nxp,lpc1850-usb-otg-phy"
9
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- clocks : must be exactly one entry
10
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See: Documentation/devicetree/bindings/clock/clock-bindings.txt
11
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- #phy-cells : must be 0 for this phy
12
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See: Documentation/devicetree/bindings/phy/phy-bindings.txt
13
-
14
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The phy node must be a child of the creg syscon node.
15
-
16
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Example:
17
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creg: syscon@40043000 {
18
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compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
19
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reg = <0x40043000 0x1000>;
20
-
21
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usb0_otg_phy: phy {
22
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compatible = "nxp,lpc1850-usb-otg-phy";
23
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clocks = <&ccu1 CLK_USB0>;
24
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#phy-cells = <0>;
25
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};
26
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};