Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/display: Split DisplayPort header into core and helper
Move DisplayPort protocol constants and structures into the new
header drm_dp.h, which can be used by DRM core components. The
existing header drm_dp_helper.h now only contains helper code for
graphics drivers. No functional changes.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-5-tzimmermann@suse.de
+1693
-1660
+3
Documentation/gpu/drm-kms-helpers.rst
+3
Documentation/gpu/drm-kms-helpers.rst
+1688
include/drm/display/drm_dp.h
+1688
include/drm/display/drm_dp.h
···
1
+
/*
2
+
* Copyright © 2008 Keith Packard
3
+
*
4
+
* Permission to use, copy, modify, distribute, and sell this software and its
5
+
* documentation for any purpose is hereby granted without fee, provided that
6
+
* the above copyright notice appear in all copies and that both that copyright
7
+
* notice and this permission notice appear in supporting documentation, and
8
+
* that the name of the copyright holders not be used in advertising or
9
+
* publicity pertaining to distribution of the software without specific,
10
+
* written prior permission. The copyright holders make no representations
11
+
* about the suitability of this software for any purpose. It is provided "as
12
+
* is" without express or implied warranty.
13
+
*
14
+
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15
+
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16
+
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17
+
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18
+
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19
+
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20
+
* OF THIS SOFTWARE.
21
+
*/
22
+
23
+
#ifndef _DRM_DP_H_
24
+
#define _DRM_DP_H_
25
+
26
+
#include <linux/types.h>
27
+
28
+
/*
29
+
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
30
+
* DP and DPCD versions are independent. Differences from 1.0 are not noted,
31
+
* 1.0 devices basically don't exist in the wild.
32
+
*
33
+
* Abbreviations, in chronological order:
34
+
*
35
+
* eDP: Embedded DisplayPort version 1
36
+
* DPI: DisplayPort Interoperability Guideline v1.1a
37
+
* 1.2: DisplayPort 1.2
38
+
* MST: Multistream Transport - part of DP 1.2a
39
+
*
40
+
* 1.2 formally includes both eDP and DPI definitions.
41
+
*/
42
+
43
+
/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
44
+
#define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
45
+
#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
46
+
#define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
47
+
#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
48
+
#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
49
+
/* bits per component for non-RAW */
50
+
#define DP_MSA_MISC_6_BPC (0 << 5)
51
+
#define DP_MSA_MISC_8_BPC (1 << 5)
52
+
#define DP_MSA_MISC_10_BPC (2 << 5)
53
+
#define DP_MSA_MISC_12_BPC (3 << 5)
54
+
#define DP_MSA_MISC_16_BPC (4 << 5)
55
+
/* bits per component for RAW */
56
+
#define DP_MSA_MISC_RAW_6_BPC (1 << 5)
57
+
#define DP_MSA_MISC_RAW_7_BPC (2 << 5)
58
+
#define DP_MSA_MISC_RAW_8_BPC (3 << 5)
59
+
#define DP_MSA_MISC_RAW_10_BPC (4 << 5)
60
+
#define DP_MSA_MISC_RAW_12_BPC (5 << 5)
61
+
#define DP_MSA_MISC_RAW_14_BPC (6 << 5)
62
+
#define DP_MSA_MISC_RAW_16_BPC (7 << 5)
63
+
/* pixel encoding/colorimetry format */
64
+
#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
65
+
((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
66
+
#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67
+
#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68
+
#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69
+
#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70
+
#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71
+
#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72
+
#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
73
+
#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
74
+
#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
75
+
#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
76
+
#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
77
+
#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
78
+
#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
79
+
#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
80
+
#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
81
+
#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
82
+
#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
83
+
#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
84
+
85
+
#define DP_AUX_MAX_PAYLOAD_BYTES 16
86
+
87
+
#define DP_AUX_I2C_WRITE 0x0
88
+
#define DP_AUX_I2C_READ 0x1
89
+
#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
90
+
#define DP_AUX_I2C_MOT 0x4
91
+
#define DP_AUX_NATIVE_WRITE 0x8
92
+
#define DP_AUX_NATIVE_READ 0x9
93
+
94
+
#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
95
+
#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
96
+
#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
97
+
#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
98
+
99
+
#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
100
+
#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
101
+
#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
102
+
#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
103
+
104
+
/* DPCD Field Address Mapping */
105
+
106
+
/* Receiver Capability */
107
+
#define DP_DPCD_REV 0x000
108
+
# define DP_DPCD_REV_10 0x10
109
+
# define DP_DPCD_REV_11 0x11
110
+
# define DP_DPCD_REV_12 0x12
111
+
# define DP_DPCD_REV_13 0x13
112
+
# define DP_DPCD_REV_14 0x14
113
+
114
+
#define DP_MAX_LINK_RATE 0x001
115
+
116
+
#define DP_MAX_LANE_COUNT 0x002
117
+
# define DP_MAX_LANE_COUNT_MASK 0x1f
118
+
# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
119
+
# define DP_ENHANCED_FRAME_CAP (1 << 7)
120
+
121
+
#define DP_MAX_DOWNSPREAD 0x003
122
+
# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
123
+
# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
124
+
# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
125
+
# define DP_TPS4_SUPPORTED (1 << 7)
126
+
127
+
#define DP_NORP 0x004
128
+
129
+
#define DP_DOWNSTREAMPORT_PRESENT 0x005
130
+
# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
131
+
# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
132
+
# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
133
+
# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
134
+
# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
135
+
# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
136
+
# define DP_FORMAT_CONVERSION (1 << 3)
137
+
# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
138
+
139
+
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
140
+
# define DP_CAP_ANSI_8B10B (1 << 0)
141
+
# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
142
+
143
+
#define DP_DOWN_STREAM_PORT_COUNT 0x007
144
+
# define DP_PORT_COUNT_MASK 0x0f
145
+
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
146
+
# define DP_OUI_SUPPORT (1 << 7)
147
+
148
+
#define DP_RECEIVE_PORT_0_CAP_0 0x008
149
+
# define DP_LOCAL_EDID_PRESENT (1 << 1)
150
+
# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
151
+
152
+
#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
153
+
154
+
#define DP_RECEIVE_PORT_1_CAP_0 0x00a
155
+
#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
156
+
157
+
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
158
+
# define DP_I2C_SPEED_1K 0x01
159
+
# define DP_I2C_SPEED_5K 0x02
160
+
# define DP_I2C_SPEED_10K 0x04
161
+
# define DP_I2C_SPEED_100K 0x08
162
+
# define DP_I2C_SPEED_400K 0x10
163
+
# define DP_I2C_SPEED_1M 0x20
164
+
165
+
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
166
+
# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
167
+
# define DP_FRAMING_CHANGE_CAP (1 << 1)
168
+
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
169
+
170
+
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
171
+
# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
172
+
# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
173
+
174
+
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
175
+
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
176
+
# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
177
+
178
+
#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
179
+
# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
180
+
181
+
/* Multiple stream transport */
182
+
#define DP_FAUX_CAP 0x020 /* 1.2 */
183
+
# define DP_FAUX_CAP_1 (1 << 0)
184
+
185
+
#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
186
+
# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
187
+
# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
188
+
# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
189
+
190
+
#define DP_MSTM_CAP 0x021 /* 1.2 */
191
+
# define DP_MST_CAP (1 << 0)
192
+
# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
193
+
194
+
#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
195
+
196
+
/* AV_SYNC_DATA_BLOCK 1.2 */
197
+
#define DP_AV_GRANULARITY 0x023
198
+
# define DP_AG_FACTOR_MASK (0xf << 0)
199
+
# define DP_AG_FACTOR_3MS (0 << 0)
200
+
# define DP_AG_FACTOR_2MS (1 << 0)
201
+
# define DP_AG_FACTOR_1MS (2 << 0)
202
+
# define DP_AG_FACTOR_500US (3 << 0)
203
+
# define DP_AG_FACTOR_200US (4 << 0)
204
+
# define DP_AG_FACTOR_100US (5 << 0)
205
+
# define DP_AG_FACTOR_10US (6 << 0)
206
+
# define DP_AG_FACTOR_1US (7 << 0)
207
+
# define DP_VG_FACTOR_MASK (0xf << 4)
208
+
# define DP_VG_FACTOR_3MS (0 << 4)
209
+
# define DP_VG_FACTOR_2MS (1 << 4)
210
+
# define DP_VG_FACTOR_1MS (2 << 4)
211
+
# define DP_VG_FACTOR_500US (3 << 4)
212
+
# define DP_VG_FACTOR_200US (4 << 4)
213
+
# define DP_VG_FACTOR_100US (5 << 4)
214
+
215
+
#define DP_AUD_DEC_LAT0 0x024
216
+
#define DP_AUD_DEC_LAT1 0x025
217
+
218
+
#define DP_AUD_PP_LAT0 0x026
219
+
#define DP_AUD_PP_LAT1 0x027
220
+
221
+
#define DP_VID_INTER_LAT 0x028
222
+
223
+
#define DP_VID_PROG_LAT 0x029
224
+
225
+
#define DP_REP_LAT 0x02a
226
+
227
+
#define DP_AUD_DEL_INS0 0x02b
228
+
#define DP_AUD_DEL_INS1 0x02c
229
+
#define DP_AUD_DEL_INS2 0x02d
230
+
/* End of AV_SYNC_DATA_BLOCK */
231
+
232
+
#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
233
+
# define DP_ALPM_CAP (1 << 0)
234
+
235
+
#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
236
+
# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
237
+
238
+
#define DP_GUID 0x030 /* 1.2 */
239
+
240
+
#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
241
+
# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
242
+
243
+
#define DP_DSC_REV 0x061
244
+
# define DP_DSC_MAJOR_MASK (0xf << 0)
245
+
# define DP_DSC_MINOR_MASK (0xf << 4)
246
+
# define DP_DSC_MAJOR_SHIFT 0
247
+
# define DP_DSC_MINOR_SHIFT 4
248
+
249
+
#define DP_DSC_RC_BUF_BLK_SIZE 0x062
250
+
# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
251
+
# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
252
+
# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
253
+
# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
254
+
255
+
#define DP_DSC_RC_BUF_SIZE 0x063
256
+
257
+
#define DP_DSC_SLICE_CAP_1 0x064
258
+
# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
259
+
# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
260
+
# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
261
+
# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
262
+
# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
263
+
# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
264
+
# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
265
+
266
+
#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
267
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
268
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
269
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
270
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
271
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
272
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
273
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
274
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
275
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
276
+
# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
277
+
278
+
#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
279
+
# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
280
+
281
+
#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
282
+
283
+
#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
284
+
# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
285
+
# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
286
+
287
+
#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
288
+
# define DP_DSC_RGB (1 << 0)
289
+
# define DP_DSC_YCbCr444 (1 << 1)
290
+
# define DP_DSC_YCbCr422_Simple (1 << 2)
291
+
# define DP_DSC_YCbCr422_Native (1 << 3)
292
+
# define DP_DSC_YCbCr420_Native (1 << 4)
293
+
294
+
#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
295
+
# define DP_DSC_8_BPC (1 << 1)
296
+
# define DP_DSC_10_BPC (1 << 2)
297
+
# define DP_DSC_12_BPC (1 << 3)
298
+
299
+
#define DP_DSC_PEAK_THROUGHPUT 0x06B
300
+
# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
301
+
# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
302
+
# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
303
+
# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
304
+
# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
305
+
# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
306
+
# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
307
+
# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
308
+
# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
309
+
# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
310
+
# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
311
+
# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
312
+
# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
313
+
# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
314
+
# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
315
+
# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
316
+
# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
317
+
# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
318
+
# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
319
+
# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
320
+
# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
321
+
# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
322
+
# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
323
+
# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
324
+
# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
325
+
# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
326
+
# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
327
+
# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
328
+
# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
329
+
# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
330
+
# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
331
+
# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
332
+
# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
333
+
# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
334
+
# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
335
+
# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
336
+
337
+
#define DP_DSC_MAX_SLICE_WIDTH 0x06C
338
+
#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
339
+
#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
340
+
341
+
#define DP_DSC_SLICE_CAP_2 0x06D
342
+
# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
343
+
# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
344
+
# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
345
+
346
+
#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
347
+
# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
348
+
# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
349
+
# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
350
+
# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
351
+
# define DP_DSC_BITS_PER_PIXEL_1 0x4
352
+
353
+
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
354
+
# define DP_PSR_IS_SUPPORTED 1
355
+
# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
356
+
# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
357
+
358
+
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
359
+
# define DP_PSR_NO_TRAIN_ON_EXIT 1
360
+
# define DP_PSR_SETUP_TIME_330 (0 << 1)
361
+
# define DP_PSR_SETUP_TIME_275 (1 << 1)
362
+
# define DP_PSR_SETUP_TIME_220 (2 << 1)
363
+
# define DP_PSR_SETUP_TIME_165 (3 << 1)
364
+
# define DP_PSR_SETUP_TIME_110 (4 << 1)
365
+
# define DP_PSR_SETUP_TIME_55 (5 << 1)
366
+
# define DP_PSR_SETUP_TIME_0 (6 << 1)
367
+
# define DP_PSR_SETUP_TIME_MASK (7 << 1)
368
+
# define DP_PSR_SETUP_TIME_SHIFT 1
369
+
# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
370
+
# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
371
+
372
+
#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
373
+
#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
374
+
375
+
/*
376
+
* 0x80-0x8f describe downstream port capabilities, but there are two layouts
377
+
* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
378
+
* each port's descriptor is one byte wide. If it was set, each port's is
379
+
* four bytes wide, starting with the one byte from the base info. As of
380
+
* DP interop v1.1a only VGA defines additional detail.
381
+
*/
382
+
383
+
/* offset 0 */
384
+
#define DP_DOWNSTREAM_PORT_0 0x80
385
+
# define DP_DS_PORT_TYPE_MASK (7 << 0)
386
+
# define DP_DS_PORT_TYPE_DP 0
387
+
# define DP_DS_PORT_TYPE_VGA 1
388
+
# define DP_DS_PORT_TYPE_DVI 2
389
+
# define DP_DS_PORT_TYPE_HDMI 3
390
+
# define DP_DS_PORT_TYPE_NON_EDID 4
391
+
# define DP_DS_PORT_TYPE_DP_DUALMODE 5
392
+
# define DP_DS_PORT_TYPE_WIRELESS 6
393
+
# define DP_DS_PORT_HPD (1 << 3)
394
+
# define DP_DS_NON_EDID_MASK (0xf << 4)
395
+
# define DP_DS_NON_EDID_720x480i_60 (1 << 4)
396
+
# define DP_DS_NON_EDID_720x480i_50 (2 << 4)
397
+
# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
398
+
# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
399
+
# define DP_DS_NON_EDID_1280x720_60 (5 << 4)
400
+
# define DP_DS_NON_EDID_1280x720_50 (7 << 4)
401
+
/* offset 1 for VGA is maximum megapixels per second / 8 */
402
+
/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
403
+
/* offset 2 for VGA/DVI/HDMI */
404
+
# define DP_DS_MAX_BPC_MASK (3 << 0)
405
+
# define DP_DS_8BPC 0
406
+
# define DP_DS_10BPC 1
407
+
# define DP_DS_12BPC 2
408
+
# define DP_DS_16BPC 3
409
+
/* HDMI2.1 PCON FRL CONFIGURATION */
410
+
# define DP_PCON_MAX_FRL_BW (7 << 2)
411
+
# define DP_PCON_MAX_0GBPS (0 << 2)
412
+
# define DP_PCON_MAX_9GBPS (1 << 2)
413
+
# define DP_PCON_MAX_18GBPS (2 << 2)
414
+
# define DP_PCON_MAX_24GBPS (3 << 2)
415
+
# define DP_PCON_MAX_32GBPS (4 << 2)
416
+
# define DP_PCON_MAX_40GBPS (5 << 2)
417
+
# define DP_PCON_MAX_48GBPS (6 << 2)
418
+
# define DP_PCON_SOURCE_CTL_MODE (1 << 5)
419
+
420
+
/* offset 3 for DVI */
421
+
# define DP_DS_DVI_DUAL_LINK (1 << 1)
422
+
# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
423
+
/* offset 3 for HDMI */
424
+
# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
425
+
# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
426
+
# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
427
+
# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
428
+
# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
429
+
430
+
/*
431
+
* VESA DP-to-HDMI PCON Specification adds caps for colorspace
432
+
* conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
433
+
* Based on the available support the source can enable
434
+
* color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
435
+
* DPCD 3052h.
436
+
*/
437
+
# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
438
+
# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
439
+
# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
440
+
441
+
#define DP_MAX_DOWNSTREAM_PORTS 0x10
442
+
443
+
/* DP Forward error Correction Registers */
444
+
#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
445
+
# define DP_FEC_CAPABLE (1 << 0)
446
+
# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
447
+
# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
448
+
# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
449
+
#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
450
+
451
+
/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
452
+
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
453
+
#define DP_PCON_DSC_ENCODER 0x092
454
+
# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
455
+
# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
456
+
457
+
/* DP-HDMI2.1 PCON DSC Version */
458
+
#define DP_PCON_DSC_VERSION 0x093
459
+
# define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
460
+
# define DP_PCON_DSC_MINOR_MASK (0xF << 4)
461
+
# define DP_PCON_DSC_MAJOR_SHIFT 0
462
+
# define DP_PCON_DSC_MINOR_SHIFT 4
463
+
464
+
/* DP-HDMI2.1 PCON DSC RC Buffer block size */
465
+
#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
466
+
# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
467
+
# define DP_PCON_DSC_RC_BUF_BLK_1KB 0
468
+
# define DP_PCON_DSC_RC_BUF_BLK_4KB 1
469
+
# define DP_PCON_DSC_RC_BUF_BLK_16KB 2
470
+
# define DP_PCON_DSC_RC_BUF_BLK_64KB 3
471
+
472
+
/* DP-HDMI2.1 PCON DSC RC Buffer size */
473
+
#define DP_PCON_DSC_RC_BUF_SIZE 0x095
474
+
475
+
/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
476
+
#define DP_PCON_DSC_SLICE_CAP_1 0x096
477
+
# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
478
+
# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
479
+
# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
480
+
# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
481
+
# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
482
+
# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
483
+
# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
484
+
485
+
#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
486
+
# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
487
+
# define DP_PCON_DSC_DEPTH_9_BITS 0
488
+
# define DP_PCON_DSC_DEPTH_10_BITS 1
489
+
# define DP_PCON_DSC_DEPTH_11_BITS 2
490
+
# define DP_PCON_DSC_DEPTH_12_BITS 3
491
+
# define DP_PCON_DSC_DEPTH_13_BITS 4
492
+
# define DP_PCON_DSC_DEPTH_14_BITS 5
493
+
# define DP_PCON_DSC_DEPTH_15_BITS 6
494
+
# define DP_PCON_DSC_DEPTH_16_BITS 7
495
+
# define DP_PCON_DSC_DEPTH_8_BITS 8
496
+
497
+
#define DP_PCON_DSC_BLOCK_PREDICTION 0x098
498
+
# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
499
+
500
+
#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
501
+
# define DP_PCON_DSC_ENC_RGB (0x1 << 0)
502
+
# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
503
+
# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
504
+
# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
505
+
# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
506
+
507
+
#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
508
+
# define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
509
+
# define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
510
+
# define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
511
+
512
+
#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
513
+
514
+
/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
515
+
#define DP_PCON_DSC_SLICE_CAP_2 0x09C
516
+
# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
517
+
# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
518
+
# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
519
+
520
+
/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
521
+
#define DP_PCON_DSC_BPP_INCR 0x09E
522
+
# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
523
+
# define DP_PCON_DSC_ONE_16TH_BPP 0
524
+
# define DP_PCON_DSC_ONE_8TH_BPP 1
525
+
# define DP_PCON_DSC_ONE_4TH_BPP 2
526
+
# define DP_PCON_DSC_ONE_HALF_BPP 3
527
+
# define DP_PCON_DSC_ONE_BPP 4
528
+
529
+
/* DP Extended DSC Capabilities */
530
+
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
531
+
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
532
+
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
533
+
534
+
/* DFP Capability Extension */
535
+
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
536
+
537
+
/* Link Configuration */
538
+
#define DP_LINK_BW_SET 0x100
539
+
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
540
+
# define DP_LINK_BW_1_62 0x06
541
+
# define DP_LINK_BW_2_7 0x0a
542
+
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
543
+
# define DP_LINK_BW_8_1 0x1e /* 1.4 */
544
+
# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
545
+
# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
546
+
# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
547
+
548
+
#define DP_LANE_COUNT_SET 0x101
549
+
# define DP_LANE_COUNT_MASK 0x0f
550
+
# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
551
+
552
+
#define DP_TRAINING_PATTERN_SET 0x102
553
+
# define DP_TRAINING_PATTERN_DISABLE 0
554
+
# define DP_TRAINING_PATTERN_1 1
555
+
# define DP_TRAINING_PATTERN_2 2
556
+
# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
557
+
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
558
+
# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
559
+
# define DP_TRAINING_PATTERN_MASK 0x3
560
+
# define DP_TRAINING_PATTERN_MASK_1_4 0xf
561
+
562
+
/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
563
+
# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
564
+
# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
565
+
# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
566
+
# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
567
+
# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
568
+
569
+
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
570
+
# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
571
+
572
+
# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
573
+
# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
574
+
# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
575
+
# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
576
+
577
+
#define DP_TRAINING_LANE0_SET 0x103
578
+
#define DP_TRAINING_LANE1_SET 0x104
579
+
#define DP_TRAINING_LANE2_SET 0x105
580
+
#define DP_TRAINING_LANE3_SET 0x106
581
+
582
+
# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
583
+
# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
584
+
# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
585
+
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
586
+
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
587
+
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
588
+
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
589
+
590
+
# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
591
+
# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
592
+
# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
593
+
# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
594
+
# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
595
+
596
+
# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
597
+
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
598
+
599
+
# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
600
+
601
+
#define DP_DOWNSPREAD_CTRL 0x107
602
+
# define DP_SPREAD_AMP_0_5 (1 << 4)
603
+
# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
604
+
605
+
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
606
+
# define DP_SET_ANSI_8B10B (1 << 0)
607
+
# define DP_SET_ANSI_128B132B (1 << 1)
608
+
609
+
#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
610
+
/* bitmask as for DP_I2C_SPEED_CAP */
611
+
612
+
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
613
+
# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
614
+
# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
615
+
# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
616
+
617
+
#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
618
+
#define DP_LINK_QUAL_LANE1_SET 0x10c
619
+
#define DP_LINK_QUAL_LANE2_SET 0x10d
620
+
#define DP_LINK_QUAL_LANE3_SET 0x10e
621
+
# define DP_LINK_QUAL_PATTERN_DISABLE 0
622
+
# define DP_LINK_QUAL_PATTERN_D10_2 1
623
+
# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
624
+
# define DP_LINK_QUAL_PATTERN_PRBS7 3
625
+
# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
626
+
# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
627
+
# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
628
+
# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
629
+
/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
630
+
# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
631
+
# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
632
+
# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
633
+
# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
634
+
# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
635
+
# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
636
+
# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
637
+
# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
638
+
# define DP_LINK_QUAL_PATTERN_SQUARE 0x48
639
+
640
+
#define DP_TRAINING_LANE0_1_SET2 0x10f
641
+
#define DP_TRAINING_LANE2_3_SET2 0x110
642
+
# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
643
+
# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
644
+
# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
645
+
# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
646
+
647
+
#define DP_MSTM_CTRL 0x111 /* 1.2 */
648
+
# define DP_MST_EN (1 << 0)
649
+
# define DP_UP_REQ_EN (1 << 1)
650
+
# define DP_UPSTREAM_IS_SRC (1 << 2)
651
+
652
+
#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
653
+
#define DP_AUDIO_DELAY1 0x113
654
+
#define DP_AUDIO_DELAY2 0x114
655
+
656
+
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
657
+
# define DP_LINK_RATE_SET_SHIFT 0
658
+
# define DP_LINK_RATE_SET_MASK (7 << 0)
659
+
660
+
#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
661
+
# define DP_ALPM_ENABLE (1 << 0)
662
+
# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
663
+
664
+
#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
665
+
# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
666
+
# define DP_IRQ_HPD_ENABLE (1 << 1)
667
+
668
+
#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
669
+
# define DP_PWR_NOT_NEEDED (1 << 0)
670
+
671
+
#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
672
+
# define DP_FEC_READY (1 << 0)
673
+
# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
674
+
# define DP_FEC_ERR_COUNT_DIS (0 << 1)
675
+
# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
676
+
# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
677
+
# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
678
+
# define DP_FEC_LANE_SELECT_MASK (3 << 4)
679
+
# define DP_FEC_LANE_0_SELECT (0 << 4)
680
+
# define DP_FEC_LANE_1_SELECT (1 << 4)
681
+
# define DP_FEC_LANE_2_SELECT (2 << 4)
682
+
# define DP_FEC_LANE_3_SELECT (3 << 4)
683
+
684
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
685
+
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
686
+
687
+
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
688
+
# define DP_DECOMPRESSION_EN (1 << 0)
689
+
#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
690
+
691
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
692
+
# define DP_PSR_ENABLE BIT(0)
693
+
# define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
694
+
# define DP_PSR_CRC_VERIFICATION BIT(2)
695
+
# define DP_PSR_FRAME_CAPTURE BIT(3)
696
+
# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
697
+
# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
698
+
# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
699
+
700
+
#define DP_ADAPTER_CTRL 0x1a0
701
+
# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
702
+
703
+
#define DP_BRANCH_DEVICE_CTRL 0x1a1
704
+
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
705
+
706
+
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
707
+
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
708
+
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
709
+
710
+
/* Link/Sink Device Status */
711
+
#define DP_SINK_COUNT 0x200
712
+
/* prior to 1.2 bit 7 was reserved mbz */
713
+
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
714
+
# define DP_SINK_CP_READY (1 << 6)
715
+
716
+
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
717
+
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
718
+
# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
719
+
# define DP_CP_IRQ (1 << 2)
720
+
# define DP_MCCS_IRQ (1 << 3)
721
+
# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
722
+
# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
723
+
# define DP_SINK_SPECIFIC_IRQ (1 << 6)
724
+
725
+
#define DP_LANE0_1_STATUS 0x202
726
+
#define DP_LANE2_3_STATUS 0x203
727
+
# define DP_LANE_CR_DONE (1 << 0)
728
+
# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
729
+
# define DP_LANE_SYMBOL_LOCKED (1 << 2)
730
+
731
+
#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
732
+
DP_LANE_CHANNEL_EQ_DONE | \
733
+
DP_LANE_SYMBOL_LOCKED)
734
+
735
+
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
736
+
#define DP_INTERLANE_ALIGN_DONE (1 << 0)
737
+
#define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */
738
+
#define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */
739
+
#define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */
740
+
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
741
+
#define DP_LINK_STATUS_UPDATED (1 << 7)
742
+
743
+
#define DP_SINK_STATUS 0x205
744
+
# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
745
+
# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
746
+
# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
747
+
# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
748
+
749
+
#define DP_ADJUST_REQUEST_LANE0_1 0x206
750
+
#define DP_ADJUST_REQUEST_LANE2_3 0x207
751
+
# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
752
+
# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
753
+
# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
754
+
# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
755
+
# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
756
+
# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
757
+
# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
758
+
# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
759
+
760
+
/* DP 2.0 128b/132b Link Layer */
761
+
# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
762
+
# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
763
+
# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
764
+
# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
765
+
766
+
#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
767
+
# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
768
+
# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
769
+
# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
770
+
# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
771
+
# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
772
+
# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
773
+
# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
774
+
# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
775
+
776
+
#define DP_TEST_REQUEST 0x218
777
+
# define DP_TEST_LINK_TRAINING (1 << 0)
778
+
# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
779
+
# define DP_TEST_LINK_EDID_READ (1 << 2)
780
+
# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
781
+
# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
782
+
# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
783
+
# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
784
+
785
+
#define DP_TEST_LINK_RATE 0x219
786
+
# define DP_LINK_RATE_162 (0x6)
787
+
# define DP_LINK_RATE_27 (0xa)
788
+
789
+
#define DP_TEST_LANE_COUNT 0x220
790
+
791
+
#define DP_TEST_PATTERN 0x221
792
+
# define DP_NO_TEST_PATTERN 0x0
793
+
# define DP_COLOR_RAMP 0x1
794
+
# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
795
+
# define DP_COLOR_SQUARE 0x3
796
+
797
+
#define DP_TEST_H_TOTAL_HI 0x222
798
+
#define DP_TEST_H_TOTAL_LO 0x223
799
+
800
+
#define DP_TEST_V_TOTAL_HI 0x224
801
+
#define DP_TEST_V_TOTAL_LO 0x225
802
+
803
+
#define DP_TEST_H_START_HI 0x226
804
+
#define DP_TEST_H_START_LO 0x227
805
+
806
+
#define DP_TEST_V_START_HI 0x228
807
+
#define DP_TEST_V_START_LO 0x229
808
+
809
+
#define DP_TEST_HSYNC_HI 0x22A
810
+
# define DP_TEST_HSYNC_POLARITY (1 << 7)
811
+
# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
812
+
#define DP_TEST_HSYNC_WIDTH_LO 0x22B
813
+
814
+
#define DP_TEST_VSYNC_HI 0x22C
815
+
# define DP_TEST_VSYNC_POLARITY (1 << 7)
816
+
# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
817
+
#define DP_TEST_VSYNC_WIDTH_LO 0x22D
818
+
819
+
#define DP_TEST_H_WIDTH_HI 0x22E
820
+
#define DP_TEST_H_WIDTH_LO 0x22F
821
+
822
+
#define DP_TEST_V_HEIGHT_HI 0x230
823
+
#define DP_TEST_V_HEIGHT_LO 0x231
824
+
825
+
#define DP_TEST_MISC0 0x232
826
+
# define DP_TEST_SYNC_CLOCK (1 << 0)
827
+
# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
828
+
# define DP_TEST_COLOR_FORMAT_SHIFT 1
829
+
# define DP_COLOR_FORMAT_RGB (0 << 1)
830
+
# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
831
+
# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
832
+
# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
833
+
# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
834
+
# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
835
+
# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
836
+
# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
837
+
# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
838
+
# define DP_TEST_BIT_DEPTH_SHIFT 5
839
+
# define DP_TEST_BIT_DEPTH_6 (0 << 5)
840
+
# define DP_TEST_BIT_DEPTH_8 (1 << 5)
841
+
# define DP_TEST_BIT_DEPTH_10 (2 << 5)
842
+
# define DP_TEST_BIT_DEPTH_12 (3 << 5)
843
+
# define DP_TEST_BIT_DEPTH_16 (4 << 5)
844
+
845
+
#define DP_TEST_MISC1 0x233
846
+
# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
847
+
# define DP_TEST_INTERLACED (1 << 1)
848
+
849
+
#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
850
+
851
+
#define DP_TEST_MISC0 0x232
852
+
853
+
#define DP_TEST_CRC_R_CR 0x240
854
+
#define DP_TEST_CRC_G_Y 0x242
855
+
#define DP_TEST_CRC_B_CB 0x244
856
+
857
+
#define DP_TEST_SINK_MISC 0x246
858
+
# define DP_TEST_CRC_SUPPORTED (1 << 5)
859
+
# define DP_TEST_COUNT_MASK 0xf
860
+
861
+
#define DP_PHY_TEST_PATTERN 0x248
862
+
# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
863
+
# define DP_PHY_TEST_PATTERN_NONE 0x0
864
+
# define DP_PHY_TEST_PATTERN_D10_2 0x1
865
+
# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
866
+
# define DP_PHY_TEST_PATTERN_PRBS7 0x3
867
+
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
868
+
# define DP_PHY_TEST_PATTERN_CP2520 0x5
869
+
870
+
#define DP_PHY_SQUARE_PATTERN 0x249
871
+
872
+
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
873
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
874
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
875
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
876
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
877
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
878
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
879
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
880
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
881
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
882
+
#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
883
+
884
+
#define DP_TEST_RESPONSE 0x260
885
+
# define DP_TEST_ACK (1 << 0)
886
+
# define DP_TEST_NAK (1 << 1)
887
+
# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
888
+
889
+
#define DP_TEST_EDID_CHECKSUM 0x261
890
+
891
+
#define DP_TEST_SINK 0x270
892
+
# define DP_TEST_SINK_START (1 << 0)
893
+
#define DP_TEST_AUDIO_MODE 0x271
894
+
#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
895
+
#define DP_TEST_AUDIO_PERIOD_CH1 0x273
896
+
#define DP_TEST_AUDIO_PERIOD_CH2 0x274
897
+
#define DP_TEST_AUDIO_PERIOD_CH3 0x275
898
+
#define DP_TEST_AUDIO_PERIOD_CH4 0x276
899
+
#define DP_TEST_AUDIO_PERIOD_CH5 0x277
900
+
#define DP_TEST_AUDIO_PERIOD_CH6 0x278
901
+
#define DP_TEST_AUDIO_PERIOD_CH7 0x279
902
+
#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
903
+
904
+
#define DP_FEC_STATUS 0x280 /* 1.4 */
905
+
# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
906
+
# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
907
+
908
+
#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
909
+
910
+
#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
911
+
# define DP_FEC_ERROR_COUNT_MASK 0x7F
912
+
# define DP_FEC_ERR_COUNT_VALID (1 << 7)
913
+
914
+
#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
915
+
# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
916
+
# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
917
+
918
+
#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
919
+
/* up to ID_SLOT_63 at 0x2ff */
920
+
921
+
/* Source Device-specific */
922
+
#define DP_SOURCE_OUI 0x300
923
+
924
+
/* Sink Device-specific */
925
+
#define DP_SINK_OUI 0x400
926
+
927
+
/* Branch Device-specific */
928
+
#define DP_BRANCH_OUI 0x500
929
+
#define DP_BRANCH_ID 0x503
930
+
#define DP_BRANCH_REVISION_START 0x509
931
+
#define DP_BRANCH_HW_REV 0x509
932
+
#define DP_BRANCH_SW_REV 0x50A
933
+
934
+
/* Link/Sink Device Power Control */
935
+
#define DP_SET_POWER 0x600
936
+
# define DP_SET_POWER_D0 0x1
937
+
# define DP_SET_POWER_D3 0x2
938
+
# define DP_SET_POWER_MASK 0x3
939
+
# define DP_SET_POWER_D3_AUX_ON 0x5
940
+
941
+
/* eDP-specific */
942
+
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
943
+
# define DP_EDP_11 0x00
944
+
# define DP_EDP_12 0x01
945
+
# define DP_EDP_13 0x02
946
+
# define DP_EDP_14 0x03
947
+
# define DP_EDP_14a 0x04 /* eDP 1.4a */
948
+
# define DP_EDP_14b 0x05 /* eDP 1.4b */
949
+
950
+
#define DP_EDP_GENERAL_CAP_1 0x701
951
+
# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
952
+
# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
953
+
# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
954
+
# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
955
+
# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
956
+
# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
957
+
# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
958
+
# define DP_EDP_SET_POWER_CAP (1 << 7)
959
+
960
+
#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
961
+
# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
962
+
# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
963
+
# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
964
+
# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
965
+
# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
966
+
# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
967
+
# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
968
+
# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
969
+
970
+
#define DP_EDP_GENERAL_CAP_2 0x703
971
+
# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
972
+
973
+
#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
974
+
# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
975
+
# define DP_EDP_X_REGION_CAP_SHIFT 0
976
+
# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
977
+
# define DP_EDP_Y_REGION_CAP_SHIFT 4
978
+
979
+
#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
980
+
# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
981
+
# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
982
+
# define DP_EDP_FRC_ENABLE (1 << 2)
983
+
# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
984
+
# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
985
+
986
+
#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
987
+
# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
988
+
# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
989
+
# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
990
+
# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
991
+
# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
992
+
# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
993
+
# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
994
+
# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
995
+
# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
996
+
# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
997
+
998
+
#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
999
+
#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1000
+
1001
+
#define DP_EDP_PWMGEN_BIT_COUNT 0x724
1002
+
#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1003
+
#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1004
+
# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1005
+
1006
+
#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1007
+
1008
+
#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1009
+
# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
1010
+
1011
+
#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1012
+
#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1013
+
#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1014
+
1015
+
#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1016
+
#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1017
+
#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1018
+
1019
+
#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1020
+
#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1021
+
1022
+
#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1023
+
#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1024
+
1025
+
#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1026
+
# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1027
+
# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1028
+
# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
1029
+
1030
+
/* Sideband MSG Buffers */
1031
+
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1032
+
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1033
+
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1034
+
#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1035
+
1036
+
/* DPRX Event Status Indicator */
1037
+
#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1038
+
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1039
+
1040
+
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1041
+
# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1042
+
# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
1043
+
# define DP_CEC_IRQ (1 << 2)
1044
+
1045
+
#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1046
+
# define RX_CAP_CHANGED (1 << 0)
1047
+
# define LINK_STATUS_CHANGED (1 << 1)
1048
+
# define STREAM_STATUS_CHANGED (1 << 2)
1049
+
# define HDMI_LINK_STATUS_CHANGED (1 << 3)
1050
+
# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
1051
+
1052
+
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1053
+
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
1054
+
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
1055
+
# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
1056
+
1057
+
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1058
+
# define DP_PSR_CAPS_CHANGE (1 << 0)
1059
+
1060
+
#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1061
+
# define DP_PSR_SINK_INACTIVE 0
1062
+
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
1063
+
# define DP_PSR_SINK_ACTIVE_RFB 2
1064
+
# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
1065
+
# define DP_PSR_SINK_ACTIVE_RESYNC 4
1066
+
# define DP_PSR_SINK_INTERNAL_ERROR 7
1067
+
# define DP_PSR_SINK_STATE_MASK 0x07
1068
+
1069
+
#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1070
+
# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1071
+
# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1072
+
# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1073
+
# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
1074
+
1075
+
#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1076
+
# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1077
+
# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
1078
+
# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
1079
+
# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
1080
+
# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
1081
+
# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
1082
+
# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
1083
+
1084
+
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1085
+
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1086
+
1087
+
#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1088
+
#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1089
+
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1090
+
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1091
+
1092
+
/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
1093
+
#define DP_DP13_DPCD_REV 0x2200
1094
+
1095
+
#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1096
+
# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1097
+
# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
1098
+
# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
1099
+
# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
1100
+
# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
1101
+
# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
1102
+
# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
1103
+
# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
1104
+
1105
+
#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1106
+
# define DP_UHBR10 (1 << 0)
1107
+
# define DP_UHBR20 (1 << 1)
1108
+
# define DP_UHBR13_5 (1 << 2)
1109
+
1110
+
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1111
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
1112
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1113
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1114
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1115
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1116
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1117
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1118
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1119
+
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1120
+
1121
+
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1122
+
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1123
+
1124
+
/* DSC Extended Capability Branch Total DSC Resources */
1125
+
#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1126
+
# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1127
+
# define DP_DSC_DECODER_COUNT_SHIFT 5
1128
+
#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1129
+
# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1130
+
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1131
+
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
1132
+
1133
+
/* Protocol Converter Extension */
1134
+
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
1135
+
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
1136
+
# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1137
+
# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
1138
+
# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
1139
+
1140
+
#define DP_CEC_TUNNELING_CONTROL 0x3001
1141
+
# define DP_CEC_TUNNELING_ENABLE (1 << 0)
1142
+
# define DP_CEC_SNOOPING_ENABLE (1 << 1)
1143
+
1144
+
#define DP_CEC_RX_MESSAGE_INFO 0x3002
1145
+
# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1146
+
# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1147
+
# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
1148
+
# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
1149
+
# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
1150
+
# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
1151
+
1152
+
#define DP_CEC_TX_MESSAGE_INFO 0x3003
1153
+
# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1154
+
# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1155
+
# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1156
+
# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
1157
+
# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
1158
+
1159
+
#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1160
+
# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1161
+
# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
1162
+
# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
1163
+
# define DP_CEC_TX_LINE_ERROR (1 << 5)
1164
+
# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
1165
+
# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
1166
+
1167
+
#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1168
+
# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1169
+
# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
1170
+
# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
1171
+
# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
1172
+
# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
1173
+
# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
1174
+
# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
1175
+
# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
1176
+
#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1177
+
# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1178
+
# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
1179
+
# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
1180
+
# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
1181
+
# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
1182
+
# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
1183
+
# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
1184
+
# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
1185
+
1186
+
#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1187
+
#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1188
+
#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1189
+
1190
+
/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1191
+
#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1192
+
# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1193
+
# define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1194
+
# define DP_PCON_ENABLE_MAX_BW_9GBPS 1
1195
+
# define DP_PCON_ENABLE_MAX_BW_18GBPS 2
1196
+
# define DP_PCON_ENABLE_MAX_BW_24GBPS 3
1197
+
# define DP_PCON_ENABLE_MAX_BW_32GBPS 4
1198
+
# define DP_PCON_ENABLE_MAX_BW_40GBPS 5
1199
+
# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
1200
+
# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
1201
+
# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1202
+
# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1203
+
# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
1204
+
# define DP_PCON_ENABLE_HPD_READY (1 << 6)
1205
+
# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
1206
+
1207
+
/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1208
+
#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1209
+
# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1210
+
# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1211
+
# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
1212
+
# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
1213
+
# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
1214
+
# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
1215
+
# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
1216
+
# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1217
+
# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1218
+
1219
+
/* PCON HDMI LINK STATUS */
1220
+
#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1221
+
# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1222
+
# define DP_PCON_FRL_READY (1 << 1)
1223
+
1224
+
/* PCON HDMI POST FRL STATUS */
1225
+
#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1226
+
# define DP_PCON_HDMI_LINK_MODE (1 << 0)
1227
+
# define DP_PCON_HDMI_MODE_TMDS 0
1228
+
# define DP_PCON_HDMI_MODE_FRL 1
1229
+
# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1230
+
# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
1231
+
# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
1232
+
# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
1233
+
# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
1234
+
# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
1235
+
# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
1236
+
1237
+
#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1238
+
# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1239
+
#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1240
+
# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1241
+
# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
1242
+
# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
1243
+
# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
1244
+
#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1245
+
# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1246
+
# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
1247
+
# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1248
+
# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1249
+
# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
1250
+
# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
1251
+
# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
1252
+
# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
1253
+
# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
1254
+
# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1255
+
1256
+
/* PCON Downstream HDMI ERROR Status per Lane */
1257
+
#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1258
+
#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1259
+
#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1260
+
#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1261
+
# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1262
+
# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1263
+
# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
1264
+
# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1265
+
1266
+
/* PCON HDMI CONFIG PPS Override Buffer
1267
+
* Valid Offsets to be added to Base : 0-127
1268
+
*/
1269
+
#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1270
+
1271
+
/* PCON HDMI CONFIG PPS Override Parameter: Slice height
1272
+
* Offset-0 8LSBs of the Slice height.
1273
+
* Offset-1 8MSBs of the Slice height.
1274
+
*/
1275
+
#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1276
+
1277
+
/* PCON HDMI CONFIG PPS Override Parameter: Slice width
1278
+
* Offset-0 8LSBs of the Slice width.
1279
+
* Offset-1 8MSBs of the Slice width.
1280
+
*/
1281
+
#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1282
+
1283
+
/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
1284
+
* Offset-0 8LSBs of the bits_per_pixel.
1285
+
* Offset-1 2MSBs of the bits_per_pixel.
1286
+
*/
1287
+
#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1288
+
1289
+
/* HDCP 1.3 and HDCP 2.2 */
1290
+
#define DP_AUX_HDCP_BKSV 0x68000
1291
+
#define DP_AUX_HDCP_RI_PRIME 0x68005
1292
+
#define DP_AUX_HDCP_AKSV 0x68007
1293
+
#define DP_AUX_HDCP_AN 0x6800C
1294
+
#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1295
+
#define DP_AUX_HDCP_BCAPS 0x68028
1296
+
# define DP_BCAPS_REPEATER_PRESENT BIT(1)
1297
+
# define DP_BCAPS_HDCP_CAPABLE BIT(0)
1298
+
#define DP_AUX_HDCP_BSTATUS 0x68029
1299
+
# define DP_BSTATUS_REAUTH_REQ BIT(3)
1300
+
# define DP_BSTATUS_LINK_FAILURE BIT(2)
1301
+
# define DP_BSTATUS_R0_PRIME_READY BIT(1)
1302
+
# define DP_BSTATUS_READY BIT(0)
1303
+
#define DP_AUX_HDCP_BINFO 0x6802A
1304
+
#define DP_AUX_HDCP_KSV_FIFO 0x6802C
1305
+
#define DP_AUX_HDCP_AINFO 0x6803B
1306
+
1307
+
/* DP HDCP2.2 parameter offsets in DPCD address space */
1308
+
#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1309
+
#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1310
+
#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1311
+
#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1312
+
#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1313
+
#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1314
+
#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1315
+
#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1316
+
#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1317
+
#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1318
+
#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1319
+
#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1320
+
#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1321
+
#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1322
+
#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1323
+
#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1324
+
#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1325
+
#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1326
+
#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1327
+
#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1328
+
#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1329
+
#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1330
+
#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1331
+
#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1332
+
#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1333
+
#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1334
+
1335
+
/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1336
+
#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1337
+
#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1338
+
#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1339
+
#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1340
+
#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1341
+
#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1342
+
#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1343
+
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1344
+
# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1345
+
/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
1346
+
#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1347
+
#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1348
+
1349
+
enum drm_dp_phy {
1350
+
DP_PHY_DPRX,
1351
+
1352
+
DP_PHY_LTTPR1,
1353
+
DP_PHY_LTTPR2,
1354
+
DP_PHY_LTTPR3,
1355
+
DP_PHY_LTTPR4,
1356
+
DP_PHY_LTTPR5,
1357
+
DP_PHY_LTTPR6,
1358
+
DP_PHY_LTTPR7,
1359
+
DP_PHY_LTTPR8,
1360
+
1361
+
DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1362
+
};
1363
+
1364
+
#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
1365
+
1366
+
#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1367
+
#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1368
+
#define DP_LTTPR_BASE(dp_phy) \
1369
+
(__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1370
+
((dp_phy) - DP_PHY_LTTPR1))
1371
+
1372
+
#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1373
+
(DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1374
+
1375
+
#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1376
+
#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1377
+
DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1378
+
1379
+
#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1380
+
#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1381
+
DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1382
+
1383
+
#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1384
+
#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1385
+
#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1386
+
#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1387
+
#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1388
+
DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1389
+
1390
+
#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1391
+
# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1392
+
# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
1393
+
1394
+
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1395
+
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1396
+
DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1397
+
/* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */
1398
+
1399
+
#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1400
+
#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1401
+
DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1402
+
1403
+
#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1404
+
1405
+
#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1406
+
#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1407
+
#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1408
+
#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1409
+
#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1410
+
#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1411
+
#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1412
+
1413
+
#define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1414
+
#define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1415
+
#define DP_FEC_BASE(dp_phy) \
1416
+
(__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1417
+
((dp_phy) - DP_PHY_LTTPR1)))
1418
+
1419
+
#define DP_FEC_REG(dp_phy, fec1_reg) \
1420
+
(DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1421
+
1422
+
#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1423
+
#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
1424
+
DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
1425
+
1426
+
#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1427
+
#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1428
+
1429
+
#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1430
+
1431
+
#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1432
+
1433
+
/* Repeater modes */
1434
+
#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1435
+
#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1436
+
1437
+
/* DP HDCP message start offsets in DPCD address space */
1438
+
#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1439
+
#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1440
+
#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1441
+
#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1442
+
#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1443
+
#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1444
+
DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1445
+
#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1446
+
#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1447
+
#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1448
+
#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1449
+
#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1450
+
#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1451
+
#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1452
+
1453
+
#define HDCP_2_2_DP_RXSTATUS_LEN 1
1454
+
#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1455
+
#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1456
+
#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1457
+
#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1458
+
#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1459
+
1460
+
/* DP 1.2 Sideband message defines */
1461
+
/* peer device type - DP 1.2a Table 2-92 */
1462
+
#define DP_PEER_DEVICE_NONE 0x0
1463
+
#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1464
+
#define DP_PEER_DEVICE_MST_BRANCHING 0x2
1465
+
#define DP_PEER_DEVICE_SST_SINK 0x3
1466
+
#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1467
+
1468
+
/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1469
+
#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1470
+
#define DP_LINK_ADDRESS 0x01
1471
+
#define DP_CONNECTION_STATUS_NOTIFY 0x02
1472
+
#define DP_ENUM_PATH_RESOURCES 0x10
1473
+
#define DP_ALLOCATE_PAYLOAD 0x11
1474
+
#define DP_QUERY_PAYLOAD 0x12
1475
+
#define DP_RESOURCE_STATUS_NOTIFY 0x13
1476
+
#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1477
+
#define DP_REMOTE_DPCD_READ 0x20
1478
+
#define DP_REMOTE_DPCD_WRITE 0x21
1479
+
#define DP_REMOTE_I2C_READ 0x22
1480
+
#define DP_REMOTE_I2C_WRITE 0x23
1481
+
#define DP_POWER_UP_PHY 0x24
1482
+
#define DP_POWER_DOWN_PHY 0x25
1483
+
#define DP_SINK_EVENT_NOTIFY 0x30
1484
+
#define DP_QUERY_STREAM_ENC_STATUS 0x38
1485
+
#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1486
+
#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
1487
+
#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
1488
+
1489
+
/* DP 1.2 MST sideband reply types */
1490
+
#define DP_SIDEBAND_REPLY_ACK 0x00
1491
+
#define DP_SIDEBAND_REPLY_NAK 0x01
1492
+
1493
+
/* DP 1.2 MST sideband nak reasons - table 2.84 */
1494
+
#define DP_NAK_WRITE_FAILURE 0x01
1495
+
#define DP_NAK_INVALID_READ 0x02
1496
+
#define DP_NAK_CRC_FAILURE 0x03
1497
+
#define DP_NAK_BAD_PARAM 0x04
1498
+
#define DP_NAK_DEFER 0x05
1499
+
#define DP_NAK_LINK_FAILURE 0x06
1500
+
#define DP_NAK_NO_RESOURCES 0x07
1501
+
#define DP_NAK_DPCD_FAIL 0x08
1502
+
#define DP_NAK_I2C_NAK 0x09
1503
+
#define DP_NAK_ALLOCATE_FAIL 0x0a
1504
+
1505
+
#define MODE_I2C_START 1
1506
+
#define MODE_I2C_WRITE 2
1507
+
#define MODE_I2C_READ 4
1508
+
#define MODE_I2C_STOP 8
1509
+
1510
+
/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1511
+
#define DP_MST_PHYSICAL_PORT_0 0
1512
+
#define DP_MST_LOGICAL_PORT_0 8
1513
+
1514
+
#define DP_LINK_CONSTANT_N_VALUE 0x8000
1515
+
#define DP_LINK_STATUS_SIZE 6
1516
+
1517
+
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
1518
+
#define DP_RECEIVER_CAP_SIZE 0xf
1519
+
#define DP_DSC_RECEIVER_CAP_SIZE 0xf
1520
+
#define EDP_PSR_RECEIVER_CAP_SIZE 2
1521
+
#define EDP_DISPLAY_CTL_CAP_SIZE 3
1522
+
#define DP_LTTPR_COMMON_CAP_SIZE 8
1523
+
#define DP_LTTPR_PHY_CAP_SIZE 3
1524
+
1525
+
#define DP_SDP_AUDIO_TIMESTAMP 0x01
1526
+
#define DP_SDP_AUDIO_STREAM 0x02
1527
+
#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1528
+
#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1529
+
#define DP_SDP_ISRC 0x06 /* DP 1.2 */
1530
+
#define DP_SDP_VSC 0x07 /* DP 1.2 */
1531
+
#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1532
+
#define DP_SDP_PPS 0x10 /* DP 1.4 */
1533
+
#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1534
+
#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1535
+
/* 0x80+ CEA-861 infoframe types */
1536
+
1537
+
/**
1538
+
* struct dp_sdp_header - DP secondary data packet header
1539
+
* @HB0: Secondary Data Packet ID
1540
+
* @HB1: Secondary Data Packet Type
1541
+
* @HB2: Secondary Data Packet Specific header, Byte 0
1542
+
* @HB3: Secondary Data packet Specific header, Byte 1
1543
+
*/
1544
+
struct dp_sdp_header {
1545
+
u8 HB0;
1546
+
u8 HB1;
1547
+
u8 HB2;
1548
+
u8 HB3;
1549
+
} __packed;
1550
+
1551
+
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
1552
+
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1553
+
#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1554
+
1555
+
/**
1556
+
* struct dp_sdp - DP secondary data packet
1557
+
* @sdp_header: DP secondary data packet header
1558
+
* @db: DP secondaray data packet data blocks
1559
+
* VSC SDP Payload for PSR
1560
+
* db[0]: Stereo Interface
1561
+
* db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1562
+
* db[2]: CRC value bits 7:0 of the R or Cr component
1563
+
* db[3]: CRC value bits 15:8 of the R or Cr component
1564
+
* db[4]: CRC value bits 7:0 of the G or Y component
1565
+
* db[5]: CRC value bits 15:8 of the G or Y component
1566
+
* db[6]: CRC value bits 7:0 of the B or Cb component
1567
+
* db[7]: CRC value bits 15:8 of the B or Cb component
1568
+
* db[8] - db[31]: Reserved
1569
+
* VSC SDP Payload for Pixel Encoding/Colorimetry Format
1570
+
* db[0] - db[15]: Reserved
1571
+
* db[16]: Pixel Encoding and Colorimetry Formats
1572
+
* db[17]: Dynamic Range and Component Bit Depth
1573
+
* db[18]: Content Type
1574
+
* db[19] - db[31]: Reserved
1575
+
*/
1576
+
struct dp_sdp {
1577
+
struct dp_sdp_header sdp_header;
1578
+
u8 db[32];
1579
+
} __packed;
1580
+
1581
+
#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1582
+
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1583
+
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1584
+
1585
+
/**
1586
+
* enum dp_pixelformat - drm DP Pixel encoding formats
1587
+
*
1588
+
* This enum is used to indicate DP VSC SDP Pixel encoding formats.
1589
+
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1590
+
* DB18]
1591
+
*
1592
+
* @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1593
+
* @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1594
+
* @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1595
+
* @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1596
+
* @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1597
+
* @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1598
+
* @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1599
+
*/
1600
+
enum dp_pixelformat {
1601
+
DP_PIXELFORMAT_RGB = 0,
1602
+
DP_PIXELFORMAT_YUV444 = 0x1,
1603
+
DP_PIXELFORMAT_YUV422 = 0x2,
1604
+
DP_PIXELFORMAT_YUV420 = 0x3,
1605
+
DP_PIXELFORMAT_Y_ONLY = 0x4,
1606
+
DP_PIXELFORMAT_RAW = 0x5,
1607
+
DP_PIXELFORMAT_RESERVED = 0x6,
1608
+
};
1609
+
1610
+
/**
1611
+
* enum dp_colorimetry - drm DP Colorimetry formats
1612
+
*
1613
+
* This enum is used to indicate DP VSC SDP Colorimetry formats.
1614
+
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1615
+
* DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
1616
+
*
1617
+
* @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1618
+
* ITU-R BT.601 colorimetry format
1619
+
* @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1620
+
* @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1621
+
* @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1622
+
* (scRGB (IEC 61966-2-2)) colorimetry format
1623
+
* @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1624
+
* @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1625
+
* @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1626
+
* @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1627
+
* @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1628
+
* @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1629
+
* @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1630
+
* @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1631
+
* @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1632
+
* @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1633
+
*/
1634
+
enum dp_colorimetry {
1635
+
DP_COLORIMETRY_DEFAULT = 0,
1636
+
DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1637
+
DP_COLORIMETRY_BT709_YCC = 0x1,
1638
+
DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1639
+
DP_COLORIMETRY_XVYCC_601 = 0x2,
1640
+
DP_COLORIMETRY_OPRGB = 0x3,
1641
+
DP_COLORIMETRY_XVYCC_709 = 0x3,
1642
+
DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1643
+
DP_COLORIMETRY_SYCC_601 = 0x4,
1644
+
DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1645
+
DP_COLORIMETRY_OPYCC_601 = 0x5,
1646
+
DP_COLORIMETRY_BT2020_RGB = 0x6,
1647
+
DP_COLORIMETRY_BT2020_CYCC = 0x6,
1648
+
DP_COLORIMETRY_BT2020_YCC = 0x7,
1649
+
};
1650
+
1651
+
/**
1652
+
* enum dp_dynamic_range - drm DP Dynamic Range
1653
+
*
1654
+
* This enum is used to indicate DP VSC SDP Dynamic Range.
1655
+
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1656
+
* DB18]
1657
+
*
1658
+
* @DP_DYNAMIC_RANGE_VESA: VESA range
1659
+
* @DP_DYNAMIC_RANGE_CTA: CTA range
1660
+
*/
1661
+
enum dp_dynamic_range {
1662
+
DP_DYNAMIC_RANGE_VESA = 0,
1663
+
DP_DYNAMIC_RANGE_CTA = 1,
1664
+
};
1665
+
1666
+
/**
1667
+
* enum dp_content_type - drm DP Content Type
1668
+
*
1669
+
* This enum is used to indicate DP VSC SDP Content Types.
1670
+
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1671
+
* DB18]
1672
+
* CTA-861-G defines content types and expected processing by a sink device
1673
+
*
1674
+
* @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1675
+
* @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1676
+
* @DP_CONTENT_TYPE_PHOTO: Photo type
1677
+
* @DP_CONTENT_TYPE_VIDEO: Video type
1678
+
* @DP_CONTENT_TYPE_GAME: Game type
1679
+
*/
1680
+
enum dp_content_type {
1681
+
DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1682
+
DP_CONTENT_TYPE_GRAPHICS = 0x01,
1683
+
DP_CONTENT_TYPE_PHOTO = 0x02,
1684
+
DP_CONTENT_TYPE_VIDEO = 0x03,
1685
+
DP_CONTENT_TYPE_GAME = 0x04,
1686
+
};
1687
+
1688
+
#endif /* _DRM_DP_H_ */
+2
-1660
include/drm/display/drm_dp_helper.h
+2
-1660
include/drm/display/drm_dp_helper.h
···
25
25
26
26
#include <linux/delay.h>
27
27
#include <linux/i2c.h>
28
-
#include <linux/types.h>
28
+
29
+
#include <drm/display/drm_dp.h>
29
30
#include <drm/drm_connector.h>
30
31
31
32
struct drm_device;
32
33
struct drm_dp_aux;
33
34
struct drm_panel;
34
35
35
-
/*
36
-
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
37
-
* DP and DPCD versions are independent. Differences from 1.0 are not noted,
38
-
* 1.0 devices basically don't exist in the wild.
39
-
*
40
-
* Abbreviations, in chronological order:
41
-
*
42
-
* eDP: Embedded DisplayPort version 1
43
-
* DPI: DisplayPort Interoperability Guideline v1.1a
44
-
* 1.2: DisplayPort 1.2
45
-
* MST: Multistream Transport - part of DP 1.2a
46
-
*
47
-
* 1.2 formally includes both eDP and DPI definitions.
48
-
*/
49
-
50
-
/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
51
-
#define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
52
-
#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
53
-
#define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
54
-
#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
55
-
#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
56
-
/* bits per component for non-RAW */
57
-
#define DP_MSA_MISC_6_BPC (0 << 5)
58
-
#define DP_MSA_MISC_8_BPC (1 << 5)
59
-
#define DP_MSA_MISC_10_BPC (2 << 5)
60
-
#define DP_MSA_MISC_12_BPC (3 << 5)
61
-
#define DP_MSA_MISC_16_BPC (4 << 5)
62
-
/* bits per component for RAW */
63
-
#define DP_MSA_MISC_RAW_6_BPC (1 << 5)
64
-
#define DP_MSA_MISC_RAW_7_BPC (2 << 5)
65
-
#define DP_MSA_MISC_RAW_8_BPC (3 << 5)
66
-
#define DP_MSA_MISC_RAW_10_BPC (4 << 5)
67
-
#define DP_MSA_MISC_RAW_12_BPC (5 << 5)
68
-
#define DP_MSA_MISC_RAW_14_BPC (6 << 5)
69
-
#define DP_MSA_MISC_RAW_16_BPC (7 << 5)
70
-
/* pixel encoding/colorimetry format */
71
-
#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
72
-
((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
73
-
#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
74
-
#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
75
-
#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
76
-
#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
77
-
#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
78
-
#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
79
-
#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
80
-
#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
81
-
#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
82
-
#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
83
-
#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
84
-
#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
85
-
#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
86
-
#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
87
-
#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
88
-
#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
89
-
#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
90
-
#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
91
-
92
-
#define DP_AUX_MAX_PAYLOAD_BYTES 16
93
-
94
-
#define DP_AUX_I2C_WRITE 0x0
95
-
#define DP_AUX_I2C_READ 0x1
96
-
#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
97
-
#define DP_AUX_I2C_MOT 0x4
98
-
#define DP_AUX_NATIVE_WRITE 0x8
99
-
#define DP_AUX_NATIVE_READ 0x9
100
-
101
-
#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
102
-
#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
103
-
#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
104
-
#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
105
-
106
-
#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
107
-
#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
108
-
#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
109
-
#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
110
-
111
-
/* DPCD Field Address Mapping */
112
-
113
-
/* Receiver Capability */
114
-
#define DP_DPCD_REV 0x000
115
-
# define DP_DPCD_REV_10 0x10
116
-
# define DP_DPCD_REV_11 0x11
117
-
# define DP_DPCD_REV_12 0x12
118
-
# define DP_DPCD_REV_13 0x13
119
-
# define DP_DPCD_REV_14 0x14
120
-
121
-
#define DP_MAX_LINK_RATE 0x001
122
-
123
-
#define DP_MAX_LANE_COUNT 0x002
124
-
# define DP_MAX_LANE_COUNT_MASK 0x1f
125
-
# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
126
-
# define DP_ENHANCED_FRAME_CAP (1 << 7)
127
-
128
-
#define DP_MAX_DOWNSPREAD 0x003
129
-
# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
130
-
# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
131
-
# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
132
-
# define DP_TPS4_SUPPORTED (1 << 7)
133
-
134
-
#define DP_NORP 0x004
135
-
136
-
#define DP_DOWNSTREAMPORT_PRESENT 0x005
137
-
# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
138
-
# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
139
-
# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
140
-
# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
141
-
# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
142
-
# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
143
-
# define DP_FORMAT_CONVERSION (1 << 3)
144
-
# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
145
-
146
-
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
147
-
# define DP_CAP_ANSI_8B10B (1 << 0)
148
-
# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
149
-
150
-
#define DP_DOWN_STREAM_PORT_COUNT 0x007
151
-
# define DP_PORT_COUNT_MASK 0x0f
152
-
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
153
-
# define DP_OUI_SUPPORT (1 << 7)
154
-
155
-
#define DP_RECEIVE_PORT_0_CAP_0 0x008
156
-
# define DP_LOCAL_EDID_PRESENT (1 << 1)
157
-
# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
158
-
159
-
#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
160
-
161
-
#define DP_RECEIVE_PORT_1_CAP_0 0x00a
162
-
#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
163
-
164
-
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
165
-
# define DP_I2C_SPEED_1K 0x01
166
-
# define DP_I2C_SPEED_5K 0x02
167
-
# define DP_I2C_SPEED_10K 0x04
168
-
# define DP_I2C_SPEED_100K 0x08
169
-
# define DP_I2C_SPEED_400K 0x10
170
-
# define DP_I2C_SPEED_1M 0x20
171
-
172
-
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
173
-
# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
174
-
# define DP_FRAMING_CHANGE_CAP (1 << 1)
175
-
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
176
-
177
-
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
178
-
# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
179
-
# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
180
-
181
-
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
182
-
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
183
-
# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
184
-
185
-
#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
186
-
# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
187
-
188
-
/* Multiple stream transport */
189
-
#define DP_FAUX_CAP 0x020 /* 1.2 */
190
-
# define DP_FAUX_CAP_1 (1 << 0)
191
-
192
-
#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
193
-
# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
194
-
# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
195
-
# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
196
-
197
-
#define DP_MSTM_CAP 0x021 /* 1.2 */
198
-
# define DP_MST_CAP (1 << 0)
199
-
# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
200
-
201
-
#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
202
-
203
-
/* AV_SYNC_DATA_BLOCK 1.2 */
204
-
#define DP_AV_GRANULARITY 0x023
205
-
# define DP_AG_FACTOR_MASK (0xf << 0)
206
-
# define DP_AG_FACTOR_3MS (0 << 0)
207
-
# define DP_AG_FACTOR_2MS (1 << 0)
208
-
# define DP_AG_FACTOR_1MS (2 << 0)
209
-
# define DP_AG_FACTOR_500US (3 << 0)
210
-
# define DP_AG_FACTOR_200US (4 << 0)
211
-
# define DP_AG_FACTOR_100US (5 << 0)
212
-
# define DP_AG_FACTOR_10US (6 << 0)
213
-
# define DP_AG_FACTOR_1US (7 << 0)
214
-
# define DP_VG_FACTOR_MASK (0xf << 4)
215
-
# define DP_VG_FACTOR_3MS (0 << 4)
216
-
# define DP_VG_FACTOR_2MS (1 << 4)
217
-
# define DP_VG_FACTOR_1MS (2 << 4)
218
-
# define DP_VG_FACTOR_500US (3 << 4)
219
-
# define DP_VG_FACTOR_200US (4 << 4)
220
-
# define DP_VG_FACTOR_100US (5 << 4)
221
-
222
-
#define DP_AUD_DEC_LAT0 0x024
223
-
#define DP_AUD_DEC_LAT1 0x025
224
-
225
-
#define DP_AUD_PP_LAT0 0x026
226
-
#define DP_AUD_PP_LAT1 0x027
227
-
228
-
#define DP_VID_INTER_LAT 0x028
229
-
230
-
#define DP_VID_PROG_LAT 0x029
231
-
232
-
#define DP_REP_LAT 0x02a
233
-
234
-
#define DP_AUD_DEL_INS0 0x02b
235
-
#define DP_AUD_DEL_INS1 0x02c
236
-
#define DP_AUD_DEL_INS2 0x02d
237
-
/* End of AV_SYNC_DATA_BLOCK */
238
-
239
-
#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
240
-
# define DP_ALPM_CAP (1 << 0)
241
-
242
-
#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
243
-
# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
244
-
245
-
#define DP_GUID 0x030 /* 1.2 */
246
-
247
-
#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
248
-
# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
249
-
250
-
#define DP_DSC_REV 0x061
251
-
# define DP_DSC_MAJOR_MASK (0xf << 0)
252
-
# define DP_DSC_MINOR_MASK (0xf << 4)
253
-
# define DP_DSC_MAJOR_SHIFT 0
254
-
# define DP_DSC_MINOR_SHIFT 4
255
-
256
-
#define DP_DSC_RC_BUF_BLK_SIZE 0x062
257
-
# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
258
-
# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
259
-
# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
260
-
# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
261
-
262
-
#define DP_DSC_RC_BUF_SIZE 0x063
263
-
264
-
#define DP_DSC_SLICE_CAP_1 0x064
265
-
# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
266
-
# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
267
-
# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
268
-
# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
269
-
# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
270
-
# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
271
-
# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
272
-
273
-
#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
274
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
275
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
276
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
277
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
278
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
279
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
280
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
281
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
282
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
283
-
# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
284
-
285
-
#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
286
-
# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
287
-
288
-
#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
289
-
290
-
#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
291
-
# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
292
-
# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
293
-
294
-
#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
295
-
# define DP_DSC_RGB (1 << 0)
296
-
# define DP_DSC_YCbCr444 (1 << 1)
297
-
# define DP_DSC_YCbCr422_Simple (1 << 2)
298
-
# define DP_DSC_YCbCr422_Native (1 << 3)
299
-
# define DP_DSC_YCbCr420_Native (1 << 4)
300
-
301
-
#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
302
-
# define DP_DSC_8_BPC (1 << 1)
303
-
# define DP_DSC_10_BPC (1 << 2)
304
-
# define DP_DSC_12_BPC (1 << 3)
305
-
306
-
#define DP_DSC_PEAK_THROUGHPUT 0x06B
307
-
# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
308
-
# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
309
-
# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
310
-
# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
311
-
# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
312
-
# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
313
-
# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
314
-
# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
315
-
# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
316
-
# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
317
-
# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
318
-
# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
319
-
# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
320
-
# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
321
-
# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
322
-
# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
323
-
# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
324
-
# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
325
-
# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
326
-
# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
327
-
# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
328
-
# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
329
-
# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
330
-
# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
331
-
# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
332
-
# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
333
-
# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
334
-
# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
335
-
# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
336
-
# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
337
-
# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
338
-
# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
339
-
# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
340
-
# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
341
-
# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
342
-
# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
343
-
344
-
#define DP_DSC_MAX_SLICE_WIDTH 0x06C
345
-
#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
346
-
#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
347
-
348
-
#define DP_DSC_SLICE_CAP_2 0x06D
349
-
# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
350
-
# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
351
-
# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
352
-
353
-
#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
354
-
# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
355
-
# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
356
-
# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
357
-
# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
358
-
# define DP_DSC_BITS_PER_PIXEL_1 0x4
359
-
360
-
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
361
-
# define DP_PSR_IS_SUPPORTED 1
362
-
# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
363
-
# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
364
-
365
-
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
366
-
# define DP_PSR_NO_TRAIN_ON_EXIT 1
367
-
# define DP_PSR_SETUP_TIME_330 (0 << 1)
368
-
# define DP_PSR_SETUP_TIME_275 (1 << 1)
369
-
# define DP_PSR_SETUP_TIME_220 (2 << 1)
370
-
# define DP_PSR_SETUP_TIME_165 (3 << 1)
371
-
# define DP_PSR_SETUP_TIME_110 (4 << 1)
372
-
# define DP_PSR_SETUP_TIME_55 (5 << 1)
373
-
# define DP_PSR_SETUP_TIME_0 (6 << 1)
374
-
# define DP_PSR_SETUP_TIME_MASK (7 << 1)
375
-
# define DP_PSR_SETUP_TIME_SHIFT 1
376
-
# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
377
-
# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
378
-
379
-
#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
380
-
#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
381
-
382
-
/*
383
-
* 0x80-0x8f describe downstream port capabilities, but there are two layouts
384
-
* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
385
-
* each port's descriptor is one byte wide. If it was set, each port's is
386
-
* four bytes wide, starting with the one byte from the base info. As of
387
-
* DP interop v1.1a only VGA defines additional detail.
388
-
*/
389
-
390
-
/* offset 0 */
391
-
#define DP_DOWNSTREAM_PORT_0 0x80
392
-
# define DP_DS_PORT_TYPE_MASK (7 << 0)
393
-
# define DP_DS_PORT_TYPE_DP 0
394
-
# define DP_DS_PORT_TYPE_VGA 1
395
-
# define DP_DS_PORT_TYPE_DVI 2
396
-
# define DP_DS_PORT_TYPE_HDMI 3
397
-
# define DP_DS_PORT_TYPE_NON_EDID 4
398
-
# define DP_DS_PORT_TYPE_DP_DUALMODE 5
399
-
# define DP_DS_PORT_TYPE_WIRELESS 6
400
-
# define DP_DS_PORT_HPD (1 << 3)
401
-
# define DP_DS_NON_EDID_MASK (0xf << 4)
402
-
# define DP_DS_NON_EDID_720x480i_60 (1 << 4)
403
-
# define DP_DS_NON_EDID_720x480i_50 (2 << 4)
404
-
# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
405
-
# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
406
-
# define DP_DS_NON_EDID_1280x720_60 (5 << 4)
407
-
# define DP_DS_NON_EDID_1280x720_50 (7 << 4)
408
-
/* offset 1 for VGA is maximum megapixels per second / 8 */
409
-
/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
410
-
/* offset 2 for VGA/DVI/HDMI */
411
-
# define DP_DS_MAX_BPC_MASK (3 << 0)
412
-
# define DP_DS_8BPC 0
413
-
# define DP_DS_10BPC 1
414
-
# define DP_DS_12BPC 2
415
-
# define DP_DS_16BPC 3
416
-
/* HDMI2.1 PCON FRL CONFIGURATION */
417
-
# define DP_PCON_MAX_FRL_BW (7 << 2)
418
-
# define DP_PCON_MAX_0GBPS (0 << 2)
419
-
# define DP_PCON_MAX_9GBPS (1 << 2)
420
-
# define DP_PCON_MAX_18GBPS (2 << 2)
421
-
# define DP_PCON_MAX_24GBPS (3 << 2)
422
-
# define DP_PCON_MAX_32GBPS (4 << 2)
423
-
# define DP_PCON_MAX_40GBPS (5 << 2)
424
-
# define DP_PCON_MAX_48GBPS (6 << 2)
425
-
# define DP_PCON_SOURCE_CTL_MODE (1 << 5)
426
-
427
-
/* offset 3 for DVI */
428
-
# define DP_DS_DVI_DUAL_LINK (1 << 1)
429
-
# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
430
-
/* offset 3 for HDMI */
431
-
# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
432
-
# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
433
-
# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
434
-
# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
435
-
# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
436
-
437
-
/*
438
-
* VESA DP-to-HDMI PCON Specification adds caps for colorspace
439
-
* conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
440
-
* Based on the available support the source can enable
441
-
* color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
442
-
* DPCD 3052h.
443
-
*/
444
-
# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
445
-
# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
446
-
# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
447
-
448
-
#define DP_MAX_DOWNSTREAM_PORTS 0x10
449
-
450
-
/* DP Forward error Correction Registers */
451
-
#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
452
-
# define DP_FEC_CAPABLE (1 << 0)
453
-
# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
454
-
# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
455
-
# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
456
-
#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
457
-
458
-
/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
459
-
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
460
-
#define DP_PCON_DSC_ENCODER 0x092
461
-
# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
462
-
# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
463
-
464
-
/* DP-HDMI2.1 PCON DSC Version */
465
-
#define DP_PCON_DSC_VERSION 0x093
466
-
# define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
467
-
# define DP_PCON_DSC_MINOR_MASK (0xF << 4)
468
-
# define DP_PCON_DSC_MAJOR_SHIFT 0
469
-
# define DP_PCON_DSC_MINOR_SHIFT 4
470
-
471
-
/* DP-HDMI2.1 PCON DSC RC Buffer block size */
472
-
#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
473
-
# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
474
-
# define DP_PCON_DSC_RC_BUF_BLK_1KB 0
475
-
# define DP_PCON_DSC_RC_BUF_BLK_4KB 1
476
-
# define DP_PCON_DSC_RC_BUF_BLK_16KB 2
477
-
# define DP_PCON_DSC_RC_BUF_BLK_64KB 3
478
-
479
-
/* DP-HDMI2.1 PCON DSC RC Buffer size */
480
-
#define DP_PCON_DSC_RC_BUF_SIZE 0x095
481
-
482
-
/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
483
-
#define DP_PCON_DSC_SLICE_CAP_1 0x096
484
-
# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
485
-
# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
486
-
# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
487
-
# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
488
-
# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
489
-
# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
490
-
# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
491
-
492
-
#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
493
-
# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
494
-
# define DP_PCON_DSC_DEPTH_9_BITS 0
495
-
# define DP_PCON_DSC_DEPTH_10_BITS 1
496
-
# define DP_PCON_DSC_DEPTH_11_BITS 2
497
-
# define DP_PCON_DSC_DEPTH_12_BITS 3
498
-
# define DP_PCON_DSC_DEPTH_13_BITS 4
499
-
# define DP_PCON_DSC_DEPTH_14_BITS 5
500
-
# define DP_PCON_DSC_DEPTH_15_BITS 6
501
-
# define DP_PCON_DSC_DEPTH_16_BITS 7
502
-
# define DP_PCON_DSC_DEPTH_8_BITS 8
503
-
504
-
#define DP_PCON_DSC_BLOCK_PREDICTION 0x098
505
-
# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
506
-
507
-
#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
508
-
# define DP_PCON_DSC_ENC_RGB (0x1 << 0)
509
-
# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
510
-
# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
511
-
# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
512
-
# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
513
-
514
-
#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
515
-
# define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
516
-
# define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
517
-
# define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
518
-
519
-
#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
520
-
521
-
/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
522
-
#define DP_PCON_DSC_SLICE_CAP_2 0x09C
523
-
# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
524
-
# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
525
-
# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
526
-
527
-
/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
528
-
#define DP_PCON_DSC_BPP_INCR 0x09E
529
-
# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
530
-
# define DP_PCON_DSC_ONE_16TH_BPP 0
531
-
# define DP_PCON_DSC_ONE_8TH_BPP 1
532
-
# define DP_PCON_DSC_ONE_4TH_BPP 2
533
-
# define DP_PCON_DSC_ONE_HALF_BPP 3
534
-
# define DP_PCON_DSC_ONE_BPP 4
535
-
536
-
/* DP Extended DSC Capabilities */
537
-
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
538
-
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
539
-
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
540
-
541
-
/* DFP Capability Extension */
542
-
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
543
-
544
-
/* Link Configuration */
545
-
#define DP_LINK_BW_SET 0x100
546
-
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
547
-
# define DP_LINK_BW_1_62 0x06
548
-
# define DP_LINK_BW_2_7 0x0a
549
-
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
550
-
# define DP_LINK_BW_8_1 0x1e /* 1.4 */
551
-
# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
552
-
# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
553
-
# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
554
-
555
-
#define DP_LANE_COUNT_SET 0x101
556
-
# define DP_LANE_COUNT_MASK 0x0f
557
-
# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
558
-
559
-
#define DP_TRAINING_PATTERN_SET 0x102
560
-
# define DP_TRAINING_PATTERN_DISABLE 0
561
-
# define DP_TRAINING_PATTERN_1 1
562
-
# define DP_TRAINING_PATTERN_2 2
563
-
# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
564
-
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
565
-
# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
566
-
# define DP_TRAINING_PATTERN_MASK 0x3
567
-
# define DP_TRAINING_PATTERN_MASK_1_4 0xf
568
-
569
-
/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
570
-
# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
571
-
# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
572
-
# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
573
-
# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
574
-
# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
575
-
576
-
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
577
-
# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
578
-
579
-
# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
580
-
# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
581
-
# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
582
-
# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
583
-
584
-
#define DP_TRAINING_LANE0_SET 0x103
585
-
#define DP_TRAINING_LANE1_SET 0x104
586
-
#define DP_TRAINING_LANE2_SET 0x105
587
-
#define DP_TRAINING_LANE3_SET 0x106
588
-
589
-
# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
590
-
# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
591
-
# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
592
-
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
593
-
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
594
-
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
595
-
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
596
-
597
-
# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
598
-
# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
599
-
# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
600
-
# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
601
-
# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
602
-
603
-
# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
604
-
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
605
-
606
-
# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
607
-
608
-
#define DP_DOWNSPREAD_CTRL 0x107
609
-
# define DP_SPREAD_AMP_0_5 (1 << 4)
610
-
# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
611
-
612
-
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
613
-
# define DP_SET_ANSI_8B10B (1 << 0)
614
-
# define DP_SET_ANSI_128B132B (1 << 1)
615
-
616
-
#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
617
-
/* bitmask as for DP_I2C_SPEED_CAP */
618
-
619
-
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
620
-
# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
621
-
# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
622
-
# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
623
-
624
-
#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
625
-
#define DP_LINK_QUAL_LANE1_SET 0x10c
626
-
#define DP_LINK_QUAL_LANE2_SET 0x10d
627
-
#define DP_LINK_QUAL_LANE3_SET 0x10e
628
-
# define DP_LINK_QUAL_PATTERN_DISABLE 0
629
-
# define DP_LINK_QUAL_PATTERN_D10_2 1
630
-
# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
631
-
# define DP_LINK_QUAL_PATTERN_PRBS7 3
632
-
# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
633
-
# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
634
-
# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
635
-
# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
636
-
/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
637
-
# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
638
-
# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
639
-
# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
640
-
# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
641
-
# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
642
-
# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
643
-
# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
644
-
# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
645
-
# define DP_LINK_QUAL_PATTERN_SQUARE 0x48
646
-
647
-
#define DP_TRAINING_LANE0_1_SET2 0x10f
648
-
#define DP_TRAINING_LANE2_3_SET2 0x110
649
-
# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
650
-
# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
651
-
# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
652
-
# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
653
-
654
-
#define DP_MSTM_CTRL 0x111 /* 1.2 */
655
-
# define DP_MST_EN (1 << 0)
656
-
# define DP_UP_REQ_EN (1 << 1)
657
-
# define DP_UPSTREAM_IS_SRC (1 << 2)
658
-
659
-
#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
660
-
#define DP_AUDIO_DELAY1 0x113
661
-
#define DP_AUDIO_DELAY2 0x114
662
-
663
-
#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
664
-
# define DP_LINK_RATE_SET_SHIFT 0
665
-
# define DP_LINK_RATE_SET_MASK (7 << 0)
666
-
667
-
#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
668
-
# define DP_ALPM_ENABLE (1 << 0)
669
-
# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
670
-
671
-
#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
672
-
# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
673
-
# define DP_IRQ_HPD_ENABLE (1 << 1)
674
-
675
-
#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
676
-
# define DP_PWR_NOT_NEEDED (1 << 0)
677
-
678
-
#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
679
-
# define DP_FEC_READY (1 << 0)
680
-
# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
681
-
# define DP_FEC_ERR_COUNT_DIS (0 << 1)
682
-
# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
683
-
# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
684
-
# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
685
-
# define DP_FEC_LANE_SELECT_MASK (3 << 4)
686
-
# define DP_FEC_LANE_0_SELECT (0 << 4)
687
-
# define DP_FEC_LANE_1_SELECT (1 << 4)
688
-
# define DP_FEC_LANE_2_SELECT (2 << 4)
689
-
# define DP_FEC_LANE_3_SELECT (3 << 4)
690
-
691
-
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
692
-
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
693
-
694
-
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
695
-
# define DP_DECOMPRESSION_EN (1 << 0)
696
-
#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
697
-
698
-
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
699
-
# define DP_PSR_ENABLE BIT(0)
700
-
# define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
701
-
# define DP_PSR_CRC_VERIFICATION BIT(2)
702
-
# define DP_PSR_FRAME_CAPTURE BIT(3)
703
-
# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
704
-
# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
705
-
# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
706
-
707
-
#define DP_ADAPTER_CTRL 0x1a0
708
-
# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
709
-
710
-
#define DP_BRANCH_DEVICE_CTRL 0x1a1
711
-
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
712
-
713
-
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
714
-
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
715
-
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
716
-
717
-
/* Link/Sink Device Status */
718
-
#define DP_SINK_COUNT 0x200
719
-
/* prior to 1.2 bit 7 was reserved mbz */
720
-
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
721
-
# define DP_SINK_CP_READY (1 << 6)
722
-
723
-
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
724
-
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
725
-
# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
726
-
# define DP_CP_IRQ (1 << 2)
727
-
# define DP_MCCS_IRQ (1 << 3)
728
-
# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
729
-
# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
730
-
# define DP_SINK_SPECIFIC_IRQ (1 << 6)
731
-
732
-
#define DP_LANE0_1_STATUS 0x202
733
-
#define DP_LANE2_3_STATUS 0x203
734
-
# define DP_LANE_CR_DONE (1 << 0)
735
-
# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
736
-
# define DP_LANE_SYMBOL_LOCKED (1 << 2)
737
-
738
-
#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
739
-
DP_LANE_CHANNEL_EQ_DONE | \
740
-
DP_LANE_SYMBOL_LOCKED)
741
-
742
-
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
743
-
#define DP_INTERLANE_ALIGN_DONE (1 << 0)
744
-
#define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */
745
-
#define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */
746
-
#define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */
747
-
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
748
-
#define DP_LINK_STATUS_UPDATED (1 << 7)
749
-
750
-
#define DP_SINK_STATUS 0x205
751
-
# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
752
-
# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
753
-
# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
754
-
# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
755
-
756
-
#define DP_ADJUST_REQUEST_LANE0_1 0x206
757
-
#define DP_ADJUST_REQUEST_LANE2_3 0x207
758
-
# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
759
-
# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
760
-
# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
761
-
# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
762
-
# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
763
-
# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
764
-
# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
765
-
# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
766
-
767
-
/* DP 2.0 128b/132b Link Layer */
768
-
# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
769
-
# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
770
-
# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
771
-
# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
772
-
773
-
#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
774
-
# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
775
-
# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
776
-
# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
777
-
# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
778
-
# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
779
-
# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
780
-
# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
781
-
# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
782
-
783
-
#define DP_TEST_REQUEST 0x218
784
-
# define DP_TEST_LINK_TRAINING (1 << 0)
785
-
# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
786
-
# define DP_TEST_LINK_EDID_READ (1 << 2)
787
-
# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
788
-
# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
789
-
# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
790
-
# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
791
-
792
-
#define DP_TEST_LINK_RATE 0x219
793
-
# define DP_LINK_RATE_162 (0x6)
794
-
# define DP_LINK_RATE_27 (0xa)
795
-
796
-
#define DP_TEST_LANE_COUNT 0x220
797
-
798
-
#define DP_TEST_PATTERN 0x221
799
-
# define DP_NO_TEST_PATTERN 0x0
800
-
# define DP_COLOR_RAMP 0x1
801
-
# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
802
-
# define DP_COLOR_SQUARE 0x3
803
-
804
-
#define DP_TEST_H_TOTAL_HI 0x222
805
-
#define DP_TEST_H_TOTAL_LO 0x223
806
-
807
-
#define DP_TEST_V_TOTAL_HI 0x224
808
-
#define DP_TEST_V_TOTAL_LO 0x225
809
-
810
-
#define DP_TEST_H_START_HI 0x226
811
-
#define DP_TEST_H_START_LO 0x227
812
-
813
-
#define DP_TEST_V_START_HI 0x228
814
-
#define DP_TEST_V_START_LO 0x229
815
-
816
-
#define DP_TEST_HSYNC_HI 0x22A
817
-
# define DP_TEST_HSYNC_POLARITY (1 << 7)
818
-
# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
819
-
#define DP_TEST_HSYNC_WIDTH_LO 0x22B
820
-
821
-
#define DP_TEST_VSYNC_HI 0x22C
822
-
# define DP_TEST_VSYNC_POLARITY (1 << 7)
823
-
# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
824
-
#define DP_TEST_VSYNC_WIDTH_LO 0x22D
825
-
826
-
#define DP_TEST_H_WIDTH_HI 0x22E
827
-
#define DP_TEST_H_WIDTH_LO 0x22F
828
-
829
-
#define DP_TEST_V_HEIGHT_HI 0x230
830
-
#define DP_TEST_V_HEIGHT_LO 0x231
831
-
832
-
#define DP_TEST_MISC0 0x232
833
-
# define DP_TEST_SYNC_CLOCK (1 << 0)
834
-
# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
835
-
# define DP_TEST_COLOR_FORMAT_SHIFT 1
836
-
# define DP_COLOR_FORMAT_RGB (0 << 1)
837
-
# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
838
-
# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
839
-
# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
840
-
# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
841
-
# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
842
-
# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
843
-
# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
844
-
# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
845
-
# define DP_TEST_BIT_DEPTH_SHIFT 5
846
-
# define DP_TEST_BIT_DEPTH_6 (0 << 5)
847
-
# define DP_TEST_BIT_DEPTH_8 (1 << 5)
848
-
# define DP_TEST_BIT_DEPTH_10 (2 << 5)
849
-
# define DP_TEST_BIT_DEPTH_12 (3 << 5)
850
-
# define DP_TEST_BIT_DEPTH_16 (4 << 5)
851
-
852
-
#define DP_TEST_MISC1 0x233
853
-
# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
854
-
# define DP_TEST_INTERLACED (1 << 1)
855
-
856
-
#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
857
-
858
-
#define DP_TEST_MISC0 0x232
859
-
860
-
#define DP_TEST_CRC_R_CR 0x240
861
-
#define DP_TEST_CRC_G_Y 0x242
862
-
#define DP_TEST_CRC_B_CB 0x244
863
-
864
-
#define DP_TEST_SINK_MISC 0x246
865
-
# define DP_TEST_CRC_SUPPORTED (1 << 5)
866
-
# define DP_TEST_COUNT_MASK 0xf
867
-
868
-
#define DP_PHY_TEST_PATTERN 0x248
869
-
# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
870
-
# define DP_PHY_TEST_PATTERN_NONE 0x0
871
-
# define DP_PHY_TEST_PATTERN_D10_2 0x1
872
-
# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
873
-
# define DP_PHY_TEST_PATTERN_PRBS7 0x3
874
-
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
875
-
# define DP_PHY_TEST_PATTERN_CP2520 0x5
876
-
877
-
#define DP_PHY_SQUARE_PATTERN 0x249
878
-
879
-
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
880
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
881
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
882
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
883
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
884
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
885
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
886
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
887
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
888
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
889
-
#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
890
-
891
-
#define DP_TEST_RESPONSE 0x260
892
-
# define DP_TEST_ACK (1 << 0)
893
-
# define DP_TEST_NAK (1 << 1)
894
-
# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
895
-
896
-
#define DP_TEST_EDID_CHECKSUM 0x261
897
-
898
-
#define DP_TEST_SINK 0x270
899
-
# define DP_TEST_SINK_START (1 << 0)
900
-
#define DP_TEST_AUDIO_MODE 0x271
901
-
#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
902
-
#define DP_TEST_AUDIO_PERIOD_CH1 0x273
903
-
#define DP_TEST_AUDIO_PERIOD_CH2 0x274
904
-
#define DP_TEST_AUDIO_PERIOD_CH3 0x275
905
-
#define DP_TEST_AUDIO_PERIOD_CH4 0x276
906
-
#define DP_TEST_AUDIO_PERIOD_CH5 0x277
907
-
#define DP_TEST_AUDIO_PERIOD_CH6 0x278
908
-
#define DP_TEST_AUDIO_PERIOD_CH7 0x279
909
-
#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
910
-
911
-
#define DP_FEC_STATUS 0x280 /* 1.4 */
912
-
# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
913
-
# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
914
-
915
-
#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
916
-
917
-
#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
918
-
# define DP_FEC_ERROR_COUNT_MASK 0x7F
919
-
# define DP_FEC_ERR_COUNT_VALID (1 << 7)
920
-
921
-
#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
922
-
# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
923
-
# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
924
-
925
-
#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
926
-
/* up to ID_SLOT_63 at 0x2ff */
927
-
928
-
/* Source Device-specific */
929
-
#define DP_SOURCE_OUI 0x300
930
-
931
-
/* Sink Device-specific */
932
-
#define DP_SINK_OUI 0x400
933
-
934
-
/* Branch Device-specific */
935
-
#define DP_BRANCH_OUI 0x500
936
-
#define DP_BRANCH_ID 0x503
937
-
#define DP_BRANCH_REVISION_START 0x509
938
-
#define DP_BRANCH_HW_REV 0x509
939
-
#define DP_BRANCH_SW_REV 0x50A
940
-
941
-
/* Link/Sink Device Power Control */
942
-
#define DP_SET_POWER 0x600
943
-
# define DP_SET_POWER_D0 0x1
944
-
# define DP_SET_POWER_D3 0x2
945
-
# define DP_SET_POWER_MASK 0x3
946
-
# define DP_SET_POWER_D3_AUX_ON 0x5
947
-
948
-
/* eDP-specific */
949
-
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
950
-
# define DP_EDP_11 0x00
951
-
# define DP_EDP_12 0x01
952
-
# define DP_EDP_13 0x02
953
-
# define DP_EDP_14 0x03
954
-
# define DP_EDP_14a 0x04 /* eDP 1.4a */
955
-
# define DP_EDP_14b 0x05 /* eDP 1.4b */
956
-
957
-
#define DP_EDP_GENERAL_CAP_1 0x701
958
-
# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
959
-
# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
960
-
# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
961
-
# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
962
-
# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
963
-
# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
964
-
# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
965
-
# define DP_EDP_SET_POWER_CAP (1 << 7)
966
-
967
-
#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
968
-
# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
969
-
# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
970
-
# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
971
-
# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
972
-
# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
973
-
# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
974
-
# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
975
-
# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
976
-
977
-
#define DP_EDP_GENERAL_CAP_2 0x703
978
-
# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
979
-
980
-
#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
981
-
# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
982
-
# define DP_EDP_X_REGION_CAP_SHIFT 0
983
-
# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
984
-
# define DP_EDP_Y_REGION_CAP_SHIFT 4
985
-
986
-
#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
987
-
# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
988
-
# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
989
-
# define DP_EDP_FRC_ENABLE (1 << 2)
990
-
# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
991
-
# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
992
-
993
-
#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
994
-
# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
995
-
# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
996
-
# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
997
-
# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
998
-
# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
999
-
# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
1000
-
# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
1001
-
# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
1002
-
# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
1003
-
# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
1004
-
1005
-
#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
1006
-
#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1007
-
1008
-
#define DP_EDP_PWMGEN_BIT_COUNT 0x724
1009
-
#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1010
-
#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1011
-
# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1012
-
1013
-
#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1014
-
1015
-
#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1016
-
# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
1017
-
1018
-
#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1019
-
#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1020
-
#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1021
-
1022
-
#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1023
-
#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1024
-
#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1025
-
1026
-
#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1027
-
#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1028
-
1029
-
#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1030
-
#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1031
-
1032
-
#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1033
-
# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1034
-
# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1035
-
# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
1036
-
1037
-
/* Sideband MSG Buffers */
1038
-
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1039
-
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1040
-
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1041
-
#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1042
-
1043
-
/* DPRX Event Status Indicator */
1044
-
#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1045
-
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1046
-
1047
-
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1048
-
# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1049
-
# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
1050
-
# define DP_CEC_IRQ (1 << 2)
1051
-
1052
-
#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1053
-
# define RX_CAP_CHANGED (1 << 0)
1054
-
# define LINK_STATUS_CHANGED (1 << 1)
1055
-
# define STREAM_STATUS_CHANGED (1 << 2)
1056
-
# define HDMI_LINK_STATUS_CHANGED (1 << 3)
1057
-
# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
1058
-
1059
-
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1060
-
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
1061
-
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
1062
-
# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
1063
-
1064
-
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1065
-
# define DP_PSR_CAPS_CHANGE (1 << 0)
1066
-
1067
-
#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1068
-
# define DP_PSR_SINK_INACTIVE 0
1069
-
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
1070
-
# define DP_PSR_SINK_ACTIVE_RFB 2
1071
-
# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
1072
-
# define DP_PSR_SINK_ACTIVE_RESYNC 4
1073
-
# define DP_PSR_SINK_INTERNAL_ERROR 7
1074
-
# define DP_PSR_SINK_STATE_MASK 0x07
1075
-
1076
-
#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1077
-
# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1078
-
# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1079
-
# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1080
-
# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
1081
-
1082
-
#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1083
-
# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1084
-
# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
1085
-
# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
1086
-
# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
1087
-
# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
1088
-
# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
1089
-
# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
1090
-
1091
-
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1092
-
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1093
-
1094
-
#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1095
-
#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1096
-
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1097
-
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1098
-
1099
-
/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
1100
-
#define DP_DP13_DPCD_REV 0x2200
1101
-
1102
-
#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1103
-
# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1104
-
# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
1105
-
# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
1106
-
# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
1107
-
# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
1108
-
# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
1109
-
# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
1110
-
# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
1111
-
1112
-
#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1113
-
# define DP_UHBR10 (1 << 0)
1114
-
# define DP_UHBR20 (1 << 1)
1115
-
# define DP_UHBR13_5 (1 << 2)
1116
-
1117
-
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1118
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
1119
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1120
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1121
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1122
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1123
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1124
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1125
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1126
-
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1127
-
1128
-
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1129
-
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1130
-
1131
-
/* DSC Extended Capability Branch Total DSC Resources */
1132
-
#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1133
-
# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1134
-
# define DP_DSC_DECODER_COUNT_SHIFT 5
1135
-
#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1136
-
# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1137
-
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1138
-
# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
1139
-
1140
-
/* Protocol Converter Extension */
1141
-
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
1142
-
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
1143
-
# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1144
-
# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
1145
-
# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
1146
-
1147
-
#define DP_CEC_TUNNELING_CONTROL 0x3001
1148
-
# define DP_CEC_TUNNELING_ENABLE (1 << 0)
1149
-
# define DP_CEC_SNOOPING_ENABLE (1 << 1)
1150
-
1151
-
#define DP_CEC_RX_MESSAGE_INFO 0x3002
1152
-
# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1153
-
# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1154
-
# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
1155
-
# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
1156
-
# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
1157
-
# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
1158
-
1159
-
#define DP_CEC_TX_MESSAGE_INFO 0x3003
1160
-
# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1161
-
# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1162
-
# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1163
-
# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
1164
-
# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
1165
-
1166
-
#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1167
-
# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1168
-
# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
1169
-
# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
1170
-
# define DP_CEC_TX_LINE_ERROR (1 << 5)
1171
-
# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
1172
-
# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
1173
-
1174
-
#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1175
-
# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1176
-
# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
1177
-
# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
1178
-
# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
1179
-
# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
1180
-
# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
1181
-
# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
1182
-
# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
1183
-
#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1184
-
# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1185
-
# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
1186
-
# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
1187
-
# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
1188
-
# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
1189
-
# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
1190
-
# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
1191
-
# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
1192
-
1193
-
#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1194
-
#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1195
-
#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1196
-
1197
-
/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1198
-
#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1199
-
# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1200
-
# define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1201
-
# define DP_PCON_ENABLE_MAX_BW_9GBPS 1
1202
-
# define DP_PCON_ENABLE_MAX_BW_18GBPS 2
1203
-
# define DP_PCON_ENABLE_MAX_BW_24GBPS 3
1204
-
# define DP_PCON_ENABLE_MAX_BW_32GBPS 4
1205
-
# define DP_PCON_ENABLE_MAX_BW_40GBPS 5
1206
-
# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
1207
-
# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
1208
-
# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1209
-
# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1210
-
# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
1211
-
# define DP_PCON_ENABLE_HPD_READY (1 << 6)
1212
-
# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
1213
-
1214
-
/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1215
-
#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1216
-
# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1217
-
# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1218
-
# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
1219
-
# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
1220
-
# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
1221
-
# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
1222
-
# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
1223
-
# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1224
-
# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1225
-
1226
-
/* PCON HDMI LINK STATUS */
1227
-
#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1228
-
# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1229
-
# define DP_PCON_FRL_READY (1 << 1)
1230
-
1231
-
/* PCON HDMI POST FRL STATUS */
1232
-
#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1233
-
# define DP_PCON_HDMI_LINK_MODE (1 << 0)
1234
-
# define DP_PCON_HDMI_MODE_TMDS 0
1235
-
# define DP_PCON_HDMI_MODE_FRL 1
1236
-
# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1237
-
# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
1238
-
# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
1239
-
# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
1240
-
# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
1241
-
# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
1242
-
# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
1243
-
1244
-
#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1245
-
# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1246
-
#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1247
-
# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1248
-
# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
1249
-
# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
1250
-
# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
1251
-
#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1252
-
# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1253
-
# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
1254
-
# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1255
-
# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1256
-
# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
1257
-
# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
1258
-
# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
1259
-
# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
1260
-
# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
1261
-
# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1262
-
1263
-
/* PCON Downstream HDMI ERROR Status per Lane */
1264
-
#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1265
-
#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1266
-
#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1267
-
#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1268
-
# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1269
-
# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1270
-
# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
1271
-
# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1272
-
1273
-
/* PCON HDMI CONFIG PPS Override Buffer
1274
-
* Valid Offsets to be added to Base : 0-127
1275
-
*/
1276
-
#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1277
-
1278
-
/* PCON HDMI CONFIG PPS Override Parameter: Slice height
1279
-
* Offset-0 8LSBs of the Slice height.
1280
-
* Offset-1 8MSBs of the Slice height.
1281
-
*/
1282
-
#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1283
-
1284
-
/* PCON HDMI CONFIG PPS Override Parameter: Slice width
1285
-
* Offset-0 8LSBs of the Slice width.
1286
-
* Offset-1 8MSBs of the Slice width.
1287
-
*/
1288
-
#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1289
-
1290
-
/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
1291
-
* Offset-0 8LSBs of the bits_per_pixel.
1292
-
* Offset-1 2MSBs of the bits_per_pixel.
1293
-
*/
1294
-
#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1295
-
1296
-
/* HDCP 1.3 and HDCP 2.2 */
1297
-
#define DP_AUX_HDCP_BKSV 0x68000
1298
-
#define DP_AUX_HDCP_RI_PRIME 0x68005
1299
-
#define DP_AUX_HDCP_AKSV 0x68007
1300
-
#define DP_AUX_HDCP_AN 0x6800C
1301
-
#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1302
-
#define DP_AUX_HDCP_BCAPS 0x68028
1303
-
# define DP_BCAPS_REPEATER_PRESENT BIT(1)
1304
-
# define DP_BCAPS_HDCP_CAPABLE BIT(0)
1305
-
#define DP_AUX_HDCP_BSTATUS 0x68029
1306
-
# define DP_BSTATUS_REAUTH_REQ BIT(3)
1307
-
# define DP_BSTATUS_LINK_FAILURE BIT(2)
1308
-
# define DP_BSTATUS_R0_PRIME_READY BIT(1)
1309
-
# define DP_BSTATUS_READY BIT(0)
1310
-
#define DP_AUX_HDCP_BINFO 0x6802A
1311
-
#define DP_AUX_HDCP_KSV_FIFO 0x6802C
1312
-
#define DP_AUX_HDCP_AINFO 0x6803B
1313
-
1314
-
/* DP HDCP2.2 parameter offsets in DPCD address space */
1315
-
#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1316
-
#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1317
-
#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1318
-
#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1319
-
#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1320
-
#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1321
-
#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1322
-
#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1323
-
#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1324
-
#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1325
-
#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1326
-
#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1327
-
#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1328
-
#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1329
-
#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1330
-
#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1331
-
#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1332
-
#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1333
-
#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1334
-
#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1335
-
#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1336
-
#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1337
-
#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1338
-
#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1339
-
#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1340
-
#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1341
-
1342
-
/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1343
-
#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1344
-
#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1345
-
#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1346
-
#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1347
-
#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1348
-
#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1349
-
#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1350
-
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1351
-
# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1352
-
/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
1353
-
#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1354
-
#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1355
-
1356
-
enum drm_dp_phy {
1357
-
DP_PHY_DPRX,
1358
-
1359
-
DP_PHY_LTTPR1,
1360
-
DP_PHY_LTTPR2,
1361
-
DP_PHY_LTTPR3,
1362
-
DP_PHY_LTTPR4,
1363
-
DP_PHY_LTTPR5,
1364
-
DP_PHY_LTTPR6,
1365
-
DP_PHY_LTTPR7,
1366
-
DP_PHY_LTTPR8,
1367
-
1368
-
DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1369
-
};
1370
-
1371
-
#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
1372
-
1373
-
#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1374
-
#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1375
-
#define DP_LTTPR_BASE(dp_phy) \
1376
-
(__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1377
-
((dp_phy) - DP_PHY_LTTPR1))
1378
-
1379
-
#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1380
-
(DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1381
-
1382
-
#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1383
-
#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1384
-
DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1385
-
1386
-
#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1387
-
#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1388
-
DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1389
-
1390
-
#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1391
-
#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1392
-
#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1393
-
#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1394
-
#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1395
-
DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1396
-
1397
-
#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1398
-
# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1399
-
# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
1400
-
1401
-
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1402
-
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1403
-
DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1404
-
/* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */
1405
-
1406
-
#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1407
-
#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1408
-
DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1409
-
1410
-
#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1411
-
1412
-
#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1413
-
#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1414
-
#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1415
-
#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1416
-
#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1417
-
#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1418
-
#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1419
-
1420
-
#define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1421
-
#define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1422
-
#define DP_FEC_BASE(dp_phy) \
1423
-
(__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1424
-
((dp_phy) - DP_PHY_LTTPR1)))
1425
-
1426
-
#define DP_FEC_REG(dp_phy, fec1_reg) \
1427
-
(DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1428
-
1429
-
#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1430
-
#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
1431
-
DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
1432
-
1433
-
#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1434
-
#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1435
-
1436
-
#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1437
-
1438
-
#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1439
-
1440
-
/* Repeater modes */
1441
-
#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1442
-
#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1443
-
1444
-
/* DP HDCP message start offsets in DPCD address space */
1445
-
#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1446
-
#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1447
-
#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1448
-
#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1449
-
#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1450
-
#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1451
-
DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1452
-
#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1453
-
#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1454
-
#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1455
-
#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1456
-
#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1457
-
#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1458
-
#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1459
-
1460
-
#define HDCP_2_2_DP_RXSTATUS_LEN 1
1461
-
#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1462
-
#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1463
-
#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1464
-
#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1465
-
#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1466
-
1467
-
/* DP 1.2 Sideband message defines */
1468
-
/* peer device type - DP 1.2a Table 2-92 */
1469
-
#define DP_PEER_DEVICE_NONE 0x0
1470
-
#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1471
-
#define DP_PEER_DEVICE_MST_BRANCHING 0x2
1472
-
#define DP_PEER_DEVICE_SST_SINK 0x3
1473
-
#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1474
-
1475
-
/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1476
-
#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1477
-
#define DP_LINK_ADDRESS 0x01
1478
-
#define DP_CONNECTION_STATUS_NOTIFY 0x02
1479
-
#define DP_ENUM_PATH_RESOURCES 0x10
1480
-
#define DP_ALLOCATE_PAYLOAD 0x11
1481
-
#define DP_QUERY_PAYLOAD 0x12
1482
-
#define DP_RESOURCE_STATUS_NOTIFY 0x13
1483
-
#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1484
-
#define DP_REMOTE_DPCD_READ 0x20
1485
-
#define DP_REMOTE_DPCD_WRITE 0x21
1486
-
#define DP_REMOTE_I2C_READ 0x22
1487
-
#define DP_REMOTE_I2C_WRITE 0x23
1488
-
#define DP_POWER_UP_PHY 0x24
1489
-
#define DP_POWER_DOWN_PHY 0x25
1490
-
#define DP_SINK_EVENT_NOTIFY 0x30
1491
-
#define DP_QUERY_STREAM_ENC_STATUS 0x38
1492
-
#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1493
-
#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
1494
-
#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
1495
-
1496
-
/* DP 1.2 MST sideband reply types */
1497
-
#define DP_SIDEBAND_REPLY_ACK 0x00
1498
-
#define DP_SIDEBAND_REPLY_NAK 0x01
1499
-
1500
-
/* DP 1.2 MST sideband nak reasons - table 2.84 */
1501
-
#define DP_NAK_WRITE_FAILURE 0x01
1502
-
#define DP_NAK_INVALID_READ 0x02
1503
-
#define DP_NAK_CRC_FAILURE 0x03
1504
-
#define DP_NAK_BAD_PARAM 0x04
1505
-
#define DP_NAK_DEFER 0x05
1506
-
#define DP_NAK_LINK_FAILURE 0x06
1507
-
#define DP_NAK_NO_RESOURCES 0x07
1508
-
#define DP_NAK_DPCD_FAIL 0x08
1509
-
#define DP_NAK_I2C_NAK 0x09
1510
-
#define DP_NAK_ALLOCATE_FAIL 0x0a
1511
-
1512
-
#define MODE_I2C_START 1
1513
-
#define MODE_I2C_WRITE 2
1514
-
#define MODE_I2C_READ 4
1515
-
#define MODE_I2C_STOP 8
1516
-
1517
-
/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1518
-
#define DP_MST_PHYSICAL_PORT_0 0
1519
-
#define DP_MST_LOGICAL_PORT_0 8
1520
-
1521
-
#define DP_LINK_CONSTANT_N_VALUE 0x8000
1522
-
#define DP_LINK_STATUS_SIZE 6
1523
36
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1524
37
int lane_count);
1525
38
bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
···
43
1530
int lane);
44
1531
u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
45
1532
int lane);
46
-
47
-
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
48
-
#define DP_RECEIVER_CAP_SIZE 0xf
49
-
#define DP_DSC_RECEIVER_CAP_SIZE 0xf
50
-
#define EDP_PSR_RECEIVER_CAP_SIZE 2
51
-
#define EDP_DISPLAY_CTL_CAP_SIZE 3
52
-
#define DP_LTTPR_COMMON_CAP_SIZE 8
53
-
#define DP_LTTPR_PHY_CAP_SIZE 3
54
1533
55
1534
int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
56
1535
enum drm_dp_phy dp_phy, bool uhbr);
···
68
1563
69
1564
u8 drm_dp_link_rate_to_bw_code(int link_rate);
70
1565
int drm_dp_bw_code_to_link_rate(u8 link_bw);
71
-
72
-
#define DP_SDP_AUDIO_TIMESTAMP 0x01
73
-
#define DP_SDP_AUDIO_STREAM 0x02
74
-
#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
75
-
#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
76
-
#define DP_SDP_ISRC 0x06 /* DP 1.2 */
77
-
#define DP_SDP_VSC 0x07 /* DP 1.2 */
78
-
#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
79
-
#define DP_SDP_PPS 0x10 /* DP 1.4 */
80
-
#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
81
-
#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
82
-
/* 0x80+ CEA-861 infoframe types */
83
-
84
-
/**
85
-
* struct dp_sdp_header - DP secondary data packet header
86
-
* @HB0: Secondary Data Packet ID
87
-
* @HB1: Secondary Data Packet Type
88
-
* @HB2: Secondary Data Packet Specific header, Byte 0
89
-
* @HB3: Secondary Data packet Specific header, Byte 1
90
-
*/
91
-
struct dp_sdp_header {
92
-
u8 HB0;
93
-
u8 HB1;
94
-
u8 HB2;
95
-
u8 HB3;
96
-
} __packed;
97
-
98
-
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
99
-
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
100
-
#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
101
-
102
-
/**
103
-
* struct dp_sdp - DP secondary data packet
104
-
* @sdp_header: DP secondary data packet header
105
-
* @db: DP secondaray data packet data blocks
106
-
* VSC SDP Payload for PSR
107
-
* db[0]: Stereo Interface
108
-
* db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
109
-
* db[2]: CRC value bits 7:0 of the R or Cr component
110
-
* db[3]: CRC value bits 15:8 of the R or Cr component
111
-
* db[4]: CRC value bits 7:0 of the G or Y component
112
-
* db[5]: CRC value bits 15:8 of the G or Y component
113
-
* db[6]: CRC value bits 7:0 of the B or Cb component
114
-
* db[7]: CRC value bits 15:8 of the B or Cb component
115
-
* db[8] - db[31]: Reserved
116
-
* VSC SDP Payload for Pixel Encoding/Colorimetry Format
117
-
* db[0] - db[15]: Reserved
118
-
* db[16]: Pixel Encoding and Colorimetry Formats
119
-
* db[17]: Dynamic Range and Component Bit Depth
120
-
* db[18]: Content Type
121
-
* db[19] - db[31]: Reserved
122
-
*/
123
-
struct dp_sdp {
124
-
struct dp_sdp_header sdp_header;
125
-
u8 db[32];
126
-
} __packed;
127
-
128
-
#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
129
-
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
130
-
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
131
-
132
-
/**
133
-
* enum dp_pixelformat - drm DP Pixel encoding formats
134
-
*
135
-
* This enum is used to indicate DP VSC SDP Pixel encoding formats.
136
-
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
137
-
* DB18]
138
-
*
139
-
* @DP_PIXELFORMAT_RGB: RGB pixel encoding format
140
-
* @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
141
-
* @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
142
-
* @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
143
-
* @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
144
-
* @DP_PIXELFORMAT_RAW: RAW pixel encoding format
145
-
* @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
146
-
*/
147
-
enum dp_pixelformat {
148
-
DP_PIXELFORMAT_RGB = 0,
149
-
DP_PIXELFORMAT_YUV444 = 0x1,
150
-
DP_PIXELFORMAT_YUV422 = 0x2,
151
-
DP_PIXELFORMAT_YUV420 = 0x3,
152
-
DP_PIXELFORMAT_Y_ONLY = 0x4,
153
-
DP_PIXELFORMAT_RAW = 0x5,
154
-
DP_PIXELFORMAT_RESERVED = 0x6,
155
-
};
156
-
157
-
/**
158
-
* enum dp_colorimetry - drm DP Colorimetry formats
159
-
*
160
-
* This enum is used to indicate DP VSC SDP Colorimetry formats.
161
-
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
162
-
* DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
163
-
*
164
-
* @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
165
-
* ITU-R BT.601 colorimetry format
166
-
* @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
167
-
* @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
168
-
* @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
169
-
* (scRGB (IEC 61966-2-2)) colorimetry format
170
-
* @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
171
-
* @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
172
-
* @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
173
-
* @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
174
-
* @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
175
-
* @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
176
-
* @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
177
-
* @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
178
-
* @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
179
-
* @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
180
-
*/
181
-
enum dp_colorimetry {
182
-
DP_COLORIMETRY_DEFAULT = 0,
183
-
DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
184
-
DP_COLORIMETRY_BT709_YCC = 0x1,
185
-
DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
186
-
DP_COLORIMETRY_XVYCC_601 = 0x2,
187
-
DP_COLORIMETRY_OPRGB = 0x3,
188
-
DP_COLORIMETRY_XVYCC_709 = 0x3,
189
-
DP_COLORIMETRY_DCI_P3_RGB = 0x4,
190
-
DP_COLORIMETRY_SYCC_601 = 0x4,
191
-
DP_COLORIMETRY_RGB_CUSTOM = 0x5,
192
-
DP_COLORIMETRY_OPYCC_601 = 0x5,
193
-
DP_COLORIMETRY_BT2020_RGB = 0x6,
194
-
DP_COLORIMETRY_BT2020_CYCC = 0x6,
195
-
DP_COLORIMETRY_BT2020_YCC = 0x7,
196
-
};
197
-
198
-
/**
199
-
* enum dp_dynamic_range - drm DP Dynamic Range
200
-
*
201
-
* This enum is used to indicate DP VSC SDP Dynamic Range.
202
-
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
203
-
* DB18]
204
-
*
205
-
* @DP_DYNAMIC_RANGE_VESA: VESA range
206
-
* @DP_DYNAMIC_RANGE_CTA: CTA range
207
-
*/
208
-
enum dp_dynamic_range {
209
-
DP_DYNAMIC_RANGE_VESA = 0,
210
-
DP_DYNAMIC_RANGE_CTA = 1,
211
-
};
212
-
213
-
/**
214
-
* enum dp_content_type - drm DP Content Type
215
-
*
216
-
* This enum is used to indicate DP VSC SDP Content Types.
217
-
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
218
-
* DB18]
219
-
* CTA-861-G defines content types and expected processing by a sink device
220
-
*
221
-
* @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
222
-
* @DP_CONTENT_TYPE_GRAPHICS: Graphics type
223
-
* @DP_CONTENT_TYPE_PHOTO: Photo type
224
-
* @DP_CONTENT_TYPE_VIDEO: Video type
225
-
* @DP_CONTENT_TYPE_GAME: Game type
226
-
*/
227
-
enum dp_content_type {
228
-
DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
229
-
DP_CONTENT_TYPE_GRAPHICS = 0x01,
230
-
DP_CONTENT_TYPE_PHOTO = 0x02,
231
-
DP_CONTENT_TYPE_VIDEO = 0x03,
232
-
DP_CONTENT_TYPE_GAME = 0x04,
233
-
};
234
1566
235
1567
/**
236
1568
* struct drm_dp_vsc_sdp - drm DP VSC SDP