Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
dmaengine: at_hdmac: fix buffer transfer size specification
fsldma: fix issue of slow dma
dmaengine i.MX SDMA: initialize on module_init
dma : EG20T PCH: Fix miss-setting DMA descriptor
intel_mid_dma: fix section mismatch warnings
dmaengine: imx-sdma: fix bug in buffer descriptor initialization
drivers/dma/ppc4xx: Use printf extension %pR for struct resource
drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGS
drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGS
dma: intel_mid_dma: fix double free on mid_setup_dma error path
dma: imx-dma: fix imxdma_probe error path
+32
-25
+2
-2
drivers/dma/Makefile
+2
-2
drivers/dma/Makefile
+1
-1
drivers/dma/at_hdmac.c
+1
-1
drivers/dma/at_hdmac.c
+4
-2
drivers/dma/fsldma.c
+4
-2
drivers/dma/fsldma.c
···
50
50
* EIE - Error interrupt enable
51
51
* EOSIE - End of segments interrupt enable (basic mode)
52
52
* EOLNIE - End of links interrupt enable
53
+
* BWC - Bandwidth sharing among channels
53
54
*/
54
-
DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
55
-
| FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
55
+
DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
56
+
| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
57
+
| FSL_DMA_MR_EOSIE, 32);
56
58
break;
57
59
case FSL_DMA_IP_83XX:
58
60
/* Set the channel to below modes:
+8
-1
drivers/dma/fsldma.h
+8
-1
drivers/dma/fsldma.h
···
1
1
/*
2
-
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
2
+
* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
3
3
*
4
4
* Author:
5
5
* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
···
35
35
#define FSL_DMA_MR_EMS_EN 0x00040000
36
36
#define FSL_DMA_MR_DAHE 0x00002000
37
37
#define FSL_DMA_MR_SAHE 0x00001000
38
+
39
+
/*
40
+
* Bandwidth/pause control determines how many bytes a given
41
+
* channel is allowed to transfer before the DMA engine pauses
42
+
* the current channel and switches to the next channel
43
+
*/
44
+
#define FSL_DMA_MR_BWC 0x08000000
38
45
39
46
/* Special MR definition for MPC8349 */
40
47
#define FSL_DMA_MR_EOTIE 0x00000080
+1
-1
drivers/dma/imx-dma.c
+1
-1
drivers/dma/imx-dma.c
+2
-2
drivers/dma/imx-sdma.c
+2
-2
drivers/dma/imx-sdma.c
···
951
951
struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
952
952
int param;
953
953
954
-
bd->buffer_addr = sgl->dma_address;
954
+
bd->buffer_addr = sg->dma_address;
955
955
956
956
count = sg->length;
957
957
···
1385
1385
{
1386
1386
return platform_driver_probe(&sdma_driver, sdma_probe);
1387
1387
}
1388
-
subsys_initcall(sdma_module_init);
1388
+
module_init(sdma_module_init);
1389
1389
1390
1390
MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1391
1391
MODULE_DESCRIPTION("i.MX SDMA driver");
+3
-5
drivers/dma/intel_mid_dma.c
+3
-5
drivers/dma/intel_mid_dma.c
···
1075
1075
if (NULL == dma->dma_pool) {
1076
1076
pr_err("ERR_MDMA:pci_pool_create failed\n");
1077
1077
err = -ENOMEM;
1078
-
kfree(dma);
1079
1078
goto err_dma_pool;
1080
1079
}
1081
1080
···
1185
1186
free_irq(pdev->irq, dma);
1186
1187
err_irq:
1187
1188
pci_pool_destroy(dma->dma_pool);
1188
-
kfree(dma);
1189
1189
err_dma_pool:
1190
1190
pr_err("ERR_MDMA:setup_dma failed: %d\n", err);
1191
1191
return err;
···
1411
1413
.runtime_idle = dma_runtime_idle,
1412
1414
};
1413
1415
1414
-
static struct pci_driver intel_mid_dma_pci = {
1416
+
static struct pci_driver intel_mid_dma_pci_driver = {
1415
1417
.name = "Intel MID DMA",
1416
1418
.id_table = intel_mid_dma_ids,
1417
1419
.probe = intel_mid_dma_probe,
···
1429
1431
{
1430
1432
pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n",
1431
1433
INTEL_MID_DMA_DRIVER_VERSION);
1432
-
return pci_register_driver(&intel_mid_dma_pci);
1434
+
return pci_register_driver(&intel_mid_dma_pci_driver);
1433
1435
}
1434
1436
fs_initcall(intel_mid_dma_init);
1435
1437
1436
1438
static void __exit intel_mid_dma_exit(void)
1437
1439
{
1438
-
pci_unregister_driver(&intel_mid_dma_pci);
1440
+
pci_unregister_driver(&intel_mid_dma_pci_driver);
1439
1441
}
1440
1442
module_exit(intel_mid_dma_exit);
1441
1443
+1
-1
drivers/dma/ioat/Makefile
+1
-1
drivers/dma/ioat/Makefile
+8
-7
drivers/dma/pch_dma.c
+8
-7
drivers/dma/pch_dma.c
···
259
259
return;
260
260
}
261
261
262
-
channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
263
-
channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
264
-
channel_writel(pd_chan, SIZE, desc->regs.size);
265
-
channel_writel(pd_chan, NEXT, desc->regs.next);
266
-
267
262
dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
268
263
pd_chan->chan.chan_id, desc->regs.dev_addr);
269
264
dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
···
268
273
dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
269
274
pd_chan->chan.chan_id, desc->regs.next);
270
275
271
-
if (list_empty(&desc->tx_list))
276
+
if (list_empty(&desc->tx_list)) {
277
+
channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
278
+
channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
279
+
channel_writel(pd_chan, SIZE, desc->regs.size);
280
+
channel_writel(pd_chan, NEXT, desc->regs.next);
272
281
pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
273
-
else
282
+
} else {
283
+
channel_writel(pd_chan, NEXT, desc->txd.phys);
274
284
pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
285
+
}
275
286
276
287
val = dma_readl(pd, CTL2);
277
288
val |= 1 << (DMA_CTL2_START_SHIFT_BITS + pd_chan->chan.chan_id);
+2
-3
drivers/dma/ppc4xx/adma.c
+2
-3
drivers/dma/ppc4xx/adma.c
···
4449
4449
4450
4450
if (!request_mem_region(res.start, resource_size(&res),
4451
4451
dev_driver_string(&ofdev->dev))) {
4452
-
dev_err(&ofdev->dev, "failed to request memory region "
4453
-
"(0x%016llx-0x%016llx)\n",
4454
-
(u64)res.start, (u64)res.end);
4452
+
dev_err(&ofdev->dev, "failed to request memory region %pR\n",
4453
+
&res);
4455
4454
initcode = PPC_ADMA_INIT_MEMREG;
4456
4455
ret = -EBUSY;
4457
4456
goto out;