Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Paul Burton:
- Fix IPI handling for Lantiq SoCs, which was broken by changes made
back in v4.12.
- Enable OF/DT serial support in ath79_defconfig to give us working
serial by default.
- Fix 64b builds for the Jazz platform.
- Set up a struct device for the BCM47xx SoC to allow BCM47xx drivers
to perform DMA again following the major DMA mapping changes made in
v4.19.
- Disable MSI on Cavium Octeon systems when the pcie_disable command
line parameter introduced in v3.3 is used, in order to avoid
inadvetently accessing PCIe controller registers despite the command
line.
- Fix a build failure for Cavium Octeon kernels with kexec enabled,
introduced in v4.20.
- Fix a regression in the behaviour of semctl/shmctl/msgctl IPC
syscalls for kernels including n32 support but not o32 support caused
by some cleanup in v3.19.
* tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: OCTEON: fix kexec support
mips: fix n32 compat_ipc_parse_version
Disable MSI also when pcie-octeon.pcie_disable on
MIPS: BCM47XX: Setup struct device for the SoC
MIPS: jazz: fix 64bit build
MIPS: ath79: Enable OF serial ports in the default config
MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ
MIPS: lantiq: Fix IPI interrupt handling
+47
-79
+1
arch/mips/Kconfig
+1
arch/mips/Kconfig
+31
arch/mips/bcm47xx/setup.c
+31
arch/mips/bcm47xx/setup.c
···
173
173
pm_power_off = bcm47xx_machine_halt;
174
174
}
175
175
176
+
#ifdef CONFIG_BCM47XX_BCMA
177
+
static struct device * __init bcm47xx_setup_device(void)
178
+
{
179
+
struct device *dev;
180
+
int err;
181
+
182
+
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
183
+
if (!dev)
184
+
return NULL;
185
+
186
+
err = dev_set_name(dev, "bcm47xx_soc");
187
+
if (err) {
188
+
pr_err("Failed to set SoC device name: %d\n", err);
189
+
kfree(dev);
190
+
return NULL;
191
+
}
192
+
193
+
err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
194
+
if (err)
195
+
pr_err("Failed to set SoC DMA mask: %d\n", err);
196
+
197
+
return dev;
198
+
}
199
+
#endif
200
+
176
201
/*
177
202
* This finishes bus initialization doing things that were not possible without
178
203
* kmalloc. Make sure to call it late enough (after mm_init).
···
207
182
#ifdef CONFIG_BCM47XX_BCMA
208
183
if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
209
184
int err;
185
+
186
+
bcm47xx_bus.bcma.dev = bcm47xx_setup_device();
187
+
if (!bcm47xx_bus.bcma.dev)
188
+
panic("Failed to setup SoC device\n");
210
189
211
190
err = bcma_host_soc_init(&bcm47xx_bus.bcma);
212
191
if (err)
···
264
235
#endif
265
236
#ifdef CONFIG_BCM47XX_BCMA
266
237
case BCM47XX_BUS_TYPE_BCMA:
238
+
if (device_register(bcm47xx_bus.bcma.dev))
239
+
pr_err("Failed to register SoC device\n");
267
240
bcma_bus_register(&bcm47xx_bus.bcma.bus);
268
241
break;
269
242
#endif
+1
-1
arch/mips/cavium-octeon/setup.c
+1
-1
arch/mips/cavium-octeon/setup.c
+1
arch/mips/configs/ath79_defconfig
+1
arch/mips/configs/ath79_defconfig
-2
arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
-2
arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
-2
arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-2
arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+3
-2
arch/mips/jazz/jazzdma.c
+3
-2
arch/mips/jazz/jazzdma.c
···
74
74
get_order(VDMA_PGTBL_SIZE));
75
75
BUG_ON(!pgtbl);
76
76
dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
77
-
pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
77
+
pgtbl = (VDMA_PGTBL_ENTRY *)CKSEG1ADDR((unsigned long)pgtbl);
78
78
79
79
/*
80
80
* Clear the R4030 translation table
81
81
*/
82
82
vdma_pgtbl_init();
83
83
84
-
r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
84
+
r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE,
85
+
CPHYSADDR((unsigned long)pgtbl));
85
86
r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
86
87
r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
87
88
+6
-71
arch/mips/lantiq/irq.c
+6
-71
arch/mips/lantiq/irq.c
···
224
224
.irq_set_type = ltq_eiu_settype,
225
225
};
226
226
227
-
static void ltq_hw_irqdispatch(int module)
227
+
static void ltq_hw_irq_handler(struct irq_desc *desc)
228
228
{
229
+
int module = irq_desc_get_irq(desc) - 2;
229
230
u32 irq;
231
+
int hwirq;
230
232
231
233
irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
232
234
if (irq == 0)
···
239
237
* other bits might be bogus
240
238
*/
241
239
irq = __fls(irq);
242
-
do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
240
+
hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
241
+
generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
243
242
244
243
/* if this is a EBU irq, we need to ack it or get a deadlock */
245
244
if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
246
245
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
247
246
LTQ_EBU_PCC_ISTAT);
248
-
}
249
-
250
-
#define DEFINE_HWx_IRQDISPATCH(x) \
251
-
static void ltq_hw ## x ## _irqdispatch(void) \
252
-
{ \
253
-
ltq_hw_irqdispatch(x); \
254
-
}
255
-
DEFINE_HWx_IRQDISPATCH(0)
256
-
DEFINE_HWx_IRQDISPATCH(1)
257
-
DEFINE_HWx_IRQDISPATCH(2)
258
-
DEFINE_HWx_IRQDISPATCH(3)
259
-
DEFINE_HWx_IRQDISPATCH(4)
260
-
261
-
#if MIPS_CPU_TIMER_IRQ == 7
262
-
static void ltq_hw5_irqdispatch(void)
263
-
{
264
-
do_IRQ(MIPS_CPU_TIMER_IRQ);
265
-
}
266
-
#else
267
-
DEFINE_HWx_IRQDISPATCH(5)
268
-
#endif
269
-
270
-
static void ltq_hw_irq_handler(struct irq_desc *desc)
271
-
{
272
-
ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
273
-
}
274
-
275
-
asmlinkage void plat_irq_dispatch(void)
276
-
{
277
-
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
278
-
int irq;
279
-
280
-
if (!pending) {
281
-
spurious_interrupt();
282
-
return;
283
-
}
284
-
285
-
pending >>= CAUSEB_IP;
286
-
while (pending) {
287
-
irq = fls(pending) - 1;
288
-
do_IRQ(MIPS_CPU_IRQ_BASE + irq);
289
-
pending &= ~BIT(irq);
290
-
}
291
247
}
292
248
293
249
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
···
303
343
for (i = 0; i < MAX_IM; i++)
304
344
irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
305
345
306
-
if (cpu_has_vint) {
307
-
pr_info("Setting up vectored interrupts\n");
308
-
set_vi_handler(2, ltq_hw0_irqdispatch);
309
-
set_vi_handler(3, ltq_hw1_irqdispatch);
310
-
set_vi_handler(4, ltq_hw2_irqdispatch);
311
-
set_vi_handler(5, ltq_hw3_irqdispatch);
312
-
set_vi_handler(6, ltq_hw4_irqdispatch);
313
-
set_vi_handler(7, ltq_hw5_irqdispatch);
314
-
}
315
-
316
346
ltq_domain = irq_domain_add_linear(node,
317
347
(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
318
348
&irq_domain_ops, 0);
319
349
320
-
#ifndef CONFIG_MIPS_MT_SMP
321
-
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
322
-
IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
323
-
#else
324
-
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
325
-
IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
326
-
#endif
327
-
328
350
/* tell oprofile which irq to use */
329
351
ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
330
-
331
-
/*
332
-
* if the timer irq is not one of the mips irqs we need to
333
-
* create a mapping
334
-
*/
335
-
if (MIPS_CPU_TIMER_IRQ != 7)
336
-
irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
337
352
338
353
/* the external interrupts are optional and xway only */
339
354
eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
···
346
411
347
412
unsigned int get_c0_compare_int(void)
348
413
{
349
-
return MIPS_CPU_TIMER_IRQ;
414
+
return CP0_LEGACY_COMPARE_IRQ;
350
415
}
351
416
352
417
static struct of_device_id __initdata of_irq_ids[] = {
+3
-1
arch/mips/pci/msi-octeon.c
+3
-1
arch/mips/pci/msi-octeon.c
···
369
369
int irq;
370
370
struct irq_chip *msi;
371
371
372
-
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
372
+
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) {
373
+
return 0;
374
+
} else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
373
375
msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
374
376
msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
375
377
msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;