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Merge tag 'x86_urgent_for_v6.16_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Borislav Petkov:

- Update Kirill's email address

- Allow hugetlb PMD sharing only on 64-bit as it doesn't make a whole
lotta sense on 32-bit

- Add fixes for a misconfigured AMD Zen2 client which wasn't even
supposed to run Linux

* tag 'x86_urgent_for_v6.16_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
MAINTAINERS: Update Kirill Shutemov's email address for TDX
x86/mm: Disable hugetlb page table sharing on 32-bit
x86/CPU/AMD: Disable INVLPGB on Zen2
x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

+15 -2
+1
.mailmap
··· 416 416 Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org> 417 417 Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org> 418 418 Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com> 419 + Kirill A. Shutemov <kas@kernel.org> <kirill.shutemov@linux.intel.com> 419 420 Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com> 420 421 Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@linaro.org> 421 422 Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@somainline.org>
+1 -1
MAINTAINERS
··· 26939 26939 F: arch/x86/kernel/unwind_*.c 26940 26940 26941 26941 X86 TRUST DOMAIN EXTENSIONS (TDX) 26942 - M: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> 26942 + M: Kirill A. Shutemov <kas@kernel.org> 26943 26943 R: Dave Hansen <dave.hansen@linux.intel.com> 26944 26944 L: x86@kernel.org 26945 26945 L: linux-coco@lists.linux.dev
+1 -1
arch/x86/Kconfig
··· 147 147 select ARCH_WANTS_DYNAMIC_TASK_STRUCT 148 148 select ARCH_WANTS_NO_INSTR 149 149 select ARCH_WANT_GENERAL_HUGETLB 150 - select ARCH_WANT_HUGE_PMD_SHARE 150 + select ARCH_WANT_HUGE_PMD_SHARE if X86_64 151 151 select ARCH_WANT_LD_ORPHAN_WARN 152 152 select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP if X86_64 153 153 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if X86_64
+1
arch/x86/include/asm/msr-index.h
··· 628 628 #define MSR_AMD64_OSVW_STATUS 0xc0010141 629 629 #define MSR_AMD_PPIN_CTL 0xc00102f0 630 630 #define MSR_AMD_PPIN 0xc00102f1 631 + #define MSR_AMD64_CPUID_FN_7 0xc0011002 631 632 #define MSR_AMD64_CPUID_FN_1 0xc0011004 632 633 #define MSR_AMD64_LS_CFG 0xc0011020 633 634 #define MSR_AMD64_DC_CFG 0xc0011022
+10
arch/x86/kernel/cpu/amd.c
··· 974 974 init_spectral_chicken(c); 975 975 fix_erratum_1386(c); 976 976 zen2_zenbleed_check(c); 977 + 978 + /* Disable RDSEED on AMD Cyan Skillfish because of an error. */ 979 + if (c->x86_model == 0x47 && c->x86_stepping == 0x0) { 980 + clear_cpu_cap(c, X86_FEATURE_RDSEED); 981 + msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18); 982 + pr_emerg("RDSEED is not reliable on this platform; disabling.\n"); 983 + } 984 + 985 + /* Correct misconfigured CPUID on some clients. */ 986 + clear_cpu_cap(c, X86_FEATURE_INVLPGB); 977 987 } 978 988 979 989 static void init_amd_zen3(struct cpuinfo_x86 *c)
+1
tools/arch/x86/include/asm/msr-index.h
··· 628 628 #define MSR_AMD64_OSVW_STATUS 0xc0010141 629 629 #define MSR_AMD_PPIN_CTL 0xc00102f0 630 630 #define MSR_AMD_PPIN 0xc00102f1 631 + #define MSR_AMD64_CPUID_FN_7 0xc0011002 631 632 #define MSR_AMD64_CPUID_FN_1 0xc0011004 632 633 #define MSR_AMD64_LS_CFG 0xc0011020 633 634 #define MSR_AMD64_DC_CFG 0xc0011022