tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2019-11-22' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Two sets of fixes in here, one for amdgpu, and one for i915.

The amdgpu ones are pretty small, i915's CI system seems to have a few
problems in the last week or so, there is one major regression fix for
fb_mmap, but there are a bunch of other issues fixed in there as well,
oops, screen flashes and rcu related.

amdgpu:
- Remove experimental flag for navi14
- Fix confusing power message failures on older VI parts
- Hang fix for gfxoff when using the read register interface
- Two stability regression fixes for Raven

i915:
- Fix kernel oops on dumb_create ioctl on no crtc situation
- Fix bad ugly colored flash on VLV/CHV related to gamma LUT update
- Fix unity of the frequencies reported on PMU
- Fix kernel oops on set_page_dirty using better locks around it
- Protect the request pointer with RCU to prevent it being freed
while we might need still
- Make pool objects read-only
- Restore physical addresses for fb_map to avoid corrupted page
table"

* tag 'drm-fixes-2019-11-22' of git://anongit.freedesktop.org/drm/drm:
drm/i915/fbdev: Restore physical addresses for fb_mmap()
Revert "drm/amd/display: enable S/G for RAVEN chip"
drm/amdgpu: disable gfxoff on original raven
drm/amdgpu: disable gfxoff when using register read interface
drm/amd/powerplay: correct fine grained dpm force level setting
drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr on unsupported ASICs
drm/amdgpu: remove experimental flag for Navi14
drm/i915: make pool objects read-only
drm/i915: Protect request peeking with RCU
drm/i915/userptr: Try to acquire the page lock around set_page_dirty()
drm/i915/pmu: "Frequency" is reported as accumulated cycles
drm/i915: Preload LUTs if the hw isn't currently using them
drm/i915: Don't oops in dumb_create ioctl if we have no crtcs

Linus Torvalds 5d867ab0 81429eb8

+183 -32
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 511 511 * Also, don't allow GTT domain if the BO doens't have USWC falg set. 512 512 */ 513 513 if (adev->asic_type >= CHIP_CARRIZO && 514 - adev->asic_type <= CHIP_RAVEN && 514 + adev->asic_type < CHIP_RAVEN && 515 515 (adev->flags & AMD_IS_APU) && 516 516 (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 517 517 amdgpu_bo_support_uswc(bo_flags) &&
+4 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 1013 1013 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1014 1014 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1015 1015 /* Navi14 */ 1016 - {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1017 - {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1018 - {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1019 - {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT}, 1016 + {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1017 + {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1018 + {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1019 + {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1020 1020 1021 1021 /* Renoir */ 1022 1022 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
+5 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
··· 649 649 return -ENOMEM; 650 650 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 651 651 652 - for (i = 0; i < info->read_mmr_reg.count; i++) 652 + amdgpu_gfx_off_ctrl(adev, false); 653 + for (i = 0; i < info->read_mmr_reg.count; i++) { 653 654 if (amdgpu_asic_read_register(adev, se_num, sh_num, 654 655 info->read_mmr_reg.dword_offset + i, 655 656 &regs[i])) { 656 657 DRM_DEBUG_KMS("unallowed offset %#x\n", 657 658 info->read_mmr_reg.dword_offset + i); 658 659 kfree(regs); 660 + amdgpu_gfx_off_ctrl(adev, true); 659 661 return -EFAULT; 660 662 } 663 + } 664 + amdgpu_gfx_off_ctrl(adev, true); 661 665 n = copy_to_user(out, regs, min(size, alloc_size)); 662 666 kfree(regs); 663 667 return n ? -EFAULT : 0;
+7 -2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 1038 1038 case CHIP_VEGA20: 1039 1039 break; 1040 1040 case CHIP_RAVEN: 1041 - if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) 1042 - &&((adev->gfx.rlc_fw_version != 106 && 1041 + /* Disable GFXOFF on original raven. There are combinations 1042 + * of sbios and platforms that are not stable. 1043 + */ 1044 + if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)) 1045 + adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1046 + else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) 1047 + &&((adev->gfx.rlc_fw_version != 106 && 1043 1048 adev->gfx.rlc_fw_version < 531) || 1044 1049 (adev->gfx.rlc_fw_version == 53815) || 1045 1050 (adev->gfx.rlc_feature_version < 1) ||
+1 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 688 688 */ 689 689 if (adev->flags & AMD_IS_APU && 690 690 adev->asic_type >= CHIP_CARRIZO && 691 - adev->asic_type <= CHIP_RAVEN) 691 + adev->asic_type < CHIP_RAVEN) 692 692 init_data.flags.gpu_vm_support = true; 693 693 694 694 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
+18 -5
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
··· 3478 3478 3479 3479 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) 3480 3480 { 3481 + struct amdgpu_device *adev = hwmgr->adev; 3481 3482 int i; 3482 3483 u32 tmp = 0; 3483 3484 3484 3485 if (!query) 3485 3486 return -EINVAL; 3486 3487 3487 - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0); 3488 - tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3489 - *query = tmp; 3488 + /* 3489 + * PPSMC_MSG_GetCurrPkgPwr is not supported on: 3490 + * - Hawaii 3491 + * - Bonaire 3492 + * - Fiji 3493 + * - Tonga 3494 + */ 3495 + if ((adev->asic_type != CHIP_HAWAII) && 3496 + (adev->asic_type != CHIP_BONAIRE) && 3497 + (adev->asic_type != CHIP_FIJI) && 3498 + (adev->asic_type != CHIP_TONGA)) { 3499 + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0); 3500 + tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3501 + *query = tmp; 3490 3502 3491 - if (tmp != 0) 3492 - return 0; 3503 + if (tmp != 0) 3504 + return 0; 3505 + } 3493 3506 3494 3507 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart); 3495 3508 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+6
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
··· 759 759 case SMU_UCLK: 760 760 case SMU_DCEFCLK: 761 761 case SMU_FCLK: 762 + /* There is only 2 levels for fine grained DPM */ 763 + if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { 764 + soft_max_level = (soft_max_level >= 1 ? 1 : 0); 765 + soft_min_level = (soft_min_level >= 1 ? 1 : 0); 766 + } 767 + 762 768 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 763 769 if (ret) 764 770 return size;
+1
drivers/gpu/drm/i915/display/intel_atomic.c
··· 201 201 crtc_state->update_wm_post = false; 202 202 crtc_state->fb_changed = false; 203 203 crtc_state->fifo_changed = false; 204 + crtc_state->preload_luts = false; 204 205 crtc_state->wm.need_postvbl_update = false; 205 206 crtc_state->fb_bits = 0; 206 207 crtc_state->update_planes = 0;
+61
drivers/gpu/drm/i915/display/intel_color.c
··· 990 990 dev_priv->display.color_commit(crtc_state); 991 991 } 992 992 993 + static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 994 + { 995 + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); 996 + struct intel_atomic_state *state = 997 + to_intel_atomic_state(new_crtc_state->base.state); 998 + const struct intel_crtc_state *old_crtc_state = 999 + intel_atomic_get_old_crtc_state(state, crtc); 1000 + 1001 + return !old_crtc_state->base.gamma_lut && 1002 + !old_crtc_state->base.degamma_lut; 1003 + } 1004 + 1005 + static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1006 + { 1007 + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); 1008 + struct intel_atomic_state *state = 1009 + to_intel_atomic_state(new_crtc_state->base.state); 1010 + const struct intel_crtc_state *old_crtc_state = 1011 + intel_atomic_get_old_crtc_state(state, crtc); 1012 + 1013 + /* 1014 + * CGM_PIPE_MODE is itself single buffered. We'd have to 1015 + * somehow split it out from chv_load_luts() if we wanted 1016 + * the ability to preload the CGM LUTs/CSC without tearing. 1017 + */ 1018 + if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1019 + return false; 1020 + 1021 + return !old_crtc_state->base.gamma_lut; 1022 + } 1023 + 1024 + static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1025 + { 1026 + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); 1027 + struct intel_atomic_state *state = 1028 + to_intel_atomic_state(new_crtc_state->base.state); 1029 + const struct intel_crtc_state *old_crtc_state = 1030 + intel_atomic_get_old_crtc_state(state, crtc); 1031 + 1032 + /* 1033 + * The hardware degamma is active whenever the pipe 1034 + * CSC is active. Thus even if the old state has no 1035 + * software degamma we need to avoid clobbering the 1036 + * linear hardware degamma mid scanout. 1037 + */ 1038 + return !old_crtc_state->csc_enable && 1039 + !old_crtc_state->base.gamma_lut; 1040 + } 1041 + 993 1042 int intel_color_check(struct intel_crtc_state *crtc_state) 994 1043 { 995 1044 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); ··· 1182 1133 if (ret) 1183 1134 return ret; 1184 1135 1136 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1137 + 1185 1138 return 0; 1186 1139 } 1187 1140 ··· 1236 1185 if (ret) 1237 1186 return ret; 1238 1187 1188 + crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1189 + 1239 1190 return 0; 1240 1191 } 1241 1192 ··· 1276 1223 ret = intel_color_add_affected_planes(crtc_state); 1277 1224 if (ret) 1278 1225 return ret; 1226 + 1227 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1279 1228 1280 1229 return 0; 1281 1230 } ··· 1336 1281 if (ret) 1337 1282 return ret; 1338 1283 1284 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1285 + 1339 1286 return 0; 1340 1287 } 1341 1288 ··· 1375 1318 ret = intel_color_add_affected_planes(crtc_state); 1376 1319 if (ret) 1377 1320 return ret; 1321 + 1322 + crtc_state->preload_luts = glk_can_preload_luts(crtc_state); 1378 1323 1379 1324 return 0; 1380 1325 } ··· 1426 1367 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 1427 1368 1428 1369 crtc_state->csc_mode = icl_csc_mode(crtc_state); 1370 + 1371 + crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1429 1372 1430 1373 return 0; 1431 1374 }
+9
drivers/gpu/drm/i915/display/intel_display.c
··· 2504 2504 * the highest stride limits of them all. 2505 2505 */ 2506 2506 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); 2507 + if (!crtc) 2508 + return 0; 2509 + 2507 2510 plane = to_intel_plane(crtc->base.primary); 2508 2511 2509 2512 return plane->max_stride(plane, pixel_format, modifier, ··· 13743 13740 /* vblanks work again, re-enable pipe CRC. */ 13744 13741 intel_crtc_enable_pipe_crc(crtc); 13745 13742 } else { 13743 + if (new_crtc_state->preload_luts && 13744 + (new_crtc_state->base.color_mgmt_changed || 13745 + new_crtc_state->update_pipe)) 13746 + intel_color_load_luts(new_crtc_state); 13747 + 13746 13748 intel_pre_plane_update(old_crtc_state, new_crtc_state); 13747 13749 13748 13750 if (new_crtc_state->update_pipe) ··· 14042 14034 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 14043 14035 if (new_crtc_state->base.active && 14044 14036 !needs_modeset(new_crtc_state) && 14037 + !new_crtc_state->preload_luts && 14045 14038 (new_crtc_state->base.color_mgmt_changed || 14046 14039 new_crtc_state->update_pipe)) 14047 14040 intel_color_load_luts(new_crtc_state);
+1
drivers/gpu/drm/i915/display/intel_display_types.h
··· 761 761 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 762 762 bool fb_changed; /* fb on any of the planes is changed */ 763 763 bool fifo_changed; /* FIFO split is changed */ 764 + bool preload_luts; 764 765 765 766 /* Pipe source size (ie. panel fitter input size) 766 767 * All planes will be positioned inside this space,
+5 -4
drivers/gpu/drm/i915/display/intel_fbdev.c
··· 235 235 info->apertures->ranges[0].base = ggtt->gmadr.start; 236 236 info->apertures->ranges[0].size = ggtt->mappable_end; 237 237 238 + /* Our framebuffer is the entirety of fbdev's system memory */ 239 + info->fix.smem_start = 240 + (unsigned long)(ggtt->gmadr.start + vma->node.start); 241 + info->fix.smem_len = vma->node.size; 242 + 238 243 vaddr = i915_vma_pin_iomap(vma); 239 244 if (IS_ERR(vaddr)) { 240 245 DRM_ERROR("Failed to remap framebuffer into virtual memory\n"); ··· 248 243 } 249 244 info->screen_base = vaddr; 250 245 info->screen_size = vma->node.size; 251 - 252 - /* Our framebuffer is the entirety of fbdev's system memory */ 253 - info->fix.smem_start = (unsigned long)info->screen_base; 254 - info->fix.smem_len = info->screen_size; 255 246 256 247 drm_fb_helper_fill_info(info, &ifbdev->helper, sizes); 257 248
+21 -1
drivers/gpu/drm/i915/gem/i915_gem_userptr.c
··· 671 671 obj->mm.dirty = false; 672 672 673 673 for_each_sgt_page(page, sgt_iter, pages) { 674 - if (obj->mm.dirty) 674 + if (obj->mm.dirty && trylock_page(page)) { 675 + /* 676 + * As this may not be anonymous memory (e.g. shmem) 677 + * but exist on a real mapping, we have to lock 678 + * the page in order to dirty it -- holding 679 + * the page reference is not sufficient to 680 + * prevent the inode from being truncated. 681 + * Play safe and take the lock. 682 + * 683 + * However...! 684 + * 685 + * The mmu-notifier can be invalidated for a 686 + * migrate_page, that is alreadying holding the lock 687 + * on the page. Such a try_to_unmap() will result 688 + * in us calling put_pages() and so recursively try 689 + * to lock the page. We avoid that deadlock with 690 + * a trylock_page() and in exchange we risk missing 691 + * some page dirtying. 692 + */ 675 693 set_page_dirty(page); 694 + unlock_page(page); 695 + } 676 696 677 697 mark_page_accessed(page); 678 698 put_page(page);
+2
drivers/gpu/drm/i915/gt/intel_engine_pool.c
··· 103 103 return ERR_CAST(obj); 104 104 } 105 105 106 + i915_gem_object_set_readonly(obj); 107 + 106 108 node->obj = obj; 107 109 return node; 108 110 }
+2 -2
drivers/gpu/drm/i915/i915_pmu.c
··· 843 843 const char *name; 844 844 const char *unit; 845 845 } events[] = { 846 - __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "MHz"), 847 - __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "MHz"), 846 + __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"), 847 + __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"), 848 848 __event(I915_PMU_INTERRUPTS, "interrupts", NULL), 849 849 __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"), 850 850 };
+39 -11
drivers/gpu/drm/i915/i915_scheduler.c
··· 177 177 return rq->sched.attr.priority | __NO_PREEMPTION; 178 178 } 179 179 180 - static void kick_submission(struct intel_engine_cs *engine, int prio) 180 + static inline bool need_preempt(int prio, int active) 181 181 { 182 - const struct i915_request *inflight = *engine->execlists.active; 182 + /* 183 + * Allow preemption of low -> normal -> high, but we do 184 + * not allow low priority tasks to preempt other low priority 185 + * tasks under the impression that latency for low priority 186 + * tasks does not matter (as much as background throughput), 187 + * so kiss. 188 + */ 189 + return prio >= max(I915_PRIORITY_NORMAL, active); 190 + } 191 + 192 + static void kick_submission(struct intel_engine_cs *engine, 193 + const struct i915_request *rq, 194 + int prio) 195 + { 196 + const struct i915_request *inflight; 197 + 198 + /* 199 + * We only need to kick the tasklet once for the high priority 200 + * new context we add into the queue. 201 + */ 202 + if (prio <= engine->execlists.queue_priority_hint) 203 + return; 204 + 205 + rcu_read_lock(); 206 + 207 + /* Nothing currently active? We're overdue for a submission! */ 208 + inflight = execlists_active(&engine->execlists); 209 + if (!inflight) 210 + goto unlock; 183 211 184 212 /* 185 213 * If we are already the currently executing context, don't ··· 216 188 * tasklet, i.e. we have not change the priority queue 217 189 * sufficiently to oust the running context. 218 190 */ 219 - if (!inflight || !i915_scheduler_need_preempt(prio, rq_prio(inflight))) 220 - return; 191 + if (inflight->hw_context == rq->hw_context) 192 + goto unlock; 221 193 222 - tasklet_hi_schedule(&engine->execlists.tasklet); 194 + engine->execlists.queue_priority_hint = prio; 195 + if (need_preempt(prio, rq_prio(inflight))) 196 + tasklet_hi_schedule(&engine->execlists.tasklet); 197 + 198 + unlock: 199 + rcu_read_unlock(); 223 200 } 224 201 225 202 static void __i915_schedule(struct i915_sched_node *node, ··· 350 317 list_move_tail(&node->link, cache.priolist); 351 318 } 352 319 353 - if (prio <= engine->execlists.queue_priority_hint) 354 - continue; 355 - 356 - engine->execlists.queue_priority_hint = prio; 357 - 358 320 /* Defer (tasklet) submission until after all of our updates. */ 359 - kick_submission(engine, prio); 321 + kick_submission(engine, node_to_request(node), prio); 360 322 } 361 323 362 324 spin_unlock(&engine->active.lock);