Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- Build fix when !CONFIG_UID16 (the patch is touching generic files but
it only affects arm64 builds; submitted by Arnd Bergmann)
- EFI fixes to deal with early_memremap() returning NULL and correctly
mapping run-time regions
- Fix CPUID register extraction of unsigned fields (not to be
sign-extended)
- ASID allocator fix to deal with long-running tasks over multiple
generation roll-overs
- Revert support for marking page ranges as contiguous PTEs (it leads
to TLB conflicts and requires additional non-trivial kernel changes)
- Proper early_alloc() failure check
- Disable KASan for 48-bit VA and 16KB page configuration (the pgd is
larger than the KASan shadow memory)
- Update the fault_info table (original descriptions based on early
engineering spec)
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: efi: fix initcall return values
arm64: efi: deal with NULL return value of early_memremap()
arm64: debug: Treat the BRPs/WRPs as unsigned
arm64: cpufeature: Track unsigned fields
arm64: cpufeature: Add helpers for extracting unsigned values
Revert "arm64: Mark kernel page ranges contiguous"
arm64: mm: keep reserved ASIDs in sync with mm after multiple rollovers
arm64: KASAN depends on !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
arm64: efi: correctly map runtime regions
arm64: mm: fix fault_info table xFSC decoding
arm64: fix building without CONFIG_UID16
arm64: early_alloc: Fix check for allocation failure
+124
-123
+1
-1
arch/arm64/Kconfig
+1
-1
arch/arm64/Kconfig
···
49
49
select HAVE_ARCH_AUDITSYSCALL
50
50
select HAVE_ARCH_BITREVERSE
51
51
select HAVE_ARCH_JUMP_LABEL
52
-
select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
52
+
select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
53
53
select HAVE_ARCH_KGDB
54
54
select HAVE_ARCH_SECCOMP_FILTER
55
55
select HAVE_ARCH_TRACEHOOK
+20
-2
arch/arm64/include/asm/cpufeature.h
+20
-2
arch/arm64/include/asm/cpufeature.h
···
47
47
#define FTR_STRICT true /* SANITY check strict matching required */
48
48
#define FTR_NONSTRICT false /* SANITY check ignored */
49
49
50
+
#define FTR_SIGNED true /* Value should be treated as signed */
51
+
#define FTR_UNSIGNED false /* Value should be treated as unsigned */
52
+
50
53
struct arm64_ftr_bits {
51
-
bool strict; /* CPU Sanity check: strict matching required ? */
54
+
bool sign; /* Value is signed ? */
55
+
bool strict; /* CPU Sanity check: strict matching required ? */
52
56
enum ftr_type type;
53
57
u8 shift;
54
58
u8 width;
···
128
124
return cpuid_feature_extract_field_width(features, field, 4);
129
125
}
130
126
127
+
static inline unsigned int __attribute_const__
128
+
cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
129
+
{
130
+
return (u64)(features << (64 - width - field)) >> (64 - width);
131
+
}
132
+
133
+
static inline unsigned int __attribute_const__
134
+
cpuid_feature_extract_unsigned_field(u64 features, int field)
135
+
{
136
+
return cpuid_feature_extract_unsigned_field_width(features, field, 4);
137
+
}
138
+
131
139
static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
132
140
{
133
141
return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
···
147
131
148
132
static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
149
133
{
150
-
return cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width);
134
+
return ftrp->sign ?
135
+
cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width) :
136
+
cpuid_feature_extract_unsigned_field_width(val, ftrp->shift, ftrp->width);
151
137
}
152
138
153
139
static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
+4
-2
arch/arm64/include/asm/hw_breakpoint.h
+4
-2
arch/arm64/include/asm/hw_breakpoint.h
···
138
138
/* Determine number of BRP registers available. */
139
139
static inline int get_num_brps(void)
140
140
{
141
+
u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
141
142
return 1 +
142
-
cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
143
+
cpuid_feature_extract_unsigned_field(dfr0,
143
144
ID_AA64DFR0_BRPS_SHIFT);
144
145
}
145
146
146
147
/* Determine number of WRP registers available. */
147
148
static inline int get_num_wrps(void)
148
149
{
150
+
u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
149
151
return 1 +
150
-
cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
152
+
cpuid_feature_extract_unsigned_field(dfr0,
151
153
ID_AA64DFR0_WRPS_SHIFT);
152
154
}
153
155
+23
-14
arch/arm64/kernel/cpufeature.c
+23
-14
arch/arm64/kernel/cpufeature.c
···
44
44
45
45
DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
46
46
47
-
#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
47
+
#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
48
48
{ \
49
+
.sign = SIGNED, \
49
50
.strict = STRICT, \
50
51
.type = TYPE, \
51
52
.shift = SHIFT, \
52
53
.width = WIDTH, \
53
54
.safe_val = SAFE_VAL, \
54
55
}
56
+
57
+
/* Define a feature with signed values */
58
+
#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
59
+
__ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
60
+
61
+
/* Define a feature with unsigned value */
62
+
#define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
63
+
__ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
55
64
56
65
#define ARM64_FTR_END \
57
66
{ \
···
108
99
* Differing PARange is fine as long as all peripherals and memory are mapped
109
100
* within the minimum PARange of all CPUs
110
101
*/
111
-
ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
102
+
U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
112
103
ARM64_FTR_END,
113
104
};
114
105
···
124
115
};
125
116
126
117
static struct arm64_ftr_bits ftr_ctr[] = {
127
-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
118
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
128
119
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
129
-
ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
130
-
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
131
-
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
120
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
121
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
122
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
132
123
/*
133
124
* Linux can handle differing I-cache policies. Userspace JITs will
134
125
* make use of *minLine
135
126
*/
136
-
ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
127
+
U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
137
128
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
138
-
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
129
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
139
130
ARM64_FTR_END,
140
131
};
141
132
···
153
144
154
145
static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
155
146
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
156
-
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
157
-
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
158
-
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
159
-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
160
-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
161
-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
147
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
148
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
149
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
150
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
151
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
152
+
U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
162
153
ARM64_FTR_END,
163
154
};
164
155
+20
-13
arch/arm64/kernel/efi.c
+20
-13
arch/arm64/kernel/efi.c
···
127
127
table_size = sizeof(efi_config_table_64_t) * efi.systab->nr_tables;
128
128
config_tables = early_memremap(efi_to_phys(efi.systab->tables),
129
129
table_size);
130
-
130
+
if (config_tables == NULL) {
131
+
pr_warn("Unable to map EFI config table array.\n");
132
+
retval = -ENOMEM;
133
+
goto out;
134
+
}
131
135
retval = efi_config_parse_tables(config_tables, efi.systab->nr_tables,
132
136
sizeof(efi_config_table_64_t), NULL);
133
137
···
213
209
PAGE_ALIGN(params.mmap_size + (params.mmap & ~PAGE_MASK)));
214
210
memmap.phys_map = params.mmap;
215
211
memmap.map = early_memremap(params.mmap, params.mmap_size);
212
+
if (memmap.map == NULL) {
213
+
/*
214
+
* If we are booting via UEFI, the UEFI memory map is the only
215
+
* description of memory we have, so there is little point in
216
+
* proceeding if we cannot access it.
217
+
*/
218
+
panic("Unable to map EFI memory map.\n");
219
+
}
216
220
memmap.map_end = memmap.map + params.mmap_size;
217
221
memmap.desc_size = params.desc_size;
218
222
memmap.desc_version = params.desc_ver;
···
239
227
init_new_context(NULL, &efi_mm);
240
228
241
229
for_each_efi_memory_desc(&memmap, md) {
242
-
u64 paddr, npages, size;
243
230
pgprot_t prot;
244
231
245
232
if (!(md->attribute & EFI_MEMORY_RUNTIME))
246
233
continue;
247
234
if (md->virt_addr == 0)
248
235
return false;
249
-
250
-
paddr = md->phys_addr;
251
-
npages = md->num_pages;
252
-
memrange_efi_to_native(&paddr, &npages);
253
-
size = npages << PAGE_SHIFT;
254
236
255
237
pr_info(" EFI remap 0x%016llx => %p\n",
256
238
md->phys_addr, (void *)md->virt_addr);
···
262
256
else
263
257
prot = PAGE_KERNEL;
264
258
265
-
create_pgd_mapping(&efi_mm, paddr, md->virt_addr, size,
259
+
create_pgd_mapping(&efi_mm, md->phys_addr, md->virt_addr,
260
+
md->num_pages << EFI_PAGE_SHIFT,
266
261
__pgprot(pgprot_val(prot) | PTE_NG));
267
262
}
268
263
return true;
···
280
273
281
274
if (!efi_enabled(EFI_BOOT)) {
282
275
pr_info("EFI services will not be available.\n");
283
-
return -1;
276
+
return 0;
284
277
}
285
278
286
279
if (efi_runtime_disabled()) {
287
280
pr_info("EFI runtime services will be disabled.\n");
288
-
return -1;
281
+
return 0;
289
282
}
290
283
291
284
pr_info("Remapping and enabling EFI services.\n");
···
295
288
mapsize);
296
289
if (!memmap.map) {
297
290
pr_err("Failed to remap EFI memory map\n");
298
-
return -1;
291
+
return -ENOMEM;
299
292
}
300
293
memmap.map_end = memmap.map + mapsize;
301
294
efi.memmap = &memmap;
···
304
297
sizeof(efi_system_table_t));
305
298
if (!efi.systab) {
306
299
pr_err("Failed to remap EFI System Table\n");
307
-
return -1;
300
+
return -ENOMEM;
308
301
}
309
302
set_bit(EFI_SYSTEM_TABLES, &efi.flags);
310
303
311
304
if (!efi_virtmap_init()) {
312
305
pr_err("No UEFI virtual mapping was installed -- runtime services will not be available\n");
313
-
return -1;
306
+
return -ENOMEM;
314
307
}
315
308
316
309
/* Set up runtime services function pointers */
+26
-12
arch/arm64/mm/context.c
+26
-12
arch/arm64/mm/context.c
···
76
76
__flush_icache_all();
77
77
}
78
78
79
-
static int is_reserved_asid(u64 asid)
79
+
static bool check_update_reserved_asid(u64 asid, u64 newasid)
80
80
{
81
81
int cpu;
82
-
for_each_possible_cpu(cpu)
83
-
if (per_cpu(reserved_asids, cpu) == asid)
84
-
return 1;
85
-
return 0;
82
+
bool hit = false;
83
+
84
+
/*
85
+
* Iterate over the set of reserved ASIDs looking for a match.
86
+
* If we find one, then we can update our mm to use newasid
87
+
* (i.e. the same ASID in the current generation) but we can't
88
+
* exit the loop early, since we need to ensure that all copies
89
+
* of the old ASID are updated to reflect the mm. Failure to do
90
+
* so could result in us missing the reserved ASID in a future
91
+
* generation.
92
+
*/
93
+
for_each_possible_cpu(cpu) {
94
+
if (per_cpu(reserved_asids, cpu) == asid) {
95
+
hit = true;
96
+
per_cpu(reserved_asids, cpu) = newasid;
97
+
}
98
+
}
99
+
100
+
return hit;
86
101
}
87
102
88
103
static u64 new_context(struct mm_struct *mm, unsigned int cpu)
···
107
92
u64 generation = atomic64_read(&asid_generation);
108
93
109
94
if (asid != 0) {
95
+
u64 newasid = generation | (asid & ~ASID_MASK);
96
+
110
97
/*
111
98
* If our current ASID was active during a rollover, we
112
99
* can continue to use it and this was just a false alarm.
113
100
*/
114
-
if (is_reserved_asid(asid))
115
-
return generation | (asid & ~ASID_MASK);
101
+
if (check_update_reserved_asid(asid, newasid))
102
+
return newasid;
116
103
117
104
/*
118
105
* We had a valid ASID in a previous life, so try to re-use
···
122
105
*/
123
106
asid &= ~ASID_MASK;
124
107
if (!__test_and_set_bit(asid, asid_map))
125
-
goto bump_gen;
108
+
return newasid;
126
109
}
127
110
128
111
/*
···
146
129
set_asid:
147
130
__set_bit(asid, asid_map);
148
131
cur_idx = asid;
149
-
150
-
bump_gen:
151
-
asid |= generation;
152
-
return asid;
132
+
return asid | generation;
153
133
}
154
134
155
135
void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
+14
-14
arch/arm64/mm/fault.c
+14
-14
arch/arm64/mm/fault.c
···
393
393
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
394
394
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
395
395
{ do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
396
-
{ do_bad, SIGBUS, 0, "reserved access flag fault" },
396
+
{ do_bad, SIGBUS, 0, "unknown 8" },
397
397
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
398
398
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },
399
399
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" },
400
-
{ do_bad, SIGBUS, 0, "reserved permission fault" },
400
+
{ do_bad, SIGBUS, 0, "unknown 12" },
401
401
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
402
402
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
403
403
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
404
404
{ do_bad, SIGBUS, 0, "synchronous external abort" },
405
-
{ do_bad, SIGBUS, 0, "asynchronous external abort" },
405
+
{ do_bad, SIGBUS, 0, "unknown 17" },
406
406
{ do_bad, SIGBUS, 0, "unknown 18" },
407
407
{ do_bad, SIGBUS, 0, "unknown 19" },
408
408
{ do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
···
410
410
{ do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
411
411
{ do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
412
412
{ do_bad, SIGBUS, 0, "synchronous parity error" },
413
-
{ do_bad, SIGBUS, 0, "asynchronous parity error" },
413
+
{ do_bad, SIGBUS, 0, "unknown 25" },
414
414
{ do_bad, SIGBUS, 0, "unknown 26" },
415
415
{ do_bad, SIGBUS, 0, "unknown 27" },
416
-
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
417
-
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
418
-
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
419
-
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
416
+
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
417
+
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
418
+
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
419
+
{ do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
420
420
{ do_bad, SIGBUS, 0, "unknown 32" },
421
421
{ do_bad, SIGBUS, BUS_ADRALN, "alignment fault" },
422
-
{ do_bad, SIGBUS, 0, "debug event" },
422
+
{ do_bad, SIGBUS, 0, "unknown 34" },
423
423
{ do_bad, SIGBUS, 0, "unknown 35" },
424
424
{ do_bad, SIGBUS, 0, "unknown 36" },
425
425
{ do_bad, SIGBUS, 0, "unknown 37" },
···
433
433
{ do_bad, SIGBUS, 0, "unknown 45" },
434
434
{ do_bad, SIGBUS, 0, "unknown 46" },
435
435
{ do_bad, SIGBUS, 0, "unknown 47" },
436
-
{ do_bad, SIGBUS, 0, "unknown 48" },
436
+
{ do_bad, SIGBUS, 0, "TLB conflict abort" },
437
437
{ do_bad, SIGBUS, 0, "unknown 49" },
438
438
{ do_bad, SIGBUS, 0, "unknown 50" },
439
439
{ do_bad, SIGBUS, 0, "unknown 51" },
440
440
{ do_bad, SIGBUS, 0, "implementation fault (lockdown abort)" },
441
-
{ do_bad, SIGBUS, 0, "unknown 53" },
441
+
{ do_bad, SIGBUS, 0, "implementation fault (unsupported exclusive)" },
442
442
{ do_bad, SIGBUS, 0, "unknown 54" },
443
443
{ do_bad, SIGBUS, 0, "unknown 55" },
444
444
{ do_bad, SIGBUS, 0, "unknown 56" },
445
445
{ do_bad, SIGBUS, 0, "unknown 57" },
446
-
{ do_bad, SIGBUS, 0, "implementation fault (coprocessor abort)" },
446
+
{ do_bad, SIGBUS, 0, "unknown 58" },
447
447
{ do_bad, SIGBUS, 0, "unknown 59" },
448
448
{ do_bad, SIGBUS, 0, "unknown 60" },
449
-
{ do_bad, SIGBUS, 0, "unknown 61" },
450
-
{ do_bad, SIGBUS, 0, "unknown 62" },
449
+
{ do_bad, SIGBUS, 0, "section domain fault" },
450
+
{ do_bad, SIGBUS, 0, "page domain fault" },
451
451
{ do_bad, SIGBUS, 0, "unknown 63" },
452
452
};
453
453
+14
-63
arch/arm64/mm/mmu.c
+14
-63
arch/arm64/mm/mmu.c
···
64
64
65
65
static void __init *early_alloc(unsigned long sz)
66
66
{
67
-
void *ptr = __va(memblock_alloc(sz, sz));
68
-
BUG_ON(!ptr);
67
+
phys_addr_t phys;
68
+
void *ptr;
69
+
70
+
phys = memblock_alloc(sz, sz);
71
+
BUG_ON(!phys);
72
+
ptr = __va(phys);
69
73
memset(ptr, 0, sz);
70
74
return ptr;
71
75
}
···
85
81
do {
86
82
/*
87
83
* Need to have the least restrictive permissions available
88
-
* permissions will be fixed up later. Default the new page
89
-
* range as contiguous ptes.
84
+
* permissions will be fixed up later
90
85
*/
91
-
set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC_CONT));
86
+
set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC));
92
87
pfn++;
93
88
} while (pte++, i++, i < PTRS_PER_PTE);
94
89
}
95
90
96
-
/*
97
-
* Given a PTE with the CONT bit set, determine where the CONT range
98
-
* starts, and clear the entire range of PTE CONT bits.
99
-
*/
100
-
static void clear_cont_pte_range(pte_t *pte, unsigned long addr)
101
-
{
102
-
int i;
103
-
104
-
pte -= CONT_RANGE_OFFSET(addr);
105
-
for (i = 0; i < CONT_PTES; i++) {
106
-
set_pte(pte, pte_mknoncont(*pte));
107
-
pte++;
108
-
}
109
-
flush_tlb_all();
110
-
}
111
-
112
-
/*
113
-
* Given a range of PTEs set the pfn and provided page protection flags
114
-
*/
115
-
static void __populate_init_pte(pte_t *pte, unsigned long addr,
116
-
unsigned long end, phys_addr_t phys,
117
-
pgprot_t prot)
118
-
{
119
-
unsigned long pfn = __phys_to_pfn(phys);
120
-
121
-
do {
122
-
/* clear all the bits except the pfn, then apply the prot */
123
-
set_pte(pte, pfn_pte(pfn, prot));
124
-
pte++;
125
-
pfn++;
126
-
addr += PAGE_SIZE;
127
-
} while (addr != end);
128
-
}
129
-
130
91
static void alloc_init_pte(pmd_t *pmd, unsigned long addr,
131
-
unsigned long end, phys_addr_t phys,
92
+
unsigned long end, unsigned long pfn,
132
93
pgprot_t prot,
133
94
void *(*alloc)(unsigned long size))
134
95
{
135
96
pte_t *pte;
136
-
unsigned long next;
137
97
138
98
if (pmd_none(*pmd) || pmd_sect(*pmd)) {
139
99
pte = alloc(PTRS_PER_PTE * sizeof(pte_t));
···
110
142
111
143
pte = pte_offset_kernel(pmd, addr);
112
144
do {
113
-
next = min(end, (addr + CONT_SIZE) & CONT_MASK);
114
-
if (((addr | next | phys) & ~CONT_MASK) == 0) {
115
-
/* a block of CONT_PTES */
116
-
__populate_init_pte(pte, addr, next, phys,
117
-
__pgprot(pgprot_val(prot) | PTE_CONT));
118
-
} else {
119
-
/*
120
-
* If the range being split is already inside of a
121
-
* contiguous range but this PTE isn't going to be
122
-
* contiguous, then we want to unmark the adjacent
123
-
* ranges, then update the portion of the range we
124
-
* are interrested in.
125
-
*/
126
-
clear_cont_pte_range(pte, addr);
127
-
__populate_init_pte(pte, addr, next, phys, prot);
128
-
}
129
-
130
-
pte += (next - addr) >> PAGE_SHIFT;
131
-
phys += next - addr;
132
-
addr = next;
133
-
} while (addr != end);
145
+
set_pte(pte, pfn_pte(pfn, prot));
146
+
pfn++;
147
+
} while (pte++, addr += PAGE_SIZE, addr != end);
134
148
}
135
149
136
150
static void split_pud(pud_t *old_pud, pmd_t *pmd)
···
173
223
}
174
224
}
175
225
} else {
176
-
alloc_init_pte(pmd, addr, next, phys, prot, alloc);
226
+
alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys),
227
+
prot, alloc);
177
228
}
178
229
phys += next - addr;
179
230
} while (pmd++, addr = next, addr != end);
+1
-1
include/linux/syscalls.h
+1
-1
include/linux/syscalls.h
···
524
524
asmlinkage long sys_lchown(const char __user *filename,
525
525
uid_t user, gid_t group);
526
526
asmlinkage long sys_fchown(unsigned int fd, uid_t user, gid_t group);
527
-
#ifdef CONFIG_UID16
527
+
#ifdef CONFIG_HAVE_UID16
528
528
asmlinkage long sys_chown16(const char __user *filename,
529
529
old_uid_t user, old_gid_t group);
530
530
asmlinkage long sys_lchown16(const char __user *filename,