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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
phy: qcom-qmp-ufs: rename regs layout arrays
Rename regs layouts to follow the QMP PHY version.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221110192248.873973-9-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
5db22640
3b4bf465
+21
-16
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
+4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
···
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#define QCOM_PHY_QMP_PCS_UFS_V5_H_
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/* Only for QMP V5 PHY - UFS PCS registers */
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+
#define QPHY_V5_PCS_UFS_PHY_START 0x000
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+
#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V5_PCS_UFS_SW_RESET 0x008
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
···
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
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#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
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#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
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+
#define QPHY_V5_PCS_UFS_READY_STATUS 0x180
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#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
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#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
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+17
-16
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+17
-16
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
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QPHY_LAYOUT_SIZE
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};
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-
static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
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[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
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};
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-
static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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+
static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
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[QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
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};
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-
static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
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-
[QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
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-
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
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-
};
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-
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-
static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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+
static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
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[QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
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[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
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};
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static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
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[QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
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[QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
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};
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static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
···
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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-
.regs = msm8996_ufsphy_regs_layout,
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+
.regs = ufsphy_v2_regs_layout,
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.no_pcs_sw_reset = true,
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};
···
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm8150_ufsphy_regs_layout,
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.regs = ufsphy_v5_regs_layout,
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};
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static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
···
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sdm845_ufsphy_regs_layout,
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.regs = ufsphy_v3_regs_layout,
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.no_pcs_sw_reset = true,
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};
···
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm6115_ufsphy_regs_layout,
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.regs = ufsphy_v2_regs_layout,
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.no_pcs_sw_reset = true,
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};
···
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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-
.regs = sm8150_ufsphy_regs_layout,
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.regs = ufsphy_v4_regs_layout,
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};
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static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
···
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm8150_ufsphy_regs_layout,
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.regs = ufsphy_v5_regs_layout,
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};
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static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
···
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.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm8150_ufsphy_regs_layout,
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.regs = ufsphy_v5_regs_layout,
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};
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static void qmp_ufs_configure_lane(void __iomem *base,