Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Adding interface to log hw state when underflow happens
[why]
Will help us better debug underflow issues.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Muhammad Ahmed <Muhammad.Ahmed@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Muhammad Ahmed
and committed by
Alex Deucher
5dc0ec78
20ea30a7
+236
-7
+18
drivers/gpu/drm/amd/display/dc/core/dc.c
+18
drivers/gpu/drm/amd/display/dc/core/dc.c
···
6339
6339
6340
6340
return false;
6341
6341
}
6342
+
6343
+
void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,
6344
+
struct dc_underflow_debug_data *out_data)
6345
+
{
6346
+
struct timing_generator *tg = NULL;
6347
+
6348
+
for (int i = 0; i < MAX_PIPES; i++) {
6349
+
if (dc->res_pool->timing_generators[i] &&
6350
+
dc->res_pool->timing_generators[i]->inst == primary_otg_inst) {
6351
+
tg = dc->res_pool->timing_generators[i];
6352
+
break;
6353
+
}
6354
+
}
6355
+
6356
+
dc_exit_ips_for_hw_access(dc);
6357
+
if (dc->hwss.get_underflow_debug_data)
6358
+
dc->hwss.get_underflow_debug_data(dc, tg, out_data);
6359
+
}
+30
drivers/gpu/drm/amd/display/dc/dc.h
+30
drivers/gpu/drm/amd/display/dc/dc.h
···
1819
1819
struct dc_bias_and_scale bias_and_scale;
1820
1820
};
1821
1821
1822
+
struct dc_underflow_debug_data {
1823
+
uint32_t otg_inst;
1824
+
uint32_t otg_underflow;
1825
+
uint32_t h_position;
1826
+
uint32_t v_position;
1827
+
uint32_t otg_frame_count;
1828
+
struct dc_underflow_per_hubp_debug_data {
1829
+
uint32_t hubp_underflow;
1830
+
uint32_t hubp_in_blank;
1831
+
uint32_t hubp_readline;
1832
+
uint32_t det_config_error;
1833
+
} hubps[MAX_PIPES];
1834
+
uint32_t curr_det_sizes[MAX_PIPES];
1835
+
uint32_t target_det_sizes[MAX_PIPES];
1836
+
uint32_t compbuf_config_error;
1837
+
};
1838
+
1822
1839
/*
1823
1840
* Create a new surface with default parameters;
1824
1841
*/
···
2729
2712
2730
2713
bool dc_is_cursor_limit_pending(struct dc *dc);
2731
2714
bool dc_can_clear_cursor_limit(struct dc *dc);
2715
+
2716
+
/**
2717
+
* dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.
2718
+
*
2719
+
* @dc: Pointer to the display core context.
2720
+
* @primary_otg_inst: Instance index of the primary OTG that underflowed.
2721
+
* @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information.
2722
+
*
2723
+
* This function collects and logs underflow-related HW states when underflow happens,
2724
+
* including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
2725
+
* The results are stored in the provided out_data structure for further analysis or logging.
2726
+
*/
2727
+
void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);
2732
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#endif /* DC_INTERFACE_H_ */
+31
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
+31
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
···
440
440
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
441
441
}
442
442
443
+
void hubbub3_get_det_sizes(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes)
444
+
{
445
+
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
446
+
447
+
REG_GET_2(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, &curr_det_sizes[0],
448
+
DET0_SIZE, &target_det_sizes[0]);
449
+
450
+
REG_GET_2(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, &curr_det_sizes[1],
451
+
DET1_SIZE, &target_det_sizes[1]);
452
+
453
+
REG_GET_2(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, &curr_det_sizes[2],
454
+
DET2_SIZE, &target_det_sizes[2]);
455
+
456
+
REG_GET_2(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, &curr_det_sizes[3],
457
+
DET3_SIZE, &target_det_sizes[3]);
458
+
459
+
}
460
+
461
+
uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub)
462
+
{
463
+
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
464
+
uint32_t compbuf_config_error = 0;
465
+
466
+
REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR,
467
+
&compbuf_config_error);
468
+
469
+
return compbuf_config_error;
470
+
}
471
+
443
472
static const struct hubbub_funcs hubbub30_funcs = {
444
473
.update_dchub = hubbub2_update_dchub,
445
474
.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
···
486
457
.force_pstate_change_control = hubbub3_force_pstate_change_control,
487
458
.init_watermarks = hubbub3_init_watermarks,
488
459
.hubbub_read_state = hubbub2_read_state,
460
+
.get_det_sizes = hubbub3_get_det_sizes,
461
+
.compbuf_config_error = hubbub3_compbuf_config_error,
489
462
};
490
463
491
464
void hubbub3_construct(struct dcn20_hubbub *hubbub3,
+6
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
+6
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
···
1071
1071
.program_compbuf_size = dcn31_program_compbuf_size,
1072
1072
.init_crb = dcn31_init_crb,
1073
1073
.hubbub_read_state = hubbub2_read_state,
1074
+
.get_det_sizes = hubbub3_get_det_sizes,
1075
+
.compbuf_config_error = hubbub3_compbuf_config_error,
1074
1076
};
1075
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1076
1078
void hubbub31_construct(struct dcn20_hubbub *hubbub31,
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
···
1009
1009
.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
1010
1010
.set_request_limit = hubbub32_set_request_limit,
1011
1011
.get_mall_en = hubbub32_get_mall_en,
1012
+
.get_det_sizes = hubbub3_get_det_sizes,
1013
+
.compbuf_config_error = hubbub3_compbuf_config_error,
1012
1014
};
1013
1015
1014
1016
void hubbub32_construct(struct dcn20_hubbub *hubbub2,
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
···
589
589
.hubbub_read_state = hubbub2_read_state,
590
590
.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
591
591
.dchubbub_init = hubbub35_init,
592
+
.get_det_sizes = hubbub3_get_det_sizes,
593
+
.compbuf_config_error = hubbub3_compbuf_config_error,
592
594
};
593
595
594
596
void hubbub35_construct(struct dcn20_hubbub *hubbub2,
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
+2
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
···
1247
1247
.program_compbuf_segments = dcn401_program_compbuf_segments,
1248
1248
.wait_for_det_update = dcn401_wait_for_det_update,
1249
1249
.program_arbiter = dcn401_program_arbiter,
1250
+
.get_det_sizes = hubbub3_get_det_sizes,
1251
+
.compbuf_config_error = hubbub3_compbuf_config_error,
1250
1252
};
1251
1253
1252
1254
void hubbub401_construct(struct dcn20_hubbub *hubbub2,
+6
-2
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
+6
-2
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
···
104
104
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
105
105
SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
106
106
SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
107
-
SRI(HUBP_CLK_CNTL, HUBP, id)
107
+
SRI(HUBP_CLK_CNTL, HUBP, id),\
108
+
SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
108
109
109
110
/* Register address initialization macro for ASICs with VM */
110
111
#define HUBP_REG_LIST_DCN_VM(id)\
···
250
249
uint32_t CURSOR_POSITION; \
251
250
uint32_t CURSOR_HOT_SPOT; \
252
251
uint32_t CURSOR_DST_OFFSET; \
253
-
uint32_t HUBP_CLK_CNTL
252
+
uint32_t HUBP_CLK_CNTL; \
253
+
uint32_t HUBPRET_READ_LINE_VALUE
254
254
255
255
#define HUBP_SF(reg_name, field_name, post_fix)\
256
256
.field_name = reg_name ## __ ## field_name ## post_fix
···
624
622
type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
625
623
type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
626
624
type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
625
+
type PIPE_READ_LINE;\
626
+
type HUBP_SEG_ALLOC_ERR_STATUS;\
627
627
/* todo: get these from GVM instead of reading registers ourselves */\
628
628
type PAGE_DIRECTORY_ENTRY_HI32;\
629
629
type PAGE_DIRECTORY_ENTRY_LO32;\
+26
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+26
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
···
505
505
hubp_reset(hubp);
506
506
}
507
507
508
+
uint32_t hubp3_get_current_read_line(struct hubp *hubp)
509
+
{
510
+
uint32_t read_line = 0;
511
+
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
512
+
513
+
REG_GET(HUBPRET_READ_LINE_VALUE,
514
+
PIPE_READ_LINE,
515
+
&read_line);
516
+
517
+
return read_line;
518
+
}
519
+
520
+
unsigned int hubp3_get_underflow_status(struct hubp *hubp)
521
+
{
522
+
uint32_t hubp_underflow = 0;
523
+
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
524
+
525
+
REG_GET(DCHUBP_CNTL,
526
+
HUBP_UNDERFLOW_STATUS,
527
+
&hubp_underflow);
528
+
529
+
return hubp_underflow;
530
+
}
531
+
508
532
static struct hubp_funcs dcn30_hubp_funcs = {
509
533
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
510
534
.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
···
558
534
.hubp_soft_reset = hubp1_soft_reset,
559
535
.hubp_set_flip_int = hubp1_set_flip_int,
560
536
.hubp_clear_tiling = hubp3_clear_tiling,
537
+
.hubp_get_underflow_status = hubp3_get_underflow_status,
538
+
.hubp_get_current_read_line = hubp3_get_current_read_line,
561
539
};
562
540
563
541
bool hubp3_construct(
+7
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
+7
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h
···
243
243
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
244
244
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
245
245
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
246
-
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
246
+
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
247
+
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh)
247
248
248
249
bool hubp3_construct(
249
250
struct dcn20_hubp *hubp2,
···
299
298
void hubp3_init(struct hubp *hubp);
300
299
301
300
void hubp3_clear_tiling(struct hubp *hubp);
301
+
302
+
uint32_t hubp3_get_current_read_line(struct hubp *hubp);
303
+
304
+
uint32_t hubp3_get_underflow_status(struct hubp *hubp);
305
+
302
306
303
307
#endif /* __DC_HUBP_DCN30_H__ */
304
308
+15
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
+15
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c
···
68
68
hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);
69
69
}
70
70
71
+
uint32_t hubp31_get_det_config_error(struct hubp *hubp)
72
+
{
73
+
uint32_t config_error = 0;
74
+
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
75
+
76
+
REG_GET(DCHUBP_CNTL,
77
+
HUBP_SEG_ALLOC_ERR_STATUS,
78
+
&config_error);
79
+
80
+
return config_error;
81
+
}
82
+
71
83
static struct hubp_funcs dcn31_hubp_funcs = {
72
84
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
73
85
.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
···
110
98
.hubp_in_blank = hubp1_in_blank,
111
99
.program_extended_blank = hubp31_program_extended_blank,
112
100
.hubp_clear_tiling = hubp3_clear_tiling,
101
+
.hubp_get_underflow_status = hubp3_get_underflow_status,
102
+
.hubp_get_current_read_line = hubp3_get_current_read_line,
103
+
.hubp_get_det_config_error = hubp31_get_det_config_error,
113
104
};
114
105
115
106
bool hubp31_construct(
+5
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
+5
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h
···
228
228
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
229
229
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
230
230
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
231
-
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
231
+
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\
232
+
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\
233
+
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)
232
234
233
235
234
236
bool hubp31_construct(
···
247
245
248
246
void hubp31_program_extended_blank_value(
249
247
struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);
248
+
249
+
uint32_t hubp31_get_det_config_error(struct hubp *hubp);
250
250
251
251
#endif /* __DC_HUBP_DCN31_H__ */
+3
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
+3
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
···
206
206
.hubp_update_mall_sel = hubp32_update_mall_sel,
207
207
.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,
208
208
.hubp_clear_tiling = hubp3_clear_tiling,
209
+
.hubp_get_underflow_status = hubp3_get_underflow_status,
210
+
.hubp_get_current_read_line = hubp3_get_current_read_line,
211
+
.hubp_get_det_config_error = hubp31_get_det_config_error,
209
212
};
210
213
211
214
bool hubp32_construct(
+3
drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
+3
drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
···
218
218
.hubp_in_blank = hubp1_in_blank,
219
219
.program_extended_blank = hubp31_program_extended_blank_value,
220
220
.hubp_clear_tiling = hubp3_clear_tiling,
221
+
.hubp_get_underflow_status = hubp3_get_underflow_status,
222
+
.hubp_get_current_read_line = hubp3_get_current_read_line,
223
+
.hubp_get_det_config_error = hubp31_get_det_config_error,
221
224
};
222
225
223
226
bool hubp35_construct(
+3
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+3
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
···
1071
1071
.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,
1072
1072
.hubp_clear_tiling = hubp401_clear_tiling,
1073
1073
.hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config,
1074
+
.hubp_get_underflow_status = hubp3_get_underflow_status,
1075
+
.hubp_get_current_read_line = hubp3_get_current_read_line,
1076
+
.hubp_get_det_config_error = hubp31_get_det_config_error,
1074
1077
};
1075
1078
1076
1079
bool hubp401_construct(
+3
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+3
-1
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
···
252
252
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P0, mask_sh),\
253
253
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P0, mask_sh),\
254
254
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P1, mask_sh),\
255
-
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh)
255
+
HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh),\
256
+
HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\
257
+
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)
256
258
257
259
void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
258
260
+48
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+48
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
···
1228
1228
}
1229
1229
}
1230
1230
}
1231
+
1232
+
void dcn30_get_underflow_debug_data(const struct dc *dc,
1233
+
struct timing_generator *tg,
1234
+
struct dc_underflow_debug_data *out_data)
1235
+
{
1236
+
struct hubbub *hubbub = dc->res_pool->hubbub;
1237
+
1238
+
if (tg) {
1239
+
uint32_t v_blank_start = 0, v_blank_end = 0;
1240
+
1241
+
out_data->otg_inst = tg->inst;
1242
+
1243
+
tg->funcs->get_scanoutpos(tg,
1244
+
&v_blank_start,
1245
+
&v_blank_end,
1246
+
&out_data->h_position,
1247
+
&out_data->v_position);
1248
+
1249
+
out_data->otg_frame_count = tg->funcs->get_frame_count(tg);
1250
+
1251
+
out_data->otg_underflow = tg->funcs->is_optc_underflow_occurred(tg);
1252
+
}
1253
+
1254
+
for (int i = 0; i < MAX_PIPES; i++) {
1255
+
struct hubp *hubp = dc->res_pool->hubps[i];
1256
+
1257
+
if (hubp) {
1258
+
if (hubp->funcs->hubp_get_underflow_status)
1259
+
out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp);
1260
+
1261
+
if (hubp->funcs->hubp_in_blank)
1262
+
out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp);
1263
+
1264
+
if (hubp->funcs->hubp_get_current_read_line)
1265
+
out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp);
1266
+
1267
+
if (hubp->funcs->hubp_get_det_config_error)
1268
+
out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp);
1269
+
}
1270
+
}
1271
+
1272
+
if (hubbub->funcs->get_det_sizes)
1273
+
hubbub->funcs->get_det_sizes(hubbub, out_data->curr_det_sizes, out_data->target_det_sizes);
1274
+
1275
+
if (hubbub->funcs->compbuf_config_error)
1276
+
out_data->compbuf_config_error = hubbub->funcs->compbuf_config_error(hubbub);
1277
+
1278
+
}
+5
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
+5
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
···
29
29
#include "hw_sequencer_private.h"
30
30
31
31
struct dc;
32
+
struct dc_underflow_debug_data;
32
33
33
34
void dcn30_init_hw(struct dc *dc);
34
35
void dcn30_program_all_writeback_pipes_in_tree(
···
98
97
struct dc_state *context);
99
98
100
99
void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);
100
+
101
+
void dcn30_get_underflow_debug_data(const struct dc *dc,
102
+
struct timing_generator *tg,
103
+
struct dc_underflow_debug_data *out_data);
101
104
102
105
#endif /* __DC_HWSS_DCN30_H__ */
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
···
110
110
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
111
111
.is_abm_supported = dcn21_is_abm_supported,
112
112
.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
113
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
113
114
};
114
115
115
116
static const struct hwseq_private_funcs dcn30_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
···
112
112
.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
113
113
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
114
114
.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
115
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
115
116
};
116
117
117
118
static const struct hwseq_private_funcs dcn31_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
···
115
115
.update_visual_confirm_color = dcn10_update_visual_confirm_color,
116
116
.calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider,
117
117
.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
118
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
118
119
};
119
120
120
121
static const struct hwseq_private_funcs dcn314_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
···
121
121
.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
122
122
.program_outstanding_updates = dcn32_program_outstanding_updates,
123
123
.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,
124
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
124
125
};
125
126
126
127
static const struct hwseq_private_funcs dcn32_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
···
128
128
.enable_plane = dcn20_enable_plane,
129
129
.update_dchubp_dpp = dcn20_update_dchubp_dpp,
130
130
.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
131
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
131
132
};
132
133
133
134
static const struct hwseq_private_funcs dcn35_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
···
123
123
.set_long_vtotal = dcn35_set_long_vblank,
124
124
.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
125
125
.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
126
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
126
127
};
127
128
128
129
static const struct hwseq_private_funcs dcn351_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
···
104
104
.enable_plane = dcn20_enable_plane,
105
105
.update_dchubp_dpp = dcn20_update_dchubp_dpp,
106
106
.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,
107
+
.get_underflow_debug_data = dcn30_get_underflow_debug_data,
107
108
};
108
109
109
110
static const struct hwseq_private_funcs dcn401_private_funcs = {
+4
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+4
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
···
47
47
struct dc_dmub_cmd;
48
48
struct pg_block_update;
49
49
struct drr_params;
50
+
struct dc_underflow_debug_data;
50
51
51
52
struct subvp_pipe_control_lock_fast_params {
52
53
struct dc *dc;
···
476
475
struct dc_state *context);
477
476
void (*post_unlock_reset_opp)(struct dc *dc,
478
477
struct pipe_ctx *opp_head);
478
+
void (*get_underflow_debug_data)(const struct dc *dc,
479
+
struct timing_generator *tg,
480
+
struct dc_underflow_debug_data *out_data);
479
481
};
480
482
481
483
void color_space_to_black_color(
+2
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+2
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
···
229
229
void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);
230
230
void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst);
231
231
bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower);
232
+
void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes);
233
+
uint32_t (*compbuf_config_error)(struct hubbub *hubbub);
232
234
};
233
235
234
236
struct hubbub {
+2
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+2
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
···
306
306
int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
307
307
void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);
308
308
void (*hubp_clear_tiling)(struct hubp *hubp);
309
+
uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);
310
+
uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);
309
311
};
310
312
311
313
#endif
+2
-1
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+2
-1
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
···
1141
1141
SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \
1142
1142
SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \
1143
1143
SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \
1144
-
SRI_ARR(HUBP_CLK_CNTL, HUBP, id)
1144
+
SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \
1145
+
SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
1145
1146
#define HUBP_REG_LIST_DCN2_COMMON_RI(id) \
1146
1147
HUBP_REG_LIST_DCN_RI(id), HUBP_REG_LIST_DCN_VM_RI(id), \
1147
1148
SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \
+2
-1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+2
-1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
···
140
140
SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \
141
141
HUBP_3DLUT_FL_REG_LIST_DCN401(id), \
142
142
SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \
143
-
SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id)
143
+
SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id), \
144
+
SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)
144
145
145
146
/* ABM */
146
147
#define ABM_DCN401_REG_LIST_RI(id) \