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usb: xhci: cleanup xhci_hub_report_usb3_link_state()

Improve readability of xhci_hub_report_usb3_link_state().

Comments are shortened and clarified, and the code now makes it explicit
when the Port Link State (PLS) value is modified versus when other status
bits are updated.

No functional changes.

Signed-off-by: Niklas Neronin <niklas.neronin@linux.intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://patch.msgid.link/20260402131342.2628648-22-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Niklas Neronin and committed by
Greg Kroah-Hartman 5dfc7f98 aef5305d

+21 -37
+21 -37
drivers/usb/host/xhci-hub.c
··· 850 850 } 851 851 852 852 /* Updates Link Status for super Speed port */ 853 - static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, 854 - u32 *status, u32 portsc) 853 + static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, u32 *status, u32 portsc) 855 854 { 856 855 u32 pls = portsc & PORT_PLS_MASK; 857 856 858 - /* When the CAS bit is set then warm reset 859 - * should be performed on port 857 + /* 858 + * CAS indicates that a warm reset is required, it may be set in any 859 + * link state and is only present on roothubs. 860 860 */ 861 861 if (portsc & PORT_CAS) { 862 - /* The CAS bit can be set while the port is 863 - * in any link state. 864 - * Only roothubs have CAS bit, so we 865 - * pretend to be in compliance mode 866 - * unless we're already in compliance 867 - * or the inactive state. 862 + /* 863 + * If not already in Compliance or Inactive state, 864 + * report Compliance Mode so the hub logic triggers a warm reset. 868 865 */ 869 - if (pls != XDEV_COMP_MODE && 870 - pls != XDEV_INACTIVE) { 866 + if (pls != XDEV_COMP_MODE && pls != XDEV_INACTIVE) 871 867 pls = USB_SS_PORT_LS_COMP_MOD; 872 - } 873 - /* Return also connection bit - 874 - * hub state machine resets port 875 - * when this bit is set. 876 - */ 877 - pls |= USB_PORT_STAT_CONNECTION; 878 - } else { 879 - /* 880 - * Resume state is an xHCI internal state. Do not report it to 881 - * usb core, instead, pretend to be U3, thus usb core knows 882 - * it's not ready for transfer. 883 - */ 884 - if (pls == XDEV_RESUME) { 885 - *status |= USB_SS_PORT_LS_U3; 886 - return; 887 - } 888 868 869 + /* Signal a connection change to force a reset */ 870 + *status |= USB_PORT_STAT_CONNECTION; 871 + } else if (pls == XDEV_RESUME) { 889 872 /* 890 - * If CAS bit isn't set but the Port is already at 891 - * Compliance Mode, fake a connection so the USB core 892 - * notices the Compliance state and resets the port. 893 - * This resolves an issue generated by the SN65LVPE502CP 894 - * in which sometimes the port enters compliance mode 895 - * caused by a delay on the host-device negotiation. 873 + * Resume is an internal xHCI-only state and must not be exposed 874 + * to usbcore. Report it as U3 so transfers are blocked. 896 875 */ 897 - if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && 898 - (pls == XDEV_COMP_MODE)) 899 - pls |= USB_PORT_STAT_CONNECTION; 876 + pls = USB_SS_PORT_LS_U3; 877 + } else if (pls == XDEV_COMP_MODE) { 878 + /* 879 + * Some hardware may enter Compliance Mode without CAS. 880 + * Fake a connection event so usbcore notices and resets the port. 881 + */ 882 + if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 883 + *status |= USB_PORT_STAT_CONNECTION; 900 884 } 901 885 902 886 /* update status field */