Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Intel and radeon fixes.
Post KS/LC git requests from i915 and radeon stacked up. They are all
fixes along with some new pci ids for radeon, and one maintainers file
entry.
- i915: display fixes and irq fixes
- radeon: pci ids, and misc gpuvm, dpm and hdp cache"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (29 commits)
MAINTAINERS: Add entry for Renesas DRM drivers
drm/radeon: add additional SI pci ids
drm/radeon: add new bonaire pci ids
drm/radeon: add new KV pci id
Revert "drm/radeon: Use write-combined CPU mappings of ring buffers with PCIe"
drm/radeon: fix active_cu mask on SI and CIK after re-init (v3)
drm/radeon: fix active cu count for SI and CIK
drm/radeon: re-enable selective GPUVM flushing
drm/radeon: Sync ME and PFP after CP semaphore waits v4
drm/radeon: fix display handling in radeon_gpu_reset
drm/radeon: fix pm handling in radeon_gpu_reset
drm/radeon: Only flush HDP cache for indirect buffers from userspace
drm/radeon: properly document reloc priority mask
drm/i915: don't try to retrain a DP link on an inactive CRTC
drm/i915: make sure VDD is turned off during system suspend
drm/i915: cancel hotplug and dig_port work during suspend and unload
drm/i915: fix HPD IRQ reenable work cancelation
drm/i915: take display port power domain in DP HPD handler
drm/i915: Don't try to enable cursor from setplane when crtc is disabled
drm/i915: Skip load detect when intel_crtc->new_enable==true
...
+328
-167
+11
MAINTAINERS
+11
MAINTAINERS
···
3121
3121
F: include/uapi/drm/tegra_drm.h
3122
3122
F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
3123
3123
3124
+
DRM DRIVERS FOR RENESAS
3125
+
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
3126
+
L: dri-devel@lists.freedesktop.org
3127
+
L: linux-sh@vger.kernel.org
3128
+
T: git git://people.freedesktop.org/~airlied/linux
3129
+
S: Supported
3130
+
F: drivers/gpu/drm/rcar-du/
3131
+
F: drivers/gpu/drm/shmobile/
3132
+
F: include/linux/platform_data/rcar-du.h
3133
+
F: include/linux/platform_data/shmob_drm.h
3134
+
3124
3135
DSBR100 USB FM RADIO DRIVER
3125
3136
M: Alexey Klimov <klimov.linux@gmail.com>
3126
3137
L: linux-media@vger.kernel.org
+33
drivers/gpu/drm/i915/i915_drv.c
+33
drivers/gpu/drm/i915/i915_drv.c
···
494
494
return true;
495
495
}
496
496
497
+
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
498
+
{
499
+
spin_lock_irq(&dev_priv->irq_lock);
500
+
501
+
dev_priv->long_hpd_port_mask = 0;
502
+
dev_priv->short_hpd_port_mask = 0;
503
+
dev_priv->hpd_event_bits = 0;
504
+
505
+
spin_unlock_irq(&dev_priv->irq_lock);
506
+
507
+
cancel_work_sync(&dev_priv->dig_port_work);
508
+
cancel_work_sync(&dev_priv->hotplug_work);
509
+
cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
510
+
}
511
+
512
+
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
513
+
{
514
+
struct drm_device *dev = dev_priv->dev;
515
+
struct drm_encoder *encoder;
516
+
517
+
drm_modeset_lock_all(dev);
518
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
519
+
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
520
+
521
+
if (intel_encoder->suspend)
522
+
intel_encoder->suspend(intel_encoder);
523
+
}
524
+
drm_modeset_unlock_all(dev);
525
+
}
526
+
497
527
static int i915_drm_freeze(struct drm_device *dev)
498
528
{
499
529
struct drm_i915_private *dev_priv = dev->dev_private;
···
568
538
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
569
539
570
540
intel_runtime_pm_disable_interrupts(dev);
541
+
intel_hpd_cancel_work(dev_priv);
542
+
543
+
intel_suspend_encoders(dev_priv);
571
544
572
545
intel_suspend_gt_powersave(dev);
573
546
+2
-1
drivers/gpu/drm/i915/i915_drv.h
+2
-1
drivers/gpu/drm/i915/i915_drv.h
···
1458
1458
} hpd_mark;
1459
1459
} hpd_stats[HPD_NUM_PINS];
1460
1460
u32 hpd_event_bits;
1461
-
struct timer_list hotplug_reenable_timer;
1461
+
struct delayed_work hotplug_reenable_work;
1462
1462
1463
1463
struct i915_fbc fbc;
1464
1464
struct i915_drrs drrs;
···
2178
2178
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2179
2179
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2180
2180
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2181
+
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2181
2182
2182
2183
extern void intel_console_resume(struct work_struct *work);
2183
2184
+12
-21
drivers/gpu/drm/i915/i915_irq.c
+12
-21
drivers/gpu/drm/i915/i915_irq.c
···
1189
1189
* some connectors */
1190
1190
if (hpd_disabled) {
1191
1191
drm_kms_helper_poll_enable(dev);
1192
-
mod_timer(&dev_priv->hotplug_reenable_timer,
1193
-
jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1192
+
mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
1193
+
msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1194
1194
}
1195
1195
1196
1196
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
···
1211
1211
1212
1212
if (changed)
1213
1213
drm_kms_helper_hotplug_event(dev);
1214
-
}
1215
-
1216
-
static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1217
-
{
1218
-
del_timer_sync(&dev_priv->hotplug_reenable_timer);
1219
1214
}
1220
1215
1221
1216
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
···
3887
3892
if (!dev_priv)
3888
3893
return;
3889
3894
3890
-
intel_hpd_irq_uninstall(dev_priv);
3891
-
3892
3895
gen8_irq_reset(dev);
3893
3896
}
3894
3897
···
3900
3907
return;
3901
3908
3902
3909
I915_WRITE(VLV_MASTER_IER, 0);
3903
-
3904
-
intel_hpd_irq_uninstall(dev_priv);
3905
3910
3906
3911
for_each_pipe(pipe)
3907
3912
I915_WRITE(PIPESTAT(pipe), 0xffff);
···
3978
3987
3979
3988
if (!dev_priv)
3980
3989
return;
3981
-
3982
-
intel_hpd_irq_uninstall(dev_priv);
3983
3990
3984
3991
ironlake_irq_reset(dev);
3985
3992
}
···
4349
4360
struct drm_i915_private *dev_priv = dev->dev_private;
4350
4361
int pipe;
4351
4362
4352
-
intel_hpd_irq_uninstall(dev_priv);
4353
-
4354
4363
if (I915_HAS_HOTPLUG(dev)) {
4355
4364
I915_WRITE(PORT_HOTPLUG_EN, 0);
4356
4365
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
···
4585
4598
if (!dev_priv)
4586
4599
return;
4587
4600
4588
-
intel_hpd_irq_uninstall(dev_priv);
4589
-
4590
4601
I915_WRITE(PORT_HOTPLUG_EN, 0);
4591
4602
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4592
4603
···
4600
4615
I915_WRITE(IIR, I915_READ(IIR));
4601
4616
}
4602
4617
4603
-
static void intel_hpd_irq_reenable(unsigned long data)
4618
+
static void intel_hpd_irq_reenable(struct work_struct *work)
4604
4619
{
4605
-
struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4620
+
struct drm_i915_private *dev_priv =
4621
+
container_of(work, typeof(*dev_priv),
4622
+
hotplug_reenable_work.work);
4606
4623
struct drm_device *dev = dev_priv->dev;
4607
4624
struct drm_mode_config *mode_config = &dev->mode_config;
4608
4625
unsigned long irqflags;
4609
4626
int i;
4627
+
4628
+
intel_runtime_pm_get(dev_priv);
4610
4629
4611
4630
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4612
4631
for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
···
4637
4648
if (dev_priv->display.hpd_irq_setup)
4638
4649
dev_priv->display.hpd_irq_setup(dev);
4639
4650
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4651
+
4652
+
intel_runtime_pm_put(dev_priv);
4640
4653
}
4641
4654
4642
4655
void intel_irq_init(struct drm_device *dev)
···
4661
4670
setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4662
4671
i915_hangcheck_elapsed,
4663
4672
(unsigned long) dev);
4664
-
setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4665
-
(unsigned long) dev_priv);
4673
+
INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4674
+
intel_hpd_irq_reenable);
4666
4675
4667
4676
pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4668
4677
+6
-1
drivers/gpu/drm/i915/intel_crt.c
+6
-1
drivers/gpu/drm/i915/intel_crt.c
···
699
699
goto out;
700
700
}
701
701
702
+
drm_modeset_acquire_init(&ctx, 0);
703
+
702
704
/* for pre-945g platforms use load detect */
703
705
if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
704
706
if (intel_crt_detect_ddc(connector))
705
707
status = connector_status_connected;
706
708
else
707
709
status = intel_crt_load_detect(crt);
708
-
intel_release_load_detect_pipe(connector, &tmp, &ctx);
710
+
intel_release_load_detect_pipe(connector, &tmp);
709
711
} else
710
712
status = connector_status_unknown;
713
+
714
+
drm_modeset_drop_locks(&ctx);
715
+
drm_modeset_acquire_fini(&ctx);
711
716
712
717
out:
713
718
intel_display_power_put(dev_priv, power_domain);
+15
-24
drivers/gpu/drm/i915/intel_display.c
+15
-24
drivers/gpu/drm/i915/intel_display.c
···
8462
8462
connector->base.id, connector->name,
8463
8463
encoder->base.id, encoder->name);
8464
8464
8465
-
drm_modeset_acquire_init(ctx, 0);
8466
-
8467
8465
retry:
8468
8466
ret = drm_modeset_lock(&config->connection_mutex, ctx);
8469
8467
if (ret)
···
8500
8502
i++;
8501
8503
if (!(encoder->possible_crtcs & (1 << i)))
8502
8504
continue;
8503
-
if (!possible_crtc->enabled) {
8504
-
crtc = possible_crtc;
8505
-
break;
8506
-
}
8505
+
if (possible_crtc->enabled)
8506
+
continue;
8507
+
/* This can occur when applying the pipe A quirk on resume. */
8508
+
if (to_intel_crtc(possible_crtc)->new_enabled)
8509
+
continue;
8510
+
8511
+
crtc = possible_crtc;
8512
+
break;
8507
8513
}
8508
8514
8509
8515
/*
···
8576
8574
goto retry;
8577
8575
}
8578
8576
8579
-
drm_modeset_drop_locks(ctx);
8580
-
drm_modeset_acquire_fini(ctx);
8581
-
8582
8577
return false;
8583
8578
}
8584
8579
8585
8580
void intel_release_load_detect_pipe(struct drm_connector *connector,
8586
-
struct intel_load_detect_pipe *old,
8587
-
struct drm_modeset_acquire_ctx *ctx)
8581
+
struct intel_load_detect_pipe *old)
8588
8582
{
8589
8583
struct intel_encoder *intel_encoder =
8590
8584
intel_attached_encoder(connector);
···
8604
8606
drm_framebuffer_unreference(old->release_fb);
8605
8607
}
8606
8608
8607
-
goto unlock;
8608
8609
return;
8609
8610
}
8610
8611
8611
8612
/* Switch crtc and encoder back off if necessary */
8612
8613
if (old->dpms_mode != DRM_MODE_DPMS_ON)
8613
8614
connector->funcs->dpms(connector, old->dpms_mode);
8614
-
8615
-
unlock:
8616
-
drm_modeset_drop_locks(ctx);
8617
-
drm_modeset_acquire_fini(ctx);
8618
8615
}
8619
8616
8620
8617
static int i9xx_pll_refclk(struct drm_device *dev,
···
11693
11700
};
11694
11701
const struct drm_rect clip = {
11695
11702
/* integer pixels */
11696
-
.x2 = intel_crtc->config.pipe_src_w,
11697
-
.y2 = intel_crtc->config.pipe_src_h,
11703
+
.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11704
+
.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11698
11705
};
11699
11706
bool visible;
11700
11707
int ret;
···
12652
12659
struct intel_connector *connector;
12653
12660
struct drm_connector *crt = NULL;
12654
12661
struct intel_load_detect_pipe load_detect_temp;
12655
-
struct drm_modeset_acquire_ctx ctx;
12662
+
struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12656
12663
12657
12664
/* We can't just switch on the pipe A, we need to set things up with a
12658
12665
* proper mode and output configuration. As a gross hack, enable pipe A
···
12669
12676
if (!crt)
12670
12677
return;
12671
12678
12672
-
if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12673
-
intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12674
-
12675
-
12679
+
if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12680
+
intel_release_load_detect_pipe(crt, &load_detect_temp);
12676
12681
}
12677
12682
12678
12683
static bool
···
13103
13112
* experience fancy races otherwise.
13104
13113
*/
13105
13114
drm_irq_uninstall(dev);
13106
-
cancel_work_sync(&dev_priv->hotplug_work);
13115
+
intel_hpd_cancel_work(dev_priv);
13107
13116
dev_priv->pm._irqs_disabled = true;
13108
13117
13109
13118
/*
+28
-5
drivers/gpu/drm/i915/intel_dp.c
+28
-5
drivers/gpu/drm/i915/intel_dp.c
···
3553
3553
if (WARN_ON(!intel_encoder->base.crtc))
3554
3554
return;
3555
3555
3556
+
if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3557
+
return;
3558
+
3556
3559
/* Try to read receiver status if the link appears to be up */
3557
3560
if (!intel_dp_get_link_status(intel_dp, link_status)) {
3558
3561
return;
···
4006
4003
kfree(intel_dig_port);
4007
4004
}
4008
4005
4006
+
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4007
+
{
4008
+
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4009
+
4010
+
if (!is_edp(intel_dp))
4011
+
return;
4012
+
4013
+
edp_panel_vdd_off_sync(intel_dp);
4014
+
}
4015
+
4009
4016
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4010
4017
{
4011
4018
intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
···
4050
4037
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4051
4038
{
4052
4039
struct intel_dp *intel_dp = &intel_dig_port->dp;
4040
+
struct intel_encoder *intel_encoder = &intel_dig_port->base;
4053
4041
struct drm_device *dev = intel_dig_port->base.base.dev;
4054
4042
struct drm_i915_private *dev_priv = dev->dev_private;
4055
-
int ret;
4043
+
enum intel_display_power_domain power_domain;
4044
+
bool ret = true;
4045
+
4056
4046
if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4057
4047
intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4058
4048
4059
4049
DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4060
4050
long_hpd ? "long" : "short");
4051
+
4052
+
power_domain = intel_display_port_power_domain(intel_encoder);
4053
+
intel_display_power_get(dev_priv, power_domain);
4061
4054
4062
4055
if (long_hpd) {
4063
4056
if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
···
4080
4061
4081
4062
} else {
4082
4063
if (intel_dp->is_mst) {
4083
-
ret = intel_dp_check_mst_status(intel_dp);
4084
-
if (ret == -EINVAL)
4064
+
if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4085
4065
goto mst_fail;
4086
4066
}
4087
4067
···
4094
4076
drm_modeset_unlock(&dev->mode_config.connection_mutex);
4095
4077
}
4096
4078
}
4097
-
return false;
4079
+
ret = false;
4080
+
goto put_power;
4098
4081
mst_fail:
4099
4082
/* if we were in MST mode, and device is not there get out of MST mode */
4100
4083
if (intel_dp->is_mst) {
···
4103
4084
intel_dp->is_mst = false;
4104
4085
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4105
4086
}
4106
-
return true;
4087
+
put_power:
4088
+
intel_display_power_put(dev_priv, power_domain);
4089
+
4090
+
return ret;
4107
4091
}
4108
4092
4109
4093
/* Return which DP Port should be selected for Transcoder DP control */
···
4744
4722
intel_encoder->disable = intel_disable_dp;
4745
4723
intel_encoder->get_hw_state = intel_dp_get_hw_state;
4746
4724
intel_encoder->get_config = intel_dp_get_config;
4725
+
intel_encoder->suspend = intel_dp_encoder_suspend;
4747
4726
if (IS_CHERRYVIEW(dev)) {
4748
4727
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4749
4728
intel_encoder->pre_enable = chv_pre_enable_dp;
+7
-2
drivers/gpu/drm/i915/intel_drv.h
+7
-2
drivers/gpu/drm/i915/intel_drv.h
···
153
153
* be set correctly before calling this function. */
154
154
void (*get_config)(struct intel_encoder *,
155
155
struct intel_crtc_config *pipe_config);
156
+
/*
157
+
* Called during system suspend after all pending requests for the
158
+
* encoder are flushed (for example for DP AUX transactions) and
159
+
* device interrupts are disabled.
160
+
*/
161
+
void (*suspend)(struct intel_encoder *);
156
162
int crtc_mask;
157
163
enum hpd_pin hpd_pin;
158
164
};
···
836
830
struct intel_load_detect_pipe *old,
837
831
struct drm_modeset_acquire_ctx *ctx);
838
832
void intel_release_load_detect_pipe(struct drm_connector *connector,
839
-
struct intel_load_detect_pipe *old,
840
-
struct drm_modeset_acquire_ctx *ctx);
833
+
struct intel_load_detect_pipe *old);
841
834
int intel_pin_and_fence_fb_obj(struct drm_device *dev,
842
835
struct drm_i915_gem_object *obj,
843
836
struct intel_engine_cs *pipelined);
+6
-1
drivers/gpu/drm/i915/intel_tv.c
+6
-1
drivers/gpu/drm/i915/intel_tv.c
···
1323
1323
struct intel_load_detect_pipe tmp;
1324
1324
struct drm_modeset_acquire_ctx ctx;
1325
1325
1326
+
drm_modeset_acquire_init(&ctx, 0);
1327
+
1326
1328
if (intel_get_load_detect_pipe(connector, &mode, &tmp, &ctx)) {
1327
1329
type = intel_tv_detect_type(intel_tv, connector);
1328
-
intel_release_load_detect_pipe(connector, &tmp, &ctx);
1330
+
intel_release_load_detect_pipe(connector, &tmp);
1329
1331
} else
1330
1332
return connector_status_unknown;
1333
+
1334
+
drm_modeset_drop_locks(&ctx);
1335
+
drm_modeset_acquire_fini(&ctx);
1331
1336
} else
1332
1337
return connector->status;
1333
1338
+1
-1
drivers/gpu/drm/radeon/Makefile
+1
-1
drivers/gpu/drm/radeon/Makefile
···
76
76
evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
77
77
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
78
78
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
79
-
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
79
+
si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
80
80
r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
81
81
rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
82
82
trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
+3
drivers/gpu/drm/radeon/ci_dpm.c
+3
drivers/gpu/drm/radeon/ci_dpm.c
+30
-13
drivers/gpu/drm/radeon/cik.c
+30
-13
drivers/gpu/drm/radeon/cik.c
···
3483
3483
u32 mc_shared_chmap, mc_arb_ramcfg;
3484
3484
u32 hdp_host_path_cntl;
3485
3485
u32 tmp;
3486
-
int i, j, k;
3486
+
int i, j;
3487
3487
3488
3488
switch (rdev->family) {
3489
3489
case CHIP_BONAIRE:
···
3544
3544
(rdev->pdev->device == 0x130B) ||
3545
3545
(rdev->pdev->device == 0x130E) ||
3546
3546
(rdev->pdev->device == 0x1315) ||
3547
+
(rdev->pdev->device == 0x1318) ||
3547
3548
(rdev->pdev->device == 0x131B)) {
3548
3549
rdev->config.cik.max_cu_per_sh = 4;
3549
3550
rdev->config.cik.max_backends_per_se = 1;
···
3673
3672
rdev->config.cik.max_sh_per_se,
3674
3673
rdev->config.cik.max_backends_per_se);
3675
3674
3675
+
rdev->config.cik.active_cus = 0;
3676
3676
for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3677
3677
for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3678
-
for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {
3679
-
rdev->config.cik.active_cus +=
3680
-
hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3681
-
}
3678
+
rdev->config.cik.active_cus +=
3679
+
hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3682
3680
}
3683
3681
}
3684
3682
···
3801
3801
radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3802
3802
radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3803
3803
radeon_ring_write(ring, 0xDEADBEEF);
3804
-
radeon_ring_unlock_commit(rdev, ring);
3804
+
radeon_ring_unlock_commit(rdev, ring, false);
3805
3805
3806
3806
for (i = 0; i < rdev->usec_timeout; i++) {
3807
3807
tmp = RREG32(scratch);
···
3920
3920
radeon_ring_write(ring, 0);
3921
3921
}
3922
3922
3923
+
/**
3924
+
* cik_semaphore_ring_emit - emit a semaphore on the CP ring
3925
+
*
3926
+
* @rdev: radeon_device pointer
3927
+
* @ring: radeon ring buffer object
3928
+
* @semaphore: radeon semaphore object
3929
+
* @emit_wait: Is this a sempahore wait?
3930
+
*
3931
+
* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3932
+
* from running ahead of semaphore waits.
3933
+
*/
3923
3934
bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3924
3935
struct radeon_ring *ring,
3925
3936
struct radeon_semaphore *semaphore,
···
3942
3931
radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3943
3932
radeon_ring_write(ring, lower_32_bits(addr));
3944
3933
radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3934
+
3935
+
if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
3936
+
/* Prevent the PFP from running ahead of the semaphore wait */
3937
+
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3938
+
radeon_ring_write(ring, 0x0);
3939
+
}
3945
3940
3946
3941
return true;
3947
3942
}
···
4021
4004
return r;
4022
4005
}
4023
4006
4024
-
radeon_ring_unlock_commit(rdev, ring);
4007
+
radeon_ring_unlock_commit(rdev, ring, false);
4025
4008
radeon_semaphore_free(rdev, &sem, *fence);
4026
4009
4027
4010
return r;
···
4120
4103
ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
4121
4104
ib.ptr[2] = 0xDEADBEEF;
4122
4105
ib.length_dw = 3;
4123
-
r = radeon_ib_schedule(rdev, &ib, NULL);
4106
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
4124
4107
if (r) {
4125
4108
radeon_scratch_free(rdev, scratch);
4126
4109
radeon_ib_free(rdev, &ib);
···
4341
4324
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
4342
4325
radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
4343
4326
4344
-
radeon_ring_unlock_commit(rdev, ring);
4327
+
radeon_ring_unlock_commit(rdev, ring, false);
4345
4328
4346
4329
return 0;
4347
4330
}
···
5975
5958
5976
5959
/* update SH_MEM_* regs */
5977
5960
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5978
-
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5961
+
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5979
5962
WRITE_DATA_DST_SEL(0)));
5980
5963
radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5981
5964
radeon_ring_write(ring, 0);
5982
5965
radeon_ring_write(ring, VMID(vm->id));
5983
5966
5984
5967
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
5985
-
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5968
+
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5986
5969
WRITE_DATA_DST_SEL(0)));
5987
5970
radeon_ring_write(ring, SH_MEM_BASES >> 2);
5988
5971
radeon_ring_write(ring, 0);
···
5993
5976
radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
5994
5977
5995
5978
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5996
-
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5979
+
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
5997
5980
WRITE_DATA_DST_SEL(0)));
5998
5981
radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5999
5982
radeon_ring_write(ring, 0);
···
6004
5987
6005
5988
/* bits 0-15 are the VM contexts0-15 */
6006
5989
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6007
-
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5990
+
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6008
5991
WRITE_DATA_DST_SEL(0)));
6009
5992
radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
6010
5993
radeon_ring_write(ring, 0);
+3
-3
drivers/gpu/drm/radeon/cik_sdma.c
+3
-3
drivers/gpu/drm/radeon/cik_sdma.c
···
596
596
return r;
597
597
}
598
598
599
-
radeon_ring_unlock_commit(rdev, ring);
599
+
radeon_ring_unlock_commit(rdev, ring, false);
600
600
radeon_semaphore_free(rdev, &sem, *fence);
601
601
602
602
return r;
···
638
638
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
639
639
radeon_ring_write(ring, 1); /* number of DWs to follow */
640
640
radeon_ring_write(ring, 0xDEADBEEF);
641
-
radeon_ring_unlock_commit(rdev, ring);
641
+
radeon_ring_unlock_commit(rdev, ring, false);
642
642
643
643
for (i = 0; i < rdev->usec_timeout; i++) {
644
644
tmp = readl(ptr);
···
695
695
ib.ptr[4] = 0xDEADBEEF;
696
696
ib.length_dw = 5;
697
697
698
-
r = radeon_ib_schedule(rdev, &ib, NULL);
698
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
699
699
if (r) {
700
700
radeon_ib_free(rdev, &ib);
701
701
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
+2
-2
drivers/gpu/drm/radeon/evergreen.c
+2
-2
drivers/gpu/drm/radeon/evergreen.c
···
2869
2869
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2870
2870
radeon_ring_write(ring, 0);
2871
2871
radeon_ring_write(ring, 0);
2872
-
radeon_ring_unlock_commit(rdev, ring);
2872
+
radeon_ring_unlock_commit(rdev, ring, false);
2873
2873
2874
2874
cp_me = 0xff;
2875
2875
WREG32(CP_ME_CNTL, cp_me);
···
2912
2912
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2913
2913
radeon_ring_write(ring, 0x00000010); /* */
2914
2914
2915
-
radeon_ring_unlock_commit(rdev, ring);
2915
+
radeon_ring_unlock_commit(rdev, ring, false);
2916
2916
2917
2917
return 0;
2918
2918
}
+1
-1
drivers/gpu/drm/radeon/evergreen_dma.c
+1
-1
drivers/gpu/drm/radeon/evergreen_dma.c
+7
-4
drivers/gpu/drm/radeon/kv_dpm.c
+7
-4
drivers/gpu/drm/radeon/kv_dpm.c
···
1438
1438
return kv_enable_uvd_dpm(rdev, !gate);
1439
1439
}
1440
1440
1441
-
static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1441
+
static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)
1442
1442
{
1443
1443
u8 i;
1444
1444
struct radeon_vce_clock_voltage_dependency_table *table =
1445
1445
&rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1446
1446
1447
1447
for (i = 0; i < table->count; i++) {
1448
-
if (table->entries[i].evclk >= 0) /* XXX */
1448
+
if (table->entries[i].evclk >= evclk)
1449
1449
break;
1450
1450
}
1451
1451
···
1468
1468
if (pi->caps_stable_p_state)
1469
1469
pi->vce_boot_level = table->count - 1;
1470
1470
else
1471
-
pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1471
+
pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);
1472
1472
1473
1473
ret = kv_copy_bytes_to_smc(rdev,
1474
1474
pi->dpm_table_start +
···
2726
2726
pi->caps_sclk_ds = true;
2727
2727
pi->enable_auto_thermal_throttling = true;
2728
2728
pi->disable_nb_ps3_in_battery = false;
2729
-
pi->bapm_enable = true;
2729
+
if (radeon_bapm == 0)
2730
+
pi->bapm_enable = false;
2731
+
else
2732
+
pi->bapm_enable = true;
2730
2733
pi->voltage_drop_t = 0;
2731
2734
pi->caps_sclk_throttle_low_notification = false;
2732
2735
pi->caps_fps = false; /* true? */
+2
-2
drivers/gpu/drm/radeon/ni.c
+2
-2
drivers/gpu/drm/radeon/ni.c
···
1505
1505
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1506
1506
radeon_ring_write(ring, 0);
1507
1507
radeon_ring_write(ring, 0);
1508
-
radeon_ring_unlock_commit(rdev, ring);
1508
+
radeon_ring_unlock_commit(rdev, ring, false);
1509
1509
1510
1510
cayman_cp_enable(rdev, true);
1511
1511
···
1547
1547
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1548
1548
radeon_ring_write(ring, 0x00000010); /* */
1549
1549
1550
-
radeon_ring_unlock_commit(rdev, ring);
1550
+
radeon_ring_unlock_commit(rdev, ring, false);
1551
1551
1552
1552
/* XXX init other rings */
1553
1553
+4
-4
drivers/gpu/drm/radeon/r100.c
+4
-4
drivers/gpu/drm/radeon/r100.c
···
925
925
if (fence) {
926
926
r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
927
927
}
928
-
radeon_ring_unlock_commit(rdev, ring);
928
+
radeon_ring_unlock_commit(rdev, ring, false);
929
929
return r;
930
930
}
931
931
···
958
958
RADEON_ISYNC_ANY3D_IDLE2D |
959
959
RADEON_ISYNC_WAIT_IDLEGUI |
960
960
RADEON_ISYNC_CPSCRATCH_IDLEGUI);
961
-
radeon_ring_unlock_commit(rdev, ring);
961
+
radeon_ring_unlock_commit(rdev, ring, false);
962
962
}
963
963
964
964
···
3638
3638
}
3639
3639
radeon_ring_write(ring, PACKET0(scratch, 0));
3640
3640
radeon_ring_write(ring, 0xDEADBEEF);
3641
-
radeon_ring_unlock_commit(rdev, ring);
3641
+
radeon_ring_unlock_commit(rdev, ring, false);
3642
3642
for (i = 0; i < rdev->usec_timeout; i++) {
3643
3643
tmp = RREG32(scratch);
3644
3644
if (tmp == 0xDEADBEEF) {
···
3700
3700
ib.ptr[6] = PACKET2(0);
3701
3701
ib.ptr[7] = PACKET2(0);
3702
3702
ib.length_dw = 8;
3703
-
r = radeon_ib_schedule(rdev, &ib, NULL);
3703
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
3704
3704
if (r) {
3705
3705
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3706
3706
goto free_ib;
+1
-1
drivers/gpu/drm/radeon/r200.c
+1
-1
drivers/gpu/drm/radeon/r200.c
+1
-1
drivers/gpu/drm/radeon/r300.c
+1
-1
drivers/gpu/drm/radeon/r300.c
+2
-2
drivers/gpu/drm/radeon/r420.c
+2
-2
drivers/gpu/drm/radeon/r420.c
···
219
219
radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
220
220
radeon_ring_write(ring, rdev->config.r300.resync_scratch);
221
221
radeon_ring_write(ring, 0xDEADBEEF);
222
-
radeon_ring_unlock_commit(rdev, ring);
222
+
radeon_ring_unlock_commit(rdev, ring, false);
223
223
}
224
224
225
225
static void r420_cp_errata_fini(struct radeon_device *rdev)
···
232
232
radeon_ring_lock(rdev, ring, 8);
233
233
radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
234
234
radeon_ring_write(ring, R300_RB3D_DC_FINISH);
235
-
radeon_ring_unlock_commit(rdev, ring);
235
+
radeon_ring_unlock_commit(rdev, ring, false);
236
236
radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
237
237
}
238
238
+22
-4
drivers/gpu/drm/radeon/r600.c
+22
-4
drivers/gpu/drm/radeon/r600.c
···
2547
2547
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2548
2548
radeon_ring_write(ring, 0);
2549
2549
radeon_ring_write(ring, 0);
2550
-
radeon_ring_unlock_commit(rdev, ring);
2550
+
radeon_ring_unlock_commit(rdev, ring, false);
2551
2551
2552
2552
cp_me = 0xff;
2553
2553
WREG32(R_0086D8_CP_ME_CNTL, cp_me);
···
2683
2683
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2684
2684
radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2685
2685
radeon_ring_write(ring, 0xDEADBEEF);
2686
-
radeon_ring_unlock_commit(rdev, ring);
2686
+
radeon_ring_unlock_commit(rdev, ring, false);
2687
2687
for (i = 0; i < rdev->usec_timeout; i++) {
2688
2688
tmp = RREG32(scratch);
2689
2689
if (tmp == 0xDEADBEEF)
···
2753
2753
}
2754
2754
}
2755
2755
2756
+
/**
2757
+
* r600_semaphore_ring_emit - emit a semaphore on the CP ring
2758
+
*
2759
+
* @rdev: radeon_device pointer
2760
+
* @ring: radeon ring buffer object
2761
+
* @semaphore: radeon semaphore object
2762
+
* @emit_wait: Is this a sempahore wait?
2763
+
*
2764
+
* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2765
+
* from running ahead of semaphore waits.
2766
+
*/
2756
2767
bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2757
2768
struct radeon_ring *ring,
2758
2769
struct radeon_semaphore *semaphore,
···
2778
2767
radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2779
2768
radeon_ring_write(ring, lower_32_bits(addr));
2780
2769
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2770
+
2771
+
/* PFP_SYNC_ME packet only exists on 7xx+ */
2772
+
if (emit_wait && (rdev->family >= CHIP_RV770)) {
2773
+
/* Prevent the PFP from running ahead of the semaphore wait */
2774
+
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2775
+
radeon_ring_write(ring, 0x0);
2776
+
}
2781
2777
2782
2778
return true;
2783
2779
}
···
2863
2845
return r;
2864
2846
}
2865
2847
2866
-
radeon_ring_unlock_commit(rdev, ring);
2848
+
radeon_ring_unlock_commit(rdev, ring, false);
2867
2849
radeon_semaphore_free(rdev, &sem, *fence);
2868
2850
2869
2851
return r;
···
3183
3165
ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3184
3166
ib.ptr[2] = 0xDEADBEEF;
3185
3167
ib.length_dw = 3;
3186
-
r = radeon_ib_schedule(rdev, &ib, NULL);
3168
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
3187
3169
if (r) {
3188
3170
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3189
3171
goto free_ib;
+3
-3
drivers/gpu/drm/radeon/r600_dma.c
+3
-3
drivers/gpu/drm/radeon/r600_dma.c
···
261
261
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
262
262
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
263
263
radeon_ring_write(ring, 0xDEADBEEF);
264
-
radeon_ring_unlock_commit(rdev, ring);
264
+
radeon_ring_unlock_commit(rdev, ring, false);
265
265
266
266
for (i = 0; i < rdev->usec_timeout; i++) {
267
267
tmp = readl(ptr);
···
368
368
ib.ptr[3] = 0xDEADBEEF;
369
369
ib.length_dw = 4;
370
370
371
-
r = radeon_ib_schedule(rdev, &ib, NULL);
371
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
372
372
if (r) {
373
373
radeon_ib_free(rdev, &ib);
374
374
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
···
493
493
return r;
494
494
}
495
495
496
-
radeon_ring_unlock_commit(rdev, ring);
496
+
radeon_ring_unlock_commit(rdev, ring, false);
497
497
radeon_semaphore_free(rdev, &sem, *fence);
498
498
499
499
return r;
+1
drivers/gpu/drm/radeon/r600d.h
+1
drivers/gpu/drm/radeon/r600d.h
···
1597
1597
*/
1598
1598
# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1599
1599
# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1600
+
#define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */
1600
1601
#define PACKET3_SURFACE_SYNC 0x43
1601
1602
# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1602
1603
# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
+6
-3
drivers/gpu/drm/radeon/radeon.h
+6
-3
drivers/gpu/drm/radeon/radeon.h
···
105
105
extern int radeon_vm_block_size;
106
106
extern int radeon_deep_color;
107
107
extern int radeon_use_pflipirq;
108
+
extern int radeon_bapm;
108
109
109
110
/*
110
111
* Copy from radeon_drv.h so we don't have to include both and have conflicting
···
968
967
unsigned size);
969
968
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
970
969
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
971
-
struct radeon_ib *const_ib);
970
+
struct radeon_ib *const_ib, bool hdp_flush);
972
971
int radeon_ib_pool_init(struct radeon_device *rdev);
973
972
void radeon_ib_pool_fini(struct radeon_device *rdev);
974
973
int radeon_ib_ring_tests(struct radeon_device *rdev);
···
978
977
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
979
978
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
980
979
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
981
-
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
982
-
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
980
+
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
981
+
bool hdp_flush);
982
+
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
983
+
bool hdp_flush);
983
984
void radeon_ring_undo(struct radeon_ring *ring);
984
985
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
985
986
int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
+5
-4
drivers/gpu/drm/radeon/radeon_cs.c
+5
-4
drivers/gpu/drm/radeon/radeon_cs.c
···
132
132
* the buffers used for read only, which doubles the range
133
133
* to 0 to 31. 32 is reserved for the kernel driver.
134
134
*/
135
-
priority = (r->flags & 0xf) * 2 + !!r->write_domain;
135
+
priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
136
+
+ !!r->write_domain;
136
137
137
138
/* the first reloc of an UVD job is the msg and that must be in
138
139
VRAM, also but everything into VRAM on AGP cards to avoid
···
451
450
radeon_vce_note_usage(rdev);
452
451
453
452
radeon_cs_sync_rings(parser);
454
-
r = radeon_ib_schedule(rdev, &parser->ib, NULL);
453
+
r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
455
454
if (r) {
456
455
DRM_ERROR("Failed to schedule IB !\n");
457
456
}
···
542
541
543
542
if ((rdev->family >= CHIP_TAHITI) &&
544
543
(parser->chunk_const_ib_idx != -1)) {
545
-
r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
544
+
r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
546
545
} else {
547
-
r = radeon_ib_schedule(rdev, &parser->ib, NULL);
546
+
r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
548
547
}
549
548
550
549
out:
+32
-2
drivers/gpu/drm/radeon/radeon_device.c
+32
-2
drivers/gpu/drm/radeon/radeon_device.c
···
1680
1680
radeon_save_bios_scratch_regs(rdev);
1681
1681
/* block TTM */
1682
1682
resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1683
-
radeon_pm_suspend(rdev);
1684
1683
radeon_suspend(rdev);
1684
+
radeon_hpd_fini(rdev);
1685
1685
1686
1686
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1687
1687
ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
···
1726
1726
}
1727
1727
}
1728
1728
1729
-
radeon_pm_resume(rdev);
1729
+
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1730
+
/* do dpm late init */
1731
+
r = radeon_pm_late_init(rdev);
1732
+
if (r) {
1733
+
rdev->pm.dpm_enabled = false;
1734
+
DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1735
+
}
1736
+
} else {
1737
+
/* resume old pm late */
1738
+
radeon_pm_resume(rdev);
1739
+
}
1740
+
1741
+
/* init dig PHYs, disp eng pll */
1742
+
if (rdev->is_atom_bios) {
1743
+
radeon_atom_encoder_init(rdev);
1744
+
radeon_atom_disp_eng_pll_init(rdev);
1745
+
/* turn on the BL */
1746
+
if (rdev->mode_info.bl_encoder) {
1747
+
u8 bl_level = radeon_get_backlight_level(rdev,
1748
+
rdev->mode_info.bl_encoder);
1749
+
radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1750
+
bl_level);
1751
+
}
1752
+
}
1753
+
/* reset hpd state */
1754
+
radeon_hpd_init(rdev);
1755
+
1730
1756
drm_helper_resume_force_mode(rdev->ddev);
1757
+
1758
+
/* set the power state here in case we are a PX system or headless */
1759
+
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1760
+
radeon_pm_compute_clocks(rdev);
1731
1761
1732
1762
ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1733
1763
if (r) {
+4
drivers/gpu/drm/radeon/radeon_drv.c
+4
drivers/gpu/drm/radeon/radeon_drv.c
···
180
180
int radeon_vm_block_size = -1;
181
181
int radeon_deep_color = 0;
182
182
int radeon_use_pflipirq = 2;
183
+
int radeon_bapm = -1;
183
184
184
185
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
185
186
module_param_named(no_wb, radeon_no_wb, int, 0444);
···
259
258
260
259
MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
261
260
module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
261
+
262
+
MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
263
+
module_param_named(bapm, radeon_bapm, int, 0444);
262
264
263
265
static struct pci_device_id pciidlist[] = {
264
266
radeon_PCI_IDS
+3
-2
drivers/gpu/drm/radeon/radeon_ib.c
+3
-2
drivers/gpu/drm/radeon/radeon_ib.c
···
107
107
* @rdev: radeon_device pointer
108
108
* @ib: IB object to schedule
109
109
* @const_ib: Const IB to schedule (SI only)
110
+
* @hdp_flush: Whether or not to perform an HDP cache flush
110
111
*
111
112
* Schedule an IB on the associated ring (all asics).
112
113
* Returns 0 on success, error on failure.
···
123
122
* to SI there was just a DE IB.
124
123
*/
125
124
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
126
-
struct radeon_ib *const_ib)
125
+
struct radeon_ib *const_ib, bool hdp_flush)
127
126
{
128
127
struct radeon_ring *ring = &rdev->ring[ib->ring];
129
128
int r = 0;
···
177
176
if (ib->vm)
178
177
radeon_vm_fence(rdev, ib->vm, ib->fence);
179
178
180
-
radeon_ring_unlock_commit(rdev, ring);
179
+
radeon_ring_unlock_commit(rdev, ring, hdp_flush);
181
180
return 0;
182
181
}
183
182
+6
-10
drivers/gpu/drm/radeon/radeon_pm.c
+6
-10
drivers/gpu/drm/radeon/radeon_pm.c
···
460
460
struct radeon_device *rdev = ddev->dev_private;
461
461
enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
462
462
463
-
if ((rdev->flags & RADEON_IS_PX) &&
464
-
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
465
-
return snprintf(buf, PAGE_SIZE, "off\n");
466
-
467
463
return snprintf(buf, PAGE_SIZE, "%s\n",
468
464
(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
469
465
(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
···
472
476
{
473
477
struct drm_device *ddev = dev_get_drvdata(dev);
474
478
struct radeon_device *rdev = ddev->dev_private;
475
-
476
-
/* Can't set dpm state when the card is off */
477
-
if ((rdev->flags & RADEON_IS_PX) &&
478
-
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
479
-
return -EINVAL;
480
479
481
480
mutex_lock(&rdev->pm.mutex);
482
481
if (strncmp("battery", buf, strlen("battery")) == 0)
···
486
495
goto fail;
487
496
}
488
497
mutex_unlock(&rdev->pm.mutex);
489
-
radeon_pm_compute_clocks(rdev);
498
+
499
+
/* Can't set dpm state when the card is off */
500
+
if (!(rdev->flags & RADEON_IS_PX) ||
501
+
(ddev->switch_power_state == DRM_SWITCH_POWER_ON))
502
+
radeon_pm_compute_clocks(rdev);
503
+
490
504
fail:
491
505
return count;
492
506
}
+11
-9
drivers/gpu/drm/radeon/radeon_ring.c
+11
-9
drivers/gpu/drm/radeon/radeon_ring.c
···
177
177
*
178
178
* @rdev: radeon_device pointer
179
179
* @ring: radeon_ring structure holding ring information
180
+
* @hdp_flush: Whether or not to perform an HDP cache flush
180
181
*
181
182
* Update the wptr (write pointer) to tell the GPU to
182
183
* execute new commands on the ring buffer (all asics).
183
184
*/
184
-
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
185
+
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
186
+
bool hdp_flush)
185
187
{
186
188
/* If we are emitting the HDP flush via the ring buffer, we need to
187
189
* do it before padding.
188
190
*/
189
-
if (rdev->asic->ring[ring->idx]->hdp_flush)
191
+
if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
190
192
rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
191
193
/* We pad to match fetch size */
192
194
while (ring->wptr & ring->align_mask) {
···
198
196
/* If we are emitting the HDP flush via MMIO, we need to do it after
199
197
* all CPU writes to VRAM finished.
200
198
*/
201
-
if (rdev->asic->mmio_hdp_flush)
199
+
if (hdp_flush && rdev->asic->mmio_hdp_flush)
202
200
rdev->asic->mmio_hdp_flush(rdev);
203
201
radeon_ring_set_wptr(rdev, ring);
204
202
}
···
209
207
*
210
208
* @rdev: radeon_device pointer
211
209
* @ring: radeon_ring structure holding ring information
210
+
* @hdp_flush: Whether or not to perform an HDP cache flush
212
211
*
213
212
* Call radeon_ring_commit() then unlock the ring (all asics).
214
213
*/
215
-
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
214
+
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
215
+
bool hdp_flush)
216
216
{
217
-
radeon_ring_commit(rdev, ring);
217
+
radeon_ring_commit(rdev, ring, hdp_flush);
218
218
mutex_unlock(&rdev->ring_lock);
219
219
}
220
220
···
376
372
radeon_ring_write(ring, data[i]);
377
373
}
378
374
379
-
radeon_ring_unlock_commit(rdev, ring);
375
+
radeon_ring_unlock_commit(rdev, ring, false);
380
376
kfree(data);
381
377
return 0;
382
378
}
···
404
400
/* Allocate ring buffer */
405
401
if (ring->ring_obj == NULL) {
406
402
r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
407
-
RADEON_GEM_DOMAIN_GTT,
408
-
(rdev->flags & RADEON_IS_PCIE) ?
409
-
RADEON_GEM_GTT_WC : 0,
403
+
RADEON_GEM_DOMAIN_GTT, 0,
410
404
NULL, &ring->ring_obj);
411
405
if (r) {
412
406
dev_err(rdev->dev, "(%d) ring create failed\n", r);
+1
-1
drivers/gpu/drm/radeon/radeon_semaphore.c
+1
-1
drivers/gpu/drm/radeon/radeon_semaphore.c
+9
-9
drivers/gpu/drm/radeon/radeon_test.c
+9
-9
drivers/gpu/drm/radeon/radeon_test.c
···
288
288
return r;
289
289
}
290
290
radeon_fence_emit(rdev, fence, ring->idx);
291
-
radeon_ring_unlock_commit(rdev, ring);
291
+
radeon_ring_unlock_commit(rdev, ring, false);
292
292
}
293
293
return 0;
294
294
}
···
313
313
goto out_cleanup;
314
314
}
315
315
radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
316
-
radeon_ring_unlock_commit(rdev, ringA);
316
+
radeon_ring_unlock_commit(rdev, ringA, false);
317
317
318
318
r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
319
319
if (r)
···
325
325
goto out_cleanup;
326
326
}
327
327
radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
328
-
radeon_ring_unlock_commit(rdev, ringA);
328
+
radeon_ring_unlock_commit(rdev, ringA, false);
329
329
330
330
r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
331
331
if (r)
···
344
344
goto out_cleanup;
345
345
}
346
346
radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
347
-
radeon_ring_unlock_commit(rdev, ringB);
347
+
radeon_ring_unlock_commit(rdev, ringB, false);
348
348
349
349
r = radeon_fence_wait(fence1, false);
350
350
if (r) {
···
365
365
goto out_cleanup;
366
366
}
367
367
radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
368
-
radeon_ring_unlock_commit(rdev, ringB);
368
+
radeon_ring_unlock_commit(rdev, ringB, false);
369
369
370
370
r = radeon_fence_wait(fence2, false);
371
371
if (r) {
···
408
408
goto out_cleanup;
409
409
}
410
410
radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
411
-
radeon_ring_unlock_commit(rdev, ringA);
411
+
radeon_ring_unlock_commit(rdev, ringA, false);
412
412
413
413
r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
414
414
if (r)
···
420
420
goto out_cleanup;
421
421
}
422
422
radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
423
-
radeon_ring_unlock_commit(rdev, ringB);
423
+
radeon_ring_unlock_commit(rdev, ringB, false);
424
424
r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
425
425
if (r)
426
426
goto out_cleanup;
···
442
442
goto out_cleanup;
443
443
}
444
444
radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
445
-
radeon_ring_unlock_commit(rdev, ringC);
445
+
radeon_ring_unlock_commit(rdev, ringC, false);
446
446
447
447
for (i = 0; i < 30; ++i) {
448
448
mdelay(100);
···
468
468
goto out_cleanup;
469
469
}
470
470
radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
471
-
radeon_ring_unlock_commit(rdev, ringC);
471
+
radeon_ring_unlock_commit(rdev, ringC, false);
472
472
473
473
mdelay(1000);
474
474
+1
-1
drivers/gpu/drm/radeon/radeon_uvd.c
+1
-1
drivers/gpu/drm/radeon/radeon_uvd.c
+3
-3
drivers/gpu/drm/radeon/radeon_vce.c
+3
-3
drivers/gpu/drm/radeon/radeon_vce.c
···
368
368
for (i = ib.length_dw; i < ib_size_dw; ++i)
369
369
ib.ptr[i] = 0x0;
370
370
371
-
r = radeon_ib_schedule(rdev, &ib, NULL);
371
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
372
372
if (r) {
373
373
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
374
374
}
···
425
425
for (i = ib.length_dw; i < ib_size_dw; ++i)
426
426
ib.ptr[i] = 0x0;
427
427
428
-
r = radeon_ib_schedule(rdev, &ib, NULL);
428
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
429
429
if (r) {
430
430
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
431
431
}
···
715
715
return r;
716
716
}
717
717
radeon_ring_write(ring, VCE_CMD_END);
718
-
radeon_ring_unlock_commit(rdev, ring);
718
+
radeon_ring_unlock_commit(rdev, ring, false);
719
719
720
720
for (i = 0; i < rdev->usec_timeout; i++) {
721
721
if (vce_v1_0_get_rptr(rdev, ring) != rptr)
+7
-3
drivers/gpu/drm/radeon/radeon_vm.c
+7
-3
drivers/gpu/drm/radeon/radeon_vm.c
···
420
420
radeon_asic_vm_pad_ib(rdev, &ib);
421
421
WARN_ON(ib.length_dw > 64);
422
422
423
-
r = radeon_ib_schedule(rdev, &ib, NULL);
423
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
424
424
if (r)
425
425
goto error;
426
426
···
483
483
/* add a clone of the bo_va to clear the old address */
484
484
struct radeon_bo_va *tmp;
485
485
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
486
+
if (!tmp) {
487
+
mutex_unlock(&vm->mutex);
488
+
return -ENOMEM;
489
+
}
486
490
tmp->it.start = bo_va->it.start;
487
491
tmp->it.last = bo_va->it.last;
488
492
tmp->vm = vm;
···
697
693
radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
698
694
radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
699
695
WARN_ON(ib.length_dw > ndw);
700
-
r = radeon_ib_schedule(rdev, &ib, NULL);
696
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
701
697
if (r) {
702
698
radeon_ib_free(rdev, &ib);
703
699
return r;
···
961
957
WARN_ON(ib.length_dw > ndw);
962
958
963
959
radeon_semaphore_sync_to(ib.semaphore, vm->fence);
964
-
r = radeon_ib_schedule(rdev, &ib, NULL);
960
+
r = radeon_ib_schedule(rdev, &ib, NULL, false);
965
961
if (r) {
966
962
radeon_ib_free(rdev, &ib);
967
963
return r;
+1
-1
drivers/gpu/drm/radeon/rv515.c
+1
-1
drivers/gpu/drm/radeon/rv515.c
···
124
124
radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
125
125
radeon_ring_write(ring, PACKET0(0x20C8, 0));
126
126
radeon_ring_write(ring, 0);
127
-
radeon_ring_unlock_commit(rdev, ring);
127
+
radeon_ring_unlock_commit(rdev, ring, false);
128
128
}
129
129
130
130
int rv515_mc_wait_for_idle(struct radeon_device *rdev)
+1
-1
drivers/gpu/drm/radeon/rv770_dma.c
+1
-1
drivers/gpu/drm/radeon/rv770_dma.c
+9
-10
drivers/gpu/drm/radeon/si.c
+9
-10
drivers/gpu/drm/radeon/si.c
···
3057
3057
u32 sx_debug_1;
3058
3058
u32 hdp_host_path_cntl;
3059
3059
u32 tmp;
3060
-
int i, j, k;
3060
+
int i, j;
3061
3061
3062
3062
switch (rdev->family) {
3063
3063
case CHIP_TAHITI:
···
3255
3255
rdev->config.si.max_sh_per_se,
3256
3256
rdev->config.si.max_cu_per_sh);
3257
3257
3258
+
rdev->config.si.active_cus = 0;
3258
3259
for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3259
3260
for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3260
-
for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
3261
-
rdev->config.si.active_cus +=
3262
-
hweight32(si_get_cu_active_bitmap(rdev, i, j));
3263
-
}
3261
+
rdev->config.si.active_cus +=
3262
+
hweight32(si_get_cu_active_bitmap(rdev, i, j));
3264
3263
}
3265
3264
}
3266
3265
···
3540
3541
radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3541
3542
radeon_ring_write(ring, 0xc000);
3542
3543
radeon_ring_write(ring, 0xe000);
3543
-
radeon_ring_unlock_commit(rdev, ring);
3544
+
radeon_ring_unlock_commit(rdev, ring, false);
3544
3545
3545
3546
si_cp_enable(rdev, true);
3546
3547
···
3569
3570
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3570
3571
radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3571
3572
3572
-
radeon_ring_unlock_commit(rdev, ring);
3573
+
radeon_ring_unlock_commit(rdev, ring, false);
3573
3574
3574
3575
for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3575
3576
ring = &rdev->ring[i];
···
3579
3580
radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3580
3581
radeon_ring_write(ring, 0);
3581
3582
3582
-
radeon_ring_unlock_commit(rdev, ring);
3583
+
radeon_ring_unlock_commit(rdev, ring, false);
3583
3584
}
3584
3585
3585
3586
return 0;
···
5027
5028
5028
5029
/* flush hdp cache */
5029
5030
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5030
-
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5031
+
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5031
5032
WRITE_DATA_DST_SEL(0)));
5032
5033
radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5033
5034
radeon_ring_write(ring, 0);
···
5035
5036
5036
5037
/* bits 0-15 are the VM contexts0-15 */
5037
5038
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5038
-
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5039
+
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5039
5040
WRITE_DATA_DST_SEL(0)));
5040
5041
radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5041
5042
radeon_ring_write(ring, 0);
+1
-1
drivers/gpu/drm/radeon/si_dma.c
+1
-1
drivers/gpu/drm/radeon/si_dma.c
+15
-9
drivers/gpu/drm/radeon/trinity_dpm.c
+15
-9
drivers/gpu/drm/radeon/trinity_dpm.c
···
1874
1874
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
1875
1875
pi->at[i] = TRINITY_AT_DFLT;
1876
1876
1877
-
/* There are stability issues reported on with
1878
-
* bapm enabled when switching between AC and battery
1879
-
* power. At the same time, some MSI boards hang
1880
-
* if it's not enabled and dpm is enabled. Just enable
1881
-
* it for MSI boards right now.
1882
-
*/
1883
-
if (rdev->pdev->subsystem_vendor == 0x1462)
1884
-
pi->enable_bapm = true;
1885
-
else
1877
+
if (radeon_bapm == -1) {
1878
+
/* There are stability issues reported on with
1879
+
* bapm enabled when switching between AC and battery
1880
+
* power. At the same time, some MSI boards hang
1881
+
* if it's not enabled and dpm is enabled. Just enable
1882
+
* it for MSI boards right now.
1883
+
*/
1884
+
if (rdev->pdev->subsystem_vendor == 0x1462)
1885
+
pi->enable_bapm = true;
1886
+
else
1887
+
pi->enable_bapm = false;
1888
+
} else if (radeon_bapm == 0) {
1886
1889
pi->enable_bapm = false;
1890
+
} else {
1891
+
pi->enable_bapm = true;
1892
+
}
1887
1893
pi->enable_nbps_policy = true;
1888
1894
pi->enable_sclk_ds = true;
1889
1895
pi->enable_gfx_power_gating = true;
+2
-2
drivers/gpu/drm/radeon/uvd_v1_0.c
+2
-2
drivers/gpu/drm/radeon/uvd_v1_0.c
···
124
124
radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
125
125
radeon_ring_write(ring, 3);
126
126
127
-
radeon_ring_unlock_commit(rdev, ring);
127
+
radeon_ring_unlock_commit(rdev, ring, false);
128
128
129
129
done:
130
130
/* lower clocks again */
···
331
331
}
332
332
radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
333
333
radeon_ring_write(ring, 0xDEADBEEF);
334
-
radeon_ring_unlock_commit(rdev, ring);
334
+
radeon_ring_unlock_commit(rdev, ring, false);
335
335
for (i = 0; i < rdev->usec_timeout; i++) {
336
336
tmp = RREG32(UVD_CONTEXT_ID);
337
337
if (tmp == 0xDEADBEEF)
+7
include/drm/drm_pciids.h
+7
include/drm/drm_pciids.h
···
17
17
{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
18
18
{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
19
19
{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
20
+
{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
20
21
{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
21
22
{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
22
23
{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
···
165
164
{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
166
165
{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
167
166
{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
167
+
{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
168
+
{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
168
169
{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
169
170
{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
171
+
{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
170
172
{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
171
173
{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
172
174
{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
···
179
175
{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
180
176
{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
181
177
{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
178
+
{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
179
+
{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
182
180
{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
183
181
{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
184
182
{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
···
303
297
{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
304
298
{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
305
299
{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
300
+
{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
306
301
{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
307
302
{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
308
303
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \