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RDMA/hns: Fix wrong timer context buffer page size

The HEM page size for QPC timer and CQC timer is always 4K and there's no
need to calculate a different size by the hns driver, otherwise the ROCEE
may access an invalid address.

Fixes: 719d13415f59 ("RDMA/hns: Remove duplicated hem page size config code")
Link: https://lore.kernel.org/r/1621589395-2435-4-git-send-email-liweihang@huawei.com
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

authored by

Xi Wang and committed by
Jason Gunthorpe 5e6370d7 1f704d8c

-6
-6
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
··· 2057 2057 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2058 2058 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2059 2059 2060 - if (caps->cqc_timer_entry_sz) 2061 - calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz, 2062 - caps->cqc_timer_hop_num, caps->cqc_timer_bt_num, 2063 - &caps->cqc_timer_buf_pg_sz, 2064 - &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER); 2065 - 2066 2060 /* SRQ */ 2067 2061 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2068 2062 caps->srqc_ba_pg_sz = 0;