Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"There are a lot of minor DT fixes for Mediatek, Rockchip, Qualcomm and
Microchip and NXP, addressing both build-time warnings and bugs found
during runtime testing.
Most of these changes are machine specific fixups, but there are a few
notable regressions that affect an entire SoC:
- The Qualcomm MSI support that was improved for 6.9 ended up being
wrong on some chips and now gets fixed.
- The i.MX8MP camera interface broke due to a typo and gets updated
again.
The main driver fix is also for Qualcomm platforms, rewriting an
interface in the QSEECOM firmware support that could lead to crashing
the kernel from a trusted application.
The only other code changes are minor fixes for Mediatek SoC drivers"
* tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (50 commits)
ARM: dts: imx6ull-tarragon: fix USB over-current polarity
soc: mediatek: mtk-socinfo: depends on CONFIG_SOC_BUS
soc: mediatek: mtk-svs: Append "-thermal" to thermal zone names
arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
arm64: dts: qcom: sm8650: Fix the msi-map entries
arm64: dts: qcom: sm8550: Fix the msi-map entries
arm64: dts: qcom: sm8450: Fix the msi-map entries
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus
...
+331
-193
+1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+4
-4
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
+4
-4
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
···
242
242
243
243
regulator-state-standby {
244
244
regulator-on-in-suspend;
245
-
regulator-suspend-voltage = <1150000>;
245
+
regulator-suspend-microvolt = <1150000>;
246
246
regulator-mode = <4>;
247
247
};
248
248
···
263
263
264
264
regulator-state-standby {
265
265
regulator-on-in-suspend;
266
-
regulator-suspend-voltage = <1050000>;
266
+
regulator-suspend-microvolt = <1050000>;
267
267
regulator-mode = <4>;
268
268
};
269
269
···
280
280
regulator-always-on;
281
281
282
282
regulator-state-standby {
283
-
regulator-suspend-voltage = <1800000>;
283
+
regulator-suspend-microvolt = <1800000>;
284
284
regulator-on-in-suspend;
285
285
};
286
286
···
296
296
regulator-always-on;
297
297
298
298
regulator-state-standby {
299
-
regulator-suspend-voltage = <3300000>;
299
+
regulator-suspend-microvolt = <3300000>;
300
300
regulator-on-in-suspend;
301
301
};
302
302
+4
-4
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
+4
-4
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
···
293
293
294
294
regulator-state-standby {
295
295
regulator-on-in-suspend;
296
-
regulator-suspend-voltage = <1150000>;
296
+
regulator-suspend-microvolt = <1150000>;
297
297
regulator-mode = <4>;
298
298
};
299
299
···
314
314
315
315
regulator-state-standby {
316
316
regulator-on-in-suspend;
317
-
regulator-suspend-voltage = <1050000>;
317
+
regulator-suspend-microvolt = <1050000>;
318
318
regulator-mode = <4>;
319
319
};
320
320
···
331
331
regulator-always-on;
332
332
333
333
regulator-state-standby {
334
-
regulator-suspend-voltage = <1800000>;
334
+
regulator-suspend-microvolt = <1800000>;
335
335
regulator-on-in-suspend;
336
336
};
337
337
···
346
346
regulator-max-microvolt = <3700000>;
347
347
348
348
regulator-state-standby {
349
-
regulator-suspend-voltage = <1800000>;
349
+
regulator-suspend-microvolt = <1800000>;
350
350
regulator-on-in-suspend;
351
351
};
352
352
+1
arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+1
arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mp.dtsi
···
1672
1672
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1673
1673
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1674
1674
clock-names = "pclk", "wrap", "phy", "axi";
1675
-
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1675
+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1676
1676
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1677
1677
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1678
1678
<&clk IMX8MP_CLK_24M>;
+4
-4
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+4
-4
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
···
129
129
};
130
130
131
131
&pio {
132
-
eth_default: eth_default {
132
+
eth_default: eth-default-pins {
133
133
tx_pins {
134
134
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
135
135
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
···
156
156
};
157
157
};
158
158
159
-
eth_sleep: eth_sleep {
159
+
eth_sleep: eth-sleep-pins {
160
160
tx_pins {
161
161
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
162
162
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
···
182
182
};
183
183
};
184
184
185
-
usb0_id_pins_float: usb0_iddig {
185
+
usb0_id_pins_float: usb0-iddig-pins {
186
186
pins_iddig {
187
187
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
188
188
bias-pull-up;
189
189
};
190
190
};
191
191
192
-
usb1_id_pins_float: usb1_iddig {
192
+
usb1_id_pins_float: usb1-iddig-pins {
193
193
pins_iddig {
194
194
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
195
195
bias-pull-up;
+2
-1
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+2
-1
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
···
249
249
#clock-cells = <1>;
250
250
};
251
251
252
-
infracfg: syscon@10001000 {
252
+
infracfg: clock-controller@10001000 {
253
253
compatible = "mediatek,mt2712-infracfg", "syscon";
254
254
reg = <0 0x10001000 0 0x1000>;
255
255
#clock-cells = <1>;
256
+
#reset-cells = <1>;
256
257
};
257
258
258
259
pericfg: syscon@10003000 {
+14
-20
arch/arm64/boot/dts/mediatek/mt7622.dtsi
+14
-20
arch/arm64/boot/dts/mediatek/mt7622.dtsi
···
252
252
clock-names = "hif_sel";
253
253
};
254
254
255
-
cir: cir@10009000 {
255
+
cir: ir-receiver@10009000 {
256
256
compatible = "mediatek,mt7622-cir";
257
257
reg = <0 0x10009000 0 0x1000>;
258
258
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
···
283
283
};
284
284
};
285
285
286
-
apmixedsys: apmixedsys@10209000 {
287
-
compatible = "mediatek,mt7622-apmixedsys",
288
-
"syscon";
286
+
apmixedsys: clock-controller@10209000 {
287
+
compatible = "mediatek,mt7622-apmixedsys";
289
288
reg = <0 0x10209000 0 0x1000>;
290
289
#clock-cells = <1>;
291
290
};
292
291
293
-
topckgen: topckgen@10210000 {
294
-
compatible = "mediatek,mt7622-topckgen",
295
-
"syscon";
292
+
topckgen: clock-controller@10210000 {
293
+
compatible = "mediatek,mt7622-topckgen";
296
294
reg = <0 0x10210000 0 0x1000>;
297
295
#clock-cells = <1>;
298
296
};
···
513
515
<&pericfg CLK_PERI_AUXADC_PD>;
514
516
clock-names = "therm", "auxadc";
515
517
resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
516
-
reset-names = "therm";
517
518
mediatek,auxadc = <&auxadc>;
518
519
mediatek,apmixedsys = <&apmixedsys>;
519
520
nvmem-cells = <&thermal_calibration>;
···
731
734
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
732
735
};
733
736
734
-
ssusbsys: ssusbsys@1a000000 {
735
-
compatible = "mediatek,mt7622-ssusbsys",
736
-
"syscon";
737
+
ssusbsys: clock-controller@1a000000 {
738
+
compatible = "mediatek,mt7622-ssusbsys";
737
739
reg = <0 0x1a000000 0 0x1000>;
738
740
#clock-cells = <1>;
739
741
#reset-cells = <1>;
···
789
793
};
790
794
};
791
795
792
-
pciesys: pciesys@1a100800 {
793
-
compatible = "mediatek,mt7622-pciesys",
794
-
"syscon";
796
+
pciesys: clock-controller@1a100800 {
797
+
compatible = "mediatek,mt7622-pciesys";
795
798
reg = <0 0x1a100800 0 0x1000>;
796
799
#clock-cells = <1>;
797
800
#reset-cells = <1>;
···
916
921
};
917
922
};
918
923
919
-
hifsys: syscon@1af00000 {
920
-
compatible = "mediatek,mt7622-hifsys", "syscon";
924
+
hifsys: clock-controller@1af00000 {
925
+
compatible = "mediatek,mt7622-hifsys";
921
926
reg = <0 0x1af00000 0 0x70>;
927
+
#clock-cells = <1>;
922
928
};
923
929
924
-
ethsys: syscon@1b000000 {
930
+
ethsys: clock-controller@1b000000 {
925
931
compatible = "mediatek,mt7622-ethsys",
926
932
"syscon";
927
933
reg = <0 0x1b000000 0 0x1000>;
···
962
966
};
963
967
964
968
eth: ethernet@1b100000 {
965
-
compatible = "mediatek,mt7622-eth",
966
-
"mediatek,mt2701-eth",
967
-
"syscon";
969
+
compatible = "mediatek,mt7622-eth";
968
970
reg = <0 0x1b100000 0 0x20000>;
969
971
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
970
972
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
+3
-3
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+3
-3
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
···
146
146
147
147
&cpu_thermal {
148
148
cooling-maps {
149
-
cpu-active-high {
149
+
map-cpu-active-high {
150
150
/* active: set fan to cooling level 2 */
151
151
cooling-device = <&fan 2 2>;
152
152
trip = <&cpu_trip_active_high>;
153
153
};
154
154
155
-
cpu-active-med {
155
+
map-cpu-active-med {
156
156
/* active: set fan to cooling level 1 */
157
157
cooling-device = <&fan 1 1>;
158
158
trip = <&cpu_trip_active_med>;
159
159
};
160
160
161
-
cpu-active-low {
161
+
map-cpu-active-low {
162
162
/* active: set fan to cooling level 0 */
163
163
cooling-device = <&fan 0 0>;
164
164
trip = <&cpu_trip_active_low>;
+2
-6
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+2
-6
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
···
332
332
reg = <0 0x1100c800 0 0x800>;
333
333
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
334
334
clocks = <&infracfg CLK_INFRA_THERM_CK>,
335
-
<&infracfg CLK_INFRA_ADC_26M_CK>,
336
-
<&infracfg CLK_INFRA_ADC_FRC_CK>;
337
-
clock-names = "therm", "auxadc", "adc_32k";
335
+
<&infracfg CLK_INFRA_ADC_26M_CK>;
336
+
clock-names = "therm", "auxadc";
338
337
nvmem-cells = <&thermal_calibration>;
339
338
nvmem-cell-names = "calibration-data";
340
339
#thermal-sensor-cells = <1>;
···
491
492
compatible = "mediatek,mt7986-ethsys",
492
493
"syscon";
493
494
reg = <0 0x15000000 0 0x1000>;
494
-
#address-cells = <1>;
495
-
#size-cells = <1>;
496
495
#clock-cells = <1>;
497
496
#reset-cells = <1>;
498
497
};
···
553
556
<&topckgen CLK_TOP_SGM_325M_SEL>;
554
557
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
555
558
<&apmixedsys CLK_APMIXED_SGMPLL>;
556
-
#reset-cells = <1>;
557
559
#address-cells = <1>;
558
560
#size-cells = <0>;
559
561
mediatek,ethsys = <ðsys>;
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
-1
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+1
arch/arm64/boot/dts/mediatek/mt8183.dtsi
+1
arch/arm64/boot/dts/mediatek/mt8183.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+1
-1
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
···
1296
1296
* regulator coupling requirements.
1297
1297
*/
1298
1298
regulator-name = "ppvar_dvdd_vgpu";
1299
-
regulator-min-microvolt = <600000>;
1299
+
regulator-min-microvolt = <500000>;
1300
1300
regulator-max-microvolt = <950000>;
1301
1301
regulator-ramp-delay = <6250>;
1302
1302
regulator-enable-ramp-delay = <200>;
+3
-3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+3
-3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
···
1421
1421
mt6315_6_vbuck1: vbuck1 {
1422
1422
regulator-compatible = "vbuck1";
1423
1423
regulator-name = "Vbcpu";
1424
-
regulator-min-microvolt = <300000>;
1424
+
regulator-min-microvolt = <400000>;
1425
1425
regulator-max-microvolt = <1193750>;
1426
1426
regulator-enable-ramp-delay = <256>;
1427
1427
regulator-allowed-modes = <0 1 2>;
···
1431
1431
mt6315_6_vbuck3: vbuck3 {
1432
1432
regulator-compatible = "vbuck3";
1433
1433
regulator-name = "Vlcpu";
1434
-
regulator-min-microvolt = <300000>;
1434
+
regulator-min-microvolt = <400000>;
1435
1435
regulator-max-microvolt = <1193750>;
1436
1436
regulator-enable-ramp-delay = <256>;
1437
1437
regulator-allowed-modes = <0 1 2>;
···
1448
1448
mt6315_7_vbuck1: vbuck1 {
1449
1449
regulator-compatible = "vbuck1";
1450
1450
regulator-name = "Vgpu";
1451
-
regulator-min-microvolt = <606250>;
1451
+
regulator-min-microvolt = <400000>;
1452
1452
regulator-max-microvolt = <800000>;
1453
1453
regulator-enable-ramp-delay = <256>;
1454
1454
regulator-allowed-modes = <0 1 2>;
+1
arch/arm64/boot/dts/mediatek/mt8192.dtsi
+1
arch/arm64/boot/dts/mediatek/mt8192.dtsi
···
1464
1464
reg = <0 0x14001000 0 0x1000>;
1465
1465
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1466
1466
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1467
+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1467
1468
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1468
1469
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1469
1470
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+34
-2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+34
-2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
···
264
264
status = "okay";
265
265
};
266
266
267
+
&cpu0 {
268
+
cpu-supply = <&mt6359_vcore_buck_reg>;
269
+
};
270
+
271
+
&cpu1 {
272
+
cpu-supply = <&mt6359_vcore_buck_reg>;
273
+
};
274
+
275
+
&cpu2 {
276
+
cpu-supply = <&mt6359_vcore_buck_reg>;
277
+
};
278
+
279
+
&cpu3 {
280
+
cpu-supply = <&mt6359_vcore_buck_reg>;
281
+
};
282
+
283
+
&cpu4 {
284
+
cpu-supply = <&mt6315_6_vbuck1>;
285
+
};
286
+
287
+
&cpu5 {
288
+
cpu-supply = <&mt6315_6_vbuck1>;
289
+
};
290
+
291
+
&cpu6 {
292
+
cpu-supply = <&mt6315_6_vbuck1>;
293
+
};
294
+
295
+
&cpu7 {
296
+
cpu-supply = <&mt6315_6_vbuck1>;
297
+
};
298
+
267
299
&dp_intf0 {
268
300
status = "okay";
269
301
···
1246
1214
mt6315_6_vbuck1: vbuck1 {
1247
1215
regulator-compatible = "vbuck1";
1248
1216
regulator-name = "Vbcpu";
1249
-
regulator-min-microvolt = <300000>;
1217
+
regulator-min-microvolt = <400000>;
1250
1218
regulator-max-microvolt = <1193750>;
1251
1219
regulator-enable-ramp-delay = <256>;
1252
1220
regulator-ramp-delay = <6250>;
···
1264
1232
mt6315_7_vbuck1: vbuck1 {
1265
1233
regulator-compatible = "vbuck1";
1266
1234
regulator-name = "Vgpu";
1267
-
regulator-min-microvolt = <625000>;
1235
+
regulator-min-microvolt = <400000>;
1268
1236
regulator-max-microvolt = <1193750>;
1269
1237
regulator-enable-ramp-delay = <256>;
1270
1238
regulator-ramp-delay = <6250>;
+5
arch/arm64/boot/dts/mediatek/mt8195.dtsi
+5
arch/arm64/boot/dts/mediatek/mt8195.dtsi
···
2028
2028
compatible = "mediatek,mt8195-vppsys0", "syscon";
2029
2029
reg = <0 0x14000000 0 0x1000>;
2030
2030
#clock-cells = <1>;
2031
+
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2031
2032
};
2032
2033
2033
2034
dma-controller@14001000 {
···
2252
2251
compatible = "mediatek,mt8195-vppsys1", "syscon";
2253
2252
reg = <0 0x14f00000 0 0x1000>;
2254
2253
#clock-cells = <1>;
2254
+
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
2255
2255
};
2256
2256
2257
2257
mutex@14f01000 {
···
3082
3080
reg = <0 0x1c01a000 0 0x1000>;
3083
3081
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3084
3082
#clock-cells = <1>;
3083
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
3085
3084
};
3086
3085
3087
3086
···
3264
3261
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3265
3262
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3266
3263
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3264
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
3267
3265
mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3268
3266
};
3269
3267
···
3335
3331
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3336
3332
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3337
3333
clock-names = "vdo1_mutex";
3334
+
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
3338
3335
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3339
3336
};
3340
3337
+2
-2
arch/arm64/boot/dts/qcom/sc7280.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sc7280.dtsi
···
3707
3707
compatible = "qcom,sc7280-adsp-pas";
3708
3708
reg = <0 0x03700000 0 0x100>;
3709
3709
3710
-
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3710
+
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3711
3711
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3712
3712
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3713
3713
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
···
3944
3944
compatible = "qcom,sc7280-cdsp-pas";
3945
3945
reg = <0 0x0a300000 0 0x10000>;
3946
3946
3947
-
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3947
+
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3948
3948
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3949
3949
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3950
3950
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+1
-1
arch/arm64/boot/dts/qcom/sc8180x.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc8180x.dtsi
···
2701
2701
resets = <&gcc GCC_USB30_SEC_BCR>;
2702
2702
power-domains = <&gcc USB30_SEC_GDSC>;
2703
2703
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2704
-
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
2704
+
<&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
2705
2705
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
2706
2706
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
2707
2707
interrupt-names = "hs_phy_irq", "ss_phy_irq",
+8
-3
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+8
-3
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
···
1774
1774
reset-names = "pci";
1775
1775
1776
1776
power-domains = <&gcc PCIE_4_GDSC>;
1777
+
required-opps = <&rpmhpd_opp_nom>;
1777
1778
1778
1779
phys = <&pcie4_phy>;
1779
1780
phy-names = "pciephy";
···
1873
1872
reset-names = "pci";
1874
1873
1875
1874
power-domains = <&gcc PCIE_3B_GDSC>;
1875
+
required-opps = <&rpmhpd_opp_nom>;
1876
1876
1877
1877
phys = <&pcie3b_phy>;
1878
1878
phy-names = "pciephy";
···
1972
1970
reset-names = "pci";
1973
1971
1974
1972
power-domains = <&gcc PCIE_3A_GDSC>;
1973
+
required-opps = <&rpmhpd_opp_nom>;
1975
1974
1976
1975
phys = <&pcie3a_phy>;
1977
1976
phy-names = "pciephy";
···
2074
2071
reset-names = "pci";
2075
2072
2076
2073
power-domains = <&gcc PCIE_2B_GDSC>;
2074
+
required-opps = <&rpmhpd_opp_nom>;
2077
2075
2078
2076
phys = <&pcie2b_phy>;
2079
2077
phy-names = "pciephy";
···
2173
2169
reset-names = "pci";
2174
2170
2175
2171
power-domains = <&gcc PCIE_2A_GDSC>;
2172
+
required-opps = <&rpmhpd_opp_nom>;
2176
2173
2177
2174
phys = <&pcie2a_phy>;
2178
2175
phy-names = "pciephy";
···
2646
2641
compatible = "qcom,sc8280xp-adsp-pas";
2647
2642
reg = <0 0x03000000 0 0x100>;
2648
2643
2649
-
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2644
+
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2650
2645
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2651
2646
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2652
2647
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
···
4982
4977
compatible = "qcom,sc8280xp-nsp0-pas";
4983
4978
reg = <0 0x1b300000 0 0x100>;
4984
4979
4985
-
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
4980
+
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4986
4981
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4987
4982
<&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
4988
4983
<&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
···
5113
5108
compatible = "qcom,sc8280xp-nsp1-pas";
5114
5109
reg = <0 0x21300000 0 0x100>;
5115
5110
5116
-
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
5111
+
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5117
5112
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5118
5113
<&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5119
5114
<&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
+2
-2
arch/arm64/boot/dts/qcom/sm6350.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm6350.dtsi
···
1252
1252
compatible = "qcom,sm6350-adsp-pas";
1253
1253
reg = <0 0x03000000 0 0x100>;
1254
1254
1255
-
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1255
+
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1256
1256
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1257
1257
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1258
1258
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
···
1511
1511
compatible = "qcom,sm6350-cdsp-pas";
1512
1512
reg = <0 0x08300000 0 0x10000>;
1513
1513
1514
-
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1514
+
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1515
1515
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1516
1516
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1517
1517
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+1
-1
arch/arm64/boot/dts/qcom/sm6375.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sm6375.dtsi
···
1561
1561
compatible = "qcom,sm6375-adsp-pas";
1562
1562
reg = <0 0x0a400000 0 0x100>;
1563
1563
1564
-
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1564
+
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1565
1565
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1566
1566
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1567
1567
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+3
-3
arch/arm64/boot/dts/qcom/sm8250.dtsi
+3
-3
arch/arm64/boot/dts/qcom/sm8250.dtsi
···
3062
3062
compatible = "qcom,sm8250-slpi-pas";
3063
3063
reg = <0 0x05c00000 0 0x4000>;
3064
3064
3065
-
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3065
+
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3066
3066
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3067
3067
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3068
3068
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
···
3766
3766
compatible = "qcom,sm8250-cdsp-pas";
3767
3767
reg = <0 0x08300000 0 0x10000>;
3768
3768
3769
-
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3769
+
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3770
3770
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3771
3771
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3772
3772
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
···
5928
5928
compatible = "qcom,sm8250-adsp-pas";
5929
5929
reg = <0 0x17300000 0 0x100>;
5930
5930
5931
-
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5931
+
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5932
5932
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5933
5933
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5934
5934
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+4
-12
arch/arm64/boot/dts/qcom/sm8450.dtsi
+4
-12
arch/arm64/boot/dts/qcom/sm8450.dtsi
···
1777
1777
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778
1778
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779
1779
1780
-
/*
1781
-
* MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1782
-
* Hence, the IDs are swapped.
1783
-
*/
1784
-
msi-map = <0x0 &gic_its 0x5981 0x1>,
1785
-
<0x100 &gic_its 0x5980 0x1>;
1780
+
msi-map = <0x0 &gic_its 0x5980 0x1>,
1781
+
<0x100 &gic_its 0x5981 0x1>;
1786
1782
msi-map-mask = <0xff00>;
1787
1783
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1788
1784
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
···
1896
1900
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1897
1901
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1898
1902
1899
-
/*
1900
-
* MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1901
-
* Hence, the IDs are swapped.
1902
-
*/
1903
-
msi-map = <0x0 &gic_its 0x5a01 0x1>,
1904
-
<0x100 &gic_its 0x5a00 0x1>;
1903
+
msi-map = <0x0 &gic_its 0x5a00 0x1>,
1904
+
<0x100 &gic_its 0x5a01 0x1>;
1905
1905
msi-map-mask = <0xff00>;
1906
1906
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1907
1907
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+4
-6
arch/arm64/boot/dts/qcom/sm8550.dtsi
+4
-6
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
1755
1755
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1756
1756
interconnect-names = "pcie-mem", "cpu-pcie";
1757
1757
1758
-
/* Entries are reversed due to the unusual ITS DeviceID encoding */
1759
-
msi-map = <0x0 &gic_its 0x1401 0x1>,
1760
-
<0x100 &gic_its 0x1400 0x1>;
1758
+
msi-map = <0x0 &gic_its 0x1400 0x1>,
1759
+
<0x100 &gic_its 0x1401 0x1>;
1761
1760
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1762
1761
<0x100 &apps_smmu 0x1401 0x1>;
1763
1762
···
1866
1867
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1867
1868
interconnect-names = "pcie-mem", "cpu-pcie";
1868
1869
1869
-
/* Entries are reversed due to the unusual ITS DeviceID encoding */
1870
-
msi-map = <0x0 &gic_its 0x1481 0x1>,
1871
-
<0x100 &gic_its 0x1480 0x1>;
1870
+
msi-map = <0x0 &gic_its 0x1480 0x1>,
1871
+
<0x100 &gic_its 0x1481 0x1>;
1872
1872
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1873
1873
<0x100 &apps_smmu 0x1481 0x1>;
1874
1874
+4
-6
arch/arm64/boot/dts/qcom/sm8650.dtsi
+4
-6
arch/arm64/boot/dts/qcom/sm8650.dtsi
···
2274
2274
interrupt-map-mask = <0 0 0 0x7>;
2275
2275
#interrupt-cells = <1>;
2276
2276
2277
-
/* Entries are reversed due to the unusual ITS DeviceID encoding */
2278
-
msi-map = <0x0 &gic_its 0x1401 0x1>,
2279
-
<0x100 &gic_its 0x1400 0x1>;
2277
+
msi-map = <0x0 &gic_its 0x1400 0x1>,
2278
+
<0x100 &gic_its 0x1401 0x1>;
2280
2279
msi-map-mask = <0xff00>;
2281
2280
2282
2281
linux,pci-domain = <0>;
···
2401
2402
interrupt-map-mask = <0 0 0 0x7>;
2402
2403
#interrupt-cells = <1>;
2403
2404
2404
-
/* Entries are reversed due to the unusual ITS DeviceID encoding */
2405
-
msi-map = <0x0 &gic_its 0x1481 0x1>,
2406
-
<0x100 &gic_its 0x1480 0x1>;
2405
+
msi-map = <0x0 &gic_its 0x1480 0x1>,
2406
+
<0x100 &gic_its 0x1481 0x1>;
2407
2407
msi-map-mask = <0xff00>;
2408
2408
2409
2409
linux,pci-domain = <1>;
+2
-2
arch/arm64/boot/dts/qcom/x1e80100.dtsi
+2
-2
arch/arm64/boot/dts/qcom/x1e80100.dtsi
···
284
284
285
285
domain-idle-states {
286
286
CLUSTER_CL4: cluster-sleep-0 {
287
-
compatible = "arm,idle-state";
287
+
compatible = "domain-idle-state";
288
288
idle-state-name = "l2-ret";
289
289
arm,psci-suspend-param = <0x01000044>;
290
290
entry-latency-us = <350>;
···
293
293
};
294
294
295
295
CLUSTER_CL5: cluster-sleep-1 {
296
-
compatible = "arm,idle-state";
296
+
compatible = "domain-idle-state";
297
297
idle-state-name = "ret-pll-off";
298
298
arm,psci-suspend-param = <0x01000054>;
299
299
entry-latency-us = <2200>;
+1
-2
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+1
-2
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
···
663
663
port@1 {
664
664
reg = <1>;
665
665
666
-
mipi1_in_panel: endpoint@1 {
666
+
mipi1_in_panel: endpoint {
667
667
remote-endpoint = <&mipi1_out_panel>;
668
668
};
669
669
};
···
689
689
ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
690
690
691
691
/* PERST# asserted in S3 */
692
-
pcie-reset-suspend = <1>;
693
692
694
693
vpcie3v3-supply = <&wlan_3v3>;
695
694
vpcie1v8-supply = <&pp1800_pcie>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
-1
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-1
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+2
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+2
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+47
-6
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+47
-6
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
···
79
79
regulator-max-microvolt = <5000000>;
80
80
};
81
81
82
+
vcca_0v9: vcca-0v9-regulator {
83
+
compatible = "regulator-fixed";
84
+
regulator-name = "vcca_0v9";
85
+
regulator-always-on;
86
+
regulator-boot-on;
87
+
regulator-min-microvolt = <900000>;
88
+
regulator-max-microvolt = <900000>;
89
+
vin-supply = <&vcc_1v8>;
90
+
};
91
+
92
+
vcca_1v8: vcca-1v8-regulator {
93
+
compatible = "regulator-fixed";
94
+
regulator-name = "vcca_1v8";
95
+
regulator-always-on;
96
+
regulator-boot-on;
97
+
regulator-min-microvolt = <1800000>;
98
+
regulator-max-microvolt = <1800000>;
99
+
vin-supply = <&vcc3v3_sys>;
100
+
};
101
+
82
102
vdd_log: vdd-log {
83
103
compatible = "pwm-regulator";
84
104
pwms = <&pwm2 0 25000 1>;
···
436
416
gpio1830-supply = <&vcc_1v8>;
437
417
};
438
418
439
-
&pmu_io_domains {
440
-
status = "okay";
441
-
pmu1830-supply = <&vcc_1v8>;
419
+
&pcie0 {
420
+
/* PCIe PHY supplies */
421
+
vpcie0v9-supply = <&vcca_0v9>;
422
+
vpcie1v8-supply = <&vcca_1v8>;
442
423
};
443
424
444
-
&pwm2 {
445
-
status = "okay";
425
+
&pcie_clkreqn_cpm {
426
+
rockchip,pins =
427
+
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
446
428
};
447
429
448
430
&pinctrl {
431
+
pinctrl-names = "default";
432
+
pinctrl-0 = <&q7_thermal_pin>;
433
+
434
+
gpios {
435
+
q7_thermal_pin: q7-thermal-pin {
436
+
rockchip,pins =
437
+
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
438
+
};
439
+
};
440
+
449
441
i2c8 {
450
442
i2c8_xfer_a: i2c8-xfer {
451
443
rockchip,pins =
···
490
458
usb3 {
491
459
usb3_id: usb3-id {
492
460
rockchip,pins =
493
-
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
461
+
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
494
462
};
495
463
};
464
+
};
465
+
466
+
&pmu_io_domains {
467
+
status = "okay";
468
+
pmu1830-supply = <&vcc_1v8>;
469
+
};
470
+
471
+
&pwm2 {
472
+
status = "okay";
496
473
};
497
474
498
475
&sdhci {
-1
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
-1
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
+4
-2
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+4
-2
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
···
416
416
417
417
vccio_sd: LDO_REG5 {
418
418
regulator-name = "vccio_sd";
419
+
regulator-always-on;
420
+
regulator-boot-on;
419
421
regulator-min-microvolt = <1800000>;
420
422
regulator-max-microvolt = <3300000>;
421
423
···
527
525
#address-cells = <1>;
528
526
#size-cells = <0>;
529
527
530
-
switch@0 {
528
+
switch@1f {
531
529
compatible = "mediatek,mt7531";
532
-
reg = <0>;
530
+
reg = <0x1f>;
533
531
534
532
ports {
535
533
#address-cells = <1>;
-1
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
-1
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
···
216
216
pinctrl-0 = <&i2c7m0_xfer>;
217
217
status = "okay";
218
218
219
-
es8316: audio-codec@11 {
219
+
es8316: audio-codec@10 {
220
220
compatible = "everest,es8316";
221
-
reg = <0x11>;
221
+
reg = <0x10>;
222
222
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
223
223
assigned-clock-rates = <12288000>;
224
224
clocks = <&cru I2S0_8CH_MCLKOUT>;
+2
-1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+2
-1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
···
485
485
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
486
486
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
487
487
spi-max-frequency = <1000000>;
488
+
system-power-controller;
488
489
489
490
vcc1-supply = <&vcc5v0_sys>;
490
491
vcc2-supply = <&vcc5v0_sys>;
···
507
506
#gpio-cells = <2>;
508
507
509
508
rk806_dvs1_null: dvs1-null-pins {
510
-
pins = "gpio_pwrctrl2";
509
+
pins = "gpio_pwrctrl1";
511
510
function = "pin_fun0";
512
511
};
513
512
+1
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
+1
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
+91
-46
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
+91
-46
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
···
221
221
* alignment of 8 bytes (64 bits) for GUIDs. Our definition of efi_guid_t,
222
222
* however, has an alignment of 4 byte (32 bits). So far, this seems to work
223
223
* fine here. See also the comment on the typedef of efi_guid_t.
224
+
*
225
+
* Note: It looks like uefisecapp is quite picky about how the memory passed to
226
+
* it is structured and aligned. In particular the request/response setup used
227
+
* for QSEE_CMD_UEFI_GET_VARIABLE. While qcom_qseecom_app_send(), in theory,
228
+
* accepts separate buffers/addresses for the request and response parts, in
229
+
* practice, however, it seems to expect them to be both part of a larger
230
+
* contiguous block. We initially allocated separate buffers for the request
231
+
* and response but this caused the QSEE_CMD_UEFI_GET_VARIABLE command to
232
+
* either not write any response to the response buffer or outright crash the
233
+
* device. Therefore, we now allocate a single contiguous block of DMA memory
234
+
* for both and properly align the data using the macros below. In particular,
235
+
* request and response structs are aligned at 8 byte (via __reqdata_offs()),
236
+
* following the driver that this has been reverse-engineered from.
224
237
*/
225
238
#define qcuefi_buf_align_fields(fields...) \
226
239
({ \
···
256
243
257
244
#define __array_offs(type, count, offset) \
258
245
__field_impl(sizeof(type) * (count), __alignof__(type), offset)
246
+
247
+
#define __array_offs_aligned(type, count, align, offset) \
248
+
__field_impl(sizeof(type) * (count), align, offset)
249
+
250
+
#define __reqdata_offs(size, offset) \
251
+
__array_offs_aligned(u8, size, 8, offset)
259
252
260
253
#define __array(type, count) __array_offs(type, count, NULL)
261
254
#define __field_offs(type, offset) __array_offs(type, 1, offset)
···
296
277
unsigned long buffer_size = *data_size;
297
278
efi_status_t efi_status = EFI_SUCCESS;
298
279
unsigned long name_length;
280
+
dma_addr_t cmd_buf_dma;
281
+
size_t cmd_buf_size;
282
+
void *cmd_buf;
299
283
size_t guid_offs;
300
284
size_t name_offs;
301
285
size_t req_size;
302
286
size_t rsp_size;
287
+
size_t req_offs;
288
+
size_t rsp_offs;
303
289
ssize_t status;
304
290
305
291
if (!name || !guid)
···
328
304
__array(u8, buffer_size)
329
305
);
330
306
331
-
req_data = kzalloc(req_size, GFP_KERNEL);
332
-
if (!req_data) {
307
+
cmd_buf_size = qcuefi_buf_align_fields(
308
+
__reqdata_offs(req_size, &req_offs)
309
+
__reqdata_offs(rsp_size, &rsp_offs)
310
+
);
311
+
312
+
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
313
+
if (!cmd_buf) {
333
314
efi_status = EFI_OUT_OF_RESOURCES;
334
315
goto out;
335
316
}
336
317
337
-
rsp_data = kzalloc(rsp_size, GFP_KERNEL);
338
-
if (!rsp_data) {
339
-
efi_status = EFI_OUT_OF_RESOURCES;
340
-
goto out_free_req;
341
-
}
318
+
req_data = cmd_buf + req_offs;
319
+
rsp_data = cmd_buf + rsp_offs;
342
320
343
321
req_data->command_id = QSEE_CMD_UEFI_GET_VARIABLE;
344
322
req_data->data_size = buffer_size;
···
358
332
359
333
memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size);
360
334
361
-
status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size);
335
+
status = qcom_qseecom_app_send(qcuefi->client,
336
+
cmd_buf_dma + req_offs, req_size,
337
+
cmd_buf_dma + rsp_offs, rsp_size);
362
338
if (status) {
363
339
efi_status = EFI_DEVICE_ERROR;
364
340
goto out_free;
···
435
407
memcpy(data, ((void *)rsp_data) + rsp_data->data_offset, rsp_data->data_size);
436
408
437
409
out_free:
438
-
kfree(rsp_data);
439
-
out_free_req:
440
-
kfree(req_data);
410
+
qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
441
411
out:
442
412
return efi_status;
443
413
}
···
448
422
struct qsee_rsp_uefi_set_variable *rsp_data;
449
423
efi_status_t efi_status = EFI_SUCCESS;
450
424
unsigned long name_length;
425
+
dma_addr_t cmd_buf_dma;
426
+
size_t cmd_buf_size;
427
+
void *cmd_buf;
451
428
size_t name_offs;
452
429
size_t guid_offs;
453
430
size_t data_offs;
454
431
size_t req_size;
432
+
size_t req_offs;
433
+
size_t rsp_offs;
455
434
ssize_t status;
456
435
457
436
if (!name || !guid)
···
481
450
__array_offs(u8, data_size, &data_offs)
482
451
);
483
452
484
-
req_data = kzalloc(req_size, GFP_KERNEL);
485
-
if (!req_data) {
453
+
cmd_buf_size = qcuefi_buf_align_fields(
454
+
__reqdata_offs(req_size, &req_offs)
455
+
__reqdata_offs(sizeof(*rsp_data), &rsp_offs)
456
+
);
457
+
458
+
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
459
+
if (!cmd_buf) {
486
460
efi_status = EFI_OUT_OF_RESOURCES;
487
461
goto out;
488
462
}
489
463
490
-
rsp_data = kzalloc(sizeof(*rsp_data), GFP_KERNEL);
491
-
if (!rsp_data) {
492
-
efi_status = EFI_OUT_OF_RESOURCES;
493
-
goto out_free_req;
494
-
}
464
+
req_data = cmd_buf + req_offs;
465
+
rsp_data = cmd_buf + rsp_offs;
495
466
496
467
req_data->command_id = QSEE_CMD_UEFI_SET_VARIABLE;
497
468
req_data->attributes = attributes;
···
516
483
if (data_size)
517
484
memcpy(((void *)req_data) + req_data->data_offset, data, req_data->data_size);
518
485
519
-
status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data,
520
-
sizeof(*rsp_data));
486
+
status = qcom_qseecom_app_send(qcuefi->client,
487
+
cmd_buf_dma + req_offs, req_size,
488
+
cmd_buf_dma + rsp_offs, sizeof(*rsp_data));
521
489
if (status) {
522
490
efi_status = EFI_DEVICE_ERROR;
523
491
goto out_free;
···
541
507
}
542
508
543
509
out_free:
544
-
kfree(rsp_data);
545
-
out_free_req:
546
-
kfree(req_data);
510
+
qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
547
511
out:
548
512
return efi_status;
549
513
}
···
553
521
struct qsee_req_uefi_get_next_variable *req_data;
554
522
struct qsee_rsp_uefi_get_next_variable *rsp_data;
555
523
efi_status_t efi_status = EFI_SUCCESS;
524
+
dma_addr_t cmd_buf_dma;
525
+
size_t cmd_buf_size;
526
+
void *cmd_buf;
556
527
size_t guid_offs;
557
528
size_t name_offs;
558
529
size_t req_size;
559
530
size_t rsp_size;
531
+
size_t req_offs;
532
+
size_t rsp_offs;
560
533
ssize_t status;
561
534
562
535
if (!name_size || !name || !guid)
···
582
545
__array(*name, *name_size / sizeof(*name))
583
546
);
584
547
585
-
req_data = kzalloc(req_size, GFP_KERNEL);
586
-
if (!req_data) {
548
+
cmd_buf_size = qcuefi_buf_align_fields(
549
+
__reqdata_offs(req_size, &req_offs)
550
+
__reqdata_offs(rsp_size, &rsp_offs)
551
+
);
552
+
553
+
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
554
+
if (!cmd_buf) {
587
555
efi_status = EFI_OUT_OF_RESOURCES;
588
556
goto out;
589
557
}
590
558
591
-
rsp_data = kzalloc(rsp_size, GFP_KERNEL);
592
-
if (!rsp_data) {
593
-
efi_status = EFI_OUT_OF_RESOURCES;
594
-
goto out_free_req;
595
-
}
559
+
req_data = cmd_buf + req_offs;
560
+
rsp_data = cmd_buf + rsp_offs;
596
561
597
562
req_data->command_id = QSEE_CMD_UEFI_GET_NEXT_VARIABLE;
598
563
req_data->guid_offset = guid_offs;
···
611
572
goto out_free;
612
573
}
613
574
614
-
status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size);
575
+
status = qcom_qseecom_app_send(qcuefi->client,
576
+
cmd_buf_dma + req_offs, req_size,
577
+
cmd_buf_dma + rsp_offs, rsp_size);
615
578
if (status) {
616
579
efi_status = EFI_DEVICE_ERROR;
617
580
goto out_free;
···
686
645
}
687
646
688
647
out_free:
689
-
kfree(rsp_data);
690
-
out_free_req:
691
-
kfree(req_data);
648
+
qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
692
649
out:
693
650
return efi_status;
694
651
}
···
698
659
struct qsee_req_uefi_query_variable_info *req_data;
699
660
struct qsee_rsp_uefi_query_variable_info *rsp_data;
700
661
efi_status_t efi_status = EFI_SUCCESS;
662
+
dma_addr_t cmd_buf_dma;
663
+
size_t cmd_buf_size;
664
+
void *cmd_buf;
665
+
size_t req_offs;
666
+
size_t rsp_offs;
701
667
int status;
702
668
703
-
req_data = kzalloc(sizeof(*req_data), GFP_KERNEL);
704
-
if (!req_data) {
669
+
cmd_buf_size = qcuefi_buf_align_fields(
670
+
__reqdata_offs(sizeof(*req_data), &req_offs)
671
+
__reqdata_offs(sizeof(*rsp_data), &rsp_offs)
672
+
);
673
+
674
+
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
675
+
if (!cmd_buf) {
705
676
efi_status = EFI_OUT_OF_RESOURCES;
706
677
goto out;
707
678
}
708
679
709
-
rsp_data = kzalloc(sizeof(*rsp_data), GFP_KERNEL);
710
-
if (!rsp_data) {
711
-
efi_status = EFI_OUT_OF_RESOURCES;
712
-
goto out_free_req;
713
-
}
680
+
req_data = cmd_buf + req_offs;
681
+
rsp_data = cmd_buf + rsp_offs;
714
682
715
683
req_data->command_id = QSEE_CMD_UEFI_QUERY_VARIABLE_INFO;
716
684
req_data->attributes = attr;
717
685
req_data->length = sizeof(*req_data);
718
686
719
-
status = qcom_qseecom_app_send(qcuefi->client, req_data, sizeof(*req_data), rsp_data,
720
-
sizeof(*rsp_data));
687
+
status = qcom_qseecom_app_send(qcuefi->client,
688
+
cmd_buf_dma + req_offs, sizeof(*req_data),
689
+
cmd_buf_dma + rsp_offs, sizeof(*rsp_data));
721
690
if (status) {
722
691
efi_status = EFI_DEVICE_ERROR;
723
692
goto out_free;
···
758
711
*max_variable_size = rsp_data->max_variable_size;
759
712
760
713
out_free:
761
-
kfree(rsp_data);
762
-
out_free_req:
763
-
kfree(req_data);
714
+
qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
764
715
out:
765
716
return efi_status;
766
717
}
+6
-31
drivers/firmware/qcom/qcom_scm.c
+6
-31
drivers/firmware/qcom/qcom_scm.c
···
1576
1576
/**
1577
1577
* qcom_scm_qseecom_app_send() - Send to and receive data from a given QSEE app.
1578
1578
* @app_id: The ID of the target app.
1579
-
* @req: Request buffer sent to the app (must be DMA-mappable).
1579
+
* @req: DMA address of the request buffer sent to the app.
1580
1580
* @req_size: Size of the request buffer.
1581
-
* @rsp: Response buffer, written to by the app (must be DMA-mappable).
1581
+
* @rsp: DMA address of the response buffer, written to by the app.
1582
1582
* @rsp_size: Size of the response buffer.
1583
1583
*
1584
1584
* Sends a request to the QSEE app associated with the given ID and read back
···
1589
1589
*
1590
1590
* Return: Zero on success, nonzero on failure.
1591
1591
*/
1592
-
int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, void *rsp,
1593
-
size_t rsp_size)
1592
+
int qcom_scm_qseecom_app_send(u32 app_id, dma_addr_t req, size_t req_size,
1593
+
dma_addr_t rsp, size_t rsp_size)
1594
1594
{
1595
1595
struct qcom_scm_qseecom_resp res = {};
1596
1596
struct qcom_scm_desc desc = {};
1597
-
dma_addr_t req_phys;
1598
-
dma_addr_t rsp_phys;
1599
1597
int status;
1600
1598
1601
-
/* Map request buffer */
1602
-
req_phys = dma_map_single(__scm->dev, req, req_size, DMA_TO_DEVICE);
1603
-
status = dma_mapping_error(__scm->dev, req_phys);
1604
-
if (status) {
1605
-
dev_err(__scm->dev, "qseecom: failed to map request buffer\n");
1606
-
return status;
1607
-
}
1608
-
1609
-
/* Map response buffer */
1610
-
rsp_phys = dma_map_single(__scm->dev, rsp, rsp_size, DMA_FROM_DEVICE);
1611
-
status = dma_mapping_error(__scm->dev, rsp_phys);
1612
-
if (status) {
1613
-
dma_unmap_single(__scm->dev, req_phys, req_size, DMA_TO_DEVICE);
1614
-
dev_err(__scm->dev, "qseecom: failed to map response buffer\n");
1615
-
return status;
1616
-
}
1617
-
1618
-
/* Set up SCM call data */
1619
1599
desc.owner = QSEECOM_TZ_OWNER_TZ_APPS;
1620
1600
desc.svc = QSEECOM_TZ_SVC_APP_ID_PLACEHOLDER;
1621
1601
desc.cmd = QSEECOM_TZ_CMD_APP_SEND;
···
1603
1623
QCOM_SCM_RW, QCOM_SCM_VAL,
1604
1624
QCOM_SCM_RW, QCOM_SCM_VAL);
1605
1625
desc.args[0] = app_id;
1606
-
desc.args[1] = req_phys;
1626
+
desc.args[1] = req;
1607
1627
desc.args[2] = req_size;
1608
-
desc.args[3] = rsp_phys;
1628
+
desc.args[3] = rsp;
1609
1629
desc.args[4] = rsp_size;
1610
1630
1611
-
/* Perform call */
1612
1631
status = qcom_scm_qseecom_call(&desc, &res);
1613
-
1614
-
/* Unmap buffers */
1615
-
dma_unmap_single(__scm->dev, rsp_phys, rsp_size, DMA_FROM_DEVICE);
1616
-
dma_unmap_single(__scm->dev, req_phys, req_size, DMA_TO_DEVICE);
1617
1632
1618
1633
if (status)
1619
1634
return status;
+1
drivers/soc/mediatek/Kconfig
+1
drivers/soc/mediatek/Kconfig
+5
-2
drivers/soc/mediatek/mtk-svs.c
+5
-2
drivers/soc/mediatek/mtk-svs.c
···
1768
1768
const struct svs_bank_pdata *bdata;
1769
1769
struct svs_bank *svsb;
1770
1770
struct dev_pm_opp *opp;
1771
+
char tz_name_buf[20];
1771
1772
unsigned long freq;
1772
1773
int count, ret;
1773
1774
u32 idx, i;
···
1820
1819
}
1821
1820
1822
1821
if (!IS_ERR_OR_NULL(bdata->tzone_name)) {
1823
-
svsb->tzd = thermal_zone_get_zone_by_name(bdata->tzone_name);
1822
+
snprintf(tz_name_buf, ARRAY_SIZE(tz_name_buf),
1823
+
"%s-thermal", bdata->tzone_name);
1824
+
svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf);
1824
1825
if (IS_ERR(svsb->tzd)) {
1825
1826
dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1826
-
bdata->tzone_name);
1827
+
tz_name_buf);
1827
1828
return PTR_ERR(svsb->tzd);
1828
1829
}
1829
1830
}
+51
-4
include/linux/firmware/qcom/qcom_qseecom.h
+51
-4
include/linux/firmware/qcom/qcom_qseecom.h
···
10
10
#define __QCOM_QSEECOM_H
11
11
12
12
#include <linux/auxiliary_bus.h>
13
+
#include <linux/dma-mapping.h>
13
14
#include <linux/types.h>
14
15
15
16
#include <linux/firmware/qcom/qcom_scm.h>
···
26
25
};
27
26
28
27
/**
28
+
* qseecom_scm_dev() - Get the SCM device associated with the QSEECOM client.
29
+
* @client: The QSEECOM client device.
30
+
*
31
+
* Returns the SCM device under which the provided QSEECOM client device
32
+
* operates. This function is intended to be used for DMA allocations.
33
+
*/
34
+
static inline struct device *qseecom_scm_dev(struct qseecom_client *client)
35
+
{
36
+
return client->aux_dev.dev.parent->parent;
37
+
}
38
+
39
+
/**
40
+
* qseecom_dma_alloc() - Allocate DMA memory for a QSEECOM client.
41
+
* @client: The QSEECOM client to allocate the memory for.
42
+
* @size: The number of bytes to allocate.
43
+
* @dma_handle: Pointer to where the DMA address should be stored.
44
+
* @gfp: Allocation flags.
45
+
*
46
+
* Wrapper function for dma_alloc_coherent(), allocating DMA memory usable for
47
+
* TZ/QSEECOM communication. Refer to dma_alloc_coherent() for details.
48
+
*/
49
+
static inline void *qseecom_dma_alloc(struct qseecom_client *client, size_t size,
50
+
dma_addr_t *dma_handle, gfp_t gfp)
51
+
{
52
+
return dma_alloc_coherent(qseecom_scm_dev(client), size, dma_handle, gfp);
53
+
}
54
+
55
+
/**
56
+
* dma_free_coherent() - Free QSEECOM DMA memory.
57
+
* @client: The QSEECOM client for which the memory has been allocated.
58
+
* @size: The number of bytes allocated.
59
+
* @cpu_addr: Virtual memory address to free.
60
+
* @dma_handle: DMA memory address to free.
61
+
*
62
+
* Wrapper function for dma_free_coherent(), freeing memory previously
63
+
* allocated with qseecom_dma_alloc(). Refer to dma_free_coherent() for
64
+
* details.
65
+
*/
66
+
static inline void qseecom_dma_free(struct qseecom_client *client, size_t size,
67
+
void *cpu_addr, dma_addr_t dma_handle)
68
+
{
69
+
return dma_free_coherent(qseecom_scm_dev(client), size, cpu_addr, dma_handle);
70
+
}
71
+
72
+
/**
29
73
* qcom_qseecom_app_send() - Send to and receive data from a given QSEE app.
30
74
* @client: The QSEECOM client associated with the target app.
31
-
* @req: Request buffer sent to the app (must be DMA-mappable).
75
+
* @req: DMA address of the request buffer sent to the app.
32
76
* @req_size: Size of the request buffer.
33
-
* @rsp: Response buffer, written to by the app (must be DMA-mappable).
77
+
* @rsp: DMA address of the response buffer, written to by the app.
34
78
* @rsp_size: Size of the response buffer.
35
79
*
36
80
* Sends a request to the QSEE app associated with the given client and read
···
89
43
*
90
44
* Return: Zero on success, nonzero on failure.
91
45
*/
92
-
static inline int qcom_qseecom_app_send(struct qseecom_client *client, void *req, size_t req_size,
93
-
void *rsp, size_t rsp_size)
46
+
static inline int qcom_qseecom_app_send(struct qseecom_client *client,
47
+
dma_addr_t req, size_t req_size,
48
+
dma_addr_t rsp, size_t rsp_size)
94
49
{
95
50
return qcom_scm_qseecom_app_send(client->app_id, req, req_size, rsp, rsp_size);
96
51
}
+5
-5
include/linux/firmware/qcom/qcom_scm.h
+5
-5
include/linux/firmware/qcom/qcom_scm.h
···
118
118
#ifdef CONFIG_QCOM_QSEECOM
119
119
120
120
int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
121
-
int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, void *rsp,
122
-
size_t rsp_size);
121
+
int qcom_scm_qseecom_app_send(u32 app_id, dma_addr_t req, size_t req_size,
122
+
dma_addr_t rsp, size_t rsp_size);
123
123
124
124
#else /* CONFIG_QCOM_QSEECOM */
125
125
···
128
128
return -EINVAL;
129
129
}
130
130
131
-
static inline int qcom_scm_qseecom_app_send(u32 app_id, void *req,
132
-
size_t req_size, void *rsp,
133
-
size_t rsp_size)
131
+
static inline int qcom_scm_qseecom_app_send(u32 app_id,
132
+
dma_addr_t req, size_t req_size,
133
+
dma_addr_t rsp, size_t rsp_size)
134
134
{
135
135
return -EINVAL;
136
136
}