Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/lt_phy: Add .enable_clock hook on DDI
Enable PLL clock on DDI by moving part of the PLL enabling
sequence into a DDI clock enabling function.
v2: Reuse intel_mtl_pll_enable_clock for DDI clock enabling
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-17-mika.kahola@intel.com
+34
-21
+1
-1
drivers/gpu/drm/i915/display/intel_ddi.c
+1
-1
drivers/gpu/drm/i915/display/intel_ddi.c
···
5298
5298
encoder->pipe_mask = ~0;
5299
5299
5300
5300
if (HAS_LT_PHY(display)) {
5301
-
encoder->enable_clock = intel_xe3plpd_pll_enable;
5301
+
encoder->enable_clock = intel_mtl_pll_enable_clock;
5302
5302
encoder->disable_clock = intel_xe3plpd_pll_disable;
5303
5303
encoder->port_pll_type = intel_mtl_port_pll_type;
5304
5304
encoder->get_config = xe3plpd_ddi_get_config;
+13
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+13
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4595
4595
return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
4596
4596
}
4597
4597
4598
+
static void xe3plpd_pll_enable(struct intel_display *display,
4599
+
struct intel_dpll *pll,
4600
+
const struct intel_dpll_hw_state *dpll_hw_state)
4601
+
{
4602
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4603
+
4604
+
if (drm_WARN_ON(display->drm, !encoder))
4605
+
return;
4606
+
4607
+
intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);
4608
+
}
4609
+
4598
4610
static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
4611
+
.enable = xe3plpd_pll_enable,
4599
4612
.get_hw_state = xe3plpd_pll_get_hw_state,
4600
4613
.get_freq = xe3plpd_pll_get_freq,
4601
4614
};
+14
-18
drivers/gpu/drm/i915/display/intel_lt_phy.c
+14
-18
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1901
1901
}
1902
1902
1903
1903
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
1904
-
const struct intel_crtc_state *crtc_state)
1904
+
struct intel_dpll *pll,
1905
+
const struct intel_dpll_hw_state *dpll_hw_state)
1905
1906
{
1906
1907
struct intel_display *display = to_intel_display(encoder);
1908
+
int port_clock = intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
1907
1909
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1908
1910
bool lane_reversal = dig_port->lane_reversal;
1909
1911
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
···
1921
1919
wakeref = intel_lt_phy_transaction_begin(encoder);
1922
1920
1923
1921
/* 1. Enable MacCLK at default 162 MHz frequency. */
1924
-
intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
1922
+
intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count);
1925
1923
1926
1924
/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
1927
-
intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state->dpll_hw_state.ltpll,
1928
-
crtc_state->port_clock, lane_reversal);
1925
+
intel_lt_phy_program_port_clock_ctl(encoder, &dpll_hw_state->ltpll,
1926
+
port_clock, lane_reversal);
1929
1927
1930
1928
/* 3. Change owned PHY lanes power to Ready state. */
1931
1929
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
···
1935
1933
* 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
1936
1934
* encoded rate and encoded mode.
1937
1935
*/
1938
-
if (intel_lt_phy_config_changed(encoder, &crtc_state->dpll_hw_state.ltpll,
1939
-
crtc_state->port_clock)) {
1936
+
if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll, port_clock)) {
1940
1937
/*
1941
1938
* 5. Program the PHY internal PLL registers over PHY message bus for the desired
1942
1939
* frequency and protocol type
1943
1940
*/
1944
-
intel_lt_phy_program_pll(encoder, &crtc_state->dpll_hw_state.ltpll);
1941
+
intel_lt_phy_program_pll(encoder, &dpll_hw_state->ltpll);
1945
1942
1946
1943
/* 6. Use the P2P transaction flow */
1947
1944
/*
···
1972
1971
* Change. We handle this step in bxt_set_cdclk().
1973
1972
*/
1974
1973
/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
1975
-
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
1976
-
crtc_state->port_clock);
1974
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
1977
1975
1978
1976
/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
1979
1977
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
···
2019
2019
lane_phy_pulse_status,
2020
2020
lane_phy_pulse_status);
2021
2021
} else {
2022
-
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
2022
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
2023
2023
}
2024
2024
2025
2025
/*
···
2030
2030
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
2031
2031
XELPDP_P0_STATE_ACTIVE);
2032
2032
2033
-
intel_lt_phy_enable_disable_tx(encoder, &crtc_state->dpll_hw_state.ltpll);
2033
+
intel_lt_phy_enable_disable_tx(encoder, &dpll_hw_state->ltpll);
2034
2034
intel_lt_phy_transaction_end(encoder, wakeref);
2035
2035
}
2036
2036
···
2288
2288
}
2289
2289
2290
2290
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
2291
-
const struct intel_crtc_state *crtc_state)
2291
+
struct intel_dpll *pll,
2292
+
const struct intel_dpll_hw_state *dpll_hw_state)
2292
2293
{
2293
-
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2294
-
2295
-
if (intel_tc_port_in_tbt_alt_mode(dig_port))
2296
-
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
2297
-
else
2298
-
intel_lt_phy_pll_enable(encoder, crtc_state);
2294
+
intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
2299
2295
}
2300
2296
2301
2297
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
+6
-2
drivers/gpu/drm/i915/display/intel_lt_phy.h
+6
-2
drivers/gpu/drm/i915/display/intel_lt_phy.h
···
11
11
struct drm_printer;
12
12
struct intel_atomic_state;
13
13
struct intel_display;
14
+
struct intel_dpll;
15
+
struct intel_dpll_hw_state;
14
16
struct intel_encoder;
15
17
struct intel_crtc_state;
16
18
struct intel_crtc;
17
19
struct intel_lt_phy_pll_state;
18
20
19
21
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
20
-
const struct intel_crtc_state *crtc_state);
22
+
struct intel_dpll *pll,
23
+
const struct intel_dpll_hw_state *dpll_hw_state);
21
24
void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
22
25
int
23
26
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
···
43
40
intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
44
41
u32 frequency_khz);
45
42
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
46
-
const struct intel_crtc_state *crtc_state);
43
+
struct intel_dpll *pll,
44
+
const struct intel_dpll_hw_state *dpll_hw_state);
47
45
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
48
46
void intel_lt_phy_verify_plls(struct intel_display *display);
49
47