tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

Cross-merge networking fixes after downstream PR (net-6.17-rc5).

No conflicts.

Adjacent changes:

include/net/sock.h
c51613fa276f ("net: add sk->sk_drop_counters")
5d6b58c932ec ("net: lockless sock_i_ino()")

Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 5ef04a7b c975e1df

+5233 -1699
+1
.mailmap
··· 589 589 Nikolay Aleksandrov <razor@blackwall.org> <nikolay@cumulusnetworks.com> 590 590 Nikolay Aleksandrov <razor@blackwall.org> <nikolay@nvidia.com> 591 591 Nikolay Aleksandrov <razor@blackwall.org> <nikolay@isovalent.com> 592 + Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba> <nobuhiro1.iwamatsu@toshiba.co.jp> 592 593 Odelu Kukatla <quic_okukatla@quicinc.com> <okukatla@codeaurora.org> 593 594 Oleksandr Natalenko <oleksandr@natalenko.name> <oleksandr@redhat.com> 594 595 Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net>
+1 -4
Documentation/admin-guide/hw-vuln/attack_vector_controls.rst
··· 215 215 Spectre_v2_user X X * (Note 1) 216 216 SRBDS X X X X 217 217 SRSO X X X X 218 - SSB (Note 4) 218 + SSB X 219 219 TAA X X X X * (Note 2) 220 220 TSA X X X X 221 221 =============== ============== ============ ============= ============== ============ ======== ··· 228 228 229 229 3 -- Disables SMT if cross-thread mitigations are fully enabled, the CPU is 230 230 vulnerable, and STIBP is not supported 231 - 232 - 4 -- Speculative store bypass is always enabled by default (no kernel 233 - mitigation applied) unless overridden with spec_store_bypass_disable option 234 231 235 232 When an attack-vector is disabled, all mitigations for the vulnerabilities 236 233 listed in the above table are disabled, unless mitigation is required for a
-1
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
··· 60 60 - const: bus 61 61 - const: core 62 62 - const: vsync 63 - - const: lut 64 63 - const: tbu 65 64 - const: tbu_rt 66 65 # MSM8996 has additional iommu clock
+2 -3
Documentation/networking/napi.rst
··· 433 433 434 434 Threaded NAPI is an operating mode that uses dedicated kernel 435 435 threads rather than software IRQ context for NAPI processing. 436 - The configuration is per netdevice and will affect all 437 - NAPI instances of that device. Each NAPI instance will spawn a separate 438 - thread (called ``napi/${ifc-name}-${napi-id}``). 436 + Each threaded NAPI instance will spawn a separate thread 437 + (called ``napi/${ifc-name}-${napi-id}``). 439 438 440 439 It is recommended to pin each kernel thread to a single CPU, the same 441 440 CPU as the CPU which services the interrupt. Note that the mapping
+25 -4
Documentation/sound/alsa-configuration.rst
··· 2253 2253 Default: 0x0000 2254 2254 ignore_ctl_error 2255 2255 Ignore any USB-controller regarding mixer interface (default: no) 2256 + ``ignore_ctl_error=1`` may help when you get an error at accessing 2257 + the mixer element such as URB error -22. This happens on some 2258 + buggy USB device or the controller. This workaround corresponds to 2259 + the ``quirk_flags`` bit 14, too. 2256 2260 autoclock 2257 2261 Enable auto-clock selection for UAC2 devices (default: yes) 2262 + lowlatency 2263 + Enable low latency playback mode (default: yes). 2264 + Could disable it to switch back to the old mode if face a regression. 2258 2265 quirk_alias 2259 2266 Quirk alias list, pass strings like ``0123abcd:5678beef``, which 2260 2267 applies the existing quirk for the device 5678:beef to a new ··· 2291 2284 The driver prints a message like "Found post-registration device 2292 2285 assignment: 1234abcd:04" for such a device, so that user can 2293 2286 notice the need. 2287 + skip_validation 2288 + Skip unit descriptor validation (default: no). 2289 + The option is used to ignores the validation errors with the hexdump 2290 + of the unit descriptor instead of a driver probe error, so that we 2291 + can check its details. 2294 2292 quirk_flags 2295 2293 Contains the bit flags for various device specific workarounds. 2296 2294 Applied to the corresponding card index. ··· 2319 2307 * bit 16: Set up the interface at first like UAC1 2320 2308 * bit 17: Apply the generic implicit feedback sync mode 2321 2309 * bit 18: Don't apply implicit feedback sync mode 2310 + * bit 19: Don't closed interface during setting sample rate 2311 + * bit 20: Force an interface reset whenever stopping & restarting 2312 + a stream 2313 + * bit 21: Do not set PCM rate (frequency) when only one rate is 2314 + available for the given endpoint. 2315 + * bit 22: Set the fixed resolution 16 for Mic Capture Volume 2316 + * bit 23: Set the fixed resolution 384 for Mic Capture Volume 2317 + * bit 24: Set minimum volume control value as mute for devices 2318 + where the lowest playback value represents muted state instead 2319 + of minimum audible volume 2322 2320 2323 2321 This module supports multiple devices, autoprobe and hotplugging. 2324 2322 ··· 2336 2314 Don't put the value over 20. Changing via sysfs has no sanity 2337 2315 check. 2338 2316 2339 - NB: ``ignore_ctl_error=1`` may help when you get an error at accessing 2340 - the mixer element such as URB error -22. This happens on some 2341 - buggy USB device or the controller. This workaround corresponds to 2342 - the ``quirk_flags`` bit 14, too. 2317 + NB: ``ignore_ctl_error=1`` just provides a quick way to work around the 2318 + issues. If you have a buggy device that requires these quirks, please 2319 + report it to the upstream. 2343 2320 2344 2321 NB: ``quirk_alias`` option is provided only for testing / development. 2345 2322 If you want to have a proper support, contact to upstream for
+12 -4
MAINTAINERS
··· 931 931 F: drivers/dma/altera-msgdma.c 932 932 933 933 ALTERA PIO DRIVER 934 - M: Mun Yew Tham <mun.yew.tham@intel.com> 934 + M: Adrian Ng <adrianhoyin.ng@altera.com> 935 935 L: linux-gpio@vger.kernel.org 936 936 S: Maintained 937 937 F: drivers/gpio/gpio-altera.c ··· 3526 3526 F: arch/arm/boot/dts/nspire/ 3527 3527 3528 3528 ARM/TOSHIBA VISCONTI ARCHITECTURE 3529 - M: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 3529 + M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba> 3530 3530 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 3531 3531 S: Supported 3532 3532 T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git ··· 3667 3667 F: drivers/virt/coco/pkvm-guest/ 3668 3668 F: tools/testing/selftests/arm64/ 3669 3669 X: arch/arm64/boot/dts/ 3670 + X: arch/arm64/configs/defconfig 3670 3671 3671 3672 ARROW SPEEDCHIPS XRS7000 SERIES ETHERNET SWITCH DRIVER 3672 3673 M: George McCollister <george.mccollister@gmail.com> ··· 4206 4205 F: drivers/net/hamradio/baycom* 4207 4206 4208 4207 BCACHE (BLOCK LAYER CACHE) 4209 - M: Coly Li <colyli@kernel.org> 4208 + M: Coly Li <colyli@fnnas.com> 4210 4209 M: Kent Overstreet <kent.overstreet@linux.dev> 4211 4210 L: linux-bcache@vger.kernel.org 4212 4211 S: Maintained ··· 10390 10389 F: drivers/input/touchscreen/goodix* 10391 10390 10392 10391 GOOGLE ETHERNET DRIVERS 10393 - M: Jeroen de Borst <jeroendb@google.com> 10392 + M: Joshua Washington <joshwash@google.com> 10394 10393 M: Harshitha Ramamurthy <hramamurthy@google.com> 10395 10394 L: netdev@vger.kernel.org 10396 10395 S: Maintained ··· 17851 17850 NETWORKING [TLS] 17852 17851 M: John Fastabend <john.fastabend@gmail.com> 17853 17852 M: Jakub Kicinski <kuba@kernel.org> 17853 + M: Sabrina Dubroca <sd@queasysnail.net> 17854 17854 L: netdev@vger.kernel.org 17855 17855 S: Maintained 17856 17856 F: include/net/tls.h ··· 24270 24268 S: Maintained 24271 24269 F: Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml 24272 24270 F: drivers/input/keyboard/sun4i-lradc-keys.c 24271 + 24272 + SUNDANCE NETWORK DRIVER 24273 + M: Denis Kirjanov <dkirjanov@suse.de> 24274 + L: netdev@vger.kernel.org 24275 + S: Maintained 24276 + F: drivers/net/ethernet/dlink/sundance.c 24273 24277 24274 24278 SUNPLUS ETHERNET DRIVER 24275 24279 M: Wells Lu <wellslutw@gmail.com>
+1 -1
Makefile
··· 2 2 VERSION = 6 3 3 PATCHLEVEL = 17 4 4 SUBLEVEL = 0 5 - EXTRAVERSION = -rc3 5 + EXTRAVERSION = -rc4 6 6 NAME = Baby Opossum Posse 7 7 8 8 # *DOCUMENTATION*
+2
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts
··· 387 387 388 388 &sdmmc1 { 389 389 bus-width = <4>; 390 + no-1-8-v; 391 + sdhci-caps-mask = <0x0 0x00200000>; 390 392 pinctrl-names = "default"; 391 393 pinctrl-0 = <&pinctrl_sdmmc1_default>; 392 394 status = "okay";
+1 -1
arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
··· 272 272 phy-mode = "rmii"; 273 273 phy-handle = <&phy0>; 274 274 assigned-clocks = <&cru SCLK_MAC_SRC>; 275 - assigned-clock-rates= <50000000>; 275 + assigned-clock-rates = <50000000>; 276 276 pinctrl-names = "default"; 277 277 pinctrl-0 = <&rmii_pins>; 278 278 status = "okay";
+3 -3
arch/arm/boot/dts/rockchip/rv1109-relfor-saib.dts
··· 250 250 &i2s0 { 251 251 /delete-property/ pinctrl-0; 252 252 rockchip,trcm-sync-rx-only; 253 - pinctrl-0 = <&i2s0m0_sclk_rx>, 254 - <&i2s0m0_lrck_rx>, 255 - <&i2s0m0_sdi0>; 253 + pinctrl-0 = <&i2s0m0_sclk_rx>, 254 + <&i2s0m0_lrck_rx>, 255 + <&i2s0m0_sdi0>; 256 256 pinctrl-names = "default"; 257 257 status = "okay"; 258 258 };
+2 -1
arch/arm/include/asm/stacktrace.h
··· 2 2 #ifndef __ASM_STACKTRACE_H 3 3 #define __ASM_STACKTRACE_H 4 4 5 - #include <asm/ptrace.h> 6 5 #include <linux/llist.h> 6 + #include <asm/ptrace.h> 7 + #include <asm/sections.h> 7 8 8 9 struct stackframe { 9 10 /*
+4
arch/arm/mach-at91/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 + config ARCH_MICROCHIP 3 + bool 4 + 2 5 menuconfig ARCH_AT91 3 6 bool "AT91/Microchip SoCs" 4 7 depends on (CPU_LITTLE_ENDIAN && (ARCH_MULTI_V4T || ARCH_MULTI_V5)) || \ ··· 11 8 select GPIOLIB 12 9 select PINCTRL 13 10 select SOC_BUS 11 + select ARCH_MICROCHIP 14 12 15 13 if ARCH_AT91 16 14 config SOC_SAMV7
+3
arch/arm64/boot/dts/axiado/ax3000-evk.dts
··· 14 14 #size-cells = <2>; 15 15 16 16 aliases { 17 + serial0 = &uart0; 18 + serial1 = &uart1; 19 + serial2 = &uart2; 17 20 serial3 = &uart3; 18 21 }; 19 22
+1
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
··· 555 555 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 556 556 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 557 557 vmmc-supply = <&reg_usdhc2_vmmc>; 558 + vqmmc-supply = <&ldo5>; 558 559 bus-width = <4>; 559 560 status = "okay"; 560 561 };
+1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
··· 609 609 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 610 610 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 611 611 vmmc-supply = <&reg_usdhc2_vmmc>; 612 + vqmmc-supply = <&ldo5>; 612 613 bus-width = <4>; 613 614 status = "okay"; 614 615 };
+7 -6
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
··· 467 467 status = "okay"; 468 468 }; 469 469 470 + &reg_usdhc2_vqmmc { 471 + status = "okay"; 472 + }; 473 + 470 474 &sai5 { 471 475 pinctrl-names = "default"; 472 476 pinctrl-0 = <&pinctrl_sai5>; ··· 880 876 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 881 877 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 882 878 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 883 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 884 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 879 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 885 880 }; 886 881 887 882 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ··· 889 886 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 890 887 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 891 888 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 892 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 893 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 889 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 894 890 }; 895 891 896 892 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ··· 898 896 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 899 897 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 900 898 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 901 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 902 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 899 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 903 900 }; 904 901 905 902 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+7 -6
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
··· 604 604 status = "okay"; 605 605 }; 606 606 607 + &reg_usdhc2_vqmmc { 608 + status = "okay"; 609 + }; 610 + 607 611 &sai3 { 608 612 pinctrl-names = "default"; 609 613 pinctrl-0 = <&pinctrl_sai3>; ··· 987 983 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 988 984 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 989 985 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 990 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 991 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 986 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>; 992 987 }; 993 988 994 989 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { ··· 996 993 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 997 994 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 998 995 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 999 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1000 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 996 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1001 997 }; 1002 998 1003 999 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { ··· 1005 1003 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1006 1004 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1007 1005 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1008 - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1009 - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 1006 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1010 1007 }; 1011 1008 1012 1009 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+22 -9
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
··· 16 16 reg = <0x0 0x40000000 0 0x80000000>; 17 17 }; 18 18 19 - /* identical to buck4_reg, but should never change */ 20 - reg_vcc3v3: regulator-vcc3v3 { 21 - compatible = "regulator-fixed"; 22 - regulator-name = "VCC3V3"; 23 - regulator-min-microvolt = <3300000>; 19 + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 20 + compatible = "regulator-gpio"; 21 + pinctrl-names = "default"; 22 + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; 23 + regulator-name = "V_SD2"; 24 + regulator-min-microvolt = <1800000>; 24 25 regulator-max-microvolt = <3300000>; 25 - regulator-always-on; 26 + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 27 + states = <1800000 0x1>, 28 + <3300000 0x0>; 29 + vin-supply = <&ldo5_reg>; 30 + status = "disabled"; 26 31 }; 27 32 }; 28 33 ··· 178 173 read-only; 179 174 reg = <0x53>; 180 175 pagesize = <16>; 181 - vcc-supply = <&reg_vcc3v3>; 176 + vcc-supply = <&buck4_reg>; 182 177 }; 183 178 184 179 m24c64: eeprom@57 { 185 180 compatible = "atmel,24c64"; 186 181 reg = <0x57>; 187 182 pagesize = <32>; 188 - vcc-supply = <&reg_vcc3v3>; 183 + vcc-supply = <&buck4_reg>; 189 184 }; 185 + }; 186 + 187 + &usdhc2 { 188 + vqmmc-supply = <&reg_usdhc2_vqmmc>; 190 189 }; 191 190 192 191 &usdhc3 { ··· 202 193 non-removable; 203 194 no-sd; 204 195 no-sdio; 205 - vmmc-supply = <&reg_vcc3v3>; 196 + vmmc-supply = <&buck4_reg>; 206 197 vqmmc-supply = <&buck5_reg>; 207 198 status = "okay"; 208 199 }; ··· 240 231 241 232 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 242 233 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; 234 + }; 235 + 236 + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { 237 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>; 243 238 }; 244 239 245 240 pinctrl_usdhc3: usdhc3grp {
+5 -5
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
··· 80 80 flexcan1_phy: can-phy0 { 81 81 compatible = "nxp,tjr1443"; 82 82 #phy-cells = <0>; 83 - max-bitrate = <1000000>; 83 + max-bitrate = <8000000>; 84 84 enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>; 85 - standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>; 85 + standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_LOW>; 86 86 }; 87 87 88 88 flexcan2_phy: can-phy1 { 89 89 compatible = "nxp,tjr1443"; 90 90 #phy-cells = <0>; 91 - max-bitrate = <1000000>; 92 - enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>; 93 - standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>; 91 + max-bitrate = <8000000>; 92 + enable-gpios = <&i2c4_gpio_expander_21 4 GPIO_ACTIVE_HIGH>; 93 + standby-gpios = <&i2c4_gpio_expander_21 3 GPIO_ACTIVE_LOW>; 94 94 }; 95 95 96 96 reg_vref_1v8: regulator-1p8v {
+1 -1
arch/arm64/boot/dts/freescale/imx95.dtsi
··· 1843 1843 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 1844 1844 clocks = <&scmi_clk IMX95_CLK_VPU>, 1845 1845 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 1846 - assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1846 + assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 1847 1847 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 1848 1848 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1849 1849 };
+4 -4
arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi
··· 72 72 }; 73 73 74 74 vcc_cam_avdd: regulator-vcc-cam-avdd { 75 - compatible = "regulator-fixed"; 75 + compatible = "regulator-fixed"; 76 76 regulator-name = "vcc_cam_avdd"; 77 77 gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; 78 78 pinctrl-names = "default"; ··· 83 83 }; 84 84 85 85 vcc_cam_dovdd: regulator-vcc-cam-dovdd { 86 - compatible = "regulator-fixed"; 86 + compatible = "regulator-fixed"; 87 87 regulator-name = "vcc_cam_dovdd"; 88 88 gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; 89 89 pinctrl-names = "default"; ··· 94 94 }; 95 95 96 96 vcc_cam_dvdd: regulator-vcc-cam-dvdd { 97 - compatible = "regulator-fixed"; 97 + compatible = "regulator-fixed"; 98 98 regulator-name = "vcc_cam_dvdd"; 99 99 gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 100 100 enable-active-high; ··· 106 106 }; 107 107 108 108 vcc_lens_afvdd: regulator-vcc-lens-afvdd { 109 - compatible = "regulator-fixed"; 109 + compatible = "regulator-fixed"; 110 110 regulator-name = "vcc_lens_afvdd"; 111 111 gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; 112 112 pinctrl-names = "default";
+3 -3
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso
··· 26 26 }; 27 27 28 28 cam_afvdd_2v8: regulator-cam-afvdd-2v8 { 29 - compatible = "regulator-fixed"; 29 + compatible = "regulator-fixed"; 30 30 gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; 31 31 regulator-max-microvolt = <2800000>; 32 32 regulator-min-microvolt = <2800000>; ··· 35 35 }; 36 36 37 37 cam_avdd_2v8: regulator-cam-avdd-2v8 { 38 - compatible = "regulator-fixed"; 38 + compatible = "regulator-fixed"; 39 39 gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; 40 40 regulator-max-microvolt = <2800000>; 41 41 regulator-min-microvolt = <2800000>; ··· 44 44 }; 45 45 46 46 cam_dovdd_1v8: regulator-cam-dovdd-1v8 { 47 - compatible = "regulator-fixed"; 47 + compatible = "regulator-fixed"; 48 48 gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; 49 49 regulator-max-microvolt = <1800000>; 50 50 regulator-min-microvolt = <1800000>;
+1 -1
arch/arm64/boot/dts/rockchip/rk3308-sakurapi-rk3308b.dts
··· 260 260 status = "okay"; 261 261 }; 262 262 263 - &usb_host_ohci{ 263 + &usb_host_ohci { 264 264 status = "okay"; 265 265 };
+1 -1
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts
··· 609 609 610 610 bluetooth { 611 611 compatible = "brcm,bcm4345c5"; 612 - interrupts-extended = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 612 + interrupts-extended = <&gpio3 RK_PA7 IRQ_TYPE_LEVEL_HIGH>; 613 613 interrupt-names = "host-wakeup"; 614 614 clocks = <&rk808 RK808_CLKOUT1>; 615 615 clock-names = "lpo";
+1
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
··· 959 959 reg = <0>; 960 960 m25p,fast-read; 961 961 spi-max-frequency = <10000000>; 962 + vcc-supply = <&vcc_3v0>; 962 963 }; 963 964 }; 964 965
+1
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
··· 754 754 compatible = "jedec,spi-nor"; 755 755 reg = <0>; 756 756 spi-max-frequency = <10000000>; 757 + vcc-supply = <&vcc_1v8>; 757 758 }; 758 759 }; 759 760
+3 -3
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou-video-demo.dtso
··· 26 26 }; 27 27 28 28 cam_afvdd_2v8: regulator-cam-afvdd-2v8 { 29 - compatible = "regulator-fixed"; 29 + compatible = "regulator-fixed"; 30 30 gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; 31 31 regulator-max-microvolt = <2800000>; 32 32 regulator-min-microvolt = <2800000>; ··· 35 35 }; 36 36 37 37 cam_avdd_2v8: regulator-cam-avdd-2v8 { 38 - compatible = "regulator-fixed"; 38 + compatible = "regulator-fixed"; 39 39 gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; 40 40 regulator-max-microvolt = <2800000>; 41 41 regulator-min-microvolt = <2800000>; ··· 44 44 }; 45 45 46 46 cam_dovdd_1v8: regulator-cam-dovdd-1v8 { 47 - compatible = "regulator-fixed"; 47 + compatible = "regulator-fixed"; 48 48 gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; 49 49 regulator-max-microvolt = <1800000>; 50 50 regulator-min-microvolt = <1800000>;
+2 -2
arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi
··· 53 53 gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; 54 54 linux,default-trigger = "default-on"; 55 55 pinctrl-names = "default"; 56 - pinctrl-0 =<&blue_led>; 56 + pinctrl-0 = <&blue_led>; 57 57 }; 58 58 59 59 led-1 { ··· 62 62 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; 63 63 linux,default-trigger = "heartbeat"; 64 64 pinctrl-names = "default"; 65 - pinctrl-0 =<&heartbeat_led>; 65 + pinctrl-0 = <&heartbeat_led>; 66 66 }; 67 67 }; 68 68
+1 -4
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
··· 302 302 &eth1m0_tx_bus2 303 303 &eth1m0_rx_bus2 304 304 &eth1m0_rgmii_clk 305 - &eth1m0_rgmii_bus 306 - &ethm0_clk1_25m_out>; 305 + &eth1m0_rgmii_bus>; 307 306 status = "okay"; 308 307 }; 309 308 ··· 783 784 rgmii_phy0: phy@1 { 784 785 compatible = "ethernet-phy-ieee802.3-c22"; 785 786 reg = <0x1>; 786 - clocks = <&cru REFCLKO25M_GMAC0_OUT>; 787 787 pinctrl-names = "default"; 788 788 pinctrl-0 = <&gmac0_rst>; 789 789 reset-assert-us = <20000>; ··· 795 797 rgmii_phy1: phy@1 { 796 798 compatible = "ethernet-phy-ieee802.3-c22"; 797 799 reg = <0x1>; 798 - clocks = <&cru REFCLKO25M_GMAC1_OUT>; 799 800 pinctrl-names = "default"; 800 801 pinctrl-0 = <&gmac1_rst>; 801 802 reset-assert-us = <20000>;
+1
arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
··· 250 250 compatible = "belling,bl24c16a", "atmel,24c16"; 251 251 reg = <0x50>; 252 252 pagesize = <16>; 253 + read-only; 253 254 vcc-supply = <&vcc_3v3_pmu>; 254 255 }; 255 256 };
+1 -1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
··· 77 77 pinctrl-names = "default"; 78 78 pinctrl-0 = <&hp_detect>; 79 79 simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; 80 - simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; 80 + simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 81 81 simple-audio-card,widgets = 82 82 "Microphone", "Onboard Microphone", 83 83 "Microphone", "Microphone Jack",
+2
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
··· 365 365 max-frequency = <200000000>; 366 366 mmc-hs400-1_8v; 367 367 mmc-hs400-enhanced-strobe; 368 + vmmc-supply = <&vcc_3v3_s3>; 369 + vqmmc-supply = <&vcc_1v8_s3>; 368 370 status = "okay"; 369 371 }; 370 372
+35
arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
··· 68 68 status = "okay"; 69 69 }; 70 70 71 + &pcie30phy { 72 + data-lanes = <1 1 2 2>; 73 + }; 74 + 75 + &pcie3x2 { 76 + pinctrl-names = "default"; 77 + pinctrl-0 = <&pcie3x2_rst>; 78 + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 79 + vpcie3v3-supply = <&vcc3v3_pcie30>; 80 + status = "okay"; 81 + }; 82 + 83 + &pcie3x4 { 84 + num-lanes = <2>; 85 + }; 86 + 71 87 &pinctrl { 72 88 hdmirx { 73 89 hdmirx_hpd: hdmirx-5v-detection { ··· 106 90 }; 107 91 }; 108 92 93 + pcie3 { 94 + pcie3x2_rst: pcie3x2-rst { 95 + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 96 + }; 97 + }; 98 + 109 99 sound { 110 100 hp_detect: hp-detect { 111 101 rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 102 + }; 103 + }; 104 + 105 + usb { 106 + vcc5v0_host_en: vcc5v0-host-en { 107 + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 112 108 }; 113 109 }; 114 110 }; ··· 130 102 pinctrl-names = "default"; 131 103 pinctrl-0 = <&pcie2_0_vcc3v3_en>; 132 104 status = "okay"; 105 + }; 106 + 107 + &vcc5v0_host { 108 + enable-active-high; 109 + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; 110 + pinctrl-names = "default"; 111 + pinctrl-0 = <&vcc5v0_host_en>; 133 112 };
+2 -2
arch/arm64/boot/dts/rockchip/rk3588j.dtsi
··· 28 28 compatible = "operating-points-v2"; 29 29 opp-shared; 30 30 31 - opp-1200000000{ 31 + opp-1200000000 { 32 32 opp-hz = /bits/ 64 <1200000000>; 33 33 opp-microvolt = <750000 750000 950000>; 34 34 clock-latency-ns = <40000>; ··· 49 49 compatible = "operating-points-v2"; 50 50 opp-shared; 51 51 52 - opp-1200000000{ 52 + opp-1200000000 { 53 53 opp-hz = /bits/ 64 <1200000000>; 54 54 opp-microvolt = <750000 750000 950000>; 55 55 clock-latency-ns = <40000>;
+2 -2
arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts
··· 320 320 &i2c3 { 321 321 status = "okay"; 322 322 323 - es8388: audio-codec@10 { 323 + es8388: audio-codec@11 { 324 324 compatible = "everest,es8388", "everest,es8328"; 325 - reg = <0x10>; 325 + reg = <0x11>; 326 326 clocks = <&cru I2S1_8CH_MCLKOUT>; 327 327 AVDD-supply = <&vcc_3v3_s0>; 328 328 DVDD-supply = <&vcc_1v8_s0>;
+2 -109
arch/arm64/include/asm/kvm_host.h
··· 1160 1160 __v; \ 1161 1161 }) 1162 1162 1163 - u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 1164 - void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 1165 - 1166 - static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 1167 - { 1168 - /* 1169 - * *** VHE ONLY *** 1170 - * 1171 - * System registers listed in the switch are not saved on every 1172 - * exit from the guest but are only saved on vcpu_put. 1173 - * 1174 - * SYSREGS_ON_CPU *MUST* be checked before using this helper. 1175 - * 1176 - * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1177 - * should never be listed below, because the guest cannot modify its 1178 - * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 1179 - * thread when emulating cross-VCPU communication. 1180 - */ 1181 - if (!has_vhe()) 1182 - return false; 1183 - 1184 - switch (reg) { 1185 - case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 1186 - case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 1187 - case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 1188 - case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 1189 - case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 1190 - case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break; 1191 - case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break; 1192 - case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break; 1193 - case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break; 1194 - case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 1195 - case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 1196 - case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 1197 - case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 1198 - case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 1199 - case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 1200 - case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 1201 - case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 1202 - case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 1203 - case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 1204 - case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 1205 - case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 1206 - case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 1207 - case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break; 1208 - case PAR_EL1: *val = read_sysreg_par(); break; 1209 - case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 1210 - case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 1211 - case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 1212 - case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break; 1213 - case SCTLR2_EL1: *val = read_sysreg_s(SYS_SCTLR2_EL12); break; 1214 - default: return false; 1215 - } 1216 - 1217 - return true; 1218 - } 1219 - 1220 - static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 1221 - { 1222 - /* 1223 - * *** VHE ONLY *** 1224 - * 1225 - * System registers listed in the switch are not restored on every 1226 - * entry to the guest but are only restored on vcpu_load. 1227 - * 1228 - * SYSREGS_ON_CPU *MUST* be checked before using this helper. 1229 - * 1230 - * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1231 - * should never be listed below, because the MPIDR should only be set 1232 - * once, before running the VCPU, and never changed later. 1233 - */ 1234 - if (!has_vhe()) 1235 - return false; 1236 - 1237 - switch (reg) { 1238 - case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 1239 - case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 1240 - case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 1241 - case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 1242 - case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 1243 - case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 1244 - case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 1245 - case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 1246 - case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; 1247 - case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 1248 - case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 1249 - case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 1250 - case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 1251 - case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 1252 - case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 1253 - case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 1254 - case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 1255 - case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 1256 - case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 1257 - case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 1258 - case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 1259 - case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 1260 - case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 1261 - case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 1262 - case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 1263 - case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 1264 - case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 1265 - case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 1266 - case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; 1267 - default: return false; 1268 - } 1269 - 1270 - return true; 1271 - } 1163 + u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg); 1164 + void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg); 1272 1165 1273 1166 struct kvm_vm_stat { 1274 1167 struct kvm_vm_stat_generic generic;
+1
arch/arm64/include/asm/kvm_mmu.h
··· 180 180 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, 181 181 phys_addr_t pa, unsigned long size, bool writable); 182 182 183 + int kvm_handle_guest_sea(struct kvm_vcpu *vcpu); 183 184 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); 184 185 185 186 phys_addr_t kvm_mmu_get_httbr(void);
+30
arch/arm64/include/asm/kvm_pgtable.h
··· 355 355 return pteref; 356 356 } 357 357 358 + static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref) 359 + { 360 + return pteref; 361 + } 362 + 358 363 static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker) 359 364 { 360 365 /* ··· 387 382 kvm_pteref_t pteref) 388 383 { 389 384 return rcu_dereference_check(pteref, !(walker->flags & KVM_PGTABLE_WALK_SHARED)); 385 + } 386 + 387 + static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref) 388 + { 389 + return rcu_dereference_raw(pteref); 390 390 } 391 391 392 392 static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker) ··· 560 550 * to freeing and therefore no TLB invalidation is performed. 561 551 */ 562 552 void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt); 553 + 554 + /** 555 + * kvm_pgtable_stage2_destroy_range() - Destroy the unlinked range of addresses. 556 + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*(). 557 + * @addr: Intermediate physical address at which to place the mapping. 558 + * @size: Size of the mapping. 559 + * 560 + * The page-table is assumed to be unreachable by any hardware walkers prior 561 + * to freeing and therefore no TLB invalidation is performed. 562 + */ 563 + void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, 564 + u64 addr, u64 size); 565 + 566 + /** 567 + * kvm_pgtable_stage2_destroy_pgd() - Destroy the PGD of guest stage-2 page-table. 568 + * @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*(). 569 + * 570 + * It is assumed that the rest of the page-table is freed before this operation. 571 + */ 572 + void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt); 563 573 564 574 /** 565 575 * kvm_pgtable_stage2_free_unlinked() - Free an unlinked stage-2 paging structure.
+3 -1
arch/arm64/include/asm/kvm_pkvm.h
··· 179 179 180 180 int pkvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2_mmu *mmu, 181 181 struct kvm_pgtable_mm_ops *mm_ops); 182 - void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt); 182 + void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, 183 + u64 addr, u64 size); 184 + void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt); 183 185 int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys, 184 186 enum kvm_pgtable_prot prot, void *mc, 185 187 enum kvm_pgtable_walk_flags flags);
-25
arch/arm64/include/asm/kvm_ras.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* Copyright (C) 2018 - Arm Ltd */ 3 - 4 - #ifndef __ARM64_KVM_RAS_H__ 5 - #define __ARM64_KVM_RAS_H__ 6 - 7 - #include <linux/acpi.h> 8 - #include <linux/errno.h> 9 - #include <linux/types.h> 10 - 11 - #include <asm/acpi.h> 12 - 13 - /* 14 - * Was this synchronous external abort a RAS notification? 15 - * Returns '0' for errors handled by some RAS subsystem, or -ENOENT. 16 - */ 17 - static inline int kvm_handle_guest_sea(void) 18 - { 19 - /* apei_claim_sea(NULL) expects to mask interrupts itself */ 20 - lockdep_assert_irqs_enabled(); 21 - 22 - return apei_claim_sea(NULL); 23 - } 24 - 25 - #endif /* __ARM64_KVM_RAS_H__ */
+7
arch/arm64/include/asm/mmu.h
··· 17 17 #include <linux/refcount.h> 18 18 #include <asm/cpufeature.h> 19 19 20 + enum pgtable_type { 21 + TABLE_PTE, 22 + TABLE_PMD, 23 + TABLE_PUD, 24 + TABLE_P4D, 25 + }; 26 + 20 27 typedef struct { 21 28 atomic64_t id; 22 29 #ifdef CONFIG_COMPAT
-3
arch/arm64/include/asm/sysreg.h
··· 1142 1142 1143 1143 #define ARM64_FEATURE_FIELD_BITS 4 1144 1144 1145 - /* Defined for compatibility only, do not add new users. */ 1146 - #define ARM64_FEATURE_MASK(x) (x##_MASK) 1147 - 1148 1145 #ifdef __ASSEMBLY__ 1149 1146 1150 1147 .macro mrs_s, rt, sreg
+27 -2
arch/arm64/kernel/cpufeature.c
··· 84 84 #include <asm/hwcap.h> 85 85 #include <asm/insn.h> 86 86 #include <asm/kvm_host.h> 87 + #include <asm/mmu.h> 87 88 #include <asm/mmu_context.h> 88 89 #include <asm/mte.h> 89 90 #include <asm/hypervisor.h> ··· 1946 1945 extern 1947 1946 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1948 1947 phys_addr_t size, pgprot_t prot, 1949 - phys_addr_t (*pgtable_alloc)(int), int flags); 1948 + phys_addr_t (*pgtable_alloc)(enum pgtable_type), int flags); 1950 1949 1951 1950 static phys_addr_t __initdata kpti_ng_temp_alloc; 1952 1951 1953 - static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1952 + static phys_addr_t __init kpti_ng_pgd_alloc(enum pgtable_type type) 1954 1953 { 1955 1954 kpti_ng_temp_alloc -= PAGE_SIZE; 1956 1955 return kpti_ng_temp_alloc; ··· 2269 2268 { 2270 2269 /* Firmware may have left a deferred SError in this register. */ 2271 2270 write_sysreg_s(0, SYS_DISR_EL1); 2271 + } 2272 + static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2273 + { 2274 + const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2275 + { 2276 + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2277 + }, 2278 + { 2279 + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2280 + }, 2281 + { 2282 + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2283 + }, 2284 + }; 2285 + 2286 + return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2287 + (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2288 + has_cpuid_feature(&rasv1p1_caps[2], scope))); 2272 2289 } 2273 2290 #endif /* CONFIG_ARM64_RAS_EXTN */ 2274 2291 ··· 2705 2686 .matches = has_cpuid_feature, 2706 2687 .cpu_enable = cpu_clear_disr, 2707 2688 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2689 + }, 2690 + { 2691 + .desc = "RASv1p1 Extension Support", 2692 + .capability = ARM64_HAS_RASV1P1_EXTN, 2693 + .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2694 + .matches = has_rasv1p1, 2708 2695 }, 2709 2696 #endif /* CONFIG_ARM64_RAS_EXTN */ 2710 2697 #ifdef CONFIG_ARM64_AMU_EXTN
+4 -4
arch/arm64/kvm/arm.c
··· 2408 2408 */ 2409 2409 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 2410 2410 2411 - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | 2412 - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); 2411 + val &= ~(ID_AA64PFR0_EL1_CSV2 | 2412 + ID_AA64PFR0_EL1_CSV3); 2413 2413 2414 - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), 2414 + val |= FIELD_PREP(ID_AA64PFR0_EL1_CSV2, 2415 2415 arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED); 2416 - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), 2416 + val |= FIELD_PREP(ID_AA64PFR0_EL1_CSV3, 2417 2417 arm64_get_meltdown_state() == SPECTRE_UNAFFECTED); 2418 2418 2419 2419 return val;
+3 -3
arch/arm64/kvm/at.c
··· 1420 1420 return; 1421 1421 1422 1422 /* 1423 - * If we only have a single stage of translation (E2H=0 or 1424 - * TGE=1), exit early. Same thing if {VM,DC}=={0,0}. 1423 + * If we only have a single stage of translation (EL2&0), exit 1424 + * early. Same thing if {VM,DC}=={0,0}. 1425 1425 */ 1426 - if (!vcpu_el2_e2h_is_set(vcpu) || vcpu_el2_tge_is_set(vcpu) || 1426 + if (compute_translation_regime(vcpu, op) == TR_EL20 || 1427 1427 !(vcpu_read_sys_reg(vcpu, HCR_EL2) & (HCR_VM | HCR_DC))) 1428 1428 return; 1429 1429
+1 -1
arch/arm64/kvm/emulate-nested.c
··· 2833 2833 iabt ? ESR_ELx_EC_IABT_LOW : ESR_ELx_EC_DABT_LOW); 2834 2834 esr |= ESR_ELx_FSC_EXTABT | ESR_ELx_IL; 2835 2835 2836 - vcpu_write_sys_reg(vcpu, FAR_EL2, addr); 2836 + vcpu_write_sys_reg(vcpu, addr, FAR_EL2); 2837 2837 2838 2838 if (__vcpu_sys_reg(vcpu, SCTLR2_EL2) & SCTLR2_EL1_EASE) 2839 2839 return kvm_inject_nested(vcpu, esr, except_type_serror);
+6 -14
arch/arm64/kvm/hyp/exception.c
··· 22 22 23 23 static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 24 24 { 25 - u64 val; 26 - 27 - if (unlikely(vcpu_has_nv(vcpu))) 25 + if (has_vhe()) 28 26 return vcpu_read_sys_reg(vcpu, reg); 29 - else if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) && 30 - __vcpu_read_sys_reg_from_cpu(reg, &val)) 31 - return val; 32 27 33 28 return __vcpu_sys_reg(vcpu, reg); 34 29 } 35 30 36 31 static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 37 32 { 38 - if (unlikely(vcpu_has_nv(vcpu))) 33 + if (has_vhe()) 39 34 vcpu_write_sys_reg(vcpu, val, reg); 40 - else if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU) || 41 - !__vcpu_write_sys_reg_to_cpu(val, reg)) 35 + else 42 36 __vcpu_assign_sys_reg(vcpu, reg, val); 43 37 } 44 38 45 39 static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode, 46 40 u64 val) 47 41 { 48 - if (unlikely(vcpu_has_nv(vcpu))) { 42 + if (has_vhe()) { 49 43 if (target_mode == PSR_MODE_EL1h) 50 44 vcpu_write_sys_reg(vcpu, val, SPSR_EL1); 51 45 else 52 46 vcpu_write_sys_reg(vcpu, val, SPSR_EL2); 53 - } else if (has_vhe()) { 54 - write_sysreg_el1(val, SYS_SPSR); 55 47 } else { 56 48 __vcpu_assign_sys_reg(vcpu, SPSR_EL1, val); 57 49 } ··· 51 59 52 60 static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val) 53 61 { 54 - if (has_vhe()) 62 + if (has_vhe() && vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 55 63 write_sysreg(val, spsr_abt); 56 64 else 57 65 vcpu->arch.ctxt.spsr_abt = val; ··· 59 67 60 68 static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val) 61 69 { 62 - if (has_vhe()) 70 + if (has_vhe() && vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 63 71 write_sysreg(val, spsr_und); 64 72 else 65 73 vcpu->arch.ctxt.spsr_und = val;
+1 -1
arch/arm64/kvm/hyp/nvhe/list_debug.c
··· 17 17 bool corruption = unlikely(condition); \ 18 18 if (corruption) { \ 19 19 if (IS_ENABLED(CONFIG_BUG_ON_DATA_CORRUPTION)) { \ 20 - BUG_ON(1); \ 20 + BUG(); \ 21 21 } else \ 22 22 WARN_ON(1); \ 23 23 } \
+5
arch/arm64/kvm/hyp/nvhe/sys_regs.c
··· 253 253 254 254 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR); 255 255 *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR); 256 + __vcpu_assign_sys_reg(vcpu, read_sysreg_el1(SYS_VBAR), VBAR_EL1); 256 257 257 258 kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC); 258 259 ··· 373 372 374 373 /* Debug and Trace Registers are restricted. */ 375 374 375 + /* Group 1 ID registers */ 376 + HOST_HANDLED(SYS_REVIDR_EL1), 377 + 376 378 /* AArch64 mappings of the AArch32 ID registers */ 377 379 /* CRm=1 */ 378 380 AARCH32(SYS_ID_PFR0_EL1), ··· 464 460 465 461 HOST_HANDLED(SYS_CCSIDR_EL1), 466 462 HOST_HANDLED(SYS_CLIDR_EL1), 463 + HOST_HANDLED(SYS_AIDR_EL1), 467 464 HOST_HANDLED(SYS_CSSELR_EL1), 468 465 HOST_HANDLED(SYS_CTR_EL0), 469 466
+21 -4
arch/arm64/kvm/hyp/pgtable.c
··· 1551 1551 return 0; 1552 1552 } 1553 1553 1554 - void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) 1554 + void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, 1555 + u64 addr, u64 size) 1555 1556 { 1556 - size_t pgd_sz; 1557 1557 struct kvm_pgtable_walker walker = { 1558 1558 .cb = stage2_free_walker, 1559 1559 .flags = KVM_PGTABLE_WALK_LEAF | 1560 1560 KVM_PGTABLE_WALK_TABLE_POST, 1561 1561 }; 1562 1562 1563 - WARN_ON(kvm_pgtable_walk(pgt, 0, BIT(pgt->ia_bits), &walker)); 1563 + WARN_ON(kvm_pgtable_walk(pgt, addr, size, &walker)); 1564 + } 1565 + 1566 + void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt) 1567 + { 1568 + size_t pgd_sz; 1569 + 1564 1570 pgd_sz = kvm_pgd_pages(pgt->ia_bits, pgt->start_level) * PAGE_SIZE; 1565 - pgt->mm_ops->free_pages_exact(kvm_dereference_pteref(&walker, pgt->pgd), pgd_sz); 1571 + 1572 + /* 1573 + * Since the pgtable is unlinked at this point, and not shared with 1574 + * other walkers, safely deference pgd with kvm_dereference_pteref_raw() 1575 + */ 1576 + pgt->mm_ops->free_pages_exact(kvm_dereference_pteref_raw(pgt->pgd), pgd_sz); 1566 1577 pgt->pgd = NULL; 1578 + } 1579 + 1580 + void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) 1581 + { 1582 + kvm_pgtable_stage2_destroy_range(pgt, 0, BIT(pgt->ia_bits)); 1583 + kvm_pgtable_stage2_destroy_pgd(pgt); 1567 1584 } 1568 1585 1569 1586 void kvm_pgtable_stage2_free_unlinked(struct kvm_pgtable_mm_ops *mm_ops, void *pgtable, s8 level)
+1 -1
arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c
··· 20 20 if (vcpu_mode_is_32bit(vcpu)) 21 21 return !!(read_sysreg_el2(SYS_SPSR) & PSR_AA32_E_BIT); 22 22 23 - return !!(read_sysreg(SCTLR_EL1) & SCTLR_ELx_EE); 23 + return !!(read_sysreg_el1(SYS_SCTLR) & SCTLR_ELx_EE); 24 24 } 25 25 26 26 /*
+4 -1
arch/arm64/kvm/hyp/vhe/switch.c
··· 43 43 * 44 44 * - API/APK: they are already accounted for by vcpu_load(), and can 45 45 * only take effect across a load/put cycle (such as ERET) 46 + * 47 + * - FIEN: no way we let a guest have access to the RAS "Common Fault 48 + * Injection" thing, whatever that does 46 49 */ 47 - #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK) 50 + #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK | HCR_FIEN) 48 51 49 52 static u64 __compute_hcr(struct kvm_vcpu *vcpu) 50 53 {
+51 -14
arch/arm64/kvm/mmu.c
··· 4 4 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 5 5 */ 6 6 7 + #include <linux/acpi.h> 7 8 #include <linux/mman.h> 8 9 #include <linux/kvm_host.h> 9 10 #include <linux/io.h> 10 11 #include <linux/hugetlb.h> 11 12 #include <linux/sched/signal.h> 12 13 #include <trace/events/kvm.h> 14 + #include <asm/acpi.h> 13 15 #include <asm/pgalloc.h> 14 16 #include <asm/cacheflush.h> 15 17 #include <asm/kvm_arm.h> 16 18 #include <asm/kvm_mmu.h> 17 19 #include <asm/kvm_pgtable.h> 18 20 #include <asm/kvm_pkvm.h> 19 - #include <asm/kvm_ras.h> 20 21 #include <asm/kvm_asm.h> 21 22 #include <asm/kvm_emulate.h> 22 23 #include <asm/virt.h> ··· 904 903 return 0; 905 904 } 906 905 906 + /* 907 + * Assume that @pgt is valid and unlinked from the KVM MMU to free the 908 + * page-table without taking the kvm_mmu_lock and without performing any 909 + * TLB invalidations. 910 + * 911 + * Also, the range of addresses can be large enough to cause need_resched 912 + * warnings, for instance on CONFIG_PREEMPT_NONE kernels. Hence, invoke 913 + * cond_resched() periodically to prevent hogging the CPU for a long time 914 + * and schedule something else, if required. 915 + */ 916 + static void stage2_destroy_range(struct kvm_pgtable *pgt, phys_addr_t addr, 917 + phys_addr_t end) 918 + { 919 + u64 next; 920 + 921 + do { 922 + next = stage2_range_addr_end(addr, end); 923 + KVM_PGT_FN(kvm_pgtable_stage2_destroy_range)(pgt, addr, 924 + next - addr); 925 + if (next != end) 926 + cond_resched(); 927 + } while (addr = next, addr != end); 928 + } 929 + 930 + static void kvm_stage2_destroy(struct kvm_pgtable *pgt) 931 + { 932 + unsigned int ia_bits = VTCR_EL2_IPA(pgt->mmu->vtcr); 933 + 934 + stage2_destroy_range(pgt, 0, BIT(ia_bits)); 935 + KVM_PGT_FN(kvm_pgtable_stage2_destroy_pgd)(pgt); 936 + } 937 + 907 938 /** 908 939 * kvm_init_stage2_mmu - Initialise a S2 MMU structure 909 940 * @kvm: The pointer to the KVM structure ··· 1012 979 return 0; 1013 980 1014 981 out_destroy_pgtable: 1015 - KVM_PGT_FN(kvm_pgtable_stage2_destroy)(pgt); 982 + kvm_stage2_destroy(pgt); 1016 983 out_free_pgtable: 1017 984 kfree(pgt); 1018 985 return err; ··· 1109 1076 write_unlock(&kvm->mmu_lock); 1110 1077 1111 1078 if (pgt) { 1112 - KVM_PGT_FN(kvm_pgtable_stage2_destroy)(pgt); 1079 + kvm_stage2_destroy(pgt); 1113 1080 kfree(pgt); 1114 1081 } 1115 1082 } ··· 1844 1811 read_unlock(&vcpu->kvm->mmu_lock); 1845 1812 } 1846 1813 1814 + int kvm_handle_guest_sea(struct kvm_vcpu *vcpu) 1815 + { 1816 + /* 1817 + * Give APEI the opportunity to claim the abort before handling it 1818 + * within KVM. apei_claim_sea() expects to be called with IRQs enabled. 1819 + */ 1820 + lockdep_assert_irqs_enabled(); 1821 + if (apei_claim_sea(NULL) == 0) 1822 + return 1; 1823 + 1824 + return kvm_inject_serror(vcpu); 1825 + } 1826 + 1847 1827 /** 1848 1828 * kvm_handle_guest_abort - handles all 2nd stage aborts 1849 1829 * @vcpu: the VCPU pointer ··· 1880 1834 gfn_t gfn; 1881 1835 int ret, idx; 1882 1836 1883 - /* Synchronous External Abort? */ 1884 - if (kvm_vcpu_abt_issea(vcpu)) { 1885 - /* 1886 - * For RAS the host kernel may handle this abort. 1887 - * There is no need to pass the error into the guest. 1888 - */ 1889 - if (kvm_handle_guest_sea()) 1890 - return kvm_inject_serror(vcpu); 1891 - 1892 - return 1; 1893 - } 1837 + if (kvm_vcpu_abt_issea(vcpu)) 1838 + return kvm_handle_guest_sea(vcpu); 1894 1839 1895 1840 esr = kvm_vcpu_get_esr(vcpu); 1896 1841
+4 -1
arch/arm64/kvm/nested.c
··· 1287 1287 struct vncr_tlb *vt = vcpu->arch.vncr_tlb; 1288 1288 u64 esr = kvm_vcpu_get_esr(vcpu); 1289 1289 1290 - BUG_ON(!(esr & ESR_ELx_VNCR_SHIFT)); 1290 + WARN_ON_ONCE(!(esr & ESR_ELx_VNCR)); 1291 + 1292 + if (kvm_vcpu_abt_issea(vcpu)) 1293 + return kvm_handle_guest_sea(vcpu); 1291 1294 1292 1295 if (esr_fsc_is_permission_fault(esr)) { 1293 1296 inject_vncr_perm(vcpu);
+9 -2
arch/arm64/kvm/pkvm.c
··· 316 316 return 0; 317 317 } 318 318 319 - void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt) 319 + void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt, 320 + u64 addr, u64 size) 320 321 { 321 - __pkvm_pgtable_stage2_unmap(pgt, 0, ~(0ULL)); 322 + __pkvm_pgtable_stage2_unmap(pgt, addr, addr + size); 323 + } 324 + 325 + void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt) 326 + { 327 + /* Expected to be called after all pKVM mappings have been released. */ 328 + WARN_ON_ONCE(!RB_EMPTY_ROOT(&pgt->pkvm_mappings.rb_root)); 322 329 } 323 330 324 331 int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
+293 -138
arch/arm64/kvm/sys_regs.c
··· 82 82 "sys_reg write to read-only register"); 83 83 } 84 84 85 - #define PURE_EL2_SYSREG(el2) \ 86 - case el2: { \ 87 - *el1r = el2; \ 88 - return true; \ 89 - } 85 + enum sr_loc_attr { 86 + SR_LOC_MEMORY = 0, /* Register definitely in memory */ 87 + SR_LOC_LOADED = BIT(0), /* Register on CPU, unless it cannot */ 88 + SR_LOC_MAPPED = BIT(1), /* Register in a different CPU register */ 89 + SR_LOC_XLATED = BIT(2), /* Register translated to fit another reg */ 90 + SR_LOC_SPECIAL = BIT(3), /* Demanding register, implies loaded */ 91 + }; 90 92 91 - #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 92 - case el2: { \ 93 - *xlate = fn; \ 94 - *el1r = el1; \ 95 - return true; \ 96 - } 93 + struct sr_loc { 94 + enum sr_loc_attr loc; 95 + enum vcpu_sysreg map_reg; 96 + u64 (*xlate)(u64); 97 + }; 97 98 98 - static bool get_el2_to_el1_mapping(unsigned int reg, 99 - unsigned int *el1r, u64 (**xlate)(u64)) 99 + static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu, 100 + enum vcpu_sysreg reg) 100 101 { 101 102 switch (reg) { 102 - PURE_EL2_SYSREG( VPIDR_EL2 ); 103 - PURE_EL2_SYSREG( VMPIDR_EL2 ); 104 - PURE_EL2_SYSREG( ACTLR_EL2 ); 105 - PURE_EL2_SYSREG( HCR_EL2 ); 106 - PURE_EL2_SYSREG( MDCR_EL2 ); 107 - PURE_EL2_SYSREG( HSTR_EL2 ); 108 - PURE_EL2_SYSREG( HACR_EL2 ); 109 - PURE_EL2_SYSREG( VTTBR_EL2 ); 110 - PURE_EL2_SYSREG( VTCR_EL2 ); 111 - PURE_EL2_SYSREG( TPIDR_EL2 ); 112 - PURE_EL2_SYSREG( HPFAR_EL2 ); 113 - PURE_EL2_SYSREG( HCRX_EL2 ); 114 - PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 - PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 - PURE_EL2_SYSREG( HFGITR_EL2 ); 117 - PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 - PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 - PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 - PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 - PURE_EL2_SYSREG( CNTHCTL_EL2 ); 103 + case SCTLR_EL1: 104 + case CPACR_EL1: 105 + case TTBR0_EL1: 106 + case TTBR1_EL1: 107 + case TCR_EL1: 108 + case TCR2_EL1: 109 + case PIR_EL1: 110 + case PIRE0_EL1: 111 + case POR_EL1: 112 + case ESR_EL1: 113 + case AFSR0_EL1: 114 + case AFSR1_EL1: 115 + case FAR_EL1: 116 + case MAIR_EL1: 117 + case VBAR_EL1: 118 + case CONTEXTIDR_EL1: 119 + case AMAIR_EL1: 120 + case CNTKCTL_EL1: 121 + case ELR_EL1: 122 + case SPSR_EL1: 123 + case ZCR_EL1: 124 + case SCTLR2_EL1: 125 + /* 126 + * EL1 registers which have an ELx2 mapping are loaded if 127 + * we're not in hypervisor context. 128 + */ 129 + return is_hyp_ctxt(vcpu) ? SR_LOC_MEMORY : SR_LOC_LOADED; 130 + 131 + case TPIDR_EL0: 132 + case TPIDRRO_EL0: 133 + case TPIDR_EL1: 134 + case PAR_EL1: 135 + case DACR32_EL2: 136 + case IFSR32_EL2: 137 + case DBGVCR32_EL2: 138 + /* These registers are always loaded, no matter what */ 139 + return SR_LOC_LOADED; 140 + 141 + default: 142 + /* Non-mapped EL2 registers are by definition in memory. */ 143 + return SR_LOC_MEMORY; 144 + } 145 + } 146 + 147 + static void locate_mapped_el2_register(const struct kvm_vcpu *vcpu, 148 + enum vcpu_sysreg reg, 149 + enum vcpu_sysreg map_reg, 150 + u64 (*xlate)(u64), 151 + struct sr_loc *loc) 152 + { 153 + if (!is_hyp_ctxt(vcpu)) { 154 + loc->loc = SR_LOC_MEMORY; 155 + return; 156 + } 157 + 158 + loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED; 159 + loc->map_reg = map_reg; 160 + 161 + WARN_ON(locate_direct_register(vcpu, map_reg) != SR_LOC_MEMORY); 162 + 163 + if (xlate != NULL && !vcpu_el2_e2h_is_set(vcpu)) { 164 + loc->loc |= SR_LOC_XLATED; 165 + loc->xlate = xlate; 166 + } 167 + } 168 + 169 + #define MAPPED_EL2_SYSREG(r, m, t) \ 170 + case r: { \ 171 + locate_mapped_el2_register(vcpu, r, m, t, loc); \ 172 + break; \ 173 + } 174 + 175 + static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg, 176 + struct sr_loc *loc) 177 + { 178 + if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) { 179 + loc->loc = SR_LOC_MEMORY; 180 + return; 181 + } 182 + 183 + switch (reg) { 122 184 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 185 translate_sctlr_el2_to_sctlr_el1 ); 124 186 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, ··· 206 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 207 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 208 146 MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL ); 147 + case CNTHCTL_EL2: 148 + /* CNTHCTL_EL2 is super special, until we support NV2.1 */ 149 + loc->loc = ((is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) ? 150 + SR_LOC_SPECIAL : SR_LOC_MEMORY); 151 + break; 209 152 default: 210 - return false; 153 + loc->loc = locate_direct_register(vcpu, reg); 211 154 } 212 155 } 213 156 214 - u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 157 + static u64 read_sr_from_cpu(enum vcpu_sysreg reg) 215 158 { 216 159 u64 val = 0x8badf00d8badf00d; 217 - u64 (*xlate)(u64) = NULL; 218 - unsigned int el1r; 219 160 220 - if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 221 - goto memory_read; 161 + switch (reg) { 162 + case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break; 163 + case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break; 164 + case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break; 165 + case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break; 166 + case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break; 167 + case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break; 168 + case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break; 169 + case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break; 170 + case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break; 171 + case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break; 172 + case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break; 173 + case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break; 174 + case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break; 175 + case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break; 176 + case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break; 177 + case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 178 + case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break; 179 + case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 180 + case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break; 181 + case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break; 182 + case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break; 183 + case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break; 184 + case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break; 185 + case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 186 + case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break; 187 + case PAR_EL1: val = read_sysreg_par(); break; 188 + case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break; 189 + case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break; 190 + case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 191 + default: WARN_ON_ONCE(1); 192 + } 222 193 223 - if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 224 - if (!is_hyp_ctxt(vcpu)) 225 - goto memory_read; 194 + return val; 195 + } 196 + 197 + static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val) 198 + { 199 + switch (reg) { 200 + case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 201 + case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 202 + case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 203 + case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 204 + case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 205 + case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 206 + case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 207 + case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 208 + case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; 209 + case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 210 + case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 211 + case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 212 + case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 213 + case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 214 + case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 215 + case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 216 + case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 217 + case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 218 + case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 219 + case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 220 + case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 221 + case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; 222 + case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 223 + case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 224 + case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 225 + case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 226 + case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 227 + case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 228 + case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 229 + default: WARN_ON_ONCE(1); 230 + } 231 + } 232 + 233 + u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg) 234 + { 235 + struct sr_loc loc = {}; 236 + 237 + locate_register(vcpu, reg, &loc); 238 + 239 + WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 240 + 241 + if (loc.loc & SR_LOC_SPECIAL) { 242 + u64 val; 243 + 244 + WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 226 245 227 246 /* 228 - * CNTHCTL_EL2 requires some special treatment to 229 - * account for the bits that can be set via CNTKCTL_EL1. 247 + * CNTHCTL_EL2 requires some special treatment to account 248 + * for the bits that can be set via CNTKCTL_EL1 when E2H==1. 230 249 */ 231 250 switch (reg) { 232 251 case CNTHCTL_EL2: 233 - if (vcpu_el2_e2h_is_set(vcpu)) { 234 - val = read_sysreg_el1(SYS_CNTKCTL); 235 - val &= CNTKCTL_VALID_BITS; 236 - val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 237 - return val; 238 - } 239 - break; 252 + val = read_sysreg_el1(SYS_CNTKCTL); 253 + val &= CNTKCTL_VALID_BITS; 254 + val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 255 + return val; 256 + default: 257 + WARN_ON_ONCE(1); 240 258 } 241 - 242 - /* 243 - * If this register does not have an EL1 counterpart, 244 - * then read the stored EL2 version. 245 - */ 246 - if (reg == el1r) 247 - goto memory_read; 248 - 249 - /* 250 - * If we have a non-VHE guest and that the sysreg 251 - * requires translation to be used at EL1, use the 252 - * in-memory copy instead. 253 - */ 254 - if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 255 - goto memory_read; 256 - 257 - /* Get the current version of the EL1 counterpart. */ 258 - WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 259 - if (reg >= __SANITISED_REG_START__) 260 - val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 261 - 262 - return val; 263 259 } 264 260 265 - /* EL1 register can't be on the CPU if the guest is in vEL2. */ 266 - if (unlikely(is_hyp_ctxt(vcpu))) 267 - goto memory_read; 261 + if (loc.loc & SR_LOC_LOADED) { 262 + enum vcpu_sysreg map_reg = reg; 268 263 269 - if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 270 - return val; 264 + if (loc.loc & SR_LOC_MAPPED) 265 + map_reg = loc.map_reg; 271 266 272 - memory_read: 267 + if (!(loc.loc & SR_LOC_XLATED)) { 268 + u64 val = read_sr_from_cpu(map_reg); 269 + 270 + if (reg >= __SANITISED_REG_START__) 271 + val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 272 + 273 + return val; 274 + } 275 + } 276 + 273 277 return __vcpu_sys_reg(vcpu, reg); 274 278 } 275 279 276 - void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 280 + void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg) 277 281 { 278 - u64 (*xlate)(u64) = NULL; 279 - unsigned int el1r; 282 + struct sr_loc loc = {}; 280 283 281 - if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 282 - goto memory_write; 284 + locate_register(vcpu, reg, &loc); 283 285 284 - if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 285 - if (!is_hyp_ctxt(vcpu)) 286 - goto memory_write; 286 + WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY); 287 287 288 - /* 289 - * Always store a copy of the write to memory to avoid having 290 - * to reverse-translate virtual EL2 system registers for a 291 - * non-VHE guest hypervisor. 292 - */ 293 - __vcpu_assign_sys_reg(vcpu, reg, val); 288 + if (loc.loc & SR_LOC_SPECIAL) { 289 + 290 + WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL); 294 291 295 292 switch (reg) { 296 293 case CNTHCTL_EL2: 297 294 /* 298 - * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 299 - * Otherwise, some of the bits are backed by 295 + * If E2H=1, some of the bits are backed by 300 296 * CNTKCTL_EL1, while the rest is kept in memory. 301 297 * Yes, this is fun stuff. 302 298 */ 303 - if (vcpu_el2_e2h_is_set(vcpu)) 304 - write_sysreg_el1(val, SYS_CNTKCTL); 305 - return; 299 + write_sysreg_el1(val, SYS_CNTKCTL); 300 + break; 301 + default: 302 + WARN_ON_ONCE(1); 306 303 } 307 - 308 - /* No EL1 counterpart? We're done here.? */ 309 - if (reg == el1r) 310 - return; 311 - 312 - if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 313 - val = xlate(val); 314 - 315 - /* Redirect this to the EL1 version of the register. */ 316 - WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 317 - return; 318 304 } 319 305 320 - /* EL1 register can't be on the CPU if the guest is in vEL2. */ 321 - if (unlikely(is_hyp_ctxt(vcpu))) 322 - goto memory_write; 306 + if (loc.loc & SR_LOC_LOADED) { 307 + enum vcpu_sysreg map_reg = reg; 308 + u64 xlated_val; 323 309 324 - if (__vcpu_write_sys_reg_to_cpu(val, reg)) 325 - return; 310 + if (reg >= __SANITISED_REG_START__) 311 + val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 326 312 327 - memory_write: 313 + if (loc.loc & SR_LOC_MAPPED) 314 + map_reg = loc.map_reg; 315 + 316 + if (loc.loc & SR_LOC_XLATED) 317 + xlated_val = loc.xlate(val); 318 + else 319 + xlated_val = val; 320 + 321 + write_sr_to_cpu(map_reg, xlated_val); 322 + 323 + /* 324 + * Fall through to write the backing store anyway, which 325 + * allows translated registers to be directly read without a 326 + * reverse translation. 327 + */ 328 + } 329 + 328 330 __vcpu_assign_sys_reg(vcpu, reg, val); 329 331 } 330 332 ··· 1710 1584 } 1711 1585 1712 1586 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1587 + static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val); 1713 1588 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1714 1589 1715 1590 /* Read a sanitised cpufeature ID register by sys_reg_desc */ ··· 1733 1606 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1734 1607 break; 1735 1608 case SYS_ID_AA64PFR1_EL1: 1736 - if (!kvm_has_mte(vcpu->kvm)) { 1737 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1738 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1739 - } 1740 - 1741 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1742 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1743 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1744 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1745 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1746 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1747 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1748 - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1609 + val = sanitise_id_aa64pfr1_el1(vcpu, val); 1749 1610 break; 1750 1611 case SYS_ID_AA64PFR2_EL1: 1751 1612 val &= ID_AA64PFR2_EL1_FPMR | ··· 1743 1628 break; 1744 1629 case SYS_ID_AA64ISAR1_EL1: 1745 1630 if (!vcpu_has_ptrauth(vcpu)) 1746 - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1747 - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1748 - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1749 - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1631 + val &= ~(ID_AA64ISAR1_EL1_APA | 1632 + ID_AA64ISAR1_EL1_API | 1633 + ID_AA64ISAR1_EL1_GPA | 1634 + ID_AA64ISAR1_EL1_GPI); 1750 1635 break; 1751 1636 case SYS_ID_AA64ISAR2_EL1: 1752 1637 if (!vcpu_has_ptrauth(vcpu)) 1753 - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1754 - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1638 + val &= ~(ID_AA64ISAR2_EL1_APA3 | 1639 + ID_AA64ISAR2_EL1_GPA3); 1755 1640 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1756 1641 has_broken_cntvoff()) 1757 - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1642 + val &= ~ID_AA64ISAR2_EL1_WFxT; 1758 1643 break; 1759 1644 case SYS_ID_AA64ISAR3_EL1: 1760 1645 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; ··· 1770 1655 ID_AA64MMFR3_EL1_S1PIE; 1771 1656 break; 1772 1657 case SYS_ID_MMFR4_EL1: 1773 - val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1658 + val &= ~ID_MMFR4_EL1_CCIDX; 1774 1659 break; 1775 1660 } 1776 1661 ··· 1947 1832 * older kernels let the guest see the ID bit. 1948 1833 */ 1949 1834 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1835 + 1836 + return val; 1837 + } 1838 + 1839 + static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val) 1840 + { 1841 + u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1842 + 1843 + if (!kvm_has_mte(vcpu->kvm)) { 1844 + val &= ~ID_AA64PFR1_EL1_MTE; 1845 + val &= ~ID_AA64PFR1_EL1_MTE_frac; 1846 + } 1847 + 1848 + if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) && 1849 + SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP)) 1850 + val &= ~ID_AA64PFR1_EL1_RAS_frac; 1851 + 1852 + val &= ~ID_AA64PFR1_EL1_SME; 1853 + val &= ~ID_AA64PFR1_EL1_RNDR_trap; 1854 + val &= ~ID_AA64PFR1_EL1_NMI; 1855 + val &= ~ID_AA64PFR1_EL1_GCS; 1856 + val &= ~ID_AA64PFR1_EL1_THE; 1857 + val &= ~ID_AA64PFR1_EL1_MTEX; 1858 + val &= ~ID_AA64PFR1_EL1_PFAR; 1859 + val &= ~ID_AA64PFR1_EL1_MPAM_frac; 1950 1860 1951 1861 return val; 1952 1862 } ··· 2837 2697 struct kvm *kvm = vcpu->kvm; 2838 2698 2839 2699 switch(reg_to_encoding(r)) { 2700 + case SYS_ERXPFGCDN_EL1: 2701 + case SYS_ERXPFGCTL_EL1: 2702 + case SYS_ERXPFGF_EL1: 2703 + case SYS_ERXMISC2_EL1: 2704 + case SYS_ERXMISC3_EL1: 2705 + if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || 2706 + (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && 2707 + kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) { 2708 + kvm_inject_undefined(vcpu); 2709 + return false; 2710 + } 2711 + break; 2840 2712 default: 2841 2713 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) { 2842 2714 kvm_inject_undefined(vcpu); ··· 3081 2929 ~(ID_AA64PFR0_EL1_AMU | 3082 2930 ID_AA64PFR0_EL1_MPAM | 3083 2931 ID_AA64PFR0_EL1_SVE | 3084 - ID_AA64PFR0_EL1_RAS | 3085 2932 ID_AA64PFR0_EL1_AdvSIMD | 3086 2933 ID_AA64PFR0_EL1_FP)), 3087 2934 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, ··· 3094 2943 ID_AA64PFR1_EL1_SME | 3095 2944 ID_AA64PFR1_EL1_RES0 | 3096 2945 ID_AA64PFR1_EL1_MPAM_frac | 3097 - ID_AA64PFR1_EL1_RAS_frac | 3098 2946 ID_AA64PFR1_EL1_MTE)), 3099 2947 ID_WRITABLE(ID_AA64PFR2_EL1, 3100 2948 ID_AA64PFR2_EL1_FPMR | ··· 3213 3063 { SYS_DESC(SYS_ERXCTLR_EL1), access_ras }, 3214 3064 { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras }, 3215 3065 { SYS_DESC(SYS_ERXADDR_EL1), access_ras }, 3066 + { SYS_DESC(SYS_ERXPFGF_EL1), access_ras }, 3067 + { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras }, 3068 + { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras }, 3216 3069 { SYS_DESC(SYS_ERXMISC0_EL1), access_ras }, 3217 3070 { SYS_DESC(SYS_ERXMISC1_EL1), access_ras }, 3071 + { SYS_DESC(SYS_ERXMISC2_EL1), access_ras }, 3072 + { SYS_DESC(SYS_ERXMISC3_EL1), access_ras }, 3218 3073 3219 3074 MTE_REG(TFSR_EL1), 3220 3075 MTE_REG(TFSRE0_EL1),
+8
arch/arm64/kvm/vgic/vgic-mmio-v3.c
··· 50 50 51 51 bool vgic_supports_direct_msis(struct kvm *kvm) 52 52 { 53 + /* 54 + * Deliberately conflate vLPI and vSGI support on GICv4.1 hardware, 55 + * indirectly allowing userspace to control whether or not vPEs are 56 + * allocated for the VM. 57 + */ 58 + if (system_supports_direct_sgis() && !vgic_supports_direct_sgis(kvm)) 59 + return false; 60 + 53 61 return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); 54 62 } 55 63
+1 -1
arch/arm64/kvm/vgic/vgic-mmio.c
··· 1091 1091 len = vgic_v3_init_dist_iodev(io_device); 1092 1092 break; 1093 1093 default: 1094 - BUG_ON(1); 1094 + BUG(); 1095 1095 } 1096 1096 1097 1097 io_device->base_addr = dist_base_address;
+1 -9
arch/arm64/kvm/vgic/vgic.h
··· 396 396 397 397 static inline bool vgic_supports_direct_irqs(struct kvm *kvm) 398 398 { 399 - /* 400 - * Deliberately conflate vLPI and vSGI support on GICv4.1 hardware, 401 - * indirectly allowing userspace to control whether or not vPEs are 402 - * allocated for the VM. 403 - */ 404 - if (system_supports_direct_sgis()) 405 - return vgic_supports_direct_sgis(kvm); 406 - 407 - return vgic_supports_direct_msis(kvm); 399 + return vgic_supports_direct_msis(kvm) || vgic_supports_direct_sgis(kvm); 408 400 } 409 401 410 402 int vgic_v4_init(struct kvm *kvm);
-7
arch/arm64/mm/mmu.c
··· 47 47 #define NO_CONT_MAPPINGS BIT(1) 48 48 #define NO_EXEC_MAPPINGS BIT(2) /* assumes FEAT_HPDS is not used */ 49 49 50 - enum pgtable_type { 51 - TABLE_PTE, 52 - TABLE_PMD, 53 - TABLE_PUD, 54 - TABLE_P4D, 55 - }; 56 - 57 50 u64 kimage_voffset __ro_after_init; 58 51 EXPORT_SYMBOL(kimage_voffset); 59 52
+1
arch/arm64/tools/cpucaps
··· 53 53 HAS_S1POE 54 54 HAS_SCTLR2 55 55 HAS_RAS_EXTN 56 + HAS_RASV1P1_EXTN 56 57 HAS_RNG 57 58 HAS_SB 58 59 HAS_STAGE2_FWB
+1
arch/mips/configs/mtx1_defconfig
··· 273 273 CONFIG_ULI526X=m 274 274 CONFIG_PCMCIA_XIRCOM=m 275 275 CONFIG_DL2K=m 276 + CONFIG_SUNDANCE=m 276 277 CONFIG_PCMCIA_FMVJ18X=m 277 278 CONFIG_E100=m 278 279 CONFIG_E1000=m
+1
arch/powerpc/configs/ppc6xx_defconfig
··· 433 433 CONFIG_ULI526X=m 434 434 CONFIG_PCMCIA_XIRCOM=m 435 435 CONFIG_DL2K=m 436 + CONFIG_SUNDANCE=m 436 437 CONFIG_S2IO=m 437 438 CONFIG_FEC_MPC52xx=m 438 439 CONFIG_GIANFAR=m
+4 -1
arch/riscv/kvm/mmu.c
··· 39 39 unsigned long size, bool writable, bool in_atomic) 40 40 { 41 41 int ret = 0; 42 + pgprot_t prot; 42 43 unsigned long pfn; 43 44 phys_addr_t addr, end; 44 45 struct kvm_mmu_memory_cache pcache = { ··· 56 55 57 56 end = (gpa + size + PAGE_SIZE - 1) & PAGE_MASK; 58 57 pfn = __phys_to_pfn(hpa); 58 + prot = pgprot_noncached(PAGE_WRITE); 59 59 60 60 for (addr = gpa; addr < end; addr += PAGE_SIZE) { 61 61 map.addr = addr; 62 - map.pte = pfn_pte(pfn, PAGE_KERNEL_IO); 62 + map.pte = pfn_pte(pfn, prot); 63 + map.pte = pte_mkdirty(map.pte); 63 64 map.level = 0; 64 65 65 66 if (!writable)
+1 -1
arch/riscv/kvm/vcpu.c
··· 683 683 } 684 684 685 685 /** 686 - * check_vcpu_requests - check and handle pending vCPU requests 686 + * kvm_riscv_check_vcpu_requests - check and handle pending vCPU requests 687 687 * @vcpu: the VCPU pointer 688 688 * 689 689 * Return: 1 if we should enter the guest
+2
arch/riscv/kvm/vcpu_vector.c
··· 182 182 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 183 183 unsigned long reg_val; 184 184 185 + if (reg_size != sizeof(reg_val)) 186 + return -EINVAL; 185 187 if (copy_from_user(&reg_val, uaddr, reg_size)) 186 188 return -EFAULT; 187 189 if (reg_val != cntx->vector.vlenb)
+3
arch/x86/include/asm/pgtable_64_types.h
··· 36 36 #define pgtable_l5_enabled() cpu_feature_enabled(X86_FEATURE_LA57) 37 37 #endif /* USE_EARLY_PGTABLE_L5 */ 38 38 39 + #define ARCH_PAGE_TABLE_SYNC_MASK \ 40 + (pgtable_l5_enabled() ? PGTBL_PGD_MODIFIED : PGTBL_P4D_MODIFIED) 41 + 39 42 extern unsigned int pgdir_shift; 40 43 extern unsigned int ptrs_per_p4d; 41 44
+9
arch/x86/kernel/cpu/bugs.c
··· 416 416 cpu_attack_vector_mitigated(CPU_MITIGATE_USER_USER) || 417 417 cpu_attack_vector_mitigated(CPU_MITIGATE_GUEST_GUEST) || 418 418 (smt_mitigations != SMT_MITIGATIONS_OFF); 419 + 420 + case X86_BUG_SPEC_STORE_BYPASS: 421 + return cpu_attack_vector_mitigated(CPU_MITIGATE_USER_USER); 422 + 419 423 default: 420 424 WARN(1, "Unknown bug %x\n", bug); 421 425 return false; ··· 2714 2710 ssb_mode = SPEC_STORE_BYPASS_DISABLE; 2715 2711 break; 2716 2712 case SPEC_STORE_BYPASS_CMD_AUTO: 2713 + if (should_mitigate_vuln(X86_BUG_SPEC_STORE_BYPASS)) 2714 + ssb_mode = SPEC_STORE_BYPASS_PRCTL; 2715 + else 2716 + ssb_mode = SPEC_STORE_BYPASS_NONE; 2717 + break; 2717 2718 case SPEC_STORE_BYPASS_CMD_PRCTL: 2718 2719 ssb_mode = SPEC_STORE_BYPASS_PRCTL; 2719 2720 break;
+1 -1
arch/x86/kernel/cpu/intel.c
··· 262 262 if (c->x86_power & (1 << 8)) { 263 263 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 264 264 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 265 - } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || 265 + } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_CEDARMILL) || 266 266 (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { 267 267 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 268 268 }
+20 -2
arch/x86/kernel/cpu/microcode/amd.c
··· 171 171 return 1; 172 172 } 173 173 174 + static u32 cpuid_to_ucode_rev(unsigned int val) 175 + { 176 + union zen_patch_rev p = {}; 177 + union cpuid_1_eax c; 178 + 179 + c.full = val; 180 + 181 + p.stepping = c.stepping; 182 + p.model = c.model; 183 + p.ext_model = c.ext_model; 184 + p.ext_fam = c.ext_fam; 185 + 186 + return p.ucode_rev; 187 + } 188 + 174 189 static bool need_sha_check(u32 cur_rev) 175 190 { 191 + if (!cur_rev) { 192 + cur_rev = cpuid_to_ucode_rev(bsp_cpuid_1_eax); 193 + pr_info_once("No current revision, generating the lowest one: 0x%x\n", cur_rev); 194 + } 195 + 176 196 switch (cur_rev >> 8) { 177 197 case 0x80012: return cur_rev <= 0x800126f; break; 178 198 case 0x80082: return cur_rev <= 0x800820f; break; ··· 768 748 769 749 n.equiv_cpu = equiv_cpu; 770 750 n.patch_id = uci->cpu_sig.rev; 771 - 772 - WARN_ON_ONCE(!n.patch_id); 773 751 774 752 list_for_each_entry(p, &microcode_cache, plist) 775 753 if (patch_cpus_equivalent(p, &n, false))
+16 -11
arch/x86/kernel/cpu/topology_amd.c
··· 81 81 82 82 cpuid_leaf(0x8000001e, &leaf); 83 83 84 - tscan->c->topo.initial_apicid = leaf.ext_apic_id; 85 - 86 84 /* 87 - * If leaf 0xb is available, then the domain shifts are set 88 - * already and nothing to do here. Only valid for family >= 0x17. 85 + * If leaf 0xb/0x26 is available, then the APIC ID and the domain 86 + * shifts are set already. 89 87 */ 90 - if (!has_topoext && tscan->c->x86 >= 0x17) { 91 - /* 92 - * Leaf 0x80000008 set the CORE domain shift already. 93 - * Update the SMT domain, but do not propagate it. 94 - */ 95 - unsigned int nthreads = leaf.core_nthreads + 1; 88 + if (!has_topoext) { 89 + tscan->c->topo.initial_apicid = leaf.ext_apic_id; 96 90 97 - topology_update_dom(tscan, TOPO_SMT_DOMAIN, get_count_order(nthreads), nthreads); 91 + /* 92 + * Leaf 0x8000008 sets the CORE domain shift but not the 93 + * SMT domain shift. On CPUs with family >= 0x17, there 94 + * might be hyperthreads. 95 + */ 96 + if (tscan->c->x86 >= 0x17) { 97 + /* Update the SMT domain, but do not propagate it. */ 98 + unsigned int nthreads = leaf.core_nthreads + 1; 99 + 100 + topology_update_dom(tscan, TOPO_SMT_DOMAIN, 101 + get_count_order(nthreads), nthreads); 102 + } 98 103 } 99 104 100 105 store_node(tscan, leaf.nnodes_per_socket + 1, leaf.node_id);
+2
arch/x86/kvm/lapic.c
··· 810 810 if (min > map->max_apic_id) 811 811 return 0; 812 812 813 + min = array_index_nospec(min, map->max_apic_id + 1); 814 + 813 815 for_each_set_bit(i, ipi_bitmap, 814 816 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { 815 817 if (map->phys_map[min + i]) {
+3 -7
arch/x86/kvm/svm/sev.c
··· 719 719 static void sev_writeback_caches(struct kvm *kvm) 720 720 { 721 721 /* 722 - * Note, the caller is responsible for ensuring correctness if the mask 723 - * can be modified, e.g. if a CPU could be doing VMRUN. 724 - */ 725 - if (cpumask_empty(to_kvm_sev_info(kvm)->have_run_cpus)) 726 - return; 727 - 728 - /* 729 722 * Ensure that all dirty guest tagged cache entries are written back 730 723 * before releasing the pages back to the system for use. CLFLUSH will 731 724 * not do this without SME_COHERENT, and flushing many cache lines ··· 732 739 * serializing multiple calls and having responding CPUs (to the IPI) 733 740 * mark themselves as still running if they are running (or about to 734 741 * run) a vCPU for the VM. 742 + * 743 + * Note, the caller is responsible for ensuring correctness if the mask 744 + * can be modified, e.g. if a CPU could be doing VMRUN. 735 745 */ 736 746 wbnoinvd_on_cpus_mask(to_kvm_sev_info(kvm)->have_run_cpus); 737 747 }
+5 -2
arch/x86/kvm/x86.c
··· 9908 9908 rcu_read_lock(); 9909 9909 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9910 9910 9911 - if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9912 - target = map->phys_map[dest_id]->vcpu; 9911 + if (likely(map) && dest_id <= map->max_apic_id) { 9912 + dest_id = array_index_nospec(dest_id, map->max_apic_id + 1); 9913 + if (map->phys_map[dest_id]) 9914 + target = map->phys_map[dest_id]->vcpu; 9915 + } 9913 9916 9914 9917 rcu_read_unlock(); 9915 9918
+18
arch/x86/mm/init_64.c
··· 224 224 } 225 225 226 226 /* 227 + * Make kernel mappings visible in all page tables in the system. 228 + * This is necessary except when the init task populates kernel mappings 229 + * during the boot process. In that case, all processes originating from 230 + * the init task copies the kernel mappings, so there is no issue. 231 + * Otherwise, missing synchronization could lead to kernel crashes due 232 + * to missing page table entries for certain kernel mappings. 233 + * 234 + * Synchronization is performed at the top level, which is the PGD in 235 + * 5-level paging systems. But in 4-level paging systems, however, 236 + * pgd_populate() is a no-op, so synchronization is done at the P4D level. 237 + * sync_global_pgds() handles this difference between paging levels. 238 + */ 239 + void arch_sync_kernel_mappings(unsigned long start, unsigned long end) 240 + { 241 + sync_global_pgds(start, end); 242 + } 243 + 244 + /* 227 245 * NOTE: This function is marked __ref because it calls __init function 228 246 * (alloc_bootmem_pages). It's safe to do it ONLY when after_bootmem == 0. 229 247 */
+8 -5
block/blk-rq-qos.h
··· 149 149 q = bdev_get_queue(bio->bi_bdev); 150 150 151 151 /* 152 - * If a bio has BIO_QOS_xxx set, it implicitly implies that 153 - * q->rq_qos is present. So, we skip re-checking q->rq_qos 154 - * here as an extra optimization and directly call 155 - * __rq_qos_done_bio(). 152 + * A BIO may carry BIO_QOS_* flags even if the associated request_queue 153 + * does not have rq_qos enabled. This can happen with stacked block 154 + * devices — for example, NVMe multipath, where it's possible that the 155 + * bottom device has QoS enabled but the top device does not. Therefore, 156 + * always verify that q->rq_qos is present and QoS is enabled before 157 + * calling __rq_qos_done_bio(). 156 158 */ 157 - __rq_qos_done_bio(q->rq_qos, bio); 159 + if (test_bit(QUEUE_FLAG_QOS_ENABLED, &q->queue_flags) && q->rq_qos) 160 + __rq_qos_done_bio(q->rq_qos, bio); 158 161 } 159 162 160 163 static inline void rq_qos_throttle(struct request_queue *q, struct bio *bio)
+6 -5
block/blk-zoned.c
··· 1286 1286 struct block_device *bdev; 1287 1287 unsigned long flags; 1288 1288 struct bio *bio; 1289 + bool prepared; 1289 1290 1290 1291 /* 1291 1292 * Submit the next plugged BIO. If we do not have any, clear 1292 1293 * the plugged flag. 1293 1294 */ 1294 - spin_lock_irqsave(&zwplug->lock, flags); 1295 - 1296 1295 again: 1296 + spin_lock_irqsave(&zwplug->lock, flags); 1297 1297 bio = bio_list_pop(&zwplug->bio_list); 1298 1298 if (!bio) { 1299 1299 zwplug->flags &= ~BLK_ZONE_WPLUG_PLUGGED; ··· 1304 1304 trace_blk_zone_wplug_bio(zwplug->disk->queue, zwplug->zone_no, 1305 1305 bio->bi_iter.bi_sector, bio_sectors(bio)); 1306 1306 1307 - if (!blk_zone_wplug_prepare_bio(zwplug, bio)) { 1307 + prepared = blk_zone_wplug_prepare_bio(zwplug, bio); 1308 + spin_unlock_irqrestore(&zwplug->lock, flags); 1309 + 1310 + if (!prepared) { 1308 1311 blk_zone_wplug_bio_io_error(zwplug, bio); 1309 1312 goto again; 1310 1313 } 1311 - 1312 - spin_unlock_irqrestore(&zwplug->lock, flags); 1313 1314 1314 1315 bdev = bio->bi_bdev; 1315 1316
+40 -17
drivers/ata/ahci.c
··· 689 689 "where <pci_dev> is the PCI ID of an AHCI controller in the " 690 690 "form \"domain:bus:dev.func\""); 691 691 692 - static void ahci_apply_port_map_mask(struct device *dev, 693 - struct ahci_host_priv *hpriv, char *mask_s) 692 + static char *ahci_mask_port_ext; 693 + module_param_named(mask_port_ext, ahci_mask_port_ext, charp, 0444); 694 + MODULE_PARM_DESC(mask_port_ext, 695 + "32-bits mask to ignore the external/hotplug capability of ports. " 696 + "Valid values are: " 697 + "\"<mask>\" to apply the same mask to all AHCI controller " 698 + "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to " 699 + "specify different masks for the controllers specified, " 700 + "where <pci_dev> is the PCI ID of an AHCI controller in the " 701 + "form \"domain:bus:dev.func\""); 702 + 703 + static u32 ahci_port_mask(struct device *dev, char *mask_s) 694 704 { 695 705 unsigned int mask; 696 706 697 707 if (kstrtouint(mask_s, 0, &mask)) { 698 708 dev_err(dev, "Invalid port map mask\n"); 699 - return; 709 + return 0; 700 710 } 701 711 702 - hpriv->mask_port_map = mask; 712 + return mask; 703 713 } 704 714 705 - static void ahci_get_port_map_mask(struct device *dev, 706 - struct ahci_host_priv *hpriv) 715 + static u32 ahci_get_port_mask(struct device *dev, char *mask_p) 707 716 { 708 717 char *param, *end, *str, *mask_s; 709 718 char *name; 719 + u32 mask = 0; 710 720 711 - if (!strlen(ahci_mask_port_map)) 712 - return; 721 + if (!mask_p || !strlen(mask_p)) 722 + return 0; 713 723 714 - str = kstrdup(ahci_mask_port_map, GFP_KERNEL); 724 + str = kstrdup(mask_p, GFP_KERNEL); 715 725 if (!str) 716 - return; 726 + return 0; 717 727 718 728 /* Handle single mask case */ 719 729 if (!strchr(str, '=')) { 720 - ahci_apply_port_map_mask(dev, hpriv, str); 730 + mask = ahci_port_mask(dev, str); 721 731 goto free; 722 732 } 723 733 724 734 /* 725 - * Mask list case: parse the parameter to apply the mask only if 735 + * Mask list case: parse the parameter to get the mask only if 726 736 * the device name matches. 727 737 */ 728 738 param = str; ··· 762 752 param++; 763 753 } 764 754 765 - ahci_apply_port_map_mask(dev, hpriv, mask_s); 755 + mask = ahci_port_mask(dev, mask_s); 766 756 } 767 757 768 758 free: 769 759 kfree(str); 760 + 761 + return mask; 770 762 } 771 763 772 764 static void ahci_pci_save_initial_config(struct pci_dev *pdev, ··· 794 782 } 795 783 796 784 /* Handle port map masks passed as module parameter. */ 797 - if (ahci_mask_port_map) 798 - ahci_get_port_map_mask(&pdev->dev, hpriv); 785 + hpriv->mask_port_map = 786 + ahci_get_port_mask(&pdev->dev, ahci_mask_port_map); 787 + hpriv->mask_port_ext = 788 + ahci_get_port_mask(&pdev->dev, ahci_mask_port_ext); 799 789 800 790 ahci_save_initial_config(&pdev->dev, hpriv); 801 791 } ··· 1771 1757 void __iomem *port_mmio = ahci_port_base(ap); 1772 1758 u32 tmp; 1773 1759 1774 - /* mark external ports (hotplug-capable, eSATA) */ 1760 + /* 1761 + * Mark external ports (hotplug-capable, eSATA), unless we were asked to 1762 + * ignore this feature. 1763 + */ 1775 1764 tmp = readl(port_mmio + PORT_CMD); 1776 1765 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) || 1777 - (tmp & PORT_CMD_HPCP)) 1766 + (tmp & PORT_CMD_HPCP)) { 1767 + if (hpriv->mask_port_ext & (1U << ap->port_no)) { 1768 + ata_port_info(ap, 1769 + "Ignoring external/hotplug capability\n"); 1770 + return; 1771 + } 1778 1772 ap->pflags |= ATA_PFLAG_EXTERNAL; 1773 + } 1779 1774 } 1780 1775 1781 1776 static void ahci_update_initial_lpm_policy(struct ata_port *ap)
+1
drivers/ata/ahci.h
··· 330 330 /* Input fields */ 331 331 unsigned int flags; /* AHCI_HFLAG_* */ 332 332 u32 mask_port_map; /* Mask of valid ports */ 333 + u32 mask_port_ext; /* Mask of ports ext capability */ 333 334 334 335 void __iomem * mmio; /* bus-independent mem map */ 335 336 u32 cap; /* cap to use */
+2 -5
drivers/ata/ahci_xgene.c
··· 450 450 { 451 451 int pmp = sata_srst_pmp(link); 452 452 struct ata_port *ap = link->ap; 453 - u32 rc; 454 453 void __iomem *port_mmio = ahci_port_base(ap); 455 454 u32 port_fbs; 456 455 ··· 462 463 port_fbs |= pmp << PORT_FBS_DEV_OFFSET; 463 464 writel(port_fbs, port_mmio + PORT_FBS); 464 465 465 - rc = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 466 - 467 - return rc; 466 + return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 468 467 } 469 468 470 469 /** ··· 497 500 u32 port_fbs; 498 501 u32 port_fbs_save; 499 502 u32 retry = 1; 500 - u32 rc; 503 + int rc; 501 504 502 505 port_fbs_save = readl(port_mmio + PORT_FBS); 503 506
+16 -10
drivers/block/loop.c
··· 139 139 140 140 static loff_t lo_calculate_size(struct loop_device *lo, struct file *file) 141 141 { 142 - struct kstat stat; 143 142 loff_t loopsize; 144 143 int ret; 145 144 146 - /* 147 - * Get the accurate file size. This provides better results than 148 - * cached inode data, particularly for network filesystems where 149 - * metadata may be stale. 150 - */ 151 - ret = vfs_getattr_nosec(&file->f_path, &stat, STATX_SIZE, 0); 152 - if (ret) 153 - return 0; 145 + if (S_ISBLK(file_inode(file)->i_mode)) { 146 + loopsize = i_size_read(file->f_mapping->host); 147 + } else { 148 + struct kstat stat; 154 149 155 - loopsize = stat.size; 150 + /* 151 + * Get the accurate file size. This provides better results than 152 + * cached inode data, particularly for network filesystems where 153 + * metadata may be stale. 154 + */ 155 + ret = vfs_getattr_nosec(&file->f_path, &stat, STATX_SIZE, 0); 156 + if (ret) 157 + return 0; 158 + 159 + loopsize = stat.size; 160 + } 161 + 156 162 if (lo->lo_offset > 0) 157 163 loopsize -= lo->lo_offset; 158 164 /* offset is beyond i_size, weird but possible */
+70 -2
drivers/block/ublk_drv.c
··· 239 239 struct mutex cancel_mutex; 240 240 bool canceling; 241 241 pid_t ublksrv_tgid; 242 + struct delayed_work exit_work; 242 243 }; 243 244 244 245 /* header of ublk_params */ ··· 1596 1595 ublk_get_queue(ub, i)->canceling = canceling; 1597 1596 } 1598 1597 1599 - static int ublk_ch_release(struct inode *inode, struct file *filp) 1598 + static bool ublk_check_and_reset_active_ref(struct ublk_device *ub) 1600 1599 { 1601 - struct ublk_device *ub = filp->private_data; 1600 + int i, j; 1601 + 1602 + if (!(ub->dev_info.flags & (UBLK_F_SUPPORT_ZERO_COPY | 1603 + UBLK_F_AUTO_BUF_REG))) 1604 + return false; 1605 + 1606 + for (i = 0; i < ub->dev_info.nr_hw_queues; i++) { 1607 + struct ublk_queue *ubq = ublk_get_queue(ub, i); 1608 + 1609 + for (j = 0; j < ubq->q_depth; j++) { 1610 + struct ublk_io *io = &ubq->ios[j]; 1611 + unsigned int refs = refcount_read(&io->ref) + 1612 + io->task_registered_buffers; 1613 + 1614 + /* 1615 + * UBLK_REFCOUNT_INIT or zero means no active 1616 + * reference 1617 + */ 1618 + if (refs != UBLK_REFCOUNT_INIT && refs != 0) 1619 + return true; 1620 + 1621 + /* reset to zero if the io hasn't active references */ 1622 + refcount_set(&io->ref, 0); 1623 + io->task_registered_buffers = 0; 1624 + } 1625 + } 1626 + return false; 1627 + } 1628 + 1629 + static void ublk_ch_release_work_fn(struct work_struct *work) 1630 + { 1631 + struct ublk_device *ub = 1632 + container_of(work, struct ublk_device, exit_work.work); 1602 1633 struct gendisk *disk; 1603 1634 int i; 1635 + 1636 + /* 1637 + * For zero-copy and auto buffer register modes, I/O references 1638 + * might not be dropped naturally when the daemon is killed, but 1639 + * io_uring guarantees that registered bvec kernel buffers are 1640 + * unregistered finally when freeing io_uring context, then the 1641 + * active references are dropped. 1642 + * 1643 + * Wait until active references are dropped for avoiding use-after-free 1644 + * 1645 + * registered buffer may be unregistered in io_ring's release hander, 1646 + * so have to wait by scheduling work function for avoiding the two 1647 + * file release dependency. 1648 + */ 1649 + if (ublk_check_and_reset_active_ref(ub)) { 1650 + schedule_delayed_work(&ub->exit_work, 1); 1651 + return; 1652 + } 1604 1653 1605 1654 /* 1606 1655 * disk isn't attached yet, either device isn't live, or it has ··· 1724 1673 ublk_reset_ch_dev(ub); 1725 1674 out: 1726 1675 clear_bit(UB_STATE_OPEN, &ub->state); 1676 + 1677 + /* put the reference grabbed in ublk_ch_release() */ 1678 + ublk_put_device(ub); 1679 + } 1680 + 1681 + static int ublk_ch_release(struct inode *inode, struct file *filp) 1682 + { 1683 + struct ublk_device *ub = filp->private_data; 1684 + 1685 + /* 1686 + * Grab ublk device reference, so it won't be gone until we are 1687 + * really released from work function. 1688 + */ 1689 + ublk_get_device(ub); 1690 + 1691 + INIT_DELAYED_WORK(&ub->exit_work, ublk_ch_release_work_fn); 1692 + schedule_delayed_work(&ub->exit_work, 0); 1727 1693 return 0; 1728 1694 } 1729 1695
+41 -16
drivers/bluetooth/hci_vhci.c
··· 380 380 .write = force_devcd_write, 381 381 }; 382 382 383 + static void vhci_debugfs_init(struct vhci_data *data) 384 + { 385 + struct hci_dev *hdev = data->hdev; 386 + 387 + debugfs_create_file("force_suspend", 0644, hdev->debugfs, data, 388 + &force_suspend_fops); 389 + 390 + debugfs_create_file("force_wakeup", 0644, hdev->debugfs, data, 391 + &force_wakeup_fops); 392 + 393 + if (IS_ENABLED(CONFIG_BT_MSFTEXT)) 394 + debugfs_create_file("msft_opcode", 0644, hdev->debugfs, data, 395 + &msft_opcode_fops); 396 + 397 + if (IS_ENABLED(CONFIG_BT_AOSPEXT)) 398 + debugfs_create_file("aosp_capable", 0644, hdev->debugfs, data, 399 + &aosp_capable_fops); 400 + 401 + debugfs_create_file("force_devcoredump", 0644, hdev->debugfs, data, 402 + &force_devcoredump_fops); 403 + } 404 + 383 405 static int __vhci_create_device(struct vhci_data *data, __u8 opcode) 384 406 { 385 407 struct hci_dev *hdev; ··· 456 434 return -EBUSY; 457 435 } 458 436 459 - debugfs_create_file("force_suspend", 0644, hdev->debugfs, data, 460 - &force_suspend_fops); 461 - 462 - debugfs_create_file("force_wakeup", 0644, hdev->debugfs, data, 463 - &force_wakeup_fops); 464 - 465 - if (IS_ENABLED(CONFIG_BT_MSFTEXT)) 466 - debugfs_create_file("msft_opcode", 0644, hdev->debugfs, data, 467 - &msft_opcode_fops); 468 - 469 - if (IS_ENABLED(CONFIG_BT_AOSPEXT)) 470 - debugfs_create_file("aosp_capable", 0644, hdev->debugfs, data, 471 - &aosp_capable_fops); 472 - 473 - debugfs_create_file("force_devcoredump", 0644, hdev->debugfs, data, 474 - &force_devcoredump_fops); 437 + if (!IS_ERR_OR_NULL(hdev->debugfs)) 438 + vhci_debugfs_init(data); 475 439 476 440 hci_skb_pkt_type(skb) = HCI_VENDOR_PKT; 477 441 ··· 659 651 return 0; 660 652 } 661 653 654 + static void vhci_debugfs_remove(struct hci_dev *hdev) 655 + { 656 + debugfs_lookup_and_remove("force_suspend", hdev->debugfs); 657 + 658 + debugfs_lookup_and_remove("force_wakeup", hdev->debugfs); 659 + 660 + if (IS_ENABLED(CONFIG_BT_MSFTEXT)) 661 + debugfs_lookup_and_remove("msft_opcode", hdev->debugfs); 662 + 663 + if (IS_ENABLED(CONFIG_BT_AOSPEXT)) 664 + debugfs_lookup_and_remove("aosp_capable", hdev->debugfs); 665 + 666 + debugfs_lookup_and_remove("force_devcoredump", hdev->debugfs); 667 + } 668 + 662 669 static int vhci_release(struct inode *inode, struct file *file) 663 670 { 664 671 struct vhci_data *data = file->private_data; ··· 685 662 hdev = data->hdev; 686 663 687 664 if (hdev) { 665 + if (!IS_ERR_OR_NULL(hdev->debugfs)) 666 + vhci_debugfs_remove(hdev); 688 667 hci_unregister_dev(hdev); 689 668 hci_free_dev(hdev); 690 669 }
+27 -34
drivers/firmware/efi/stmm/tee_stmm_efi.c
··· 143 143 return var_hdr->ret_status; 144 144 } 145 145 146 + #define COMM_BUF_SIZE(__payload_size) (MM_COMMUNICATE_HEADER_SIZE + \ 147 + MM_VARIABLE_COMMUNICATE_SIZE + \ 148 + (__payload_size)) 149 + 146 150 /** 147 151 * setup_mm_hdr() - Allocate a buffer for StandAloneMM and initialize the 148 152 * header data. ··· 154 150 * @dptr: pointer address to store allocated buffer 155 151 * @payload_size: payload size 156 152 * @func: standAloneMM function number 157 - * @ret: EFI return code 158 153 * Return: pointer to corresponding StandAloneMM function buffer or NULL 159 154 */ 160 - static void *setup_mm_hdr(u8 **dptr, size_t payload_size, size_t func, 161 - efi_status_t *ret) 155 + static void *setup_mm_hdr(u8 **dptr, size_t payload_size, size_t func) 162 156 { 163 157 const efi_guid_t mm_var_guid = EFI_MM_VARIABLE_GUID; 164 158 struct efi_mm_communicate_header *mm_hdr; ··· 171 169 if (max_buffer_size && 172 170 max_buffer_size < (MM_COMMUNICATE_HEADER_SIZE + 173 171 MM_VARIABLE_COMMUNICATE_SIZE + payload_size)) { 174 - *ret = EFI_INVALID_PARAMETER; 175 172 return NULL; 176 173 } 177 174 178 - comm_buf = kzalloc(MM_COMMUNICATE_HEADER_SIZE + 179 - MM_VARIABLE_COMMUNICATE_SIZE + payload_size, 180 - GFP_KERNEL); 181 - if (!comm_buf) { 182 - *ret = EFI_OUT_OF_RESOURCES; 175 + comm_buf = alloc_pages_exact(COMM_BUF_SIZE(payload_size), 176 + GFP_KERNEL | __GFP_ZERO); 177 + if (!comm_buf) 183 178 return NULL; 184 - } 185 179 186 180 mm_hdr = (struct efi_mm_communicate_header *)comm_buf; 187 181 memcpy(&mm_hdr->header_guid, &mm_var_guid, sizeof(mm_hdr->header_guid)); ··· 185 187 186 188 var_hdr = (struct smm_variable_communicate_header *)mm_hdr->data; 187 189 var_hdr->function = func; 188 - if (dptr) 189 - *dptr = comm_buf; 190 - *ret = EFI_SUCCESS; 190 + *dptr = comm_buf; 191 191 192 192 return var_hdr->data; 193 193 } ··· 208 212 209 213 payload_size = sizeof(*var_payload); 210 214 var_payload = setup_mm_hdr(&comm_buf, payload_size, 211 - SMM_VARIABLE_FUNCTION_GET_PAYLOAD_SIZE, 212 - &ret); 215 + SMM_VARIABLE_FUNCTION_GET_PAYLOAD_SIZE); 213 216 if (!var_payload) 214 - return EFI_OUT_OF_RESOURCES; 217 + return EFI_DEVICE_ERROR; 215 218 216 219 ret = mm_communicate(comm_buf, payload_size); 217 220 if (ret != EFI_SUCCESS) ··· 234 239 */ 235 240 *size -= 2; 236 241 out: 237 - kfree(comm_buf); 242 + free_pages_exact(comm_buf, COMM_BUF_SIZE(payload_size)); 238 243 return ret; 239 244 } 240 245 ··· 254 259 255 260 smm_property = setup_mm_hdr( 256 261 &comm_buf, payload_size, 257 - SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_GET, &ret); 262 + SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_GET); 258 263 if (!smm_property) 259 - return EFI_OUT_OF_RESOURCES; 264 + return EFI_DEVICE_ERROR; 260 265 261 266 memcpy(&smm_property->guid, vendor, sizeof(smm_property->guid)); 262 267 smm_property->name_size = name_size; ··· 277 282 memcpy(var_property, &smm_property->property, sizeof(*var_property)); 278 283 279 284 out: 280 - kfree(comm_buf); 285 + free_pages_exact(comm_buf, COMM_BUF_SIZE(payload_size)); 281 286 return ret; 282 287 } 283 288 ··· 310 315 311 316 payload_size = MM_VARIABLE_ACCESS_HEADER_SIZE + name_size + tmp_dsize; 312 317 var_acc = setup_mm_hdr(&comm_buf, payload_size, 313 - SMM_VARIABLE_FUNCTION_GET_VARIABLE, &ret); 318 + SMM_VARIABLE_FUNCTION_GET_VARIABLE); 314 319 if (!var_acc) 315 - return EFI_OUT_OF_RESOURCES; 320 + return EFI_DEVICE_ERROR; 316 321 317 322 /* Fill in contents */ 318 323 memcpy(&var_acc->guid, vendor, sizeof(var_acc->guid)); ··· 342 347 memcpy(data, (u8 *)var_acc->name + var_acc->name_size, 343 348 var_acc->data_size); 344 349 out: 345 - kfree(comm_buf); 350 + free_pages_exact(comm_buf, COMM_BUF_SIZE(payload_size)); 346 351 return ret; 347 352 } 348 353 ··· 375 380 376 381 payload_size = MM_VARIABLE_GET_NEXT_HEADER_SIZE + out_name_size; 377 382 var_getnext = setup_mm_hdr(&comm_buf, payload_size, 378 - SMM_VARIABLE_FUNCTION_GET_NEXT_VARIABLE_NAME, 379 - &ret); 383 + SMM_VARIABLE_FUNCTION_GET_NEXT_VARIABLE_NAME); 380 384 if (!var_getnext) 381 - return EFI_OUT_OF_RESOURCES; 385 + return EFI_DEVICE_ERROR; 382 386 383 387 /* Fill in contents */ 384 388 memcpy(&var_getnext->guid, guid, sizeof(var_getnext->guid)); ··· 398 404 memcpy(name, var_getnext->name, var_getnext->name_size); 399 405 400 406 out: 401 - kfree(comm_buf); 407 + free_pages_exact(comm_buf, COMM_BUF_SIZE(payload_size)); 402 408 return ret; 403 409 } 404 410 ··· 431 437 * the properties, if the allocation fails 432 438 */ 433 439 var_acc = setup_mm_hdr(&comm_buf, payload_size, 434 - SMM_VARIABLE_FUNCTION_SET_VARIABLE, &ret); 440 + SMM_VARIABLE_FUNCTION_SET_VARIABLE); 435 441 if (!var_acc) 436 - return EFI_OUT_OF_RESOURCES; 442 + return EFI_DEVICE_ERROR; 437 443 438 444 /* 439 445 * The API has the ability to override RO flags. If no RO check was ··· 461 467 ret = mm_communicate(comm_buf, payload_size); 462 468 dev_dbg(pvt_data.dev, "Set Variable %s %d %lx\n", __FILE__, __LINE__, ret); 463 469 out: 464 - kfree(comm_buf); 470 + free_pages_exact(comm_buf, COMM_BUF_SIZE(payload_size)); 465 471 return ret; 466 472 } 467 473 ··· 486 492 487 493 payload_size = sizeof(*mm_query_info); 488 494 mm_query_info = setup_mm_hdr(&comm_buf, payload_size, 489 - SMM_VARIABLE_FUNCTION_QUERY_VARIABLE_INFO, 490 - &ret); 495 + SMM_VARIABLE_FUNCTION_QUERY_VARIABLE_INFO); 491 496 if (!mm_query_info) 492 - return EFI_OUT_OF_RESOURCES; 497 + return EFI_DEVICE_ERROR; 493 498 494 499 mm_query_info->attr = attributes; 495 500 ret = mm_communicate(comm_buf, payload_size); ··· 500 507 *max_variable_size = mm_query_info->max_variable_size; 501 508 502 509 out: 503 - kfree(comm_buf); 510 + free_pages_exact(comm_buf, COMM_BUF_SIZE(payload_size)); 504 511 return ret; 505 512 } 506 513
+1 -1
drivers/gpio/gpio-timberdale.c
··· 137 137 u32 ver; 138 138 int ret = 0; 139 139 140 - if (offset < 0 || offset > tgpio->gpio.ngpio) 140 + if (offset < 0 || offset >= tgpio->gpio.ngpio) 141 141 return -EINVAL; 142 142 143 143 ver = ioread32(tgpio->membase + TGPIO_VER);
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
··· 88 88 } 89 89 90 90 r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, size, 91 - AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 92 - AMDGPU_VM_PAGE_EXECUTABLE); 91 + AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | 92 + AMDGPU_PTE_EXECUTABLE); 93 93 94 94 if (r) { 95 95 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
+32 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
··· 285 285 return ret; 286 286 } 287 287 288 + static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) 289 + { 290 + struct drm_gem_object *obj = dma_buf->priv; 291 + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 292 + int ret; 293 + 294 + /* 295 + * Pin to keep buffer in place while it's vmap'ed. The actual 296 + * domain is not that important as long as it's mapable. Using 297 + * GTT and VRAM should be compatible with most use cases. 298 + */ 299 + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM); 300 + if (ret) 301 + return ret; 302 + ret = drm_gem_dmabuf_vmap(dma_buf, map); 303 + if (ret) 304 + amdgpu_bo_unpin(bo); 305 + 306 + return ret; 307 + } 308 + 309 + static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map) 310 + { 311 + struct drm_gem_object *obj = dma_buf->priv; 312 + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 313 + 314 + drm_gem_dmabuf_vunmap(dma_buf, map); 315 + amdgpu_bo_unpin(bo); 316 + } 317 + 288 318 const struct dma_buf_ops amdgpu_dmabuf_ops = { 289 319 .attach = amdgpu_dma_buf_attach, 290 320 .pin = amdgpu_dma_buf_pin, ··· 324 294 .release = drm_gem_dmabuf_release, 325 295 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, 326 296 .mmap = drm_gem_dmabuf_mmap, 327 - .vmap = drm_gem_dmabuf_vmap, 328 - .vunmap = drm_gem_dmabuf_vunmap, 297 + .vmap = amdgpu_dma_buf_vmap, 298 + .vunmap = amdgpu_dma_buf_vunmap, 329 299 }; 330 300 331 301 /**
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
··· 471 471 if (index == (uint64_t)-EINVAL) { 472 472 drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n"); 473 473 kfree(queue); 474 + r = -EINVAL; 474 475 goto unlock; 475 476 } 476 477
+9 -5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 1612 1612 case IP_VERSION(11, 0, 2): 1613 1613 case IP_VERSION(11, 0, 3): 1614 1614 if (!adev->gfx.disable_uq && 1615 - adev->gfx.me_fw_version >= 2390 && 1616 - adev->gfx.pfp_fw_version >= 2530 && 1617 - adev->gfx.mec_fw_version >= 2600 && 1615 + adev->gfx.me_fw_version >= 2420 && 1616 + adev->gfx.pfp_fw_version >= 2580 && 1617 + adev->gfx.mec_fw_version >= 2650 && 1618 1618 adev->mes.fw_version[0] >= 120) { 1619 1619 adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; 1620 1620 adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; ··· 4129 4129 #endif 4130 4130 if (prop->tmz_queue) 4131 4131 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 4132 + if (!prop->kernel_queue) 4133 + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 4132 4134 mqd->cp_gfx_hqd_cntl = tmp; 4133 4135 4134 4136 /* set up cp_doorbell_control */ ··· 4283 4281 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 4284 4282 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 4285 4283 prop->allow_tunneling); 4286 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4287 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4284 + if (prop->kernel_queue) { 4285 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4286 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4287 + } 4288 4288 if (prop->tmz_queue) 4289 4289 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 4290 4290 mqd->cp_hqd_pq_control = tmp;
+6 -2
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 3026 3026 #endif 3027 3027 if (prop->tmz_queue) 3028 3028 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); 3029 + if (!prop->kernel_queue) 3030 + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); 3029 3031 mqd->cp_gfx_hqd_cntl = tmp; 3030 3032 3031 3033 /* set up cp_doorbell_control */ ··· 3177 3175 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3178 3176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 3179 3177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3180 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3181 - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3178 + if (prop->kernel_queue) { 3179 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3180 + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3181 + } 3182 3182 if (prop->tmz_queue) 3183 3183 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); 3184 3184 mqd->cp_hqd_pq_control = tmp;
+10 -8
drivers/gpu/drm/amd/pm/amdgpu_pm.c
··· 3458 3458 effective_mode &= ~S_IWUSR; 3459 3459 3460 3460 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ 3461 - if (((adev->family == AMDGPU_FAMILY_SI) || 3462 - ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && 3463 - (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)))) && 3464 - (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3465 - attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3466 - attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3467 - attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3468 - return 0; 3461 + if (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3462 + attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3463 + attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3464 + attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr) { 3465 + if (adev->family == AMDGPU_FAMILY_SI || 3466 + ((adev->flags & AMD_IS_APU) && gc_ver != IP_VERSION(10, 3, 1) && 3467 + (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4))) || 3468 + (amdgpu_sriov_vf(adev) && gc_ver == IP_VERSION(11, 0, 3))) 3469 + return 0; 3470 + } 3469 3471 3470 3472 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ 3471 3473 if (((adev->family == AMDGPU_FAMILY_SI) ||
+40 -40
drivers/gpu/drm/drm_gpuvm.c
··· 40 40 * mapping's backing &drm_gem_object buffers. 41 41 * 42 42 * &drm_gem_object buffers maintain a list of &drm_gpuva objects representing 43 - * all existent GPU VA mappings using this &drm_gem_object as backing buffer. 43 + * all existing GPU VA mappings using this &drm_gem_object as backing buffer. 44 44 * 45 45 * GPU VAs can be flagged as sparse, such that drivers may use GPU VAs to also 46 46 * keep track of sparse PTEs in order to support Vulkan 'Sparse Resources'. ··· 72 72 * but it can also be a 'dummy' object, which can be allocated with 73 73 * drm_gpuvm_resv_object_alloc(). 74 74 * 75 - * In order to connect a struct drm_gpuva its backing &drm_gem_object each 75 + * In order to connect a struct drm_gpuva to its backing &drm_gem_object each 76 76 * &drm_gem_object maintains a list of &drm_gpuvm_bo structures, and each 77 77 * &drm_gpuvm_bo contains a list of &drm_gpuva structures. 78 78 * ··· 81 81 * This is ensured by the API through drm_gpuvm_bo_obtain() and 82 82 * drm_gpuvm_bo_obtain_prealloc() which first look into the corresponding 83 83 * &drm_gem_object list of &drm_gpuvm_bos for an existing instance of this 84 - * particular combination. If not existent a new instance is created and linked 84 + * particular combination. If not present, a new instance is created and linked 85 85 * to the &drm_gem_object. 86 86 * 87 87 * &drm_gpuvm_bo structures, since unique for a given &drm_gpuvm, are also used ··· 108 108 * sequence of operations to satisfy a given map or unmap request. 109 109 * 110 110 * Therefore the DRM GPU VA manager provides an algorithm implementing splitting 111 - * and merging of existent GPU VA mappings with the ones that are requested to 111 + * and merging of existing GPU VA mappings with the ones that are requested to 112 112 * be mapped or unmapped. This feature is required by the Vulkan API to 113 113 * implement Vulkan 'Sparse Memory Bindings' - drivers UAPIs often refer to this 114 114 * as VM BIND. ··· 119 119 * execute in order to integrate the new mapping cleanly into the current state 120 120 * of the GPU VA space. 121 121 * 122 - * Depending on how the new GPU VA mapping intersects with the existent mappings 122 + * Depending on how the new GPU VA mapping intersects with the existing mappings 123 123 * of the GPU VA space the &drm_gpuvm_ops callbacks contain an arbitrary amount 124 124 * of unmap operations, a maximum of two remap operations and a single map 125 125 * operation. The caller might receive no callback at all if no operation is ··· 139 139 * one unmap operation and one or two map operations, such that drivers can 140 140 * derive the page table update delta accordingly. 141 141 * 142 - * Note that there can't be more than two existent mappings to split up, one at 142 + * Note that there can't be more than two existing mappings to split up, one at 143 143 * the beginning and one at the end of the new mapping, hence there is a 144 144 * maximum of two remap operations. 145 145 * 146 146 * Analogous to drm_gpuvm_sm_map() drm_gpuvm_sm_unmap() uses &drm_gpuvm_ops to 147 147 * call back into the driver in order to unmap a range of GPU VA space. The 148 - * logic behind this function is way simpler though: For all existent mappings 148 + * logic behind this function is way simpler though: For all existing mappings 149 149 * enclosed by the given range unmap operations are created. For mappings which 150 - * are only partically located within the given range, remap operations are 151 - * created such that those mappings are split up and re-mapped partically. 150 + * are only partially located within the given range, remap operations are 151 + * created such that those mappings are split up and re-mapped partially. 152 152 * 153 153 * As an alternative to drm_gpuvm_sm_map() and drm_gpuvm_sm_unmap(), 154 154 * drm_gpuvm_sm_map_ops_create() and drm_gpuvm_sm_unmap_ops_create() can be used ··· 168 168 * provided helper functions drm_gpuva_map(), drm_gpuva_remap() and 169 169 * drm_gpuva_unmap() instead. 170 170 * 171 - * The following diagram depicts the basic relationships of existent GPU VA 171 + * The following diagram depicts the basic relationships of existing GPU VA 172 172 * mappings, a newly requested mapping and the resulting mappings as implemented 173 173 * by drm_gpuvm_sm_map() - it doesn't cover any arbitrary combinations of these. 174 174 * ··· 218 218 * 219 219 * 220 220 * 4) Existent mapping is a left aligned subset of the requested one, hence 221 - * replace the existent one. 221 + * replace the existing one. 222 222 * 223 223 * :: 224 224 * ··· 236 236 * and/or non-contiguous BO offset. 237 237 * 238 238 * 239 - * 5) Requested mapping's range is a left aligned subset of the existent one, 239 + * 5) Requested mapping's range is a left aligned subset of the existing one, 240 240 * but backed by a different BO. Hence, map the requested mapping and split 241 - * the existent one adjusting its BO offset. 241 + * the existing one adjusting its BO offset. 242 242 * 243 243 * :: 244 244 * ··· 271 271 * new: |-----|-----| (a.bo_offset=n, a'.bo_offset=n+1) 272 272 * 273 273 * 274 - * 7) Requested mapping's range is a right aligned subset of the existent one, 274 + * 7) Requested mapping's range is a right aligned subset of the existing one, 275 275 * but backed by a different BO. Hence, map the requested mapping and split 276 - * the existent one, without adjusting the BO offset. 276 + * the existing one, without adjusting the BO offset. 277 277 * 278 278 * :: 279 279 * ··· 304 304 * 305 305 * 9) Existent mapping is overlapped at the end by the requested mapping backed 306 306 * by a different BO. Hence, map the requested mapping and split up the 307 - * existent one, without adjusting the BO offset. 307 + * existing one, without adjusting the BO offset. 308 308 * 309 309 * :: 310 310 * ··· 334 334 * new: |-----|-----------| (a'.bo_offset=n, a.bo_offset=n+1) 335 335 * 336 336 * 337 - * 11) Requested mapping's range is a centered subset of the existent one 337 + * 11) Requested mapping's range is a centered subset of the existing one 338 338 * having a different backing BO. Hence, map the requested mapping and split 339 - * up the existent one in two mappings, adjusting the BO offset of the right 339 + * up the existing one in two mappings, adjusting the BO offset of the right 340 340 * one accordingly. 341 341 * 342 342 * :: ··· 351 351 * new: |-----|-----|-----| (a.bo_offset=n,b.bo_offset=m,a'.bo_offset=n+2) 352 352 * 353 353 * 354 - * 12) Requested mapping is a contiguous subset of the existent one. Split it 354 + * 12) Requested mapping is a contiguous subset of the existing one. Split it 355 355 * up, but indicate that the backing PTEs could be kept. 356 356 * 357 357 * :: ··· 367 367 * 368 368 * 369 369 * 13) Existent mapping is a right aligned subset of the requested one, hence 370 - * replace the existent one. 370 + * replace the existing one. 371 371 * 372 372 * :: 373 373 * ··· 386 386 * 387 387 * 388 388 * 14) Existent mapping is a centered subset of the requested one, hence 389 - * replace the existent one. 389 + * replace the existing one. 390 390 * 391 391 * :: 392 392 * ··· 406 406 * 407 407 * 15) Existent mappings is overlapped at the beginning by the requested mapping 408 408 * backed by a different BO. Hence, map the requested mapping and split up 409 - * the existent one, adjusting its BO offset accordingly. 409 + * the existing one, adjusting its BO offset accordingly. 410 410 * 411 411 * :: 412 412 * ··· 469 469 * make use of them. 470 470 * 471 471 * The below code is strictly limited to illustrate the generic usage pattern. 472 - * To maintain simplicitly, it doesn't make use of any abstractions for common 473 - * code, different (asyncronous) stages with fence signalling critical paths, 472 + * To maintain simplicity, it doesn't make use of any abstractions for common 473 + * code, different (asynchronous) stages with fence signalling critical paths, 474 474 * any other helpers or error handling in terms of freeing memory and dropping 475 475 * previously taken locks. 476 476 * ··· 479 479 * // Allocates a new &drm_gpuva. 480 480 * struct drm_gpuva * driver_gpuva_alloc(void); 481 481 * 482 - * // Typically drivers would embedd the &drm_gpuvm and &drm_gpuva 482 + * // Typically drivers would embed the &drm_gpuvm and &drm_gpuva 483 483 * // structure in individual driver structures and lock the dma-resv with 484 484 * // drm_exec or similar helpers. 485 485 * int driver_mapping_create(struct drm_gpuvm *gpuvm, ··· 582 582 * .sm_step_unmap = driver_gpuva_unmap, 583 583 * }; 584 584 * 585 - * // Typically drivers would embedd the &drm_gpuvm and &drm_gpuva 585 + * // Typically drivers would embed the &drm_gpuvm and &drm_gpuva 586 586 * // structure in individual driver structures and lock the dma-resv with 587 587 * // drm_exec or similar helpers. 588 588 * int driver_mapping_create(struct drm_gpuvm *gpuvm, ··· 680 680 * 681 681 * This helper is here to provide lockless list iteration. Lockless as in, the 682 682 * iterator releases the lock immediately after picking the first element from 683 - * the list, so list insertion deletion can happen concurrently. 683 + * the list, so list insertion and deletion can happen concurrently. 684 684 * 685 685 * Elements popped from the original list are kept in a local list, so removal 686 686 * and is_empty checks can still happen while we're iterating the list. ··· 1160 1160 } 1161 1161 1162 1162 /** 1163 - * drm_gpuvm_prepare_objects() - prepare all assoiciated BOs 1163 + * drm_gpuvm_prepare_objects() - prepare all associated BOs 1164 1164 * @gpuvm: the &drm_gpuvm 1165 1165 * @exec: the &drm_exec locking context 1166 1166 * @num_fences: the amount of &dma_fences to reserve ··· 1230 1230 EXPORT_SYMBOL_GPL(drm_gpuvm_prepare_range); 1231 1231 1232 1232 /** 1233 - * drm_gpuvm_exec_lock() - lock all dma-resv of all assoiciated BOs 1233 + * drm_gpuvm_exec_lock() - lock all dma-resv of all associated BOs 1234 1234 * @vm_exec: the &drm_gpuvm_exec wrapper 1235 1235 * 1236 1236 * Acquires all dma-resv locks of all &drm_gem_objects the given 1237 1237 * &drm_gpuvm contains mappings of. 1238 1238 * 1239 - * Addionally, when calling this function with struct drm_gpuvm_exec::extra 1239 + * Additionally, when calling this function with struct drm_gpuvm_exec::extra 1240 1240 * being set the driver receives the given @fn callback to lock additional 1241 1241 * dma-resv in the context of the &drm_gpuvm_exec instance. Typically, drivers 1242 1242 * would call drm_exec_prepare_obj() from within this callback. ··· 1293 1293 } 1294 1294 1295 1295 /** 1296 - * drm_gpuvm_exec_lock_array() - lock all dma-resv of all assoiciated BOs 1296 + * drm_gpuvm_exec_lock_array() - lock all dma-resv of all associated BOs 1297 1297 * @vm_exec: the &drm_gpuvm_exec wrapper 1298 1298 * @objs: additional &drm_gem_objects to lock 1299 1299 * @num_objs: the number of additional &drm_gem_objects to lock ··· 1588 1588 EXPORT_SYMBOL_GPL(drm_gpuvm_bo_find); 1589 1589 1590 1590 /** 1591 - * drm_gpuvm_bo_obtain() - obtains and instance of the &drm_gpuvm_bo for the 1591 + * drm_gpuvm_bo_obtain() - obtains an instance of the &drm_gpuvm_bo for the 1592 1592 * given &drm_gpuvm and &drm_gem_object 1593 1593 * @gpuvm: The &drm_gpuvm the @obj is mapped in. 1594 1594 * @obj: The &drm_gem_object being mapped in the @gpuvm. ··· 1624 1624 EXPORT_SYMBOL_GPL(drm_gpuvm_bo_obtain); 1625 1625 1626 1626 /** 1627 - * drm_gpuvm_bo_obtain_prealloc() - obtains and instance of the &drm_gpuvm_bo 1627 + * drm_gpuvm_bo_obtain_prealloc() - obtains an instance of the &drm_gpuvm_bo 1628 1628 * for the given &drm_gpuvm and &drm_gem_object 1629 1629 * @__vm_bo: A pre-allocated struct drm_gpuvm_bo. 1630 1630 * ··· 1688 1688 * @vm_bo: the &drm_gpuvm_bo to add or remove 1689 1689 * @evict: indicates whether the object is evicted 1690 1690 * 1691 - * Adds a &drm_gpuvm_bo to or removes it from the &drm_gpuvms evicted list. 1691 + * Adds a &drm_gpuvm_bo to or removes it from the &drm_gpuvm's evicted list. 1692 1692 */ 1693 1693 void 1694 1694 drm_gpuvm_bo_evict(struct drm_gpuvm_bo *vm_bo, bool evict) ··· 1790 1790 * drm_gpuva_remove() - remove a &drm_gpuva 1791 1791 * @va: the &drm_gpuva to remove 1792 1792 * 1793 - * This removes the given &va from the underlaying tree. 1793 + * This removes the given &va from the underlying tree. 1794 1794 * 1795 1795 * It is safe to use this function using the safe versions of iterating the GPU 1796 1796 * VA space, such as drm_gpuvm_for_each_va_safe() and ··· 2358 2358 * 2359 2359 * This function iterates the given range of the GPU VA space. It utilizes the 2360 2360 * &drm_gpuvm_ops to call back into the driver providing the operations to 2361 - * unmap and, if required, split existent mappings. 2361 + * unmap and, if required, split existing mappings. 2362 2362 * 2363 2363 * Drivers may use these callbacks to update the GPU VA space right away within 2364 2364 * the callback. In case the driver decides to copy and store the operations for ··· 2430 2430 * remapped, and locks+prepares (drm_exec_prepare_object()) objects that 2431 2431 * will be newly mapped. 2432 2432 * 2433 - * The expected usage is: 2433 + * The expected usage is:: 2434 2434 * 2435 2435 * .. code-block:: c 2436 2436 * ··· 2475 2475 * required without the earlier DRIVER_OP_MAP. This is safe because we've 2476 2476 * already locked the GEM object in the earlier DRIVER_OP_MAP step. 2477 2477 * 2478 - * Returns: 0 on success or a negative error codec 2478 + * Returns: 0 on success or a negative error code 2479 2479 */ 2480 2480 int 2481 2481 drm_gpuvm_sm_map_exec_lock(struct drm_gpuvm *gpuvm, ··· 2619 2619 * @req_offset: the offset within the &drm_gem_object 2620 2620 * 2621 2621 * This function creates a list of operations to perform splitting and merging 2622 - * of existent mapping(s) with the newly requested one. 2622 + * of existing mapping(s) with the newly requested one. 2623 2623 * 2624 2624 * The list can be iterated with &drm_gpuva_for_each_op and must be processed 2625 2625 * in the given order. It can contain map, unmap and remap operations, but it 2626 2626 * also can be empty if no operation is required, e.g. if the requested mapping 2627 - * already exists is the exact same way. 2627 + * already exists in the exact same way. 2628 2628 * 2629 2629 * There can be an arbitrary amount of unmap operations, a maximum of two remap 2630 2630 * operations and a single map operation. The latter one represents the original
+14 -7
drivers/gpu/drm/mediatek/mtk_drm_drv.c
··· 387 387 388 388 of_id = of_match_node(mtk_drm_of_ids, node); 389 389 if (!of_id) 390 - continue; 390 + goto next_put_node; 391 391 392 392 pdev = of_find_device_by_node(node); 393 393 if (!pdev) 394 - continue; 394 + goto next_put_node; 395 395 396 396 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 397 397 if (!drm_dev) 398 - continue; 398 + goto next_put_device_pdev_dev; 399 399 400 400 temp_drm_priv = dev_get_drvdata(drm_dev); 401 401 if (!temp_drm_priv) 402 - continue; 402 + goto next_put_device_drm_dev; 403 403 404 404 if (temp_drm_priv->data->main_len) 405 405 all_drm_priv[CRTC_MAIN] = temp_drm_priv; ··· 411 411 if (temp_drm_priv->mtk_drm_bound) 412 412 cnt++; 413 413 414 - if (cnt == MAX_CRTC) { 415 - of_node_put(node); 414 + next_put_device_drm_dev: 415 + put_device(drm_dev); 416 + 417 + next_put_device_pdev_dev: 418 + put_device(&pdev->dev); 419 + 420 + next_put_node: 421 + of_node_put(node); 422 + 423 + if (cnt == MAX_CRTC) 416 424 break; 417 - } 418 425 } 419 426 420 427 if (drm_priv->data->mmsys_dev_num == cnt) {
+6
drivers/gpu/drm/mediatek/mtk_dsi.c
··· 1002 1002 return PTR_ERR(dsi->next_bridge); 1003 1003 } 1004 1004 1005 + /* 1006 + * set flag to request the DSI host bridge be pre-enabled before device bridge 1007 + * in the chain, so the DSI host is ready when the device bridge is pre-enabled 1008 + */ 1009 + dsi->next_bridge->pre_enable_prev_first = true; 1010 + 1005 1011 drm_bridge_add(&dsi->bridge); 1006 1012 1007 1013 ret = component_add(host->dev, &mtk_dsi_component_ops);
+4 -4
drivers/gpu/drm/mediatek/mtk_hdmi.c
··· 182 182 183 183 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 184 184 { 185 - regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL, 186 - VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH); 185 + regmap_update_bits(hdmi->regs, VIDEO_CFG_4, 186 + VIDEO_SOURCE_SEL, black ? GEN_RGB : NORMAL_PATH); 187 187 } 188 188 189 189 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) ··· 310 310 311 311 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 312 312 { 313 - regmap_update_bits(hdmi->regs, AUDIO_PACKET_OFF, 314 - GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF); 313 + regmap_update_bits(hdmi->regs, GRL_SHIFT_R2, 314 + AUDIO_PACKET_OFF, enable ? 0 : AUDIO_PACKET_OFF); 315 315 } 316 316 317 317 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
+2 -1
drivers/gpu/drm/mediatek/mtk_plane.c
··· 292 292 wmb(); /* Make sure the above parameter is set before update */ 293 293 mtk_plane_state->pending.dirty = true; 294 294 295 - mtk_crtc_plane_disable(old_state->crtc, plane); 295 + if (old_state && old_state->crtc) 296 + mtk_crtc_plane_disable(old_state->crtc, plane); 296 297 } 297 298 298 299 static void mtk_plane_atomic_update(struct drm_plane *plane,
+33 -14
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
··· 11 11 static const unsigned int *gen7_0_0_external_core_regs[] __always_unused; 12 12 static const unsigned int *gen7_2_0_external_core_regs[] __always_unused; 13 13 static const unsigned int *gen7_9_0_external_core_regs[] __always_unused; 14 - static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused; 14 + static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused; 15 15 static const u32 gen7_9_0_cx_debugbus_blocks[] __always_unused; 16 16 17 17 #include "adreno_gen7_0_0_snapshot.h" ··· 174 174 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, 175 175 u32 *data) 176 176 { 177 - u32 reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | 178 - A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block); 177 + u32 reg; 178 + 179 + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { 180 + reg = A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | 181 + A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block); 182 + } else { 183 + reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | 184 + A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block); 185 + } 179 186 180 187 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); 181 188 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); ··· 205 198 readl((ptr) + ((offset) << 2)) 206 199 207 200 /* read a value from the CX debug bus */ 208 - static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset, 201 + static int cx_debugbus_read(struct msm_gpu *gpu, void __iomem *cxdbg, u32 block, u32 offset, 209 202 u32 *data) 210 203 { 211 - u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | 212 - A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); 204 + u32 reg; 205 + 206 + if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { 207 + reg = A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | 208 + A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); 209 + } else { 210 + reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | 211 + A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block); 212 + } 213 213 214 214 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A, reg); 215 215 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B, reg); ··· 329 315 ptr += debugbus_read(gpu, block->id, i, ptr); 330 316 } 331 317 332 - static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg, 318 + static void a6xx_get_cx_debugbus_block(struct msm_gpu *gpu, 319 + void __iomem *cxdbg, 333 320 struct a6xx_gpu_state *a6xx_state, 334 321 const struct a6xx_debugbus_block *block, 335 322 struct a6xx_gpu_state_obj *obj) ··· 345 330 obj->handle = block; 346 331 347 332 for (ptr = obj->data, i = 0; i < block->count; i++) 348 - ptr += cx_debugbus_read(cxdbg, block->id, i, ptr); 333 + ptr += cx_debugbus_read(gpu, cxdbg, block->id, i, ptr); 349 334 } 350 335 351 336 static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu, ··· 438 423 a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]], 439 424 &a6xx_state->debugbus[i + debugbus_blocks_count]); 440 425 } 441 - } 442 426 427 + a6xx_state->nr_debugbus = total_debugbus_blocks; 428 + } 443 429 } 444 430 445 431 static void a6xx_get_debugbus(struct msm_gpu *gpu, ··· 542 526 int i; 543 527 544 528 for (i = 0; i < nr_cx_debugbus_blocks; i++) 545 - a6xx_get_cx_debugbus_block(cxdbg, 529 + a6xx_get_cx_debugbus_block(gpu, 530 + cxdbg, 546 531 a6xx_state, 547 532 &cx_debugbus_blocks[i], 548 533 &a6xx_state->cx_debugbus[i]); ··· 776 759 size_t datasize; 777 760 int i, regcount = 0; 778 761 779 - /* Some clusters need a selector register to be programmed too */ 780 - if (cluster->sel) 781 - in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val); 782 - 783 762 in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD, 784 763 A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) | 785 764 A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) | 786 765 A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id)); 766 + 767 + /* Some clusters need a selector register to be programmed too */ 768 + if (cluster->sel) 769 + in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val); 787 770 788 771 for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) { 789 772 int count = RANGE(cluster->regs, i); ··· 1813 1796 1814 1797 print_name(p, " - type: ", a7xx_statetype_names[block->statetype]); 1815 1798 print_name(p, " - pipe: ", a7xx_pipe_names[block->pipeid]); 1799 + drm_printf(p, " - location: %d\n", block->location); 1816 1800 1817 1801 for (i = 0; i < block->num_sps; i++) { 1818 1802 drm_printf(p, " - sp: %d\n", i); ··· 1891 1873 print_name(p, " - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]); 1892 1874 print_name(p, " - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]); 1893 1875 drm_printf(p, " - context: %d\n", dbgahb->context_id); 1876 + drm_printf(p, " - location: %d\n", dbgahb->location_id); 1894 1877 a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4); 1895 1878 } 1896 1879 }
+19 -19
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
··· 419 419 REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, 420 420 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 421 421 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, 422 - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 422 + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 423 423 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 424 - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 424 + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 425 425 REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size}, 426 426 }; 427 427 428 428 static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = { 429 429 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, 430 - REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, 430 + REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL }, 431 431 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 432 432 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, 433 - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 433 + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 434 434 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 435 - { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, 436 - REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL }, 437 - { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 435 + { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR, 436 + REG_A7XX_CP_BV_SQE_STAT_DATA, 0x40, NULL }, 437 + { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 438 438 REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL }, 439 - { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 439 + { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 440 440 REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 441 - { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR, 442 - REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL }, 443 - { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 441 + { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR, 442 + REG_A7XX_CP_SQE_AC_STAT_DATA, 0x40, NULL }, 443 + { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 444 444 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL }, 445 - { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 445 + { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 446 446 REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL }, 447 - { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 447 + { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 448 448 REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL }, 449 - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 449 + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 450 450 REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size }, 451 451 }; 452 452 453 453 static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = { 454 - "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 454 + "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 455 455 REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL, 456 456 }; 457 457 458 458 static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = { 459 - { "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 460 - REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL }, 461 - { "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR, 462 - REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL }, 459 + { "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR, 460 + REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2200, NULL }, 461 + { "CP_BV_MEM_POOL_DBG", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR, 462 + REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2200, NULL }, 463 463 }; 464 464 465 465 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
+13 -6
drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h
··· 81 81 A7XX_DBGBUS_USPTP_7, 82 82 }; 83 83 84 - static struct gen7_shader_block gen7_0_0_shader_blocks[] = { 84 + static const struct gen7_shader_block gen7_0_0_shader_blocks[] = { 85 85 {A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, 86 86 {A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, 87 87 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, ··· 668 668 }; 669 669 static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8)); 670 670 671 - /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ 672 - static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = { 671 + /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */ 672 + static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] = { 673 673 0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, 674 674 0x0b60f, 0x0b621, 0x0b630, 0x0b633, 675 675 UINT_MAX, UINT_MAX, 676 + }; 677 + static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registers), 8)); 678 + 679 + /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ 680 + static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = { 681 + 0x0b600, 0x0b600, 682 + UINT_MAX, UINT_MAX, 676 683 }; 677 684 static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8)); 678 685 ··· 702 695 .val = 0x9, 703 696 }; 704 697 705 - static struct gen7_cluster_registers gen7_0_0_clusters[] = { 698 + static const struct gen7_cluster_registers gen7_0_0_clusters[] = { 706 699 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 707 700 gen7_0_0_noncontext_pipe_br_registers, }, 708 701 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, ··· 771 764 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, 772 765 }; 773 766 774 - static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = { 767 + static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = { 775 768 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 776 769 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, 777 770 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, ··· 921 914 }; 922 915 static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8)); 923 916 924 - static struct gen7_reg_list gen7_0_0_reg_list[] = { 917 + static const struct gen7_reg_list gen7_0_0_reg_list[] = { 925 918 { gen7_0_0_gpu_registers, NULL }, 926 919 { gen7_0_0_cx_misc_registers, NULL }, 927 920 { gen7_0_0_dpm_registers, NULL },
+6 -4
drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h
··· 95 95 A7XX_DBGBUS_CCHE_2, 96 96 }; 97 97 98 - static struct gen7_shader_block gen7_2_0_shader_blocks[] = { 98 + static const struct gen7_shader_block gen7_2_0_shader_blocks[] = { 99 99 {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, 100 100 {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, 101 101 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, ··· 489 489 .val = 0x9, 490 490 }; 491 491 492 - static struct gen7_cluster_registers gen7_2_0_clusters[] = { 492 + static const struct gen7_cluster_registers gen7_2_0_clusters[] = { 493 493 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 494 494 gen7_2_0_noncontext_pipe_br_registers, }, 495 495 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, ··· 558 558 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, 559 559 }; 560 560 561 - static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = { 561 + static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = { 562 562 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 563 563 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, 564 564 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, ··· 573 573 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 }, 574 574 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, 575 575 gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 }, 576 + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP, 577 + gen7_0_0_tpl1_noncontext_pipe_none_registers, 0xb600 }, 576 578 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, 577 579 gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 }, 578 580 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, ··· 739 737 }; 740 738 static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_registers), 8)); 741 739 742 - static struct gen7_reg_list gen7_2_0_reg_list[] = { 740 + static const struct gen7_reg_list gen7_2_0_reg_list[] = { 743 741 { gen7_2_0_gpu_registers, NULL }, 744 742 { gen7_2_0_cx_misc_registers, NULL }, 745 743 { gen7_2_0_dpm_registers, NULL },
+17 -17
drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
··· 117 117 A7XX_DBGBUS_GBIF_CX, 118 118 }; 119 119 120 - static struct gen7_shader_block gen7_9_0_shader_blocks[] = { 120 + static const struct gen7_shader_block gen7_9_0_shader_blocks[] = { 121 121 { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 122 122 { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, 123 123 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP }, ··· 1116 1116 .val = 0x9, 1117 1117 }; 1118 1118 1119 - static struct gen7_cluster_registers gen7_9_0_clusters[] = { 1119 + static const struct gen7_cluster_registers gen7_9_0_clusters[] = { 1120 1120 { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, 1121 1121 gen7_9_0_non_context_pipe_br_registers, }, 1122 1122 { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, ··· 1185 1185 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, }, 1186 1186 }; 1187 1187 1188 - static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { 1188 + static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = { 1189 1189 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, 1190 1190 gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00}, 1191 1191 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, ··· 1294 1294 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000}, 1295 1295 }; 1296 1296 1297 - static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { 1297 + static const struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = { 1298 1298 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, 1299 1299 REG_A6XX_CP_SQE_STAT_DATA, 0x00040}, 1300 1300 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 1301 1301 REG_A6XX_CP_DRAW_STATE_DATA, 0x00200}, 1302 - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, 1302 + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 1303 1303 REG_A6XX_CP_ROQ_DBG_DATA, 0x00800}, 1304 - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 1304 + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 1305 1305 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000}, 1306 - { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 1306 + { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR, 1307 1307 REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200}, 1308 - { "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR, 1308 + { "CP_BV_ROQ_DBG", REG_A7XX_CP_BV_ROQ_DBG_ADDR, 1309 1309 REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800}, 1310 - { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 1310 + { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, 1311 1311 REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000}, 1312 - { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, 1312 + { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR, 1313 1313 REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040}, 1314 - { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR, 1314 + { "CP_RESOURCE_TABLE_DBG", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR, 1315 1315 REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100}, 1316 - { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 1316 + { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, 1317 1317 REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200}, 1318 - { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR, 1318 + { "CP_LPAC_ROQ_DBG", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR, 1319 1319 REG_A7XX_CP_LPAC_ROQ_DBG_DATA, 0x00200}, 1320 - { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 1320 + { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, 1321 1321 REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x08000}, 1322 - { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR, 1322 + { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR, 1323 1323 REG_A7XX_CP_SQE_AC_STAT_DATA, 0x00040}, 1324 - { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 1324 + { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, 1325 1325 REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x00040}, 1326 1326 { "CP_AQE_ROQ_0", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0, 1327 1327 REG_A7XX_CP_AQE_ROQ_DBG_DATA_0, 0x00100}, ··· 1337 1337 REG_A7XX_CP_AQE_STAT_DATA_1, 0x00040}, 1338 1338 }; 1339 1339 1340 - static struct gen7_reg_list gen7_9_0_reg_list[] = { 1340 + static const struct gen7_reg_list gen7_9_0_reg_list[] = { 1341 1341 { gen7_9_0_gpu_registers, NULL}, 1342 1342 { gen7_9_0_cx_misc_registers, NULL}, 1343 1343 { gen7_9_0_cx_dbgc_registers, NULL},
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
··· 596 596 597 597 spin_lock_irqsave(&dev->event_lock, flags); 598 598 if (dpu_crtc->event) { 599 - DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 599 + DRM_DEBUG_VBL("%s: send event: %p\n", dpu_crtc->name, 600 600 dpu_crtc->event); 601 601 trace_dpu_crtc_complete_flip(DRMID(crtc)); 602 602 drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
··· 730 730 return false; 731 731 732 732 conn_state = drm_atomic_get_new_connector_state(state, connector); 733 + if (!conn_state) 734 + return false; 733 735 734 736 /** 735 737 * These checks are duplicated from dpu_encoder_update_topology() since
+2 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
··· 31 31 u32 base; 32 32 33 33 if (!ctx) { 34 - DRM_ERROR("invalid ctx %pK\n", ctx); 34 + DRM_ERROR("invalid ctx %p\n", ctx); 35 35 return; 36 36 } 37 37 38 38 base = ctx->cap->sblk->pcc.base; 39 39 40 40 if (!base) { 41 - DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base); 41 + DRM_ERROR("invalid ctx %p pcc base 0x%x\n", ctx, base); 42 42 return; 43 43 } 44 44
+2 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
··· 1345 1345 dpu_kms->mmio = NULL; 1346 1346 return ret; 1347 1347 } 1348 - DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1348 + DRM_DEBUG("mapped dpu address space @%p\n", dpu_kms->mmio); 1349 1349 1350 1350 dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev, 1351 1351 dpu_kms->pdev, ··· 1380 1380 dpu_kms->mmio = NULL; 1381 1381 return ret; 1382 1382 } 1383 - DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); 1383 + DRM_DEBUG("mapped dpu address space @%p\n", dpu_kms->mmio); 1384 1384 1385 1385 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); 1386 1386 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
+2 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
··· 1129 1129 struct drm_plane_state *old_plane_state = 1130 1130 drm_atomic_get_old_plane_state(state, plane); 1131 1131 struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); 1132 - struct drm_crtc_state *crtc_state; 1132 + struct drm_crtc_state *crtc_state = NULL; 1133 1133 int ret; 1134 1134 1135 1135 if (IS_ERR(plane_state)) ··· 1162 1162 if (!old_plane_state || !old_plane_state->fb || 1163 1163 old_plane_state->src_w != plane_state->src_w || 1164 1164 old_plane_state->src_h != plane_state->src_h || 1165 - old_plane_state->src_w != plane_state->src_w || 1165 + old_plane_state->crtc_w != plane_state->crtc_w || 1166 1166 old_plane_state->crtc_h != plane_state->crtc_h || 1167 1167 msm_framebuffer_format(old_plane_state->fb) != 1168 1168 msm_framebuffer_format(plane_state->fb))
+18 -41
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
··· 5 5 6 6 #include <linux/clk-provider.h> 7 7 #include <linux/platform_device.h> 8 + #include <linux/pm_clock.h> 9 + #include <linux/pm_runtime.h> 8 10 #include <dt-bindings/phy/phy.h> 9 11 10 12 #include "dsi_phy.h" ··· 513 511 return 0; 514 512 } 515 513 516 - static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) 517 - { 518 - struct device *dev = &phy->pdev->dev; 519 - int ret; 520 - 521 - ret = pm_runtime_resume_and_get(dev); 522 - if (ret) 523 - return ret; 524 - 525 - ret = clk_prepare_enable(phy->ahb_clk); 526 - if (ret) { 527 - DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret); 528 - pm_runtime_put_sync(dev); 529 - } 530 - 531 - return ret; 532 - } 533 - 534 - static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) 535 - { 536 - clk_disable_unprepare(phy->ahb_clk); 537 - pm_runtime_put(&phy->pdev->dev); 538 - } 539 - 540 514 static const struct of_device_id dsi_phy_dt_match[] = { 541 515 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY 542 516 { .compatible = "qcom,dsi-phy-28nm-hpm", ··· 676 698 if (ret) 677 699 return ret; 678 700 679 - phy->ahb_clk = msm_clk_get(pdev, "iface"); 680 - if (IS_ERR(phy->ahb_clk)) 681 - return dev_err_probe(dev, PTR_ERR(phy->ahb_clk), 682 - "Unable to get ahb clk\n"); 701 + platform_set_drvdata(pdev, phy); 683 702 684 - ret = devm_pm_runtime_enable(&pdev->dev); 703 + ret = devm_pm_runtime_enable(dev); 685 704 if (ret) 686 705 return ret; 687 706 688 - /* PLL init will call into clk_register which requires 689 - * register access, so we need to enable power and ahb clock. 690 - */ 691 - ret = dsi_phy_enable_resource(phy); 707 + ret = devm_pm_clk_create(dev); 692 708 if (ret) 693 709 return ret; 710 + 711 + ret = pm_clk_add(dev, "iface"); 712 + if (ret < 0) 713 + return dev_err_probe(dev, ret, "Unable to get iface clk\n"); 694 714 695 715 if (phy->cfg->ops.pll_init) { 696 716 ret = phy->cfg->ops.pll_init(phy); ··· 703 727 return dev_err_probe(dev, ret, 704 728 "Failed to register clk provider\n"); 705 729 706 - dsi_phy_disable_resource(phy); 707 - 708 - platform_set_drvdata(pdev, phy); 709 - 710 730 return 0; 711 731 } 732 + 733 + static const struct dev_pm_ops dsi_phy_pm_ops = { 734 + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) 735 + }; 712 736 713 737 static struct platform_driver dsi_phy_platform_driver = { 714 738 .probe = dsi_phy_driver_probe, 715 739 .driver = { 716 740 .name = "msm_dsi_phy", 717 741 .of_match_table = dsi_phy_dt_match, 742 + .pm = &dsi_phy_pm_ops, 718 743 }, 719 744 }; 720 745 ··· 741 764 742 765 dev = &phy->pdev->dev; 743 766 744 - ret = dsi_phy_enable_resource(phy); 767 + ret = pm_runtime_resume_and_get(dev); 745 768 if (ret) { 746 - DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n", 769 + DRM_DEV_ERROR(dev, "%s: resume failed, %d\n", 747 770 __func__, ret); 748 771 goto res_en_fail; 749 772 } ··· 787 810 phy_en_fail: 788 811 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); 789 812 reg_en_fail: 790 - dsi_phy_disable_resource(phy); 813 + pm_runtime_put(dev); 791 814 res_en_fail: 792 815 return ret; 793 816 } ··· 800 823 phy->cfg->ops.disable(phy); 801 824 802 825 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); 803 - dsi_phy_disable_resource(phy); 826 + pm_runtime_put(&phy->pdev->dev); 804 827 } 805 828 806 829 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
-1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
··· 104 104 phys_addr_t lane_size; 105 105 int id; 106 106 107 - struct clk *ahb_clk; 108 107 struct regulator_bulk_data *supplies; 109 108 110 109 struct msm_dsi_dphy_timing timing;
+7 -4
drivers/gpu/drm/msm/msm_debugfs.c
··· 325 325 326 326 static int late_init_minor(struct drm_minor *minor) 327 327 { 328 - struct drm_device *dev = minor->dev; 329 - struct msm_drm_private *priv = dev->dev_private; 328 + struct drm_device *dev; 329 + struct msm_drm_private *priv; 330 330 int ret; 331 331 332 332 if (!minor) 333 333 return 0; 334 + 335 + dev = minor->dev; 336 + priv = dev->dev_private; 334 337 335 338 if (!priv->gpu_pdev) 336 339 return 0; 337 340 338 341 ret = msm_rd_debugfs_init(minor); 339 342 if (ret) { 340 - DRM_DEV_ERROR(minor->dev->dev, "could not install rd debugfs\n"); 343 + DRM_DEV_ERROR(dev->dev, "could not install rd debugfs\n"); 341 344 return ret; 342 345 } 343 346 344 347 ret = msm_perf_debugfs_init(minor); 345 348 if (ret) { 346 - DRM_DEV_ERROR(minor->dev->dev, "could not install perf debugfs\n"); 349 + DRM_DEV_ERROR(dev->dev, "could not install perf debugfs\n"); 347 350 return ret; 348 351 } 349 352
+11 -2
drivers/gpu/drm/msm/msm_gem.c
··· 95 95 void msm_gem_vma_put(struct drm_gem_object *obj) 96 96 { 97 97 struct msm_drm_private *priv = obj->dev->dev_private; 98 - struct drm_exec exec; 99 98 100 99 if (atomic_dec_return(&to_msm_bo(obj)->vma_ref)) 101 100 return; ··· 102 103 if (!priv->kms) 103 104 return; 104 105 106 + #ifdef CONFIG_DRM_MSM_KMS 107 + struct drm_exec exec; 108 + 105 109 msm_gem_lock_vm_and_obj(&exec, obj, priv->kms->vm); 106 110 put_iova_spaces(obj, priv->kms->vm, true, "vma_put"); 107 111 drm_exec_fini(&exec); /* drop locks */ 112 + #endif 108 113 } 109 114 110 115 /* ··· 666 663 667 664 static bool is_kms_vm(struct drm_gpuvm *vm) 668 665 { 666 + #ifdef CONFIG_DRM_MSM_KMS 669 667 struct msm_drm_private *priv = vm->drm->dev_private; 670 668 671 669 return priv->kms && (priv->kms->vm == vm); 670 + #else 671 + return false; 672 + #endif 672 673 } 673 674 674 675 /* ··· 1120 1113 put_pages(obj); 1121 1114 } 1122 1115 1123 - if (msm_obj->flags & MSM_BO_NO_SHARE) { 1116 + if (obj->resv != &obj->_resv) { 1124 1117 struct drm_gem_object *r_obj = 1125 1118 container_of(obj->resv, struct drm_gem_object, _resv); 1119 + 1120 + WARN_ON(!(msm_obj->flags & MSM_BO_NO_SHARE)); 1126 1121 1127 1122 /* Drop reference we hold to shared resv obj: */ 1128 1123 drm_gem_object_put(r_obj);
+1 -1
drivers/gpu/drm/msm/msm_gem.h
··· 100 100 * 101 101 * Only used for kernel managed VMs, unused for user managed VMs. 102 102 * 103 - * Protected by @mm_lock. 103 + * Protected by vm lock. See msm_gem_lock_vm_and_obj(), for ex. 104 104 */ 105 105 struct drm_mm mm; 106 106
+41 -35
drivers/gpu/drm/msm/msm_gem_submit.c
··· 271 271 return ret; 272 272 } 273 273 274 + static int submit_lock_objects_vmbind(struct msm_gem_submit *submit) 275 + { 276 + unsigned flags = DRM_EXEC_INTERRUPTIBLE_WAIT | DRM_EXEC_IGNORE_DUPLICATES; 277 + struct drm_exec *exec = &submit->exec; 278 + int ret = 0; 279 + 280 + drm_exec_init(&submit->exec, flags, submit->nr_bos); 281 + 282 + drm_exec_until_all_locked (&submit->exec) { 283 + ret = drm_gpuvm_prepare_vm(submit->vm, exec, 1); 284 + drm_exec_retry_on_contention(exec); 285 + if (ret) 286 + break; 287 + 288 + ret = drm_gpuvm_prepare_objects(submit->vm, exec, 1); 289 + drm_exec_retry_on_contention(exec); 290 + if (ret) 291 + break; 292 + } 293 + 294 + return ret; 295 + } 296 + 274 297 /* This is where we make sure all the bo's are reserved and pin'd: */ 275 298 static int submit_lock_objects(struct msm_gem_submit *submit) 276 299 { 277 300 unsigned flags = DRM_EXEC_INTERRUPTIBLE_WAIT; 278 - struct drm_exec *exec = &submit->exec; 279 - int ret; 301 + int ret = 0; 280 302 281 - if (msm_context_is_vmbind(submit->queue->ctx)) { 282 - flags |= DRM_EXEC_IGNORE_DUPLICATES; 283 - 284 - drm_exec_init(&submit->exec, flags, submit->nr_bos); 285 - 286 - drm_exec_until_all_locked (&submit->exec) { 287 - ret = drm_gpuvm_prepare_vm(submit->vm, exec, 1); 288 - drm_exec_retry_on_contention(exec); 289 - if (ret) 290 - return ret; 291 - 292 - ret = drm_gpuvm_prepare_objects(submit->vm, exec, 1); 293 - drm_exec_retry_on_contention(exec); 294 - if (ret) 295 - return ret; 296 - } 297 - 298 - return 0; 299 - } 303 + if (msm_context_is_vmbind(submit->queue->ctx)) 304 + return submit_lock_objects_vmbind(submit); 300 305 301 306 drm_exec_init(&submit->exec, flags, submit->nr_bos); 302 307 ··· 310 305 drm_gpuvm_resv_obj(submit->vm)); 311 306 drm_exec_retry_on_contention(&submit->exec); 312 307 if (ret) 313 - return ret; 308 + break; 314 309 for (unsigned i = 0; i < submit->nr_bos; i++) { 315 310 struct drm_gem_object *obj = submit->bos[i].obj; 316 311 ret = drm_exec_prepare_obj(&submit->exec, obj, 1); 317 312 drm_exec_retry_on_contention(&submit->exec); 318 313 if (ret) 319 - return ret; 314 + break; 320 315 } 321 316 } 322 317 323 - return 0; 318 + return ret; 324 319 } 325 320 326 321 static int submit_fence_sync(struct msm_gem_submit *submit) ··· 519 514 */ 520 515 static void submit_cleanup(struct msm_gem_submit *submit, bool error) 521 516 { 517 + if (error) 518 + submit_unpin_objects(submit); 519 + 522 520 if (submit->exec.objects) 523 521 drm_exec_fini(&submit->exec); 524 522 525 - if (error) { 526 - submit_unpin_objects(submit); 527 - /* job wasn't enqueued to scheduler, so early retirement: */ 523 + /* if job wasn't enqueued to scheduler, early retirement: */ 524 + if (error) 528 525 msm_submit_retire(submit); 529 - } 530 526 } 531 527 532 528 void msm_submit_retire(struct msm_gem_submit *submit) ··· 775 769 776 770 if (ret == 0 && args->flags & MSM_SUBMIT_FENCE_FD_OUT) { 777 771 sync_file = sync_file_create(submit->user_fence); 778 - if (!sync_file) { 772 + if (!sync_file) 779 773 ret = -ENOMEM; 780 - } else { 781 - fd_install(out_fence_fd, sync_file->file); 782 - args->fence_fd = out_fence_fd; 783 - } 784 774 } 785 775 786 776 if (ret) ··· 814 812 out_unlock: 815 813 mutex_unlock(&queue->lock); 816 814 out_post_unlock: 817 - if (ret && (out_fence_fd >= 0)) { 818 - put_unused_fd(out_fence_fd); 815 + if (ret) { 816 + if (out_fence_fd >= 0) 817 + put_unused_fd(out_fence_fd); 819 818 if (sync_file) 820 819 fput(sync_file->file); 820 + } else if (sync_file) { 821 + fd_install(out_fence_fd, sync_file->file); 822 + args->fence_fd = out_fence_fd; 821 823 } 822 824 823 825 if (!IS_ERR_OR_NULL(submit)) {
+45 -15
drivers/gpu/drm/msm/msm_gem_vma.c
··· 319 319 mutex_lock(&vm->mmu_lock); 320 320 321 321 /* 322 - * NOTE: iommu/io-pgtable can allocate pages, so we cannot hold 322 + * NOTE: if not using pgtable preallocation, we cannot hold 323 323 * a lock across map/unmap which is also used in the job_run() 324 324 * path, as this can cause deadlock in job_run() vs shrinker/ 325 325 * reclaim. 326 - * 327 - * Revisit this if we can come up with a scheme to pre-alloc pages 328 - * for the pgtable in map/unmap ops. 329 326 */ 330 327 ret = vm_map_op(vm, &(struct msm_vm_map_op){ 331 328 .iova = vma->va.addr, ··· 451 454 struct op_arg { 452 455 unsigned flags; 453 456 struct msm_vm_bind_job *job; 457 + const struct msm_vm_bind_op *op; 458 + bool kept; 454 459 }; 455 460 456 461 static void ··· 474 475 } 475 476 476 477 static int 477 - msm_gem_vm_sm_step_map(struct drm_gpuva_op *op, void *arg) 478 + msm_gem_vm_sm_step_map(struct drm_gpuva_op *op, void *_arg) 478 479 { 479 - struct msm_vm_bind_job *job = ((struct op_arg *)arg)->job; 480 + struct op_arg *arg = _arg; 481 + struct msm_vm_bind_job *job = arg->job; 480 482 struct drm_gem_object *obj = op->map.gem.obj; 481 483 struct drm_gpuva *vma; 482 484 struct sg_table *sgt; 483 485 unsigned prot; 486 + 487 + if (arg->kept) 488 + return 0; 484 489 485 490 vma = vma_from_op(arg, &op->map); 486 491 if (WARN_ON(IS_ERR(vma))) ··· 605 602 } 606 603 607 604 static int 608 - msm_gem_vm_sm_step_unmap(struct drm_gpuva_op *op, void *arg) 605 + msm_gem_vm_sm_step_unmap(struct drm_gpuva_op *op, void *_arg) 609 606 { 610 - struct msm_vm_bind_job *job = ((struct op_arg *)arg)->job; 607 + struct op_arg *arg = _arg; 608 + struct msm_vm_bind_job *job = arg->job; 611 609 struct drm_gpuva *vma = op->unmap.va; 612 610 struct msm_gem_vma *msm_vma = to_msm_vma(vma); 613 611 614 612 vm_dbg("%p:%p:%p: %016llx %016llx", vma->vm, vma, vma->gem.obj, 615 613 vma->va.addr, vma->va.range); 614 + 615 + /* 616 + * Detect in-place remap. Turnip does this to change the vma flags, 617 + * in particular MSM_VMA_DUMP. In this case we want to avoid actually 618 + * touching the page tables, as that would require synchronization 619 + * against SUBMIT jobs running on the GPU. 620 + */ 621 + if (op->unmap.keep && 622 + (arg->op->op == MSM_VM_BIND_OP_MAP) && 623 + (vma->gem.obj == arg->op->obj) && 624 + (vma->gem.offset == arg->op->obj_offset) && 625 + (vma->va.addr == arg->op->iova) && 626 + (vma->va.range == arg->op->range)) { 627 + /* We are only expecting a single in-place unmap+map cb pair: */ 628 + WARN_ON(arg->kept); 629 + 630 + /* Leave the existing VMA in place, but signal that to the map cb: */ 631 + arg->kept = true; 632 + 633 + /* Only flags are changing, so update that in-place: */ 634 + unsigned orig_flags = vma->flags & (DRM_GPUVA_USERBITS - 1); 635 + vma->flags = orig_flags | arg->flags; 636 + 637 + return 0; 638 + } 616 639 617 640 if (!msm_vma->mapped) 618 641 goto out_close; ··· 1300 1271 const struct msm_vm_bind_op *op = &job->ops[i]; 1301 1272 struct op_arg arg = { 1302 1273 .job = job, 1274 + .op = op, 1303 1275 }; 1304 1276 1305 1277 switch (op->op) { ··· 1490 1460 1491 1461 if (args->flags & MSM_VM_BIND_FENCE_FD_OUT) { 1492 1462 sync_file = sync_file_create(job->fence); 1493 - if (!sync_file) { 1463 + if (!sync_file) 1494 1464 ret = -ENOMEM; 1495 - } else { 1496 - fd_install(out_fence_fd, sync_file->file); 1497 - args->fence_fd = out_fence_fd; 1498 - } 1499 1465 } 1500 1466 1501 1467 if (ret) ··· 1520 1494 out_unlock: 1521 1495 mutex_unlock(&queue->lock); 1522 1496 out_post_unlock: 1523 - if (ret && (out_fence_fd >= 0)) { 1524 - put_unused_fd(out_fence_fd); 1497 + if (ret) { 1498 + if (out_fence_fd >= 0) 1499 + put_unused_fd(out_fence_fd); 1525 1500 if (sync_file) 1526 1501 fput(sync_file->file); 1502 + } else if (sync_file) { 1503 + fd_install(out_fence_fd, sync_file->file); 1504 + args->fence_fd = out_fence_fd; 1527 1505 } 1528 1506 1529 1507 if (!IS_ERR_OR_NULL(job)) {
+16 -4
drivers/gpu/drm/msm/msm_gpu.c
··· 465 465 struct msm_gem_submit *submit; 466 466 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 467 467 char *comm = NULL, *cmd = NULL; 468 + struct task_struct *task; 468 469 int i; 469 470 470 471 mutex_lock(&gpu->lock); ··· 483 482 484 483 /* Increment the fault counts */ 485 484 submit->queue->faults++; 486 - if (submit->vm) { 485 + 486 + task = get_pid_task(submit->pid, PIDTYPE_PID); 487 + if (!task) 488 + gpu->global_faults++; 489 + else { 487 490 struct msm_gem_vm *vm = to_msm_vm(submit->vm); 488 491 489 492 vm->faults++; 490 493 491 494 /* 492 495 * If userspace has opted-in to VM_BIND (and therefore userspace 493 - * management of the VM), faults mark the VM as unusuable. This 496 + * management of the VM), faults mark the VM as unusable. This 494 497 * matches vulkan expectations (vulkan is the main target for 495 - * VM_BIND) 498 + * VM_BIND). 496 499 */ 497 500 if (!vm->managed) 498 501 msm_gem_vm_unusable(submit->vm); ··· 558 553 unsigned long flags; 559 554 560 555 spin_lock_irqsave(&ring->submit_lock, flags); 561 - list_for_each_entry(submit, &ring->submits, node) 556 + list_for_each_entry(submit, &ring->submits, node) { 557 + /* 558 + * If the submit uses an unusable vm make sure 559 + * we don't actually run it 560 + */ 561 + if (to_msm_vm(submit->vm)->unusable) 562 + submit->nr_cmds = 0; 562 563 gpu->funcs->submit(gpu, submit); 564 + } 563 565 spin_unlock_irqrestore(&ring->submit_lock, flags); 564 566 } 565 567 }
+12 -4
drivers/gpu/drm/msm/msm_iommu.c
··· 14 14 struct msm_iommu { 15 15 struct msm_mmu base; 16 16 struct iommu_domain *domain; 17 - atomic_t pagetables; 17 + 18 + struct mutex init_lock; /* protects pagetables counter and prr_page */ 19 + int pagetables; 18 20 struct page *prr_page; 19 21 20 22 struct kmem_cache *pt_cache; ··· 229 227 * If this is the last attached pagetable for the parent, 230 228 * disable TTBR0 in the arm-smmu driver 231 229 */ 232 - if (atomic_dec_return(&iommu->pagetables) == 0) { 230 + mutex_lock(&iommu->init_lock); 231 + if (--iommu->pagetables == 0) { 233 232 adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL); 234 233 235 234 if (adreno_smmu->set_prr_bit) { ··· 239 236 iommu->prr_page = NULL; 240 237 } 241 238 } 239 + mutex_unlock(&iommu->init_lock); 242 240 243 241 free_io_pgtable_ops(pagetable->pgtbl_ops); 244 242 kfree(pagetable); ··· 572 568 * If this is the first pagetable that we've allocated, send it back to 573 569 * the arm-smmu driver as a trigger to set up TTBR0 574 570 */ 575 - if (atomic_inc_return(&iommu->pagetables) == 1) { 571 + mutex_lock(&iommu->init_lock); 572 + if (iommu->pagetables++ == 0) { 576 573 ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg); 577 574 if (ret) { 575 + iommu->pagetables--; 576 + mutex_unlock(&iommu->init_lock); 578 577 free_io_pgtable_ops(pagetable->pgtbl_ops); 579 578 kfree(pagetable); 580 579 return ERR_PTR(ret); ··· 602 595 adreno_smmu->set_prr_bit(adreno_smmu->cookie, true); 603 596 } 604 597 } 598 + mutex_unlock(&iommu->init_lock); 605 599 606 600 /* Needed later for TLB flush */ 607 601 pagetable->parent = parent; ··· 738 730 iommu->domain = domain; 739 731 msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); 740 732 741 - atomic_set(&iommu->pagetables, 0); 733 + mutex_init(&iommu->init_lock); 742 734 743 735 ret = iommu_attach_device(iommu->domain, dev); 744 736 if (ret) {
+6 -4
drivers/gpu/drm/msm/msm_kms.c
··· 275 275 if (ret) 276 276 return ret; 277 277 278 + ret = msm_disp_snapshot_init(ddev); 279 + if (ret) { 280 + DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 281 + return ret; 282 + } 283 + 278 284 ret = priv->kms_init(ddev); 279 285 if (ret) { 280 286 DRM_DEV_ERROR(dev, "failed to load kms\n"); ··· 332 326 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 333 327 goto err_msm_uninit; 334 328 } 335 - 336 - ret = msm_disp_snapshot_init(ddev); 337 - if (ret) 338 - DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 339 329 340 330 drm_mode_config_reset(ddev); 341 331
+1 -1
drivers/gpu/drm/msm/msm_mdss.c
··· 423 423 if (IS_ERR(msm_mdss->mmio)) 424 424 return ERR_CAST(msm_mdss->mmio); 425 425 426 - dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 426 + dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio); 427 427 428 428 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 429 429 if (ret)
+13 -1
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
··· 594 594 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 595 595 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 596 596 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 597 - <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D"> 597 + <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A6XX"> 598 598 <bitfield high="7" low="0" name="PING_INDEX"/> 599 599 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 600 + </reg32> 601 + <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A7XX-"> 602 + <bitfield high="7" low="0" name="PING_INDEX"/> 603 + <bitfield high="24" low="16" name="PING_BLK_SEL"/> 600 604 </reg32> 601 605 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 602 606 <bitfield high="5" low="0" name="TRACEEN"/> ··· 3798 3794 3799 3795 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 3800 3796 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 3797 + </domain> 3798 + 3799 + <domain name="A7XX_CX_DBGC" width="32"> 3800 + <!-- Bitfields shifted, but otherwise the same: --> 3801 + <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 3802 + <bitfield high="7" low="0" name="PING_INDEX"/> 3803 + <bitfield high="24" low="16" name="PING_BLK_SEL"/> 3804 + </reg32> 3801 3805 </domain> 3802 3806 3803 3807 <domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">
+14 -14
drivers/gpu/drm/msm/registers/display/dsi.xml
··· 159 159 <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/> 160 160 </reg32> 161 161 <reg32 offset="0x00020" name="ACTIVE_H"> 162 - <bitfield name="START" low="0" high="11" type="uint"/> 163 - <bitfield name="END" low="16" high="27" type="uint"/> 162 + <bitfield name="START" low="0" high="15" type="uint"/> 163 + <bitfield name="END" low="16" high="31" type="uint"/> 164 164 </reg32> 165 165 <reg32 offset="0x00024" name="ACTIVE_V"> 166 - <bitfield name="START" low="0" high="11" type="uint"/> 167 - <bitfield name="END" low="16" high="27" type="uint"/> 166 + <bitfield name="START" low="0" high="15" type="uint"/> 167 + <bitfield name="END" low="16" high="31" type="uint"/> 168 168 </reg32> 169 169 <reg32 offset="0x00028" name="TOTAL"> 170 - <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> 171 - <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> 170 + <bitfield name="H_TOTAL" low="0" high="15" type="uint"/> 171 + <bitfield name="V_TOTAL" low="16" high="31" type="uint"/> 172 172 </reg32> 173 173 <reg32 offset="0x0002c" name="ACTIVE_HSYNC"> 174 - <bitfield name="START" low="0" high="11" type="uint"/> 175 - <bitfield name="END" low="16" high="27" type="uint"/> 174 + <bitfield name="START" low="0" high="15" type="uint"/> 175 + <bitfield name="END" low="16" high="31" type="uint"/> 176 176 </reg32> 177 177 <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS"> 178 - <bitfield name="START" low="0" high="11" type="uint"/> 179 - <bitfield name="END" low="16" high="27" type="uint"/> 178 + <bitfield name="START" low="0" high="15" type="uint"/> 179 + <bitfield name="END" low="16" high="31" type="uint"/> 180 180 </reg32> 181 181 <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS"> 182 - <bitfield name="START" low="0" high="11" type="uint"/> 183 - <bitfield name="END" low="16" high="27" type="uint"/> 182 + <bitfield name="START" low="0" high="15" type="uint"/> 183 + <bitfield name="END" low="16" high="31" type="uint"/> 184 184 </reg32> 185 185 186 186 <reg32 offset="0x00038" name="CMD_DMA_CTRL"> ··· 209 209 <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/> 210 210 </reg32> 211 211 <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL"> 212 - <bitfield name="H_TOTAL" low="0" high="11" type="uint"/> 213 - <bitfield name="V_TOTAL" low="16" high="27" type="uint"/> 212 + <bitfield name="H_TOTAL" low="0" high="15" type="uint"/> 213 + <bitfield name="V_TOTAL" low="16" high="31" type="uint"/> 214 214 </reg32> 215 215 <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL"> 216 216 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
+4
drivers/gpu/drm/nouveau/dispnv50/wndw.c
··· 795 795 struct nouveau_drm *drm = nouveau_drm(plane->dev); 796 796 uint8_t i; 797 797 798 + /* All chipsets can display all formats in linear layout */ 799 + if (modifier == DRM_FORMAT_MOD_LINEAR) 800 + return true; 801 + 798 802 if (drm->client.device.info.chipset < 0xc0) { 799 803 const struct drm_format_info *info = drm_format_info(format); 800 804 const uint8_t kind = (modifier >> 12) & 0xff;
+4 -11
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
··· 103 103 static void 104 104 gm200_flcn_pio_imem_wr(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len, u16 tag) 105 105 { 106 - nvkm_falcon_wr32(falcon, 0x188 + (port * 0x10), tag++); 106 + nvkm_falcon_wr32(falcon, 0x188 + (port * 0x10), tag); 107 107 while (len >= 4) { 108 108 nvkm_falcon_wr32(falcon, 0x184 + (port * 0x10), *(u32 *)img); 109 109 img += 4; ··· 249 249 gm200_flcn_fw_load(struct nvkm_falcon_fw *fw) 250 250 { 251 251 struct nvkm_falcon *falcon = fw->falcon; 252 - int target, ret; 252 + int ret; 253 253 254 254 if (fw->inst) { 255 + int target; 256 + 255 257 nvkm_falcon_mask(falcon, 0x048, 0x00000001, 0x00000001); 256 258 257 259 switch (nvkm_memory_target(fw->inst)) { ··· 287 285 } 288 286 289 287 if (fw->boot) { 290 - switch (nvkm_memory_target(&fw->fw.mem.memory)) { 291 - case NVKM_MEM_TARGET_VRAM: target = 4; break; 292 - case NVKM_MEM_TARGET_HOST: target = 5; break; 293 - case NVKM_MEM_TARGET_NCOH: target = 6; break; 294 - default: 295 - WARN_ON(1); 296 - return -EINVAL; 297 - } 298 - 299 288 ret = nvkm_falcon_pio_wr(falcon, fw->boot, 0, 0, 300 289 IMEM, falcon->code.limit - fw->boot_size, fw->boot_size, 301 290 fw->boot_addr >> 8, false);
+3 -2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/fwsec.c
··· 209 209 fw->boot_addr = bld->start_tag << 8; 210 210 fw->boot_size = bld->code_size; 211 211 fw->boot = kmemdup(bl->data + hdr->data_offset + bld->code_off, fw->boot_size, GFP_KERNEL); 212 - if (!fw->boot) 213 - ret = -ENOMEM; 214 212 215 213 nvkm_firmware_put(bl); 214 + 215 + if (!fw->boot) 216 + return -ENOMEM; 216 217 217 218 /* Patch in interface data. */ 218 219 return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd);
+1 -1
drivers/gpu/drm/tegra/gem.c
··· 526 526 if (drm_gem_is_imported(gem)) { 527 527 dma_buf_unmap_attachment_unlocked(gem->import_attach, bo->sgt, 528 528 DMA_TO_DEVICE); 529 - dma_buf_detach(gem->dma_buf, gem->import_attach); 529 + dma_buf_detach(gem->import_attach->dmabuf, gem->import_attach); 530 530 } 531 531 } 532 532
+4 -4
drivers/gpu/drm/xe/xe_bo.c
··· 812 812 } 813 813 814 814 if (ttm_bo->type == ttm_bo_type_sg) { 815 - ret = xe_bo_move_notify(bo, ctx); 815 + if (new_mem->mem_type == XE_PL_SYSTEM) 816 + ret = xe_bo_move_notify(bo, ctx); 816 817 if (!ret) 817 818 ret = xe_bo_move_dmabuf(ttm_bo, new_mem); 818 819 return ret; ··· 2439 2438 .no_wait_gpu = false, 2440 2439 .gfp_retry_mayfail = true, 2441 2440 }; 2442 - struct pin_cookie cookie; 2443 2441 int ret; 2444 2442 2445 2443 if (vm) { ··· 2449 2449 ctx.resv = xe_vm_resv(vm); 2450 2450 } 2451 2451 2452 - cookie = xe_vm_set_validating(vm, allow_res_evict); 2452 + xe_vm_set_validating(vm, allow_res_evict); 2453 2453 trace_xe_bo_validate(bo); 2454 2454 ret = ttm_bo_validate(&bo->ttm, &bo->placement, &ctx); 2455 - xe_vm_clear_validating(vm, allow_res_evict, cookie); 2455 + xe_vm_clear_validating(vm, allow_res_evict); 2456 2456 2457 2457 return ret; 2458 2458 }
+9 -1
drivers/gpu/drm/xe/xe_gen_wa_oob.c
··· 123 123 return 0; 124 124 } 125 125 126 + /* Avoid GNU vs POSIX basename() discrepancy, just use our own */ 127 + static const char *xbasename(const char *s) 128 + { 129 + const char *p = strrchr(s, '/'); 130 + 131 + return p ? p + 1 : s; 132 + } 133 + 126 134 static int fn_to_prefix(const char *fn, char *prefix, size_t size) 127 135 { 128 136 size_t len; 129 137 130 - fn = basename(fn); 138 + fn = xbasename(fn); 131 139 len = strlen(fn); 132 140 133 141 if (len > size - 1)
+1 -1
drivers/gpu/drm/xe/xe_sync.c
··· 77 77 { 78 78 struct xe_user_fence *ufence = container_of(w, struct xe_user_fence, worker); 79 79 80 + WRITE_ONCE(ufence->signalled, 1); 80 81 if (mmget_not_zero(ufence->mm)) { 81 82 kthread_use_mm(ufence->mm); 82 83 if (copy_to_user(ufence->addr, &ufence->value, sizeof(ufence->value))) ··· 92 91 * Wake up waiters only after updating the ufence state, allowing the UMD 93 92 * to safely reuse the same ufence without encountering -EBUSY errors. 94 93 */ 95 - WRITE_ONCE(ufence->signalled, 1); 96 94 wake_up_all(&ufence->xe->ufence_wq); 97 95 user_fence_put(ufence); 98 96 }
+6 -2
drivers/gpu/drm/xe/xe_vm.c
··· 1610 1610 1611 1611 for (i = MAX_HUGEPTE_LEVEL; i < vm->pt_root[id]->level; i++) { 1612 1612 vm->scratch_pt[id][i] = xe_pt_create(vm, tile, i); 1613 - if (IS_ERR(vm->scratch_pt[id][i])) 1614 - return PTR_ERR(vm->scratch_pt[id][i]); 1613 + if (IS_ERR(vm->scratch_pt[id][i])) { 1614 + int err = PTR_ERR(vm->scratch_pt[id][i]); 1615 + 1616 + vm->scratch_pt[id][i] = NULL; 1617 + return err; 1618 + } 1615 1619 1616 1620 xe_pt_populate_empty(tile, vm, vm->scratch_pt[id][i]); 1617 1621 }
+2 -13
drivers/gpu/drm/xe/xe_vm.h
··· 315 315 * Register this task as currently making bos resident for the vm. Intended 316 316 * to avoid eviction by the same task of shared bos bound to the vm. 317 317 * Call with the vm's resv lock held. 318 - * 319 - * Return: A pin cookie that should be used for xe_vm_clear_validating(). 320 318 */ 321 - static inline struct pin_cookie xe_vm_set_validating(struct xe_vm *vm, 322 - bool allow_res_evict) 319 + static inline void xe_vm_set_validating(struct xe_vm *vm, bool allow_res_evict) 323 320 { 324 - struct pin_cookie cookie = {}; 325 - 326 321 if (vm && !allow_res_evict) { 327 322 xe_vm_assert_held(vm); 328 - cookie = lockdep_pin_lock(&xe_vm_resv(vm)->lock.base); 329 323 /* Pairs with READ_ONCE in xe_vm_is_validating() */ 330 324 WRITE_ONCE(vm->validating, current); 331 325 } 332 - 333 - return cookie; 334 326 } 335 327 336 328 /** ··· 330 338 * @vm: Pointer to the vm or NULL 331 339 * @allow_res_evict: Eviction from @vm was allowed. Must be set to the same 332 340 * value as for xe_vm_set_validation(). 333 - * @cookie: Cookie obtained from xe_vm_set_validating(). 334 341 * 335 342 * Register this task as currently making bos resident for the vm. Intended 336 343 * to avoid eviction by the same task of shared bos bound to the vm. 337 344 * Call with the vm's resv lock held. 338 345 */ 339 - static inline void xe_vm_clear_validating(struct xe_vm *vm, bool allow_res_evict, 340 - struct pin_cookie cookie) 346 + static inline void xe_vm_clear_validating(struct xe_vm *vm, bool allow_res_evict) 341 347 { 342 348 if (vm && !allow_res_evict) { 343 - lockdep_unpin_lock(&xe_vm_resv(vm)->lock.base, cookie); 344 349 /* Pairs with READ_ONCE in xe_vm_is_validating() */ 345 350 WRITE_ONCE(vm->validating, NULL); 346 351 }
+1 -1
drivers/hid/Kconfig
··· 1243 1243 1244 1244 U2F Zero supports custom commands for blinking the LED 1245 1245 and getting data from the internal hardware RNG. 1246 - The internal hardware can be used to feed the enthropy pool. 1246 + The internal hardware can be used to feed the entropy pool. 1247 1247 1248 1248 U2F Zero only supports blinking its LED, so this driver doesn't 1249 1249 allow setting the brightness to anything but 1, which will
+7 -1
drivers/hid/hid-asus.c
··· 1213 1213 return ret; 1214 1214 } 1215 1215 1216 - if (!drvdata->input) { 1216 + /* 1217 + * Check that input registration succeeded. Checking that 1218 + * HID_CLAIMED_INPUT is set prevents a UAF when all input devices 1219 + * were freed during registration due to no usages being mapped, 1220 + * leaving drvdata->input pointing to freed memory. 1221 + */ 1222 + if (!drvdata->input || !(hdev->claimed & HID_CLAIMED_INPUT)) { 1217 1223 hid_err(hdev, "Asus input not registered\n"); 1218 1224 ret = -ENOMEM; 1219 1225 goto err_stop_hw;
+2
drivers/hid/hid-elecom.c
··· 101 101 */ 102 102 mouse_button_fixup(hdev, rdesc, *rsize, 12, 30, 14, 20, 8); 103 103 break; 104 + case USB_DEVICE_ID_ELECOM_M_DT2DRBK: 104 105 case USB_DEVICE_ID_ELECOM_M_HT1DRBK_011C: 105 106 /* 106 107 * Report descriptor format: ··· 124 123 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT4DRBK) }, 125 124 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_DT1URBK) }, 126 125 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_DT1DRBK) }, 126 + { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_DT2DRBK) }, 127 127 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_HT1URBK_010C) }, 128 128 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_HT1URBK_019B) }, 129 129 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_HT1DRBK_010D) },
+4
drivers/hid/hid-ids.h
··· 451 451 #define USB_DEVICE_ID_ELECOM_M_XT4DRBK 0x00fd 452 452 #define USB_DEVICE_ID_ELECOM_M_DT1URBK 0x00fe 453 453 #define USB_DEVICE_ID_ELECOM_M_DT1DRBK 0x00ff 454 + #define USB_DEVICE_ID_ELECOM_M_DT2DRBK 0x018d 454 455 #define USB_DEVICE_ID_ELECOM_M_HT1URBK_010C 0x010c 455 456 #define USB_DEVICE_ID_ELECOM_M_HT1URBK_019B 0x019b 456 457 #define USB_DEVICE_ID_ELECOM_M_HT1DRBK_010D 0x010d ··· 835 834 #define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019 0x6019 836 835 #define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_602E 0x602e 837 836 #define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6093 0x6093 837 + #define USB_DEVICE_ID_LENOVO_LEGION_GO_DUAL_DINPUT 0x6184 838 + #define USB_DEVICE_ID_LENOVO_LEGION_GO2_DUAL_DINPUT 0x61ed 838 839 839 840 #define USB_VENDOR_ID_LETSKETCH 0x6161 840 841 #define USB_DEVICE_ID_WP9620N 0x4d15 ··· 910 907 #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_2 0xc534 911 908 #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1 0xc539 912 909 #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1 0xc53f 910 + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_2 0xc543 913 911 #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_POWERPLAY 0xc53a 914 912 #define USB_DEVICE_ID_LOGITECH_BOLT_RECEIVER 0xc548 915 913 #define USB_DEVICE_ID_SPACETRAVELLER 0xc623
+5 -5
drivers/hid/hid-input-test.c
··· 7 7 8 8 #include <kunit/test.h> 9 9 10 - static void hid_test_input_set_battery_charge_status(struct kunit *test) 10 + static void hid_test_input_update_battery_charge_status(struct kunit *test) 11 11 { 12 12 struct hid_device *dev; 13 13 bool handled; ··· 15 15 dev = kunit_kzalloc(test, sizeof(*dev), GFP_KERNEL); 16 16 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev); 17 17 18 - handled = hidinput_set_battery_charge_status(dev, HID_DG_HEIGHT, 0); 18 + handled = hidinput_update_battery_charge_status(dev, HID_DG_HEIGHT, 0); 19 19 KUNIT_EXPECT_FALSE(test, handled); 20 20 KUNIT_EXPECT_EQ(test, dev->battery_charge_status, POWER_SUPPLY_STATUS_UNKNOWN); 21 21 22 - handled = hidinput_set_battery_charge_status(dev, HID_BAT_CHARGING, 0); 22 + handled = hidinput_update_battery_charge_status(dev, HID_BAT_CHARGING, 0); 23 23 KUNIT_EXPECT_TRUE(test, handled); 24 24 KUNIT_EXPECT_EQ(test, dev->battery_charge_status, POWER_SUPPLY_STATUS_DISCHARGING); 25 25 26 - handled = hidinput_set_battery_charge_status(dev, HID_BAT_CHARGING, 1); 26 + handled = hidinput_update_battery_charge_status(dev, HID_BAT_CHARGING, 1); 27 27 KUNIT_EXPECT_TRUE(test, handled); 28 28 KUNIT_EXPECT_EQ(test, dev->battery_charge_status, POWER_SUPPLY_STATUS_CHARGING); 29 29 } ··· 63 63 } 64 64 65 65 static struct kunit_case hid_input_tests[] = { 66 - KUNIT_CASE(hid_test_input_set_battery_charge_status), 66 + KUNIT_CASE(hid_test_input_update_battery_charge_status), 67 67 KUNIT_CASE(hid_test_input_get_battery_property), 68 68 { } 69 69 };
+24 -27
drivers/hid/hid-input.c
··· 595 595 dev->battery = NULL; 596 596 } 597 597 598 - static void hidinput_update_battery(struct hid_device *dev, int value) 598 + static bool hidinput_update_battery_charge_status(struct hid_device *dev, 599 + unsigned int usage, int value) 600 + { 601 + switch (usage) { 602 + case HID_BAT_CHARGING: 603 + dev->battery_charge_status = value ? 604 + POWER_SUPPLY_STATUS_CHARGING : 605 + POWER_SUPPLY_STATUS_DISCHARGING; 606 + return true; 607 + } 608 + 609 + return false; 610 + } 611 + 612 + static void hidinput_update_battery(struct hid_device *dev, unsigned int usage, 613 + int value) 599 614 { 600 615 int capacity; 601 616 602 617 if (!dev->battery) 603 618 return; 619 + 620 + if (hidinput_update_battery_charge_status(dev, usage, value)) { 621 + power_supply_changed(dev->battery); 622 + return; 623 + } 604 624 605 625 if (value == 0 || value < dev->battery_min || value > dev->battery_max) 606 626 return; ··· 637 617 power_supply_changed(dev->battery); 638 618 } 639 619 } 640 - 641 - static bool hidinput_set_battery_charge_status(struct hid_device *dev, 642 - unsigned int usage, int value) 643 - { 644 - switch (usage) { 645 - case HID_BAT_CHARGING: 646 - dev->battery_charge_status = value ? 647 - POWER_SUPPLY_STATUS_CHARGING : 648 - POWER_SUPPLY_STATUS_DISCHARGING; 649 - return true; 650 - } 651 - 652 - return false; 653 - } 654 620 #else /* !CONFIG_HID_BATTERY_STRENGTH */ 655 621 static int hidinput_setup_battery(struct hid_device *dev, unsigned report_type, 656 622 struct hid_field *field, bool is_percentage) ··· 648 642 { 649 643 } 650 644 651 - static void hidinput_update_battery(struct hid_device *dev, int value) 645 + static void hidinput_update_battery(struct hid_device *dev, unsigned int usage, 646 + int value) 652 647 { 653 - } 654 - 655 - static bool hidinput_set_battery_charge_status(struct hid_device *dev, 656 - unsigned int usage, int value) 657 - { 658 - return false; 659 648 } 660 649 #endif /* CONFIG_HID_BATTERY_STRENGTH */ 661 650 ··· 1516 1515 return; 1517 1516 1518 1517 if (usage->type == EV_PWR) { 1519 - bool handled = hidinput_set_battery_charge_status(hid, usage->hid, value); 1520 - 1521 - if (!handled) 1522 - hidinput_update_battery(hid, value); 1523 - 1518 + hidinput_update_battery(hid, usage->hid, value); 1524 1519 return; 1525 1520 } 1526 1521
+4
drivers/hid/hid-logitech-dj.c
··· 1983 1983 HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 1984 1984 USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1), 1985 1985 .driver_data = recvr_type_gaming_hidpp}, 1986 + { /* Logitech lightspeed receiver (0xc543) */ 1987 + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 1988 + USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_2), 1989 + .driver_data = recvr_type_gaming_hidpp}, 1986 1990 1987 1991 { /* Logitech 27 MHz HID++ 1.0 receiver (0xc513) */ 1988 1992 HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER),
+2
drivers/hid/hid-logitech-hidpp.c
··· 4596 4596 HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC094) }, 4597 4597 { /* Logitech G Pro X Superlight 2 Gaming Mouse over USB */ 4598 4598 HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC09b) }, 4599 + { /* Logitech G PRO 2 LIGHTSPEED Wireless Mouse over USB */ 4600 + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xc09a) }, 4599 4601 4600 4602 { /* G935 Gaming Headset */ 4601 4603 HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0x0a87),
+4
drivers/hid/hid-mcp2221.c
··· 906 906 } 907 907 if (data[2] == MCP2221_I2C_READ_COMPL || 908 908 data[2] == MCP2221_I2C_READ_PARTIAL) { 909 + if (!mcp->rxbuf || mcp->rxbuf_idx < 0 || data[3] > 60) { 910 + mcp->status = -EINVAL; 911 + break; 912 + } 909 913 buf = mcp->rxbuf; 910 914 memcpy(&buf[mcp->rxbuf_idx], &data[4], data[3]); 911 915 mcp->rxbuf_idx = mcp->rxbuf_idx + data[3];
+8
drivers/hid/hid-multitouch.c
··· 1503 1503 if (hdev->vendor == I2C_VENDOR_ID_GOODIX && 1504 1504 (hdev->product == I2C_DEVICE_ID_GOODIX_01E8 || 1505 1505 hdev->product == I2C_DEVICE_ID_GOODIX_01E9)) { 1506 + if (*size < 608) { 1507 + dev_info( 1508 + &hdev->dev, 1509 + "GT7868Q fixup: report descriptor is only %u bytes, skipping\n", 1510 + *size); 1511 + return rdesc; 1512 + } 1513 + 1506 1514 if (rdesc[607] == 0x15) { 1507 1515 rdesc[607] = 0x25; 1508 1516 dev_info(
+3
drivers/hid/hid-ntrig.c
··· 144 144 struct usb_device *usb_dev = hid_to_usb_dev(hdev); 145 145 unsigned char *data = kmalloc(8, GFP_KERNEL); 146 146 147 + if (!hid_is_usb(hdev)) 148 + return; 149 + 147 150 if (!data) 148 151 goto err_free; 149 152
+3
drivers/hid/hid-quirks.c
··· 124 124 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_V2), HID_QUIRK_MULTI_INPUT }, 125 125 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_T609A), HID_QUIRK_MULTI_INPUT }, 126 126 { HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_ODDOR_HANDBRAKE), HID_QUIRK_ALWAYS_POLL }, 127 + { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_LEGION_GO_DUAL_DINPUT), HID_QUIRK_MULTI_INPUT }, 128 + { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_LEGION_GO2_DUAL_DINPUT), HID_QUIRK_MULTI_INPUT }, 127 129 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_OPTICAL_USB_MOUSE_600E), HID_QUIRK_ALWAYS_POLL }, 128 130 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D), HID_QUIRK_ALWAYS_POLL }, 129 131 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019), HID_QUIRK_ALWAYS_POLL }, ··· 413 411 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT4DRBK) }, 414 412 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_DT1URBK) }, 415 413 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_DT1DRBK) }, 414 + { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_DT2DRBK) }, 416 415 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_HT1URBK_010C) }, 417 416 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_HT1URBK_019B) }, 418 417 { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_HT1DRBK_010D) },
-3
drivers/hid/intel-ish-hid/ipc/pci-ish.c
··· 264 264 265 265 static struct device __maybe_unused *ish_resume_device; 266 266 267 - /* 50ms to get resume response */ 268 - #define WAIT_FOR_RESUME_ACK_MS 50 269 - 270 267 /** 271 268 * ish_resume_handler() - Work function to complete resume 272 269 * @work: work struct
+3
drivers/hid/intel-ish-hid/ishtp-hid-client.c
··· 759 759 if (ishtp_wait_resume(ishtp_get_ishtp_device(hid_ishtp_cl))) { 760 760 client_data->suspended = false; 761 761 wake_up_interruptible(&client_data->ishtp_resume_wait); 762 + } else { 763 + hid_ishtp_trace(client_data, "hid client: wait for resume timed out"); 764 + dev_err(cl_data_to_dev(client_data), "wait for resume timed out"); 762 765 } 763 766 } 764 767
-3
drivers/hid/intel-ish-hid/ishtp/bus.c
··· 852 852 */ 853 853 bool ishtp_wait_resume(struct ishtp_device *dev) 854 854 { 855 - /* 50ms to get resume response */ 856 - #define WAIT_FOR_RESUME_ACK_MS 50 857 - 858 855 /* Waiting to get resume response */ 859 856 if (dev->resume_flag) 860 857 wait_event_interruptible_timeout(dev->resume_wait,
+3
drivers/hid/intel-ish-hid/ishtp/ishtp-dev.h
··· 47 47 48 48 #define MAX_DMA_DELAY 20 49 49 50 + /* 300ms to get resume response */ 51 + #define WAIT_FOR_RESUME_ACK_MS 300 52 + 50 53 /* ISHTP device states */ 51 54 enum ishtp_dev_state { 52 55 ISHTP_DEV_INITIALIZING = 0,
+1
drivers/hid/intel-thc-hid/intel-quicki2c/pci-quicki2c.c
··· 419 419 */ 420 420 static void quicki2c_dev_deinit(struct quicki2c_device *qcdev) 421 421 { 422 + thc_interrupt_quiesce(qcdev->thc_hw, true); 422 423 thc_interrupt_enable(qcdev->thc_hw, false); 423 424 thc_ltr_unconfig(qcdev->thc_hw); 424 425 thc_wot_unconfig(qcdev->thc_hw);
+2
drivers/hid/intel-thc-hid/intel-quicki2c/quicki2c-dev.h
··· 77 77 u16 device_address; 78 78 u64 connection_speed; 79 79 u8 addressing_mode; 80 + u8 reserved; 80 81 } __packed; 81 82 82 83 /** ··· 127 126 u64 HMTD; 128 127 u64 HMRD; 129 128 u64 HMSL; 129 + u8 reserved; 130 130 }; 131 131 132 132 /**
+2 -2
drivers/hid/intel-thc-hid/intel-thc/intel-thc-dev.c
··· 1540 1540 1541 1541 for (int i = 0; i < ARRAY_SIZE(i2c_subip_regs); i++) { 1542 1542 ret = thc_i2c_subip_pio_read(dev, i2c_subip_regs[i], 1543 - &read_size, (u32 *)&dev->i2c_subip_regs + i); 1543 + &read_size, &dev->i2c_subip_regs[i]); 1544 1544 if (ret < 0) 1545 1545 return ret; 1546 1546 } ··· 1563 1563 1564 1564 for (int i = 0; i < ARRAY_SIZE(i2c_subip_regs); i++) { 1565 1565 ret = thc_i2c_subip_pio_write(dev, i2c_subip_regs[i], 1566 - write_size, (u32 *)&dev->i2c_subip_regs + i); 1566 + write_size, &dev->i2c_subip_regs[i]); 1567 1567 if (ret < 0) 1568 1568 return ret; 1569 1569 }
+1
drivers/hid/wacom_wac.c
··· 684 684 case 0x885: /* Intuos3 Marker Pen */ 685 685 case 0x804: /* Intuos4/5 13HD/24HD Marker Pen */ 686 686 case 0x10804: /* Intuos4/5 13HD/24HD Art Pen */ 687 + case 0x204: /* Art Pen 2 */ 687 688 is_art_pen = true; 688 689 break; 689 690 }
+1 -1
drivers/irqchip/irq-atmel-aic.c
··· 188 188 189 189 gc = dgc->gc[idx]; 190 190 191 - guard(raw_spinlock_irq)(&gc->lock); 191 + guard(raw_spinlock_irqsave)(&gc->lock); 192 192 smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq)); 193 193 aic_common_set_priority(intspec[2], &smr); 194 194 irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
+1 -1
drivers/irqchip/irq-atmel-aic5.c
··· 279 279 if (ret) 280 280 return ret; 281 281 282 - guard(raw_spinlock_irq)(&bgc->lock); 282 + guard(raw_spinlock_irqsave)(&bgc->lock); 283 283 irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR); 284 284 smr = irq_reg_readl(bgc, AT91_AIC5_SMR); 285 285 aic_common_set_priority(intspec[2], &smr);
+7 -2
drivers/irqchip/irq-gic-v5-irs.c
··· 5 5 6 6 #define pr_fmt(fmt) "GICv5 IRS: " fmt 7 7 8 + #include <linux/kmemleak.h> 8 9 #include <linux/log2.h> 9 10 #include <linux/of.h> 10 11 #include <linux/of_address.h> ··· 118 117 kfree(ist); 119 118 return ret; 120 119 } 120 + kmemleak_ignore(ist); 121 121 122 122 return 0; 123 123 } ··· 234 232 kfree(l2ist); 235 233 return ret; 236 234 } 235 + kmemleak_ignore(l2ist); 237 236 238 237 /* 239 238 * Make sure we invalidate the cache line pulled before the IRS ··· 626 623 int cpu; 627 624 628 625 cpu_node = of_parse_phandle(node, "cpus", i); 629 - if (WARN_ON(!cpu_node)) 626 + if (!cpu_node) { 627 + pr_warn(FW_BUG "Erroneous CPU node phandle\n"); 630 628 continue; 629 + } 631 630 632 631 cpu = of_cpu_node_to_id(cpu_node); 633 632 of_node_put(cpu_node); 634 - if (WARN_ON(cpu < 0)) 633 + if (cpu < 0) 635 634 continue; 636 635 637 636 if (iaffids[i] & ~iaffid_mask) {
+1 -1
drivers/irqchip/irq-mvebu-gicp.c
··· 238 238 } 239 239 240 240 base = ioremap(gicp->res->start, resource_size(gicp->res)); 241 - if (IS_ERR(base)) { 241 + if (!base) { 242 242 dev_err(&pdev->dev, "ioremap() failed. Unable to clear pending interrupts.\n"); 243 243 } else { 244 244 for (i = 0; i < 64; i++)
+3 -3
drivers/isdn/mISDN/dsp_hwec.c
··· 51 51 goto _do; 52 52 53 53 { 54 - char *dup, *tok, *name, *val; 54 + char *dup, *next, *tok, *name, *val; 55 55 int tmp; 56 56 57 - dup = kstrdup(arg, GFP_ATOMIC); 57 + dup = next = kstrdup(arg, GFP_ATOMIC); 58 58 if (!dup) 59 59 return; 60 60 61 - while ((tok = strsep(&dup, ","))) { 61 + while ((tok = strsep(&next, ","))) { 62 62 if (!strlen(tok)) 63 63 continue; 64 64 name = strsep(&tok, "=");
+13 -4
drivers/net/dsa/mv88e6xxx/leds.c
··· 779 779 continue; 780 780 if (led_num > 1) { 781 781 dev_err(dev, "invalid LED specified port %d\n", port); 782 - return -EINVAL; 782 + ret = -EINVAL; 783 + goto err_put_led; 783 784 } 784 785 785 786 if (led_num == 0) ··· 824 823 init_data.devname_mandatory = true; 825 824 init_data.devicename = kasprintf(GFP_KERNEL, "%s:0%d:0%d", chip->info->name, 826 825 port, led_num); 827 - if (!init_data.devicename) 828 - return -ENOMEM; 826 + if (!init_data.devicename) { 827 + ret = -ENOMEM; 828 + goto err_put_led; 829 + } 829 830 830 831 ret = devm_led_classdev_register_ext(dev, l, &init_data); 831 832 kfree(init_data.devicename); 832 833 833 834 if (ret) { 834 835 dev_err(dev, "Failed to init LED %d for port %d", led_num, port); 835 - return ret; 836 + goto err_put_led; 836 837 } 837 838 } 838 839 840 + fwnode_handle_put(leds); 839 841 return 0; 842 + 843 + err_put_led: 844 + fwnode_handle_put(led); 845 + fwnode_handle_put(leds); 846 + return ret; 840 847 }
+1 -1
drivers/net/ethernet/broadcom/bnxt/bnxt.c
··· 4401 4401 for (i = 0; i < bp->rx_agg_ring_size; i++) { 4402 4402 if (bnxt_alloc_rx_netmem(bp, rxr, prod, GFP_KERNEL)) { 4403 4403 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d pages only\n", 4404 - ring_nr, i, bp->rx_ring_size); 4404 + ring_nr, i, bp->rx_agg_ring_size); 4405 4405 break; 4406 4406 } 4407 4407 prod = NEXT_RX_AGG(prod);
+16 -12
drivers/net/ethernet/cadence/macb_main.c
··· 1224 1224 { 1225 1225 struct macb *bp = queue->bp; 1226 1226 u16 queue_index = queue - bp->queues; 1227 + unsigned long flags; 1227 1228 unsigned int tail; 1228 1229 unsigned int head; 1229 1230 int packets = 0; 1230 1231 u32 bytes = 0; 1231 1232 1232 - spin_lock(&queue->tx_ptr_lock); 1233 + spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1233 1234 head = queue->tx_head; 1234 1235 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) { 1235 1236 struct macb_tx_skb *tx_skb; ··· 1293 1292 CIRC_CNT(queue->tx_head, queue->tx_tail, 1294 1293 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp)) 1295 1294 netif_wake_subqueue(bp->dev, queue_index); 1296 - spin_unlock(&queue->tx_ptr_lock); 1295 + spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1297 1296 1298 1297 return packets; 1299 1298 } ··· 1709 1708 { 1710 1709 struct macb *bp = queue->bp; 1711 1710 unsigned int head_idx, tbqp; 1711 + unsigned long flags; 1712 1712 1713 - spin_lock(&queue->tx_ptr_lock); 1713 + spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1714 1714 1715 1715 if (queue->tx_head == queue->tx_tail) 1716 1716 goto out_tx_ptr_unlock; ··· 1723 1721 if (tbqp == head_idx) 1724 1722 goto out_tx_ptr_unlock; 1725 1723 1726 - spin_lock_irq(&bp->lock); 1724 + spin_lock(&bp->lock); 1727 1725 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1728 - spin_unlock_irq(&bp->lock); 1726 + spin_unlock(&bp->lock); 1729 1727 1730 1728 out_tx_ptr_unlock: 1731 - spin_unlock(&queue->tx_ptr_lock); 1729 + spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1732 1730 } 1733 1731 1734 1732 static bool macb_tx_complete_pending(struct macb_queue *queue) 1735 1733 { 1736 1734 bool retval = false; 1735 + unsigned long flags; 1737 1736 1738 - spin_lock(&queue->tx_ptr_lock); 1737 + spin_lock_irqsave(&queue->tx_ptr_lock, flags); 1739 1738 if (queue->tx_head != queue->tx_tail) { 1740 1739 /* Make hw descriptor updates visible to CPU */ 1741 1740 rmb(); ··· 1744 1741 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED)) 1745 1742 retval = true; 1746 1743 } 1747 - spin_unlock(&queue->tx_ptr_lock); 1744 + spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 1748 1745 return retval; 1749 1746 } 1750 1747 ··· 2312 2309 struct macb_queue *queue = &bp->queues[queue_index]; 2313 2310 unsigned int desc_cnt, nr_frags, frag_size, f; 2314 2311 unsigned int hdrlen; 2312 + unsigned long flags; 2315 2313 bool is_lso; 2316 2314 netdev_tx_t ret = NETDEV_TX_OK; 2317 2315 ··· 2373 2369 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length); 2374 2370 } 2375 2371 2376 - spin_lock_bh(&queue->tx_ptr_lock); 2372 + spin_lock_irqsave(&queue->tx_ptr_lock, flags); 2377 2373 2378 2374 /* This is a hard error, log it. */ 2379 2375 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, ··· 2397 2393 netdev_tx_sent_queue(netdev_get_tx_queue(bp->dev, queue_index), 2398 2394 skb->len); 2399 2395 2400 - spin_lock_irq(&bp->lock); 2396 + spin_lock(&bp->lock); 2401 2397 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 2402 - spin_unlock_irq(&bp->lock); 2398 + spin_unlock(&bp->lock); 2403 2399 2404 2400 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) 2405 2401 netif_stop_subqueue(dev, queue_index); 2406 2402 2407 2403 unlock: 2408 - spin_unlock_bh(&queue->tx_ptr_lock); 2404 + spin_unlock_irqrestore(&queue->tx_ptr_lock, flags); 2409 2405 2410 2406 return ret; 2411 2407 }
+12 -8
drivers/net/ethernet/cavium/thunder/thunder_bgx.c
··· 1493 1493 * this cortina phy, for which there is no driver 1494 1494 * support, ignore it. 1495 1495 */ 1496 - if (phy_np && 1497 - !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) { 1498 - /* Wait until the phy drivers are available */ 1499 - pd = of_phy_find_device(phy_np); 1500 - if (!pd) 1501 - goto defer; 1502 - bgx->lmac[lmac].phydev = pd; 1496 + if (phy_np) { 1497 + if (!of_device_is_compatible(phy_np, "cortina,cs4223-slice")) { 1498 + /* Wait until the phy drivers are available */ 1499 + pd = of_phy_find_device(phy_np); 1500 + if (!pd) { 1501 + of_node_put(phy_np); 1502 + goto defer; 1503 + } 1504 + bgx->lmac[lmac].phydev = pd; 1505 + } 1506 + of_node_put(phy_np); 1503 1507 } 1504 1508 1505 1509 lmac++; ··· 1519 1515 * for phy devices we may have already found. 1520 1516 */ 1521 1517 while (lmac) { 1518 + lmac--; 1522 1519 if (bgx->lmac[lmac].phydev) { 1523 1520 put_device(&bgx->lmac[lmac].phydev->mdio.dev); 1524 1521 bgx->lmac[lmac].phydev = NULL; 1525 1522 } 1526 - lmac--; 1527 1523 } 1528 1524 of_node_put(node); 1529 1525 return -EPROBE_DEFER;
+20
drivers/net/ethernet/dlink/Kconfig
··· 32 32 To compile this driver as a module, choose M here: the 33 33 module will be called dl2k. 34 34 35 + config SUNDANCE 36 + tristate "Sundance Alta support" 37 + depends on PCI 38 + select CRC32 39 + select MII 40 + help 41 + This driver is for the Sundance "Alta" chip. 42 + More specific information and updates are available from 43 + <http://www.scyld.com/network/sundance.html>. 44 + 45 + config SUNDANCE_MMIO 46 + bool "Use MMIO instead of PIO" 47 + depends on SUNDANCE 48 + help 49 + Enable memory-mapped I/O for interaction with Sundance NIC registers. 50 + Do NOT enable this by default, PIO (enabled when MMIO is disabled) 51 + is known to solve bugs on certain chips. 52 + 53 + If unsure, say N. 54 + 35 55 endif # NET_VENDOR_DLINK
+1
drivers/net/ethernet/dlink/Makefile
··· 4 4 # 5 5 6 6 obj-$(CONFIG_DL2K) += dl2k.o 7 + obj-$(CONFIG_SUNDANCE) += sundance.o
+1990
drivers/net/ethernet/dlink/sundance.c
··· 1 + /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */ 2 + /* 3 + Written 1999-2000 by Donald Becker. 4 + 5 + This software may be used and distributed according to the terms of 6 + the GNU General Public License (GPL), incorporated herein by reference. 7 + Drivers based on or derived from this code fall under the GPL and must 8 + retain the authorship, copyright and license notice. This file is not 9 + a complete program and may only be used when the entire operating 10 + system is licensed under the GPL. 11 + 12 + The author may be reached as becker@scyld.com, or C/O 13 + Scyld Computing Corporation 14 + 410 Severn Ave., Suite 210 15 + Annapolis MD 21403 16 + 17 + Support and updates available at 18 + http://www.scyld.com/network/sundance.html 19 + [link no longer provides useful info -jgarzik] 20 + Archives of the mailing list are still available at 21 + https://www.beowulf.org/pipermail/netdrivers/ 22 + 23 + */ 24 + 25 + #define DRV_NAME "sundance" 26 + 27 + /* The user-configurable values. 28 + These may be modified when a driver module is loaded.*/ 29 + static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ 30 + /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 31 + Typical is a 64 element hash table based on the Ethernet CRC. */ 32 + static const int multicast_filter_limit = 32; 33 + 34 + /* Set the copy breakpoint for the copy-only-tiny-frames scheme. 35 + Setting to > 1518 effectively disables this feature. 36 + This chip can receive into offset buffers, so the Alpha does not 37 + need a copy-align. */ 38 + static int rx_copybreak; 39 + static int flowctrl=1; 40 + 41 + /* media[] specifies the media type the NIC operates at. 42 + autosense Autosensing active media. 43 + 10mbps_hd 10Mbps half duplex. 44 + 10mbps_fd 10Mbps full duplex. 45 + 100mbps_hd 100Mbps half duplex. 46 + 100mbps_fd 100Mbps full duplex. 47 + 0 Autosensing active media. 48 + 1 10Mbps half duplex. 49 + 2 10Mbps full duplex. 50 + 3 100Mbps half duplex. 51 + 4 100Mbps full duplex. 52 + */ 53 + #define MAX_UNITS 8 54 + static char *media[MAX_UNITS]; 55 + 56 + 57 + /* Operational parameters that are set at compile time. */ 58 + 59 + /* Keep the ring sizes a power of two for compile efficiency. 60 + The compiler will convert <unsigned>'%'<2^N> into a bit mask. 61 + Making the Tx ring too large decreases the effectiveness of channel 62 + bonding and packet priority, and more than 128 requires modifying the 63 + Tx error recovery. 64 + Large receive rings merely waste memory. */ 65 + #define TX_RING_SIZE 32 66 + #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */ 67 + #define RX_RING_SIZE 64 68 + #define RX_BUDGET 32 69 + #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc) 70 + #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc) 71 + 72 + /* Operational parameters that usually are not changed. */ 73 + /* Time in jiffies before concluding the transmitter is hung. */ 74 + #define TX_TIMEOUT (4*HZ) 75 + #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 76 + 77 + /* Include files, designed to support most kernel versions 2.0.0 and later. */ 78 + #include <linux/module.h> 79 + #include <linux/kernel.h> 80 + #include <linux/string.h> 81 + #include <linux/timer.h> 82 + #include <linux/errno.h> 83 + #include <linux/ioport.h> 84 + #include <linux/interrupt.h> 85 + #include <linux/pci.h> 86 + #include <linux/netdevice.h> 87 + #include <linux/etherdevice.h> 88 + #include <linux/skbuff.h> 89 + #include <linux/init.h> 90 + #include <linux/bitops.h> 91 + #include <linux/uaccess.h> 92 + #include <asm/processor.h> /* Processor type for cache alignment. */ 93 + #include <asm/io.h> 94 + #include <linux/delay.h> 95 + #include <linux/spinlock.h> 96 + #include <linux/dma-mapping.h> 97 + #include <linux/crc32.h> 98 + #include <linux/ethtool.h> 99 + #include <linux/mii.h> 100 + 101 + MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 102 + MODULE_DESCRIPTION("Sundance Alta Ethernet driver"); 103 + MODULE_LICENSE("GPL"); 104 + 105 + module_param(debug, int, 0); 106 + module_param(rx_copybreak, int, 0); 107 + module_param_array(media, charp, NULL, 0); 108 + module_param(flowctrl, int, 0); 109 + MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)"); 110 + MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames"); 111 + MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]"); 112 + 113 + /* 114 + Theory of Operation 115 + 116 + I. Board Compatibility 117 + 118 + This driver is designed for the Sundance Technologies "Alta" ST201 chip. 119 + 120 + II. Board-specific settings 121 + 122 + III. Driver operation 123 + 124 + IIIa. Ring buffers 125 + 126 + This driver uses two statically allocated fixed-size descriptor lists 127 + formed into rings by a branch from the final descriptor to the beginning of 128 + the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 129 + Some chips explicitly use only 2^N sized rings, while others use a 130 + 'next descriptor' pointer that the driver forms into rings. 131 + 132 + IIIb/c. Transmit/Receive Structure 133 + 134 + This driver uses a zero-copy receive and transmit scheme. 135 + The driver allocates full frame size skbuffs for the Rx ring buffers at 136 + open() time and passes the skb->data field to the chip as receive data 137 + buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 138 + a fresh skbuff is allocated and the frame is copied to the new skbuff. 139 + When the incoming frame is larger, the skbuff is passed directly up the 140 + protocol stack. Buffers consumed this way are replaced by newly allocated 141 + skbuffs in a later phase of receives. 142 + 143 + The RX_COPYBREAK value is chosen to trade-off the memory wasted by 144 + using a full-sized skbuff for small frames vs. the copying costs of larger 145 + frames. New boards are typically used in generously configured machines 146 + and the underfilled buffers have negligible impact compared to the benefit of 147 + a single allocation size, so the default value of zero results in never 148 + copying packets. When copying is done, the cost is usually mitigated by using 149 + a combined copy/checksum routine. Copying also preloads the cache, which is 150 + most useful with small frames. 151 + 152 + A subtle aspect of the operation is that the IP header at offset 14 in an 153 + ethernet frame isn't longword aligned for further processing. 154 + Unaligned buffers are permitted by the Sundance hardware, so 155 + frames are received into the skbuff at an offset of "+2", 16-byte aligning 156 + the IP header. 157 + 158 + IIId. Synchronization 159 + 160 + The driver runs as two independent, single-threaded flows of control. One 161 + is the send-packet routine, which enforces single-threaded use by the 162 + dev->tbusy flag. The other thread is the interrupt handler, which is single 163 + threaded by the hardware and interrupt handling software. 164 + 165 + The send packet thread has partial control over the Tx ring and 'dev->tbusy' 166 + flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next 167 + queue slot is empty, it clears the tbusy flag when finished otherwise it sets 168 + the 'lp->tx_full' flag. 169 + 170 + The interrupt handler has exclusive control over the Rx ring and records stats 171 + from the Tx ring. After reaping the stats, it marks the Tx queue entry as 172 + empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it 173 + clears both the tx_full and tbusy flags. 174 + 175 + IV. Notes 176 + 177 + IVb. References 178 + 179 + The Sundance ST201 datasheet, preliminary version. 180 + The Kendin KS8723 datasheet, preliminary version. 181 + The ICplus IP100 datasheet, preliminary version. 182 + http://www.scyld.com/expert/100mbps.html 183 + http://www.scyld.com/expert/NWay.html 184 + 185 + IVc. Errata 186 + 187 + */ 188 + 189 + /* Work-around for Kendin chip bugs. */ 190 + #ifndef CONFIG_SUNDANCE_MMIO 191 + #define USE_IO_OPS 1 192 + #endif 193 + 194 + static const struct pci_device_id sundance_pci_tbl[] = { 195 + { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 }, 196 + { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 }, 197 + { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 }, 198 + { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 }, 199 + { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, 200 + { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }, 201 + { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 }, 202 + { } 203 + }; 204 + MODULE_DEVICE_TABLE(pci, sundance_pci_tbl); 205 + 206 + enum { 207 + netdev_io_size = 128 208 + }; 209 + 210 + struct pci_id_info { 211 + const char *name; 212 + }; 213 + static const struct pci_id_info pci_id_tbl[] = { 214 + {"D-Link DFE-550TX FAST Ethernet Adapter"}, 215 + {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"}, 216 + {"D-Link DFE-580TX 4 port Server Adapter"}, 217 + {"D-Link DFE-530TXS FAST Ethernet Adapter"}, 218 + {"D-Link DL10050-based FAST Ethernet Adapter"}, 219 + {"Sundance Technology Alta"}, 220 + {"IC Plus Corporation IP100A FAST Ethernet Adapter"}, 221 + { } /* terminate list. */ 222 + }; 223 + 224 + /* This driver was written to use PCI memory space, however x86-oriented 225 + hardware often uses I/O space accesses. */ 226 + 227 + /* Offsets to the device registers. 228 + Unlike software-only systems, device drivers interact with complex hardware. 229 + It's not useful to define symbolic names for every register bit in the 230 + device. The name can only partially document the semantics and make 231 + the driver longer and more difficult to read. 232 + In general, only the important configuration values or bits changed 233 + multiple times should be defined symbolically. 234 + */ 235 + enum alta_offsets { 236 + DMACtrl = 0x00, 237 + TxListPtr = 0x04, 238 + TxDMABurstThresh = 0x08, 239 + TxDMAUrgentThresh = 0x09, 240 + TxDMAPollPeriod = 0x0a, 241 + RxDMAStatus = 0x0c, 242 + RxListPtr = 0x10, 243 + DebugCtrl0 = 0x1a, 244 + DebugCtrl1 = 0x1c, 245 + RxDMABurstThresh = 0x14, 246 + RxDMAUrgentThresh = 0x15, 247 + RxDMAPollPeriod = 0x16, 248 + LEDCtrl = 0x1a, 249 + ASICCtrl = 0x30, 250 + EEData = 0x34, 251 + EECtrl = 0x36, 252 + FlashAddr = 0x40, 253 + FlashData = 0x44, 254 + WakeEvent = 0x45, 255 + TxStatus = 0x46, 256 + TxFrameId = 0x47, 257 + DownCounter = 0x18, 258 + IntrClear = 0x4a, 259 + IntrEnable = 0x4c, 260 + IntrStatus = 0x4e, 261 + MACCtrl0 = 0x50, 262 + MACCtrl1 = 0x52, 263 + StationAddr = 0x54, 264 + MaxFrameSize = 0x5A, 265 + RxMode = 0x5c, 266 + MIICtrl = 0x5e, 267 + MulticastFilter0 = 0x60, 268 + MulticastFilter1 = 0x64, 269 + RxOctetsLow = 0x68, 270 + RxOctetsHigh = 0x6a, 271 + TxOctetsLow = 0x6c, 272 + TxOctetsHigh = 0x6e, 273 + TxFramesOK = 0x70, 274 + RxFramesOK = 0x72, 275 + StatsCarrierError = 0x74, 276 + StatsLateColl = 0x75, 277 + StatsMultiColl = 0x76, 278 + StatsOneColl = 0x77, 279 + StatsTxDefer = 0x78, 280 + RxMissed = 0x79, 281 + StatsTxXSDefer = 0x7a, 282 + StatsTxAbort = 0x7b, 283 + StatsBcastTx = 0x7c, 284 + StatsBcastRx = 0x7d, 285 + StatsMcastTx = 0x7e, 286 + StatsMcastRx = 0x7f, 287 + /* Aliased and bogus values! */ 288 + RxStatus = 0x0c, 289 + }; 290 + 291 + #define ASIC_HI_WORD(x) ((x) + 2) 292 + 293 + enum ASICCtrl_HiWord_bit { 294 + GlobalReset = 0x0001, 295 + RxReset = 0x0002, 296 + TxReset = 0x0004, 297 + DMAReset = 0x0008, 298 + FIFOReset = 0x0010, 299 + NetworkReset = 0x0020, 300 + HostReset = 0x0040, 301 + ResetBusy = 0x0400, 302 + }; 303 + 304 + /* Bits in the interrupt status/mask registers. */ 305 + enum intr_status_bits { 306 + IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008, 307 + IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020, 308 + IntrDrvRqst=0x0040, 309 + StatsMax=0x0080, LinkChange=0x0100, 310 + IntrTxDMADone=0x0200, IntrRxDMADone=0x0400, 311 + }; 312 + 313 + /* Bits in the RxMode register. */ 314 + enum rx_mode_bits { 315 + AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08, 316 + AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01, 317 + }; 318 + /* Bits in MACCtrl. */ 319 + enum mac_ctrl0_bits { 320 + EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40, 321 + EnbFlowCtrl=0x100, EnbPassRxCRC=0x200, 322 + }; 323 + enum mac_ctrl1_bits { 324 + StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080, 325 + TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400, 326 + RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000, 327 + }; 328 + 329 + /* Bits in WakeEvent register. */ 330 + enum wake_event_bits { 331 + WakePktEnable = 0x01, 332 + MagicPktEnable = 0x02, 333 + LinkEventEnable = 0x04, 334 + WolEnable = 0x80, 335 + }; 336 + 337 + /* The Rx and Tx buffer descriptors. */ 338 + /* Note that using only 32 bit fields simplifies conversion to big-endian 339 + architectures. */ 340 + struct netdev_desc { 341 + __le32 next_desc; 342 + __le32 status; 343 + struct desc_frag { __le32 addr, length; } frag; 344 + }; 345 + 346 + /* Bits in netdev_desc.status */ 347 + enum desc_status_bits { 348 + DescOwn=0x8000, 349 + DescEndPacket=0x4000, 350 + DescEndRing=0x2000, 351 + LastFrag=0x80000000, 352 + DescIntrOnTx=0x8000, 353 + DescIntrOnDMADone=0x80000000, 354 + DisableAlign = 0x00000001, 355 + }; 356 + 357 + #define PRIV_ALIGN 15 /* Required alignment mask */ 358 + /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment 359 + within the structure. */ 360 + #define MII_CNT 4 361 + struct netdev_private { 362 + /* Descriptor rings first for alignment. */ 363 + struct netdev_desc *rx_ring; 364 + struct netdev_desc *tx_ring; 365 + struct sk_buff* rx_skbuff[RX_RING_SIZE]; 366 + struct sk_buff* tx_skbuff[TX_RING_SIZE]; 367 + dma_addr_t tx_ring_dma; 368 + dma_addr_t rx_ring_dma; 369 + struct timer_list timer; /* Media monitoring timer. */ 370 + struct net_device *ndev; /* backpointer */ 371 + /* ethtool extra stats */ 372 + struct { 373 + u64 tx_multiple_collisions; 374 + u64 tx_single_collisions; 375 + u64 tx_late_collisions; 376 + u64 tx_deferred; 377 + u64 tx_deferred_excessive; 378 + u64 tx_aborted; 379 + u64 tx_bcasts; 380 + u64 rx_bcasts; 381 + u64 tx_mcasts; 382 + u64 rx_mcasts; 383 + } xstats; 384 + /* Frequently used values: keep some adjacent for cache effect. */ 385 + spinlock_t lock; 386 + int msg_enable; 387 + int chip_id; 388 + unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ 389 + unsigned int rx_buf_sz; /* Based on MTU+slack. */ 390 + struct netdev_desc *last_tx; /* Last Tx descriptor used. */ 391 + unsigned int cur_tx, dirty_tx; 392 + /* These values are keep track of the transceiver/media in use. */ 393 + unsigned int flowctrl:1; 394 + unsigned int default_port:4; /* Last dev->if_port value. */ 395 + unsigned int an_enable:1; 396 + unsigned int speed; 397 + unsigned int wol_enabled:1; /* Wake on LAN enabled */ 398 + struct tasklet_struct rx_tasklet; 399 + struct tasklet_struct tx_tasklet; 400 + int budget; 401 + int cur_task; 402 + /* Multicast and receive mode. */ 403 + spinlock_t mcastlock; /* SMP lock multicast updates. */ 404 + u16 mcast_filter[4]; 405 + /* MII transceiver section. */ 406 + struct mii_if_info mii_if; 407 + int mii_preamble_required; 408 + unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */ 409 + struct pci_dev *pci_dev; 410 + void __iomem *base; 411 + spinlock_t statlock; 412 + }; 413 + 414 + /* The station address location in the EEPROM. */ 415 + #define EEPROM_SA_OFFSET 0x10 416 + #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \ 417 + IntrDrvRqst | IntrTxDone | StatsMax | \ 418 + LinkChange) 419 + 420 + static int change_mtu(struct net_device *dev, int new_mtu); 421 + static int eeprom_read(void __iomem *ioaddr, int location); 422 + static int mdio_read(struct net_device *dev, int phy_id, int location); 423 + static void mdio_write(struct net_device *dev, int phy_id, int location, int value); 424 + static int mdio_wait_link(struct net_device *dev, int wait); 425 + static int netdev_open(struct net_device *dev); 426 + static void check_duplex(struct net_device *dev); 427 + static void netdev_timer(struct timer_list *t); 428 + static void tx_timeout(struct net_device *dev, unsigned int txqueue); 429 + static void init_ring(struct net_device *dev); 430 + static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); 431 + static int reset_tx (struct net_device *dev); 432 + static irqreturn_t intr_handler(int irq, void *dev_instance); 433 + static void rx_poll(struct tasklet_struct *t); 434 + static void tx_poll(struct tasklet_struct *t); 435 + static void refill_rx (struct net_device *dev); 436 + static void netdev_error(struct net_device *dev, int intr_status); 437 + static void netdev_error(struct net_device *dev, int intr_status); 438 + static void set_rx_mode(struct net_device *dev); 439 + static int __set_mac_addr(struct net_device *dev); 440 + static int sundance_set_mac_addr(struct net_device *dev, void *data); 441 + static struct net_device_stats *get_stats(struct net_device *dev); 442 + static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 443 + static int netdev_close(struct net_device *dev); 444 + static const struct ethtool_ops ethtool_ops; 445 + 446 + static void sundance_reset(struct net_device *dev, unsigned long reset_cmd) 447 + { 448 + struct netdev_private *np = netdev_priv(dev); 449 + void __iomem *ioaddr = np->base + ASICCtrl; 450 + int countdown; 451 + 452 + /* ST201 documentation states ASICCtrl is a 32bit register */ 453 + iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr); 454 + /* ST201 documentation states reset can take up to 1 ms */ 455 + countdown = 10 + 1; 456 + while (ioread32 (ioaddr) & (ResetBusy << 16)) { 457 + if (--countdown == 0) { 458 + printk(KERN_WARNING "%s : reset not completed !!\n", dev->name); 459 + break; 460 + } 461 + udelay(100); 462 + } 463 + } 464 + 465 + #ifdef CONFIG_NET_POLL_CONTROLLER 466 + static void sundance_poll_controller(struct net_device *dev) 467 + { 468 + struct netdev_private *np = netdev_priv(dev); 469 + 470 + disable_irq(np->pci_dev->irq); 471 + intr_handler(np->pci_dev->irq, dev); 472 + enable_irq(np->pci_dev->irq); 473 + } 474 + #endif 475 + 476 + static const struct net_device_ops netdev_ops = { 477 + .ndo_open = netdev_open, 478 + .ndo_stop = netdev_close, 479 + .ndo_start_xmit = start_tx, 480 + .ndo_get_stats = get_stats, 481 + .ndo_set_rx_mode = set_rx_mode, 482 + .ndo_eth_ioctl = netdev_ioctl, 483 + .ndo_tx_timeout = tx_timeout, 484 + .ndo_change_mtu = change_mtu, 485 + .ndo_set_mac_address = sundance_set_mac_addr, 486 + .ndo_validate_addr = eth_validate_addr, 487 + #ifdef CONFIG_NET_POLL_CONTROLLER 488 + .ndo_poll_controller = sundance_poll_controller, 489 + #endif 490 + }; 491 + 492 + static int sundance_probe1(struct pci_dev *pdev, 493 + const struct pci_device_id *ent) 494 + { 495 + struct net_device *dev; 496 + struct netdev_private *np; 497 + static int card_idx; 498 + int chip_idx = ent->driver_data; 499 + int irq; 500 + int i; 501 + void __iomem *ioaddr; 502 + u16 mii_ctl; 503 + void *ring_space; 504 + dma_addr_t ring_dma; 505 + #ifdef USE_IO_OPS 506 + int bar = 0; 507 + #else 508 + int bar = 1; 509 + #endif 510 + int phy, phy_end, phy_idx = 0; 511 + __le16 addr[ETH_ALEN / 2]; 512 + 513 + if (pci_enable_device(pdev)) 514 + return -EIO; 515 + pci_set_master(pdev); 516 + 517 + irq = pdev->irq; 518 + 519 + dev = alloc_etherdev(sizeof(*np)); 520 + if (!dev) 521 + return -ENOMEM; 522 + SET_NETDEV_DEV(dev, &pdev->dev); 523 + 524 + if (pci_request_regions(pdev, DRV_NAME)) 525 + goto err_out_netdev; 526 + 527 + ioaddr = pci_iomap(pdev, bar, netdev_io_size); 528 + if (!ioaddr) 529 + goto err_out_res; 530 + 531 + for (i = 0; i < 3; i++) 532 + addr[i] = 533 + cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET)); 534 + eth_hw_addr_set(dev, (u8 *)addr); 535 + 536 + np = netdev_priv(dev); 537 + np->ndev = dev; 538 + np->base = ioaddr; 539 + np->pci_dev = pdev; 540 + np->chip_id = chip_idx; 541 + np->msg_enable = (1 << debug) - 1; 542 + spin_lock_init(&np->lock); 543 + spin_lock_init(&np->statlock); 544 + tasklet_setup(&np->rx_tasklet, rx_poll); 545 + tasklet_setup(&np->tx_tasklet, tx_poll); 546 + 547 + ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, 548 + &ring_dma, GFP_KERNEL); 549 + if (!ring_space) 550 + goto err_out_cleardev; 551 + np->tx_ring = (struct netdev_desc *)ring_space; 552 + np->tx_ring_dma = ring_dma; 553 + 554 + ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, 555 + &ring_dma, GFP_KERNEL); 556 + if (!ring_space) 557 + goto err_out_unmap_tx; 558 + np->rx_ring = (struct netdev_desc *)ring_space; 559 + np->rx_ring_dma = ring_dma; 560 + 561 + np->mii_if.dev = dev; 562 + np->mii_if.mdio_read = mdio_read; 563 + np->mii_if.mdio_write = mdio_write; 564 + np->mii_if.phy_id_mask = 0x1f; 565 + np->mii_if.reg_num_mask = 0x1f; 566 + 567 + /* The chip-specific entries in the device structure. */ 568 + dev->netdev_ops = &netdev_ops; 569 + dev->ethtool_ops = &ethtool_ops; 570 + dev->watchdog_timeo = TX_TIMEOUT; 571 + 572 + /* MTU range: 68 - 8191 */ 573 + dev->min_mtu = ETH_MIN_MTU; 574 + dev->max_mtu = 8191; 575 + 576 + pci_set_drvdata(pdev, dev); 577 + 578 + i = register_netdev(dev); 579 + if (i) 580 + goto err_out_unmap_rx; 581 + 582 + printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", 583 + dev->name, pci_id_tbl[chip_idx].name, ioaddr, 584 + dev->dev_addr, irq); 585 + 586 + np->phys[0] = 1; /* Default setting */ 587 + np->mii_preamble_required++; 588 + 589 + /* 590 + * It seems some phys doesn't deal well with address 0 being accessed 591 + * first 592 + */ 593 + if (sundance_pci_tbl[np->chip_id].device == 0x0200) { 594 + phy = 0; 595 + phy_end = 31; 596 + } else { 597 + phy = 1; 598 + phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */ 599 + } 600 + for (; phy <= phy_end && phy_idx < MII_CNT; phy++) { 601 + int phyx = phy & 0x1f; 602 + int mii_status = mdio_read(dev, phyx, MII_BMSR); 603 + if (mii_status != 0xffff && mii_status != 0x0000) { 604 + np->phys[phy_idx++] = phyx; 605 + np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE); 606 + if ((mii_status & 0x0040) == 0) 607 + np->mii_preamble_required++; 608 + printk(KERN_INFO "%s: MII PHY found at address %d, status " 609 + "0x%4.4x advertising %4.4x.\n", 610 + dev->name, phyx, mii_status, np->mii_if.advertising); 611 + } 612 + } 613 + np->mii_preamble_required--; 614 + 615 + if (phy_idx == 0) { 616 + printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n", 617 + dev->name, ioread32(ioaddr + ASICCtrl)); 618 + goto err_out_unregister; 619 + } 620 + 621 + np->mii_if.phy_id = np->phys[0]; 622 + 623 + /* Parse override configuration */ 624 + np->an_enable = 1; 625 + if (card_idx < MAX_UNITS) { 626 + if (media[card_idx] != NULL) { 627 + np->an_enable = 0; 628 + if (strcmp (media[card_idx], "100mbps_fd") == 0 || 629 + strcmp (media[card_idx], "4") == 0) { 630 + np->speed = 100; 631 + np->mii_if.full_duplex = 1; 632 + } else if (strcmp (media[card_idx], "100mbps_hd") == 0 || 633 + strcmp (media[card_idx], "3") == 0) { 634 + np->speed = 100; 635 + np->mii_if.full_duplex = 0; 636 + } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || 637 + strcmp (media[card_idx], "2") == 0) { 638 + np->speed = 10; 639 + np->mii_if.full_duplex = 1; 640 + } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || 641 + strcmp (media[card_idx], "1") == 0) { 642 + np->speed = 10; 643 + np->mii_if.full_duplex = 0; 644 + } else { 645 + np->an_enable = 1; 646 + } 647 + } 648 + if (flowctrl == 1) 649 + np->flowctrl = 1; 650 + } 651 + 652 + /* Fibre PHY? */ 653 + if (ioread32 (ioaddr + ASICCtrl) & 0x80) { 654 + /* Default 100Mbps Full */ 655 + if (np->an_enable) { 656 + np->speed = 100; 657 + np->mii_if.full_duplex = 1; 658 + np->an_enable = 0; 659 + } 660 + } 661 + /* Reset PHY */ 662 + mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET); 663 + mdelay (300); 664 + /* If flow control enabled, we need to advertise it.*/ 665 + if (np->flowctrl) 666 + mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400); 667 + mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART); 668 + /* Force media type */ 669 + if (!np->an_enable) { 670 + mii_ctl = 0; 671 + mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0; 672 + mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0; 673 + mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl); 674 + printk (KERN_INFO "Override speed=%d, %s duplex\n", 675 + np->speed, np->mii_if.full_duplex ? "Full" : "Half"); 676 + 677 + } 678 + 679 + /* Perhaps move the reset here? */ 680 + /* Reset the chip to erase previous misconfiguration. */ 681 + if (netif_msg_hw(np)) 682 + printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl)); 683 + sundance_reset(dev, 0x00ff << 16); 684 + if (netif_msg_hw(np)) 685 + printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl)); 686 + 687 + card_idx++; 688 + return 0; 689 + 690 + err_out_unregister: 691 + unregister_netdev(dev); 692 + err_out_unmap_rx: 693 + dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, 694 + np->rx_ring, np->rx_ring_dma); 695 + err_out_unmap_tx: 696 + dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, 697 + np->tx_ring, np->tx_ring_dma); 698 + err_out_cleardev: 699 + pci_iounmap(pdev, ioaddr); 700 + err_out_res: 701 + pci_release_regions(pdev); 702 + err_out_netdev: 703 + free_netdev (dev); 704 + return -ENODEV; 705 + } 706 + 707 + static int change_mtu(struct net_device *dev, int new_mtu) 708 + { 709 + if (netif_running(dev)) 710 + return -EBUSY; 711 + WRITE_ONCE(dev->mtu, new_mtu); 712 + return 0; 713 + } 714 + 715 + #define eeprom_delay(ee_addr) ioread32(ee_addr) 716 + /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */ 717 + static int eeprom_read(void __iomem *ioaddr, int location) 718 + { 719 + int boguscnt = 10000; /* Typical 1900 ticks. */ 720 + iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl); 721 + do { 722 + eeprom_delay(ioaddr + EECtrl); 723 + if (! (ioread16(ioaddr + EECtrl) & 0x8000)) { 724 + return ioread16(ioaddr + EEData); 725 + } 726 + } while (--boguscnt > 0); 727 + return 0; 728 + } 729 + 730 + /* MII transceiver control section. 731 + Read and write the MII registers using software-generated serial 732 + MDIO protocol. See the MII specifications or DP83840A data sheet 733 + for details. 734 + 735 + The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 736 + met by back-to-back 33Mhz PCI cycles. */ 737 + #define mdio_delay() ioread8(mdio_addr) 738 + 739 + enum mii_reg_bits { 740 + MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004, 741 + }; 742 + #define MDIO_EnbIn (0) 743 + #define MDIO_WRITE0 (MDIO_EnbOutput) 744 + #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) 745 + 746 + /* Generate the preamble required for initial synchronization and 747 + a few older transceivers. */ 748 + static void mdio_sync(void __iomem *mdio_addr) 749 + { 750 + int bits = 32; 751 + 752 + /* Establish sync by sending at least 32 logic ones. */ 753 + while (--bits >= 0) { 754 + iowrite8(MDIO_WRITE1, mdio_addr); 755 + mdio_delay(); 756 + iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr); 757 + mdio_delay(); 758 + } 759 + } 760 + 761 + static int mdio_read(struct net_device *dev, int phy_id, int location) 762 + { 763 + struct netdev_private *np = netdev_priv(dev); 764 + void __iomem *mdio_addr = np->base + MIICtrl; 765 + int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 766 + int i, retval = 0; 767 + 768 + if (np->mii_preamble_required) 769 + mdio_sync(mdio_addr); 770 + 771 + /* Shift the read command bits out. */ 772 + for (i = 15; i >= 0; i--) { 773 + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 774 + 775 + iowrite8(dataval, mdio_addr); 776 + mdio_delay(); 777 + iowrite8(dataval | MDIO_ShiftClk, mdio_addr); 778 + mdio_delay(); 779 + } 780 + /* Read the two transition, 16 data, and wire-idle bits. */ 781 + for (i = 19; i > 0; i--) { 782 + iowrite8(MDIO_EnbIn, mdio_addr); 783 + mdio_delay(); 784 + retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0); 785 + iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); 786 + mdio_delay(); 787 + } 788 + return (retval>>1) & 0xffff; 789 + } 790 + 791 + static void mdio_write(struct net_device *dev, int phy_id, int location, int value) 792 + { 793 + struct netdev_private *np = netdev_priv(dev); 794 + void __iomem *mdio_addr = np->base + MIICtrl; 795 + int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; 796 + int i; 797 + 798 + if (np->mii_preamble_required) 799 + mdio_sync(mdio_addr); 800 + 801 + /* Shift the command bits out. */ 802 + for (i = 31; i >= 0; i--) { 803 + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 804 + 805 + iowrite8(dataval, mdio_addr); 806 + mdio_delay(); 807 + iowrite8(dataval | MDIO_ShiftClk, mdio_addr); 808 + mdio_delay(); 809 + } 810 + /* Clear out extra bits. */ 811 + for (i = 2; i > 0; i--) { 812 + iowrite8(MDIO_EnbIn, mdio_addr); 813 + mdio_delay(); 814 + iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); 815 + mdio_delay(); 816 + } 817 + } 818 + 819 + static int mdio_wait_link(struct net_device *dev, int wait) 820 + { 821 + int bmsr; 822 + int phy_id; 823 + struct netdev_private *np; 824 + 825 + np = netdev_priv(dev); 826 + phy_id = np->phys[0]; 827 + 828 + do { 829 + bmsr = mdio_read(dev, phy_id, MII_BMSR); 830 + if (bmsr & 0x0004) 831 + return 0; 832 + mdelay(1); 833 + } while (--wait > 0); 834 + return -1; 835 + } 836 + 837 + static int netdev_open(struct net_device *dev) 838 + { 839 + struct netdev_private *np = netdev_priv(dev); 840 + void __iomem *ioaddr = np->base; 841 + const int irq = np->pci_dev->irq; 842 + unsigned long flags; 843 + int i; 844 + 845 + sundance_reset(dev, 0x00ff << 16); 846 + 847 + i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); 848 + if (i) 849 + return i; 850 + 851 + if (netif_msg_ifup(np)) 852 + printk(KERN_DEBUG "%s: netdev_open() irq %d\n", dev->name, irq); 853 + 854 + init_ring(dev); 855 + 856 + iowrite32(np->rx_ring_dma, ioaddr + RxListPtr); 857 + /* The Tx list pointer is written as packets are queued. */ 858 + 859 + /* Initialize other registers. */ 860 + __set_mac_addr(dev); 861 + #if IS_ENABLED(CONFIG_VLAN_8021Q) 862 + iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize); 863 + #else 864 + iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize); 865 + #endif 866 + if (dev->mtu > 2047) 867 + iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl); 868 + 869 + /* Configure the PCI bus bursts and FIFO thresholds. */ 870 + 871 + if (dev->if_port == 0) 872 + dev->if_port = np->default_port; 873 + 874 + spin_lock_init(&np->mcastlock); 875 + 876 + set_rx_mode(dev); 877 + iowrite16(0, ioaddr + IntrEnable); 878 + iowrite16(0, ioaddr + DownCounter); 879 + /* Set the chip to poll every N*320nsec. */ 880 + iowrite8(100, ioaddr + RxDMAPollPeriod); 881 + iowrite8(127, ioaddr + TxDMAPollPeriod); 882 + /* Fix DFE-580TX packet drop issue */ 883 + if (np->pci_dev->revision >= 0x14) 884 + iowrite8(0x01, ioaddr + DebugCtrl1); 885 + netif_start_queue(dev); 886 + 887 + spin_lock_irqsave(&np->lock, flags); 888 + reset_tx(dev); 889 + spin_unlock_irqrestore(&np->lock, flags); 890 + 891 + iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); 892 + 893 + /* Disable Wol */ 894 + iowrite8(ioread8(ioaddr + WakeEvent) | 0x00, ioaddr + WakeEvent); 895 + np->wol_enabled = 0; 896 + 897 + if (netif_msg_ifup(np)) 898 + printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x " 899 + "MAC Control %x, %4.4x %4.4x.\n", 900 + dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus), 901 + ioread32(ioaddr + MACCtrl0), 902 + ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0)); 903 + 904 + /* Set the timer to check for link beat. */ 905 + timer_setup(&np->timer, netdev_timer, 0); 906 + np->timer.expires = jiffies + 3*HZ; 907 + add_timer(&np->timer); 908 + 909 + /* Enable interrupts by setting the interrupt mask. */ 910 + iowrite16(DEFAULT_INTR, ioaddr + IntrEnable); 911 + 912 + return 0; 913 + } 914 + 915 + static void check_duplex(struct net_device *dev) 916 + { 917 + struct netdev_private *np = netdev_priv(dev); 918 + void __iomem *ioaddr = np->base; 919 + int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA); 920 + int negotiated = mii_lpa & np->mii_if.advertising; 921 + int duplex; 922 + 923 + /* Force media */ 924 + if (!np->an_enable || mii_lpa == 0xffff) { 925 + if (np->mii_if.full_duplex) 926 + iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex, 927 + ioaddr + MACCtrl0); 928 + return; 929 + } 930 + 931 + /* Autonegotiation */ 932 + duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040; 933 + if (np->mii_if.full_duplex != duplex) { 934 + np->mii_if.full_duplex = duplex; 935 + if (netif_msg_link(np)) 936 + printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d " 937 + "negotiated capability %4.4x.\n", dev->name, 938 + duplex ? "full" : "half", np->phys[0], negotiated); 939 + iowrite16(ioread16(ioaddr + MACCtrl0) | (duplex ? 0x20 : 0), ioaddr + MACCtrl0); 940 + } 941 + } 942 + 943 + static void netdev_timer(struct timer_list *t) 944 + { 945 + struct netdev_private *np = timer_container_of(np, t, timer); 946 + struct net_device *dev = np->mii_if.dev; 947 + void __iomem *ioaddr = np->base; 948 + int next_tick = 10*HZ; 949 + 950 + if (netif_msg_timer(np)) { 951 + printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, " 952 + "Tx %x Rx %x.\n", 953 + dev->name, ioread16(ioaddr + IntrEnable), 954 + ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus)); 955 + } 956 + check_duplex(dev); 957 + np->timer.expires = jiffies + next_tick; 958 + add_timer(&np->timer); 959 + } 960 + 961 + static void tx_timeout(struct net_device *dev, unsigned int txqueue) 962 + { 963 + struct netdev_private *np = netdev_priv(dev); 964 + void __iomem *ioaddr = np->base; 965 + unsigned long flag; 966 + 967 + netif_stop_queue(dev); 968 + tasklet_disable_in_atomic(&np->tx_tasklet); 969 + iowrite16(0, ioaddr + IntrEnable); 970 + printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x " 971 + "TxFrameId %2.2x," 972 + " resetting...\n", dev->name, ioread8(ioaddr + TxStatus), 973 + ioread8(ioaddr + TxFrameId)); 974 + 975 + { 976 + int i; 977 + for (i=0; i<TX_RING_SIZE; i++) { 978 + printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i, 979 + (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)), 980 + le32_to_cpu(np->tx_ring[i].next_desc), 981 + le32_to_cpu(np->tx_ring[i].status), 982 + (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff, 983 + le32_to_cpu(np->tx_ring[i].frag.addr), 984 + le32_to_cpu(np->tx_ring[i].frag.length)); 985 + } 986 + printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n", 987 + ioread32(np->base + TxListPtr), 988 + netif_queue_stopped(dev)); 989 + printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n", 990 + np->cur_tx, np->cur_tx % TX_RING_SIZE, 991 + np->dirty_tx, np->dirty_tx % TX_RING_SIZE); 992 + printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx); 993 + printk(KERN_DEBUG "cur_task=%d\n", np->cur_task); 994 + } 995 + spin_lock_irqsave(&np->lock, flag); 996 + 997 + /* Stop and restart the chip's Tx processes . */ 998 + reset_tx(dev); 999 + spin_unlock_irqrestore(&np->lock, flag); 1000 + 1001 + dev->if_port = 0; 1002 + 1003 + netif_trans_update(dev); /* prevent tx timeout */ 1004 + dev->stats.tx_errors++; 1005 + if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { 1006 + netif_wake_queue(dev); 1007 + } 1008 + iowrite16(DEFAULT_INTR, ioaddr + IntrEnable); 1009 + tasklet_enable(&np->tx_tasklet); 1010 + } 1011 + 1012 + 1013 + /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1014 + static void init_ring(struct net_device *dev) 1015 + { 1016 + struct netdev_private *np = netdev_priv(dev); 1017 + int i; 1018 + 1019 + np->cur_rx = np->cur_tx = 0; 1020 + np->dirty_rx = np->dirty_tx = 0; 1021 + np->cur_task = 0; 1022 + 1023 + np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16); 1024 + 1025 + /* Initialize all Rx descriptors. */ 1026 + for (i = 0; i < RX_RING_SIZE; i++) { 1027 + np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma + 1028 + ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring)); 1029 + np->rx_ring[i].status = 0; 1030 + np->rx_ring[i].frag.length = 0; 1031 + np->rx_skbuff[i] = NULL; 1032 + } 1033 + 1034 + /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1035 + for (i = 0; i < RX_RING_SIZE; i++) { 1036 + dma_addr_t addr; 1037 + 1038 + struct sk_buff *skb = 1039 + netdev_alloc_skb(dev, np->rx_buf_sz + 2); 1040 + np->rx_skbuff[i] = skb; 1041 + if (skb == NULL) 1042 + break; 1043 + skb_reserve(skb, 2); /* 16 byte align the IP header. */ 1044 + addr = dma_map_single(&np->pci_dev->dev, skb->data, 1045 + np->rx_buf_sz, DMA_FROM_DEVICE); 1046 + if (dma_mapping_error(&np->pci_dev->dev, addr)) { 1047 + dev_kfree_skb(skb); 1048 + np->rx_skbuff[i] = NULL; 1049 + break; 1050 + } 1051 + np->rx_ring[i].frag.addr = cpu_to_le32(addr); 1052 + np->rx_ring[i].frag.length = cpu_to_le32(np->rx_buf_sz | LastFrag); 1053 + } 1054 + np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); 1055 + 1056 + for (i = 0; i < TX_RING_SIZE; i++) { 1057 + np->tx_skbuff[i] = NULL; 1058 + np->tx_ring[i].status = 0; 1059 + } 1060 + } 1061 + 1062 + static void tx_poll(struct tasklet_struct *t) 1063 + { 1064 + struct netdev_private *np = from_tasklet(np, t, tx_tasklet); 1065 + unsigned head = np->cur_task % TX_RING_SIZE; 1066 + struct netdev_desc *txdesc = 1067 + &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE]; 1068 + 1069 + /* Chain the next pointer */ 1070 + for (; np->cur_tx - np->cur_task > 0; np->cur_task++) { 1071 + int entry = np->cur_task % TX_RING_SIZE; 1072 + txdesc = &np->tx_ring[entry]; 1073 + if (np->last_tx) { 1074 + np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma + 1075 + entry*sizeof(struct netdev_desc)); 1076 + } 1077 + np->last_tx = txdesc; 1078 + } 1079 + /* Indicate the latest descriptor of tx ring */ 1080 + txdesc->status |= cpu_to_le32(DescIntrOnTx); 1081 + 1082 + if (ioread32 (np->base + TxListPtr) == 0) 1083 + iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc), 1084 + np->base + TxListPtr); 1085 + } 1086 + 1087 + static netdev_tx_t 1088 + start_tx (struct sk_buff *skb, struct net_device *dev) 1089 + { 1090 + struct netdev_private *np = netdev_priv(dev); 1091 + struct netdev_desc *txdesc; 1092 + dma_addr_t addr; 1093 + unsigned entry; 1094 + 1095 + /* Calculate the next Tx descriptor entry. */ 1096 + entry = np->cur_tx % TX_RING_SIZE; 1097 + np->tx_skbuff[entry] = skb; 1098 + txdesc = &np->tx_ring[entry]; 1099 + 1100 + addr = dma_map_single(&np->pci_dev->dev, skb->data, skb->len, 1101 + DMA_TO_DEVICE); 1102 + if (dma_mapping_error(&np->pci_dev->dev, addr)) 1103 + goto drop_frame; 1104 + 1105 + txdesc->next_desc = 0; 1106 + txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign); 1107 + txdesc->frag.addr = cpu_to_le32(addr); 1108 + txdesc->frag.length = cpu_to_le32 (skb->len | LastFrag); 1109 + 1110 + /* Increment cur_tx before tasklet_schedule() */ 1111 + np->cur_tx++; 1112 + mb(); 1113 + /* Schedule a tx_poll() task */ 1114 + tasklet_schedule(&np->tx_tasklet); 1115 + 1116 + /* On some architectures: explicitly flush cache lines here. */ 1117 + if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1 && 1118 + !netif_queue_stopped(dev)) { 1119 + /* do nothing */ 1120 + } else { 1121 + netif_stop_queue (dev); 1122 + } 1123 + if (netif_msg_tx_queued(np)) { 1124 + printk (KERN_DEBUG 1125 + "%s: Transmit frame #%d queued in slot %d.\n", 1126 + dev->name, np->cur_tx, entry); 1127 + } 1128 + return NETDEV_TX_OK; 1129 + 1130 + drop_frame: 1131 + dev_kfree_skb_any(skb); 1132 + np->tx_skbuff[entry] = NULL; 1133 + dev->stats.tx_dropped++; 1134 + return NETDEV_TX_OK; 1135 + } 1136 + 1137 + /* Reset hardware tx and free all of tx buffers */ 1138 + static int 1139 + reset_tx (struct net_device *dev) 1140 + { 1141 + struct netdev_private *np = netdev_priv(dev); 1142 + void __iomem *ioaddr = np->base; 1143 + struct sk_buff *skb; 1144 + int i; 1145 + 1146 + /* Reset tx logic, TxListPtr will be cleaned */ 1147 + iowrite16 (TxDisable, ioaddr + MACCtrl1); 1148 + sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16); 1149 + 1150 + /* free all tx skbuff */ 1151 + for (i = 0; i < TX_RING_SIZE; i++) { 1152 + np->tx_ring[i].next_desc = 0; 1153 + 1154 + skb = np->tx_skbuff[i]; 1155 + if (skb) { 1156 + dma_unmap_single(&np->pci_dev->dev, 1157 + le32_to_cpu(np->tx_ring[i].frag.addr), 1158 + skb->len, DMA_TO_DEVICE); 1159 + dev_kfree_skb_any(skb); 1160 + np->tx_skbuff[i] = NULL; 1161 + dev->stats.tx_dropped++; 1162 + } 1163 + } 1164 + np->cur_tx = np->dirty_tx = 0; 1165 + np->cur_task = 0; 1166 + 1167 + np->last_tx = NULL; 1168 + iowrite8(127, ioaddr + TxDMAPollPeriod); 1169 + 1170 + iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); 1171 + return 0; 1172 + } 1173 + 1174 + /* The interrupt handler cleans up after the Tx thread, 1175 + and schedule a Rx thread work */ 1176 + static irqreturn_t intr_handler(int irq, void *dev_instance) 1177 + { 1178 + struct net_device *dev = (struct net_device *)dev_instance; 1179 + struct netdev_private *np = netdev_priv(dev); 1180 + void __iomem *ioaddr = np->base; 1181 + int hw_frame_id; 1182 + int tx_cnt; 1183 + int tx_status; 1184 + int handled = 0; 1185 + int i; 1186 + 1187 + do { 1188 + int intr_status = ioread16(ioaddr + IntrStatus); 1189 + iowrite16(intr_status, ioaddr + IntrStatus); 1190 + 1191 + if (netif_msg_intr(np)) 1192 + printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", 1193 + dev->name, intr_status); 1194 + 1195 + if (!(intr_status & DEFAULT_INTR)) 1196 + break; 1197 + 1198 + handled = 1; 1199 + 1200 + if (intr_status & (IntrRxDMADone)) { 1201 + iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone), 1202 + ioaddr + IntrEnable); 1203 + if (np->budget < 0) 1204 + np->budget = RX_BUDGET; 1205 + tasklet_schedule(&np->rx_tasklet); 1206 + } 1207 + if (intr_status & (IntrTxDone | IntrDrvRqst)) { 1208 + tx_status = ioread16 (ioaddr + TxStatus); 1209 + for (tx_cnt=32; tx_status & 0x80; --tx_cnt) { 1210 + if (netif_msg_tx_done(np)) 1211 + printk 1212 + ("%s: Transmit status is %2.2x.\n", 1213 + dev->name, tx_status); 1214 + if (tx_status & 0x1e) { 1215 + if (netif_msg_tx_err(np)) 1216 + printk("%s: Transmit error status %4.4x.\n", 1217 + dev->name, tx_status); 1218 + dev->stats.tx_errors++; 1219 + if (tx_status & 0x10) 1220 + dev->stats.tx_fifo_errors++; 1221 + if (tx_status & 0x08) 1222 + dev->stats.collisions++; 1223 + if (tx_status & 0x04) 1224 + dev->stats.tx_fifo_errors++; 1225 + if (tx_status & 0x02) 1226 + dev->stats.tx_window_errors++; 1227 + 1228 + /* 1229 + ** This reset has been verified on 1230 + ** DFE-580TX boards ! phdm@macqel.be. 1231 + */ 1232 + if (tx_status & 0x10) { /* TxUnderrun */ 1233 + /* Restart Tx FIFO and transmitter */ 1234 + sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16); 1235 + /* No need to reset the Tx pointer here */ 1236 + } 1237 + /* Restart the Tx. Need to make sure tx enabled */ 1238 + i = 10; 1239 + do { 1240 + iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1); 1241 + if (ioread16(ioaddr + MACCtrl1) & TxEnabled) 1242 + break; 1243 + mdelay(1); 1244 + } while (--i); 1245 + } 1246 + /* Yup, this is a documentation bug. It cost me *hours*. */ 1247 + iowrite16 (0, ioaddr + TxStatus); 1248 + if (tx_cnt < 0) { 1249 + iowrite32(5000, ioaddr + DownCounter); 1250 + break; 1251 + } 1252 + tx_status = ioread16 (ioaddr + TxStatus); 1253 + } 1254 + hw_frame_id = (tx_status >> 8) & 0xff; 1255 + } else { 1256 + hw_frame_id = ioread8(ioaddr + TxFrameId); 1257 + } 1258 + 1259 + if (np->pci_dev->revision >= 0x14) { 1260 + spin_lock(&np->lock); 1261 + for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { 1262 + int entry = np->dirty_tx % TX_RING_SIZE; 1263 + struct sk_buff *skb; 1264 + int sw_frame_id; 1265 + sw_frame_id = (le32_to_cpu( 1266 + np->tx_ring[entry].status) >> 2) & 0xff; 1267 + if (sw_frame_id == hw_frame_id && 1268 + !(le32_to_cpu(np->tx_ring[entry].status) 1269 + & 0x00010000)) 1270 + break; 1271 + if (sw_frame_id == (hw_frame_id + 1) % 1272 + TX_RING_SIZE) 1273 + break; 1274 + skb = np->tx_skbuff[entry]; 1275 + /* Free the original skb. */ 1276 + dma_unmap_single(&np->pci_dev->dev, 1277 + le32_to_cpu(np->tx_ring[entry].frag.addr), 1278 + skb->len, DMA_TO_DEVICE); 1279 + dev_consume_skb_irq(np->tx_skbuff[entry]); 1280 + np->tx_skbuff[entry] = NULL; 1281 + np->tx_ring[entry].frag.addr = 0; 1282 + np->tx_ring[entry].frag.length = 0; 1283 + } 1284 + spin_unlock(&np->lock); 1285 + } else { 1286 + spin_lock(&np->lock); 1287 + for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { 1288 + int entry = np->dirty_tx % TX_RING_SIZE; 1289 + struct sk_buff *skb; 1290 + if (!(le32_to_cpu(np->tx_ring[entry].status) 1291 + & 0x00010000)) 1292 + break; 1293 + skb = np->tx_skbuff[entry]; 1294 + /* Free the original skb. */ 1295 + dma_unmap_single(&np->pci_dev->dev, 1296 + le32_to_cpu(np->tx_ring[entry].frag.addr), 1297 + skb->len, DMA_TO_DEVICE); 1298 + dev_consume_skb_irq(np->tx_skbuff[entry]); 1299 + np->tx_skbuff[entry] = NULL; 1300 + np->tx_ring[entry].frag.addr = 0; 1301 + np->tx_ring[entry].frag.length = 0; 1302 + } 1303 + spin_unlock(&np->lock); 1304 + } 1305 + 1306 + if (netif_queue_stopped(dev) && 1307 + np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { 1308 + /* The ring is no longer full, clear busy flag. */ 1309 + netif_wake_queue (dev); 1310 + } 1311 + /* Abnormal error summary/uncommon events handlers. */ 1312 + if (intr_status & (IntrPCIErr | LinkChange | StatsMax)) 1313 + netdev_error(dev, intr_status); 1314 + } while (0); 1315 + if (netif_msg_intr(np)) 1316 + printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", 1317 + dev->name, ioread16(ioaddr + IntrStatus)); 1318 + return IRQ_RETVAL(handled); 1319 + } 1320 + 1321 + static void rx_poll(struct tasklet_struct *t) 1322 + { 1323 + struct netdev_private *np = from_tasklet(np, t, rx_tasklet); 1324 + struct net_device *dev = np->ndev; 1325 + int entry = np->cur_rx % RX_RING_SIZE; 1326 + int boguscnt = np->budget; 1327 + void __iomem *ioaddr = np->base; 1328 + int received = 0; 1329 + 1330 + /* If EOP is set on the next entry, it's a new packet. Send it up. */ 1331 + while (1) { 1332 + struct netdev_desc *desc = &(np->rx_ring[entry]); 1333 + u32 frame_status = le32_to_cpu(desc->status); 1334 + int pkt_len; 1335 + 1336 + if (--boguscnt < 0) { 1337 + goto not_done; 1338 + } 1339 + if (!(frame_status & DescOwn)) 1340 + break; 1341 + pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */ 1342 + if (netif_msg_rx_status(np)) 1343 + printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", 1344 + frame_status); 1345 + if (frame_status & 0x001f4000) { 1346 + /* There was a error. */ 1347 + if (netif_msg_rx_err(np)) 1348 + printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n", 1349 + frame_status); 1350 + dev->stats.rx_errors++; 1351 + if (frame_status & 0x00100000) 1352 + dev->stats.rx_length_errors++; 1353 + if (frame_status & 0x00010000) 1354 + dev->stats.rx_fifo_errors++; 1355 + if (frame_status & 0x00060000) 1356 + dev->stats.rx_frame_errors++; 1357 + if (frame_status & 0x00080000) 1358 + dev->stats.rx_crc_errors++; 1359 + if (frame_status & 0x00100000) { 1360 + printk(KERN_WARNING "%s: Oversized Ethernet frame," 1361 + " status %8.8x.\n", 1362 + dev->name, frame_status); 1363 + } 1364 + } else { 1365 + struct sk_buff *skb; 1366 + #ifndef final_version 1367 + if (netif_msg_rx_status(np)) 1368 + printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d" 1369 + ", bogus_cnt %d.\n", 1370 + pkt_len, boguscnt); 1371 + #endif 1372 + /* Check if the packet is long enough to accept without copying 1373 + to a minimally-sized skbuff. */ 1374 + if (pkt_len < rx_copybreak && 1375 + (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { 1376 + skb_reserve(skb, 2); /* 16 byte align the IP header */ 1377 + dma_sync_single_for_cpu(&np->pci_dev->dev, 1378 + le32_to_cpu(desc->frag.addr), 1379 + np->rx_buf_sz, DMA_FROM_DEVICE); 1380 + skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len); 1381 + dma_sync_single_for_device(&np->pci_dev->dev, 1382 + le32_to_cpu(desc->frag.addr), 1383 + np->rx_buf_sz, DMA_FROM_DEVICE); 1384 + skb_put(skb, pkt_len); 1385 + } else { 1386 + dma_unmap_single(&np->pci_dev->dev, 1387 + le32_to_cpu(desc->frag.addr), 1388 + np->rx_buf_sz, DMA_FROM_DEVICE); 1389 + skb_put(skb = np->rx_skbuff[entry], pkt_len); 1390 + np->rx_skbuff[entry] = NULL; 1391 + } 1392 + skb->protocol = eth_type_trans(skb, dev); 1393 + /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */ 1394 + netif_rx(skb); 1395 + } 1396 + entry = (entry + 1) % RX_RING_SIZE; 1397 + received++; 1398 + } 1399 + np->cur_rx = entry; 1400 + refill_rx (dev); 1401 + np->budget -= received; 1402 + iowrite16(DEFAULT_INTR, ioaddr + IntrEnable); 1403 + return; 1404 + 1405 + not_done: 1406 + np->cur_rx = entry; 1407 + refill_rx (dev); 1408 + if (!received) 1409 + received = 1; 1410 + np->budget -= received; 1411 + if (np->budget <= 0) 1412 + np->budget = RX_BUDGET; 1413 + tasklet_schedule(&np->rx_tasklet); 1414 + } 1415 + 1416 + static void refill_rx (struct net_device *dev) 1417 + { 1418 + struct netdev_private *np = netdev_priv(dev); 1419 + int entry; 1420 + 1421 + /* Refill the Rx ring buffers. */ 1422 + for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0; 1423 + np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) { 1424 + struct sk_buff *skb; 1425 + dma_addr_t addr; 1426 + 1427 + entry = np->dirty_rx % RX_RING_SIZE; 1428 + if (np->rx_skbuff[entry] == NULL) { 1429 + skb = netdev_alloc_skb(dev, np->rx_buf_sz + 2); 1430 + np->rx_skbuff[entry] = skb; 1431 + if (skb == NULL) 1432 + break; /* Better luck next round. */ 1433 + skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ 1434 + addr = dma_map_single(&np->pci_dev->dev, skb->data, 1435 + np->rx_buf_sz, DMA_FROM_DEVICE); 1436 + if (dma_mapping_error(&np->pci_dev->dev, addr)) { 1437 + dev_kfree_skb_irq(skb); 1438 + np->rx_skbuff[entry] = NULL; 1439 + break; 1440 + } 1441 + 1442 + np->rx_ring[entry].frag.addr = cpu_to_le32(addr); 1443 + } 1444 + /* Perhaps we need not reset this field. */ 1445 + np->rx_ring[entry].frag.length = 1446 + cpu_to_le32(np->rx_buf_sz | LastFrag); 1447 + np->rx_ring[entry].status = 0; 1448 + } 1449 + } 1450 + static void netdev_error(struct net_device *dev, int intr_status) 1451 + { 1452 + struct netdev_private *np = netdev_priv(dev); 1453 + void __iomem *ioaddr = np->base; 1454 + u16 mii_ctl, mii_advertise, mii_lpa; 1455 + int speed; 1456 + 1457 + if (intr_status & LinkChange) { 1458 + if (mdio_wait_link(dev, 10) == 0) { 1459 + printk(KERN_INFO "%s: Link up\n", dev->name); 1460 + if (np->an_enable) { 1461 + mii_advertise = mdio_read(dev, np->phys[0], 1462 + MII_ADVERTISE); 1463 + mii_lpa = mdio_read(dev, np->phys[0], MII_LPA); 1464 + mii_advertise &= mii_lpa; 1465 + printk(KERN_INFO "%s: Link changed: ", 1466 + dev->name); 1467 + if (mii_advertise & ADVERTISE_100FULL) { 1468 + np->speed = 100; 1469 + printk("100Mbps, full duplex\n"); 1470 + } else if (mii_advertise & ADVERTISE_100HALF) { 1471 + np->speed = 100; 1472 + printk("100Mbps, half duplex\n"); 1473 + } else if (mii_advertise & ADVERTISE_10FULL) { 1474 + np->speed = 10; 1475 + printk("10Mbps, full duplex\n"); 1476 + } else if (mii_advertise & ADVERTISE_10HALF) { 1477 + np->speed = 10; 1478 + printk("10Mbps, half duplex\n"); 1479 + } else 1480 + printk("\n"); 1481 + 1482 + } else { 1483 + mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR); 1484 + speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10; 1485 + np->speed = speed; 1486 + printk(KERN_INFO "%s: Link changed: %dMbps ,", 1487 + dev->name, speed); 1488 + printk("%s duplex.\n", 1489 + (mii_ctl & BMCR_FULLDPLX) ? 1490 + "full" : "half"); 1491 + } 1492 + check_duplex(dev); 1493 + if (np->flowctrl && np->mii_if.full_duplex) { 1494 + iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200, 1495 + ioaddr + MulticastFilter1+2); 1496 + iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl, 1497 + ioaddr + MACCtrl0); 1498 + } 1499 + netif_carrier_on(dev); 1500 + } else { 1501 + printk(KERN_INFO "%s: Link down\n", dev->name); 1502 + netif_carrier_off(dev); 1503 + } 1504 + } 1505 + if (intr_status & StatsMax) { 1506 + get_stats(dev); 1507 + } 1508 + if (intr_status & IntrPCIErr) { 1509 + printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n", 1510 + dev->name, intr_status); 1511 + /* We must do a global reset of DMA to continue. */ 1512 + } 1513 + } 1514 + 1515 + static struct net_device_stats *get_stats(struct net_device *dev) 1516 + { 1517 + struct netdev_private *np = netdev_priv(dev); 1518 + void __iomem *ioaddr = np->base; 1519 + unsigned long flags; 1520 + u8 late_coll, single_coll, mult_coll; 1521 + 1522 + spin_lock_irqsave(&np->statlock, flags); 1523 + /* The chip only need report frame silently dropped. */ 1524 + dev->stats.rx_missed_errors += ioread8(ioaddr + RxMissed); 1525 + dev->stats.tx_packets += ioread16(ioaddr + TxFramesOK); 1526 + dev->stats.rx_packets += ioread16(ioaddr + RxFramesOK); 1527 + dev->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError); 1528 + 1529 + mult_coll = ioread8(ioaddr + StatsMultiColl); 1530 + np->xstats.tx_multiple_collisions += mult_coll; 1531 + single_coll = ioread8(ioaddr + StatsOneColl); 1532 + np->xstats.tx_single_collisions += single_coll; 1533 + late_coll = ioread8(ioaddr + StatsLateColl); 1534 + np->xstats.tx_late_collisions += late_coll; 1535 + dev->stats.collisions += mult_coll 1536 + + single_coll 1537 + + late_coll; 1538 + 1539 + np->xstats.tx_deferred += ioread8(ioaddr + StatsTxDefer); 1540 + np->xstats.tx_deferred_excessive += ioread8(ioaddr + StatsTxXSDefer); 1541 + np->xstats.tx_aborted += ioread8(ioaddr + StatsTxAbort); 1542 + np->xstats.tx_bcasts += ioread8(ioaddr + StatsBcastTx); 1543 + np->xstats.rx_bcasts += ioread8(ioaddr + StatsBcastRx); 1544 + np->xstats.tx_mcasts += ioread8(ioaddr + StatsMcastTx); 1545 + np->xstats.rx_mcasts += ioread8(ioaddr + StatsMcastRx); 1546 + 1547 + dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow); 1548 + dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16; 1549 + dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow); 1550 + dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16; 1551 + 1552 + spin_unlock_irqrestore(&np->statlock, flags); 1553 + 1554 + return &dev->stats; 1555 + } 1556 + 1557 + static void set_rx_mode(struct net_device *dev) 1558 + { 1559 + struct netdev_private *np = netdev_priv(dev); 1560 + void __iomem *ioaddr = np->base; 1561 + u16 mc_filter[4]; /* Multicast hash filter */ 1562 + u32 rx_mode; 1563 + int i; 1564 + 1565 + if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1566 + memset(mc_filter, 0xff, sizeof(mc_filter)); 1567 + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys; 1568 + } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 1569 + (dev->flags & IFF_ALLMULTI)) { 1570 + /* Too many to match, or accept all multicasts. */ 1571 + memset(mc_filter, 0xff, sizeof(mc_filter)); 1572 + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 1573 + } else if (!netdev_mc_empty(dev)) { 1574 + struct netdev_hw_addr *ha; 1575 + int bit; 1576 + int index; 1577 + int crc; 1578 + memset (mc_filter, 0, sizeof (mc_filter)); 1579 + netdev_for_each_mc_addr(ha, dev) { 1580 + crc = ether_crc_le(ETH_ALEN, ha->addr); 1581 + for (index=0, bit=0; bit < 6; bit++, crc <<= 1) 1582 + if (crc & 0x80000000) index |= 1 << bit; 1583 + mc_filter[index/16] |= (1 << (index % 16)); 1584 + } 1585 + rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys; 1586 + } else { 1587 + iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode); 1588 + return; 1589 + } 1590 + if (np->mii_if.full_duplex && np->flowctrl) 1591 + mc_filter[3] |= 0x0200; 1592 + 1593 + for (i = 0; i < 4; i++) 1594 + iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2); 1595 + iowrite8(rx_mode, ioaddr + RxMode); 1596 + } 1597 + 1598 + static int __set_mac_addr(struct net_device *dev) 1599 + { 1600 + struct netdev_private *np = netdev_priv(dev); 1601 + u16 addr16; 1602 + 1603 + addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8)); 1604 + iowrite16(addr16, np->base + StationAddr); 1605 + addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8)); 1606 + iowrite16(addr16, np->base + StationAddr+2); 1607 + addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8)); 1608 + iowrite16(addr16, np->base + StationAddr+4); 1609 + return 0; 1610 + } 1611 + 1612 + /* Invoked with rtnl_lock held */ 1613 + static int sundance_set_mac_addr(struct net_device *dev, void *data) 1614 + { 1615 + const struct sockaddr *addr = data; 1616 + 1617 + if (!is_valid_ether_addr(addr->sa_data)) 1618 + return -EADDRNOTAVAIL; 1619 + eth_hw_addr_set(dev, addr->sa_data); 1620 + __set_mac_addr(dev); 1621 + 1622 + return 0; 1623 + } 1624 + 1625 + static const struct { 1626 + const char name[ETH_GSTRING_LEN]; 1627 + } sundance_stats[] = { 1628 + { "tx_multiple_collisions" }, 1629 + { "tx_single_collisions" }, 1630 + { "tx_late_collisions" }, 1631 + { "tx_deferred" }, 1632 + { "tx_deferred_excessive" }, 1633 + { "tx_aborted" }, 1634 + { "tx_bcasts" }, 1635 + { "rx_bcasts" }, 1636 + { "tx_mcasts" }, 1637 + { "rx_mcasts" }, 1638 + }; 1639 + 1640 + static int check_if_running(struct net_device *dev) 1641 + { 1642 + if (!netif_running(dev)) 1643 + return -EINVAL; 1644 + return 0; 1645 + } 1646 + 1647 + static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1648 + { 1649 + struct netdev_private *np = netdev_priv(dev); 1650 + strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 1651 + strscpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); 1652 + } 1653 + 1654 + static int get_link_ksettings(struct net_device *dev, 1655 + struct ethtool_link_ksettings *cmd) 1656 + { 1657 + struct netdev_private *np = netdev_priv(dev); 1658 + spin_lock_irq(&np->lock); 1659 + mii_ethtool_get_link_ksettings(&np->mii_if, cmd); 1660 + spin_unlock_irq(&np->lock); 1661 + return 0; 1662 + } 1663 + 1664 + static int set_link_ksettings(struct net_device *dev, 1665 + const struct ethtool_link_ksettings *cmd) 1666 + { 1667 + struct netdev_private *np = netdev_priv(dev); 1668 + int res; 1669 + spin_lock_irq(&np->lock); 1670 + res = mii_ethtool_set_link_ksettings(&np->mii_if, cmd); 1671 + spin_unlock_irq(&np->lock); 1672 + return res; 1673 + } 1674 + 1675 + static int nway_reset(struct net_device *dev) 1676 + { 1677 + struct netdev_private *np = netdev_priv(dev); 1678 + return mii_nway_restart(&np->mii_if); 1679 + } 1680 + 1681 + static u32 get_link(struct net_device *dev) 1682 + { 1683 + struct netdev_private *np = netdev_priv(dev); 1684 + return mii_link_ok(&np->mii_if); 1685 + } 1686 + 1687 + static u32 get_msglevel(struct net_device *dev) 1688 + { 1689 + struct netdev_private *np = netdev_priv(dev); 1690 + return np->msg_enable; 1691 + } 1692 + 1693 + static void set_msglevel(struct net_device *dev, u32 val) 1694 + { 1695 + struct netdev_private *np = netdev_priv(dev); 1696 + np->msg_enable = val; 1697 + } 1698 + 1699 + static void get_strings(struct net_device *dev, u32 stringset, 1700 + u8 *data) 1701 + { 1702 + if (stringset == ETH_SS_STATS) 1703 + memcpy(data, sundance_stats, sizeof(sundance_stats)); 1704 + } 1705 + 1706 + static int get_sset_count(struct net_device *dev, int sset) 1707 + { 1708 + switch (sset) { 1709 + case ETH_SS_STATS: 1710 + return ARRAY_SIZE(sundance_stats); 1711 + default: 1712 + return -EOPNOTSUPP; 1713 + } 1714 + } 1715 + 1716 + static void get_ethtool_stats(struct net_device *dev, 1717 + struct ethtool_stats *stats, u64 *data) 1718 + { 1719 + struct netdev_private *np = netdev_priv(dev); 1720 + int i = 0; 1721 + 1722 + get_stats(dev); 1723 + data[i++] = np->xstats.tx_multiple_collisions; 1724 + data[i++] = np->xstats.tx_single_collisions; 1725 + data[i++] = np->xstats.tx_late_collisions; 1726 + data[i++] = np->xstats.tx_deferred; 1727 + data[i++] = np->xstats.tx_deferred_excessive; 1728 + data[i++] = np->xstats.tx_aborted; 1729 + data[i++] = np->xstats.tx_bcasts; 1730 + data[i++] = np->xstats.rx_bcasts; 1731 + data[i++] = np->xstats.tx_mcasts; 1732 + data[i++] = np->xstats.rx_mcasts; 1733 + } 1734 + 1735 + #ifdef CONFIG_PM 1736 + 1737 + static void sundance_get_wol(struct net_device *dev, 1738 + struct ethtool_wolinfo *wol) 1739 + { 1740 + struct netdev_private *np = netdev_priv(dev); 1741 + void __iomem *ioaddr = np->base; 1742 + u8 wol_bits; 1743 + 1744 + wol->wolopts = 0; 1745 + 1746 + wol->supported = (WAKE_PHY | WAKE_MAGIC); 1747 + if (!np->wol_enabled) 1748 + return; 1749 + 1750 + wol_bits = ioread8(ioaddr + WakeEvent); 1751 + if (wol_bits & MagicPktEnable) 1752 + wol->wolopts |= WAKE_MAGIC; 1753 + if (wol_bits & LinkEventEnable) 1754 + wol->wolopts |= WAKE_PHY; 1755 + } 1756 + 1757 + static int sundance_set_wol(struct net_device *dev, 1758 + struct ethtool_wolinfo *wol) 1759 + { 1760 + struct netdev_private *np = netdev_priv(dev); 1761 + void __iomem *ioaddr = np->base; 1762 + u8 wol_bits; 1763 + 1764 + if (!device_can_wakeup(&np->pci_dev->dev)) 1765 + return -EOPNOTSUPP; 1766 + 1767 + np->wol_enabled = !!(wol->wolopts); 1768 + wol_bits = ioread8(ioaddr + WakeEvent); 1769 + wol_bits &= ~(WakePktEnable | MagicPktEnable | 1770 + LinkEventEnable | WolEnable); 1771 + 1772 + if (np->wol_enabled) { 1773 + if (wol->wolopts & WAKE_MAGIC) 1774 + wol_bits |= (MagicPktEnable | WolEnable); 1775 + if (wol->wolopts & WAKE_PHY) 1776 + wol_bits |= (LinkEventEnable | WolEnable); 1777 + } 1778 + iowrite8(wol_bits, ioaddr + WakeEvent); 1779 + 1780 + device_set_wakeup_enable(&np->pci_dev->dev, np->wol_enabled); 1781 + 1782 + return 0; 1783 + } 1784 + #else 1785 + #define sundance_get_wol NULL 1786 + #define sundance_set_wol NULL 1787 + #endif /* CONFIG_PM */ 1788 + 1789 + static const struct ethtool_ops ethtool_ops = { 1790 + .begin = check_if_running, 1791 + .get_drvinfo = get_drvinfo, 1792 + .nway_reset = nway_reset, 1793 + .get_link = get_link, 1794 + .get_wol = sundance_get_wol, 1795 + .set_wol = sundance_set_wol, 1796 + .get_msglevel = get_msglevel, 1797 + .set_msglevel = set_msglevel, 1798 + .get_strings = get_strings, 1799 + .get_sset_count = get_sset_count, 1800 + .get_ethtool_stats = get_ethtool_stats, 1801 + .get_link_ksettings = get_link_ksettings, 1802 + .set_link_ksettings = set_link_ksettings, 1803 + }; 1804 + 1805 + static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1806 + { 1807 + struct netdev_private *np = netdev_priv(dev); 1808 + int rc; 1809 + 1810 + if (!netif_running(dev)) 1811 + return -EINVAL; 1812 + 1813 + spin_lock_irq(&np->lock); 1814 + rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL); 1815 + spin_unlock_irq(&np->lock); 1816 + 1817 + return rc; 1818 + } 1819 + 1820 + static int netdev_close(struct net_device *dev) 1821 + { 1822 + struct netdev_private *np = netdev_priv(dev); 1823 + void __iomem *ioaddr = np->base; 1824 + struct sk_buff *skb; 1825 + int i; 1826 + 1827 + /* Wait and kill tasklet */ 1828 + tasklet_kill(&np->rx_tasklet); 1829 + tasklet_kill(&np->tx_tasklet); 1830 + np->cur_tx = 0; 1831 + np->dirty_tx = 0; 1832 + np->cur_task = 0; 1833 + np->last_tx = NULL; 1834 + 1835 + netif_stop_queue(dev); 1836 + 1837 + if (netif_msg_ifdown(np)) { 1838 + printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x " 1839 + "Rx %4.4x Int %2.2x.\n", 1840 + dev->name, ioread8(ioaddr + TxStatus), 1841 + ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus)); 1842 + printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", 1843 + dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx); 1844 + } 1845 + 1846 + /* Disable interrupts by clearing the interrupt mask. */ 1847 + iowrite16(0x0000, ioaddr + IntrEnable); 1848 + 1849 + /* Disable Rx and Tx DMA for safely release resource */ 1850 + iowrite32(0x500, ioaddr + DMACtrl); 1851 + 1852 + /* Stop the chip's Tx and Rx processes. */ 1853 + iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1); 1854 + 1855 + for (i = 2000; i > 0; i--) { 1856 + if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0) 1857 + break; 1858 + mdelay(1); 1859 + } 1860 + 1861 + iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset, 1862 + ioaddr + ASIC_HI_WORD(ASICCtrl)); 1863 + 1864 + for (i = 2000; i > 0; i--) { 1865 + if ((ioread16(ioaddr + ASIC_HI_WORD(ASICCtrl)) & ResetBusy) == 0) 1866 + break; 1867 + mdelay(1); 1868 + } 1869 + 1870 + #ifdef __i386__ 1871 + if (netif_msg_hw(np)) { 1872 + printk(KERN_DEBUG " Tx ring at %8.8x:\n", 1873 + (int)(np->tx_ring_dma)); 1874 + for (i = 0; i < TX_RING_SIZE; i++) 1875 + printk(KERN_DEBUG " #%d desc. %4.4x %8.8x %8.8x.\n", 1876 + i, np->tx_ring[i].status, np->tx_ring[i].frag.addr, 1877 + np->tx_ring[i].frag.length); 1878 + printk(KERN_DEBUG " Rx ring %8.8x:\n", 1879 + (int)(np->rx_ring_dma)); 1880 + for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) { 1881 + printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n", 1882 + i, np->rx_ring[i].status, np->rx_ring[i].frag.addr, 1883 + np->rx_ring[i].frag.length); 1884 + } 1885 + } 1886 + #endif /* __i386__ debugging only */ 1887 + 1888 + free_irq(np->pci_dev->irq, dev); 1889 + 1890 + timer_delete_sync(&np->timer); 1891 + 1892 + /* Free all the skbuffs in the Rx queue. */ 1893 + for (i = 0; i < RX_RING_SIZE; i++) { 1894 + np->rx_ring[i].status = 0; 1895 + skb = np->rx_skbuff[i]; 1896 + if (skb) { 1897 + dma_unmap_single(&np->pci_dev->dev, 1898 + le32_to_cpu(np->rx_ring[i].frag.addr), 1899 + np->rx_buf_sz, DMA_FROM_DEVICE); 1900 + dev_kfree_skb(skb); 1901 + np->rx_skbuff[i] = NULL; 1902 + } 1903 + np->rx_ring[i].frag.addr = cpu_to_le32(0xBADF00D0); /* poison */ 1904 + } 1905 + for (i = 0; i < TX_RING_SIZE; i++) { 1906 + np->tx_ring[i].next_desc = 0; 1907 + skb = np->tx_skbuff[i]; 1908 + if (skb) { 1909 + dma_unmap_single(&np->pci_dev->dev, 1910 + le32_to_cpu(np->tx_ring[i].frag.addr), 1911 + skb->len, DMA_TO_DEVICE); 1912 + dev_kfree_skb(skb); 1913 + np->tx_skbuff[i] = NULL; 1914 + } 1915 + } 1916 + 1917 + return 0; 1918 + } 1919 + 1920 + static void sundance_remove1(struct pci_dev *pdev) 1921 + { 1922 + struct net_device *dev = pci_get_drvdata(pdev); 1923 + 1924 + if (dev) { 1925 + struct netdev_private *np = netdev_priv(dev); 1926 + unregister_netdev(dev); 1927 + dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, 1928 + np->rx_ring, np->rx_ring_dma); 1929 + dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, 1930 + np->tx_ring, np->tx_ring_dma); 1931 + pci_iounmap(pdev, np->base); 1932 + pci_release_regions(pdev); 1933 + free_netdev(dev); 1934 + } 1935 + } 1936 + 1937 + static int __maybe_unused sundance_suspend(struct device *dev_d) 1938 + { 1939 + struct net_device *dev = dev_get_drvdata(dev_d); 1940 + struct netdev_private *np = netdev_priv(dev); 1941 + void __iomem *ioaddr = np->base; 1942 + 1943 + if (!netif_running(dev)) 1944 + return 0; 1945 + 1946 + netdev_close(dev); 1947 + netif_device_detach(dev); 1948 + 1949 + if (np->wol_enabled) { 1950 + iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode); 1951 + iowrite16(RxEnable, ioaddr + MACCtrl1); 1952 + } 1953 + 1954 + device_set_wakeup_enable(dev_d, np->wol_enabled); 1955 + 1956 + return 0; 1957 + } 1958 + 1959 + static int __maybe_unused sundance_resume(struct device *dev_d) 1960 + { 1961 + struct net_device *dev = dev_get_drvdata(dev_d); 1962 + int err = 0; 1963 + 1964 + if (!netif_running(dev)) 1965 + return 0; 1966 + 1967 + err = netdev_open(dev); 1968 + if (err) { 1969 + printk(KERN_ERR "%s: Can't resume interface!\n", 1970 + dev->name); 1971 + goto out; 1972 + } 1973 + 1974 + netif_device_attach(dev); 1975 + 1976 + out: 1977 + return err; 1978 + } 1979 + 1980 + static SIMPLE_DEV_PM_OPS(sundance_pm_ops, sundance_suspend, sundance_resume); 1981 + 1982 + static struct pci_driver sundance_driver = { 1983 + .name = DRV_NAME, 1984 + .id_table = sundance_pci_tbl, 1985 + .probe = sundance_probe1, 1986 + .remove = sundance_remove1, 1987 + .driver.pm = &sundance_pm_ops, 1988 + }; 1989 + 1990 + module_pci_driver(sundance_driver);
+7 -3
drivers/net/ethernet/intel/e1000e/ethtool.c
··· 549 549 { 550 550 struct e1000_adapter *adapter = netdev_priv(netdev); 551 551 struct e1000_hw *hw = &adapter->hw; 552 + size_t total_len, max_len; 552 553 u16 *eeprom_buff; 553 - void *ptr; 554 - int max_len; 554 + int ret_val = 0; 555 555 int first_word; 556 556 int last_word; 557 - int ret_val = 0; 557 + void *ptr; 558 558 u16 i; 559 559 560 560 if (eeprom->len == 0) ··· 568 568 return -EINVAL; 569 569 570 570 max_len = hw->nvm.word_size * 2; 571 + 572 + if (check_add_overflow(eeprom->offset, eeprom->len, &total_len) || 573 + total_len > max_len) 574 + return -EFBIG; 571 575 572 576 first_word = eeprom->offset >> 1; 573 577 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
+2 -2
drivers/net/ethernet/intel/i40e/i40e_client.c
··· 359 359 if (i40e_client_get_params(vsi, &cdev->lan_info.params)) 360 360 goto free_cdev; 361 361 362 - mac = list_first_entry(&cdev->lan_info.netdev->dev_addrs.list, 363 - struct netdev_hw_addr, list); 362 + mac = list_first_entry_or_null(&cdev->lan_info.netdev->dev_addrs.list, 363 + struct netdev_hw_addr, list); 364 364 if (mac) 365 365 ether_addr_copy(cdev->lan_info.lanmac, mac->addr); 366 366 else
+19 -104
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
··· 40 40 * setup, adding or removing filters, or other things. Many of 41 41 * these will be useful for some forms of unit testing. 42 42 **************************************************************/ 43 - static char i40e_dbg_command_buf[256] = ""; 44 - 45 - /** 46 - * i40e_dbg_command_read - read for command datum 47 - * @filp: the opened file 48 - * @buffer: where to write the data for the user to read 49 - * @count: the size of the user's buffer 50 - * @ppos: file position offset 51 - **/ 52 - static ssize_t i40e_dbg_command_read(struct file *filp, char __user *buffer, 53 - size_t count, loff_t *ppos) 54 - { 55 - struct i40e_pf *pf = filp->private_data; 56 - struct i40e_vsi *main_vsi; 57 - int bytes_not_copied; 58 - int buf_size = 256; 59 - char *buf; 60 - int len; 61 - 62 - /* don't allow partial reads */ 63 - if (*ppos != 0) 64 - return 0; 65 - if (count < buf_size) 66 - return -ENOSPC; 67 - 68 - buf = kzalloc(buf_size, GFP_KERNEL); 69 - if (!buf) 70 - return -ENOSPC; 71 - 72 - main_vsi = i40e_pf_get_main_vsi(pf); 73 - len = snprintf(buf, buf_size, "%s: %s\n", main_vsi->netdev->name, 74 - i40e_dbg_command_buf); 75 - 76 - bytes_not_copied = copy_to_user(buffer, buf, len); 77 - kfree(buf); 78 - 79 - if (bytes_not_copied) 80 - return -EFAULT; 81 - 82 - *ppos = len; 83 - return len; 84 - } 85 43 86 44 static char *i40e_filter_state_string[] = { 87 45 "INVALID", ··· 1579 1621 static const struct file_operations i40e_dbg_command_fops = { 1580 1622 .owner = THIS_MODULE, 1581 1623 .open = simple_open, 1582 - .read = i40e_dbg_command_read, 1583 1624 .write = i40e_dbg_command_write, 1584 1625 }; 1585 1626 ··· 1587 1630 * The netdev_ops entry in debugfs is for giving the driver commands 1588 1631 * to be executed from the netdev operations. 1589 1632 **************************************************************/ 1590 - static char i40e_dbg_netdev_ops_buf[256] = ""; 1591 - 1592 - /** 1593 - * i40e_dbg_netdev_ops_read - read for netdev_ops datum 1594 - * @filp: the opened file 1595 - * @buffer: where to write the data for the user to read 1596 - * @count: the size of the user's buffer 1597 - * @ppos: file position offset 1598 - **/ 1599 - static ssize_t i40e_dbg_netdev_ops_read(struct file *filp, char __user *buffer, 1600 - size_t count, loff_t *ppos) 1601 - { 1602 - struct i40e_pf *pf = filp->private_data; 1603 - struct i40e_vsi *main_vsi; 1604 - int bytes_not_copied; 1605 - int buf_size = 256; 1606 - char *buf; 1607 - int len; 1608 - 1609 - /* don't allow partal reads */ 1610 - if (*ppos != 0) 1611 - return 0; 1612 - if (count < buf_size) 1613 - return -ENOSPC; 1614 - 1615 - buf = kzalloc(buf_size, GFP_KERNEL); 1616 - if (!buf) 1617 - return -ENOSPC; 1618 - 1619 - main_vsi = i40e_pf_get_main_vsi(pf); 1620 - len = snprintf(buf, buf_size, "%s: %s\n", main_vsi->netdev->name, 1621 - i40e_dbg_netdev_ops_buf); 1622 - 1623 - bytes_not_copied = copy_to_user(buffer, buf, len); 1624 - kfree(buf); 1625 - 1626 - if (bytes_not_copied) 1627 - return -EFAULT; 1628 - 1629 - *ppos = len; 1630 - return len; 1631 - } 1632 1633 1633 1634 /** 1634 1635 * i40e_dbg_netdev_ops_write - write into netdev_ops datum ··· 1600 1685 size_t count, loff_t *ppos) 1601 1686 { 1602 1687 struct i40e_pf *pf = filp->private_data; 1688 + char *cmd_buf, *buf_tmp; 1603 1689 int bytes_not_copied; 1604 1690 struct i40e_vsi *vsi; 1605 - char *buf_tmp; 1606 1691 int vsi_seid; 1607 1692 int i, cnt; 1608 1693 1609 1694 /* don't allow partial writes */ 1610 1695 if (*ppos != 0) 1611 1696 return 0; 1612 - if (count >= sizeof(i40e_dbg_netdev_ops_buf)) 1613 - return -ENOSPC; 1614 1697 1615 - memset(i40e_dbg_netdev_ops_buf, 0, sizeof(i40e_dbg_netdev_ops_buf)); 1616 - bytes_not_copied = copy_from_user(i40e_dbg_netdev_ops_buf, 1617 - buffer, count); 1618 - if (bytes_not_copied) 1698 + cmd_buf = kzalloc(count + 1, GFP_KERNEL); 1699 + if (!cmd_buf) 1700 + return count; 1701 + bytes_not_copied = copy_from_user(cmd_buf, buffer, count); 1702 + if (bytes_not_copied) { 1703 + kfree(cmd_buf); 1619 1704 return -EFAULT; 1620 - i40e_dbg_netdev_ops_buf[count] = '\0'; 1705 + } 1706 + cmd_buf[count] = '\0'; 1621 1707 1622 - buf_tmp = strchr(i40e_dbg_netdev_ops_buf, '\n'); 1708 + buf_tmp = strchr(cmd_buf, '\n'); 1623 1709 if (buf_tmp) { 1624 1710 *buf_tmp = '\0'; 1625 - count = buf_tmp - i40e_dbg_netdev_ops_buf + 1; 1711 + count = buf_tmp - cmd_buf + 1; 1626 1712 } 1627 1713 1628 - if (strncmp(i40e_dbg_netdev_ops_buf, "change_mtu", 10) == 0) { 1714 + if (strncmp(cmd_buf, "change_mtu", 10) == 0) { 1629 1715 int mtu; 1630 1716 1631 - cnt = sscanf(&i40e_dbg_netdev_ops_buf[11], "%i %i", 1717 + cnt = sscanf(&cmd_buf[11], "%i %i", 1632 1718 &vsi_seid, &mtu); 1633 1719 if (cnt != 2) { 1634 1720 dev_info(&pf->pdev->dev, "change_mtu <vsi_seid> <mtu>\n"); ··· 1651 1735 dev_info(&pf->pdev->dev, "Could not acquire RTNL - please try again\n"); 1652 1736 } 1653 1737 1654 - } else if (strncmp(i40e_dbg_netdev_ops_buf, "set_rx_mode", 11) == 0) { 1655 - cnt = sscanf(&i40e_dbg_netdev_ops_buf[11], "%i", &vsi_seid); 1738 + } else if (strncmp(cmd_buf, "set_rx_mode", 11) == 0) { 1739 + cnt = sscanf(&cmd_buf[11], "%i", &vsi_seid); 1656 1740 if (cnt != 1) { 1657 1741 dev_info(&pf->pdev->dev, "set_rx_mode <vsi_seid>\n"); 1658 1742 goto netdev_ops_write_done; ··· 1672 1756 dev_info(&pf->pdev->dev, "Could not acquire RTNL - please try again\n"); 1673 1757 } 1674 1758 1675 - } else if (strncmp(i40e_dbg_netdev_ops_buf, "napi", 4) == 0) { 1676 - cnt = sscanf(&i40e_dbg_netdev_ops_buf[4], "%i", &vsi_seid); 1759 + } else if (strncmp(cmd_buf, "napi", 4) == 0) { 1760 + cnt = sscanf(&cmd_buf[4], "%i", &vsi_seid); 1677 1761 if (cnt != 1) { 1678 1762 dev_info(&pf->pdev->dev, "napi <vsi_seid>\n"); 1679 1763 goto netdev_ops_write_done; ··· 1691 1775 dev_info(&pf->pdev->dev, "napi called\n"); 1692 1776 } 1693 1777 } else { 1694 - dev_info(&pf->pdev->dev, "unknown command '%s'\n", 1695 - i40e_dbg_netdev_ops_buf); 1778 + dev_info(&pf->pdev->dev, "unknown command '%s'\n", cmd_buf); 1696 1779 dev_info(&pf->pdev->dev, "available commands\n"); 1697 1780 dev_info(&pf->pdev->dev, " change_mtu <vsi_seid> <mtu>\n"); 1698 1781 dev_info(&pf->pdev->dev, " set_rx_mode <vsi_seid>\n"); 1699 1782 dev_info(&pf->pdev->dev, " napi <vsi_seid>\n"); 1700 1783 } 1701 1784 netdev_ops_write_done: 1785 + kfree(cmd_buf); 1702 1786 return count; 1703 1787 } 1704 1788 1705 1789 static const struct file_operations i40e_dbg_netdev_ops_fops = { 1706 1790 .owner = THIS_MODULE, 1707 1791 .open = simple_open, 1708 - .read = i40e_dbg_netdev_ops_read, 1709 1792 .write = i40e_dbg_netdev_ops_write, 1710 1793 }; 1711 1794
+7 -5
drivers/net/ethernet/intel/ice/ice_main.c
··· 3176 3176 hw = &pf->hw; 3177 3177 tx = &pf->ptp.port.tx; 3178 3178 spin_lock_irqsave(&tx->lock, flags); 3179 - ice_ptp_complete_tx_single_tstamp(tx); 3179 + if (tx->init) { 3180 + ice_ptp_complete_tx_single_tstamp(tx); 3180 3181 3181 - idx = find_next_bit_wrap(tx->in_use, tx->len, 3182 - tx->last_ll_ts_idx_read + 1); 3183 - if (idx != tx->len) 3184 - ice_ptp_req_tx_single_tstamp(tx, idx); 3182 + idx = find_next_bit_wrap(tx->in_use, tx->len, 3183 + tx->last_ll_ts_idx_read + 1); 3184 + if (idx != tx->len) 3185 + ice_ptp_req_tx_single_tstamp(tx, idx); 3186 + } 3185 3187 spin_unlock_irqrestore(&tx->lock, flags); 3186 3188 3187 3189 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
+8 -5
drivers/net/ethernet/intel/ice/ice_ptp.c
··· 2701 2701 */ 2702 2702 if (hw->dev_caps.ts_dev_info.ts_ll_int_read) { 2703 2703 struct ice_ptp_tx *tx = &pf->ptp.port.tx; 2704 - u8 idx; 2704 + u8 idx, last; 2705 2705 2706 2706 if (!ice_pf_state_is_nominal(pf)) 2707 2707 return IRQ_HANDLED; 2708 2708 2709 2709 spin_lock(&tx->lock); 2710 - idx = find_next_bit_wrap(tx->in_use, tx->len, 2711 - tx->last_ll_ts_idx_read + 1); 2712 - if (idx != tx->len) 2713 - ice_ptp_req_tx_single_tstamp(tx, idx); 2710 + if (tx->init) { 2711 + last = tx->last_ll_ts_idx_read + 1; 2712 + idx = find_next_bit_wrap(tx->in_use, tx->len, 2713 + last); 2714 + if (idx != tx->len) 2715 + ice_ptp_req_tx_single_tstamp(tx, idx); 2716 + } 2714 2717 spin_unlock(&tx->lock); 2715 2718 2716 2719 return IRQ_HANDLED;
+2 -2
drivers/net/ethernet/intel/idpf/idpf_idc.c
··· 247 247 if (!adev) 248 248 return; 249 249 250 + ida_free(&idpf_idc_ida, adev->id); 251 + 250 252 auxiliary_device_delete(adev); 251 253 auxiliary_device_uninit(adev); 252 - 253 - ida_free(&idpf_idc_ida, adev->id); 254 254 } 255 255 256 256 /**
+6 -3
drivers/net/ethernet/intel/idpf/idpf_lib.c
··· 2434 2434 struct idpf_netdev_priv *np = netdev_priv(netdev); 2435 2435 struct idpf_vport_config *vport_config; 2436 2436 struct sockaddr *addr = p; 2437 + u8 old_mac_addr[ETH_ALEN]; 2437 2438 struct idpf_vport *vport; 2438 2439 int err = 0; 2439 2440 ··· 2458 2457 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) 2459 2458 goto unlock_mutex; 2460 2459 2460 + ether_addr_copy(old_mac_addr, vport->default_mac_addr); 2461 + ether_addr_copy(vport->default_mac_addr, addr->sa_data); 2461 2462 vport_config = vport->adapter->vport_config[vport->idx]; 2462 2463 err = idpf_add_mac_filter(vport, np, addr->sa_data, false); 2463 2464 if (err) { 2464 2465 __idpf_del_mac_filter(vport_config, addr->sa_data); 2466 + ether_addr_copy(vport->default_mac_addr, netdev->dev_addr); 2465 2467 goto unlock_mutex; 2466 2468 } 2467 2469 2468 - if (is_valid_ether_addr(vport->default_mac_addr)) 2469 - idpf_del_mac_filter(vport, np, vport->default_mac_addr, false); 2470 + if (is_valid_ether_addr(old_mac_addr)) 2471 + __idpf_del_mac_filter(vport_config, old_mac_addr); 2470 2472 2471 - ether_addr_copy(vport->default_mac_addr, addr->sa_data); 2472 2473 eth_hw_addr_set(netdev, addr->sa_data); 2473 2474 2474 2475 unlock_mutex:
+12
drivers/net/ethernet/intel/idpf/idpf_virtchnl.c
··· 3765 3765 return le32_to_cpu(vport_msg->vport_id); 3766 3766 } 3767 3767 3768 + static void idpf_set_mac_type(struct idpf_vport *vport, 3769 + struct virtchnl2_mac_addr *mac_addr) 3770 + { 3771 + bool is_primary; 3772 + 3773 + is_primary = ether_addr_equal(vport->default_mac_addr, mac_addr->addr); 3774 + mac_addr->type = is_primary ? VIRTCHNL2_MAC_ADDR_PRIMARY : 3775 + VIRTCHNL2_MAC_ADDR_EXTRA; 3776 + } 3777 + 3768 3778 /** 3769 3779 * idpf_mac_filter_async_handler - Async callback for mac filters 3770 3780 * @adapter: private data struct ··· 3904 3894 list) { 3905 3895 if (add && f->add) { 3906 3896 ether_addr_copy(mac_addr[i].addr, f->macaddr); 3897 + idpf_set_mac_type(vport, &mac_addr[i]); 3907 3898 i++; 3908 3899 f->add = false; 3909 3900 if (i == total_filters) ··· 3912 3901 } 3913 3902 if (!add && f->remove) { 3914 3903 ether_addr_copy(mac_addr[i].addr, f->macaddr); 3904 + idpf_set_mac_type(vport, &mac_addr[i]); 3915 3905 i++; 3916 3906 f->remove = false; 3917 3907 if (i == total_filters)
+2 -2
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
··· 3571 3571 3572 3572 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3573 3573 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3574 - linkmode_set_bit(ixgbe_lp_map[i].link_mode, 3574 + linkmode_set_bit(ixgbe_ls_map[i].link_mode, 3575 3575 edata->supported); 3576 3576 } 3577 3577 3578 3578 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3579 3579 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3580 - linkmode_set_bit(ixgbe_lp_map[i].link_mode, 3580 + linkmode_set_bit(ixgbe_ls_map[i].link_mode, 3581 3581 edata->advertised); 3582 3582 } 3583 3583
+9 -1
drivers/net/ethernet/mediatek/mtk_eth_soc.c
··· 1761 1761 bool gso = false; 1762 1762 int tx_num; 1763 1763 1764 + if (skb_vlan_tag_present(skb) && 1765 + !eth_proto_is_802_3(eth_hdr(skb)->h_proto)) { 1766 + skb = __vlan_hwaccel_push_inside(skb); 1767 + if (!skb) 1768 + goto dropped; 1769 + } 1770 + 1764 1771 /* normally we can rely on the stack not calling this more than once, 1765 1772 * however we have 2 queues running on the same ring so we need to lock 1766 1773 * the ring access ··· 1813 1806 1814 1807 drop: 1815 1808 spin_unlock(&eth->page_lock); 1816 - stats->tx_dropped++; 1817 1809 dev_kfree_skb_any(skb); 1810 + dropped: 1811 + stats->tx_dropped++; 1818 1812 return NETDEV_TX_OK; 1819 1813 } 1820 1814
+3 -1
drivers/net/ethernet/mellanox/mlx4/en_rx.c
··· 267 267 pp.dma_dir = priv->dma_dir; 268 268 269 269 ring->pp = page_pool_create(&pp); 270 - if (!ring->pp) 270 + if (IS_ERR(ring->pp)) { 271 + err = PTR_ERR(ring->pp); 271 272 goto err_ring; 273 + } 272 274 273 275 if (xdp_rxq_info_reg(&ring->xdp_rxq, priv->dev, queue_index, 0) < 0) 274 276 goto err_pp;
+5 -2
drivers/net/ethernet/microchip/lan865x/lan865x.c
··· 424 424 free_netdev(priv->netdev); 425 425 } 426 426 427 - static const struct spi_device_id spidev_spi_ids[] = { 427 + static const struct spi_device_id lan865x_ids[] = { 428 428 { .name = "lan8650" }, 429 + { .name = "lan8651" }, 429 430 {}, 430 431 }; 432 + MODULE_DEVICE_TABLE(spi, lan865x_ids); 431 433 432 434 static const struct of_device_id lan865x_dt_ids[] = { 433 435 { .compatible = "microchip,lan8650" }, 436 + { .compatible = "microchip,lan8651" }, 434 437 { /* Sentinel */ } 435 438 }; 436 439 MODULE_DEVICE_TABLE(of, lan865x_dt_ids); ··· 445 442 }, 446 443 .probe = lan865x_probe, 447 444 .remove = lan865x_remove, 448 - .id_table = spidev_spi_ids, 445 + .id_table = lan865x_ids, 449 446 }; 450 447 module_spi_driver(lan865x_driver); 451 448
+2 -1
drivers/net/ethernet/oa_tc6.c
··· 1249 1249 1250 1250 /* Set the SPI controller to pump at realtime priority */ 1251 1251 tc6->spi->rt = true; 1252 - spi_setup(tc6->spi); 1252 + if (spi_setup(tc6->spi) < 0) 1253 + return NULL; 1253 1254 1254 1255 tc6->spi_ctrl_tx_buf = devm_kzalloc(&tc6->spi->dev, 1255 1256 OA_TC6_CTRL_SPI_BUF_SIZE,
+1 -1
drivers/net/ethernet/ti/am65-cpsw-nuss.c
··· 1522 1522 } 1523 1523 } 1524 1524 1525 - if (single_port) { 1525 + if (single_port && num_tx) { 1526 1526 netif_txq = netdev_get_tx_queue(ndev, chn); 1527 1527 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1528 1528 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
+10
drivers/net/ethernet/xilinx/xilinx_axienet_main.c
··· 1168 1168 &meta_max_len); 1169 1169 dma_unmap_single(lp->dev, skbuf_dma->dma_address, lp->max_frm_size, 1170 1170 DMA_FROM_DEVICE); 1171 + 1172 + if (IS_ERR(app_metadata)) { 1173 + if (net_ratelimit()) 1174 + netdev_err(lp->ndev, "Failed to get RX metadata pointer\n"); 1175 + dev_kfree_skb_any(skb); 1176 + lp->ndev->stats.rx_dropped++; 1177 + goto rx_submit; 1178 + } 1179 + 1171 1180 /* TODO: Derive app word index programmatically */ 1172 1181 rx_len = (app_metadata[LEN_APP] & 0xFFFF); 1173 1182 skb_put(skb, rx_len); ··· 1189 1180 u64_stats_add(&lp->rx_bytes, rx_len); 1190 1181 u64_stats_update_end(&lp->rx_stat_sync); 1191 1182 1183 + rx_submit: 1192 1184 for (i = 0; i < CIRC_SPACE(lp->rx_ring_head, lp->rx_ring_tail, 1193 1185 RX_BUF_NUM_DEFAULT); i++) 1194 1186 axienet_rx_submit_desc(lp->ndev);
+1 -1
drivers/net/ethernet/xircom/xirc2ps_cs.c
··· 1576 1576 msleep(40); /* wait 40 msec to let it complete */ 1577 1577 } 1578 1578 if (full_duplex) 1579 - PutByte(XIRCREG1_ECR, GetByte(XIRCREG1_ECR | FullDuplex)); 1579 + PutByte(XIRCREG1_ECR, GetByte(XIRCREG1_ECR) | FullDuplex); 1580 1580 } else { /* No MII */ 1581 1581 SelectPage(0); 1582 1582 value = GetByte(XIRCREG_ESR); /* read the ESR */
+4 -4
drivers/net/macsec.c
··· 1813 1813 1814 1814 if (tb_sa[MACSEC_SA_ATTR_PN]) { 1815 1815 spin_lock_bh(&rx_sa->lock); 1816 - rx_sa->next_pn = nla_get_u64(tb_sa[MACSEC_SA_ATTR_PN]); 1816 + rx_sa->next_pn = nla_get_uint(tb_sa[MACSEC_SA_ATTR_PN]); 1817 1817 spin_unlock_bh(&rx_sa->lock); 1818 1818 } 1819 1819 ··· 2020 2020 } 2021 2021 2022 2022 spin_lock_bh(&tx_sa->lock); 2023 - tx_sa->next_pn = nla_get_u64(tb_sa[MACSEC_SA_ATTR_PN]); 2023 + tx_sa->next_pn = nla_get_uint(tb_sa[MACSEC_SA_ATTR_PN]); 2024 2024 spin_unlock_bh(&tx_sa->lock); 2025 2025 2026 2026 if (tb_sa[MACSEC_SA_ATTR_ACTIVE]) ··· 2321 2321 2322 2322 spin_lock_bh(&tx_sa->lock); 2323 2323 prev_pn = tx_sa->next_pn_halves; 2324 - tx_sa->next_pn = nla_get_u64(tb_sa[MACSEC_SA_ATTR_PN]); 2324 + tx_sa->next_pn = nla_get_uint(tb_sa[MACSEC_SA_ATTR_PN]); 2325 2325 spin_unlock_bh(&tx_sa->lock); 2326 2326 } 2327 2327 ··· 2419 2419 2420 2420 spin_lock_bh(&rx_sa->lock); 2421 2421 prev_pn = rx_sa->next_pn_halves; 2422 - rx_sa->next_pn = nla_get_u64(tb_sa[MACSEC_SA_ATTR_PN]); 2422 + rx_sa->next_pn = nla_get_uint(tb_sa[MACSEC_SA_ATTR_PN]); 2423 2423 spin_unlock_bh(&rx_sa->lock); 2424 2424 } 2425 2425
+1
drivers/net/mctp/mctp-usb.c
··· 183 183 struct mctp_usb_hdr *hdr; 184 184 u8 pkt_len; /* length of MCTP packet, no USB header */ 185 185 186 + skb_reset_mac_header(skb); 186 187 hdr = skb_pull_data(skb, sizeof(*hdr)); 187 188 if (!hdr) 188 189 break;
+1 -1
drivers/net/pcs/pcs-rzn1-miic.c
··· 19 19 #define MIIC_PRCMD 0x0 20 20 #define MIIC_ESID_CODE 0x4 21 21 22 - #define MIIC_MODCTRL 0x20 22 + #define MIIC_MODCTRL 0x8 23 23 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) 24 24 25 25 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4)
+8 -10
drivers/net/phy/mscc/mscc_ptp.c
··· 456 456 *p++ = (reg >> 24) & 0xff; 457 457 } 458 458 459 - len = skb_queue_len(&ptp->tx_queue); 459 + len = skb_queue_len_lockless(&ptp->tx_queue); 460 460 if (len < 1) 461 461 return; 462 462 463 463 while (len--) { 464 - skb = __skb_dequeue(&ptp->tx_queue); 464 + skb = skb_dequeue(&ptp->tx_queue); 465 465 if (!skb) 466 466 return; 467 467 ··· 486 486 * packet in the FIFO right now, reschedule it for later 487 487 * packets. 488 488 */ 489 - __skb_queue_tail(&ptp->tx_queue, skb); 489 + skb_queue_tail(&ptp->tx_queue, skb); 490 490 } 491 491 } 492 492 ··· 1068 1068 case HWTSTAMP_TX_ON: 1069 1069 break; 1070 1070 case HWTSTAMP_TX_OFF: 1071 + skb_queue_purge(&vsc8531->ptp->tx_queue); 1071 1072 break; 1072 1073 default: 1073 1074 return -ERANGE; ··· 1092 1091 vsc8531->ptp->rx_filter = cfg->rx_filter; 1093 1092 1094 1093 mutex_lock(&vsc8531->ts_lock); 1095 - 1096 - __skb_queue_purge(&vsc8531->ptp->tx_queue); 1097 - __skb_queue_head_init(&vsc8531->ptp->tx_queue); 1098 1094 1099 1095 /* Disable predictor while configuring the 1588 block */ 1100 1096 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, ··· 1178 1180 1179 1181 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1180 1182 1181 - mutex_lock(&vsc8531->ts_lock); 1182 - __skb_queue_tail(&vsc8531->ptp->tx_queue, skb); 1183 - mutex_unlock(&vsc8531->ts_lock); 1183 + skb_queue_tail(&vsc8531->ptp->tx_queue, skb); 1184 1184 return; 1185 1185 1186 1186 out: ··· 1544 1548 if (vsc8531->ptp->ptp_clock) { 1545 1549 ptp_clock_unregister(vsc8531->ptp->ptp_clock); 1546 1550 skb_queue_purge(&vsc8531->rx_skbs_list); 1551 + skb_queue_purge(&vsc8531->ptp->tx_queue); 1547 1552 } 1548 1553 } 1549 1554 ··· 1568 1571 if (rc & VSC85XX_1588_INT_FIFO_ADD) { 1569 1572 vsc85xx_get_tx_ts(priv->ptp); 1570 1573 } else if (rc & VSC85XX_1588_INT_FIFO_OVERFLOW) { 1571 - __skb_queue_purge(&priv->ptp->tx_queue); 1574 + skb_queue_purge(&priv->ptp->tx_queue); 1572 1575 vsc85xx_ts_reset_fifo(phydev); 1573 1576 } 1574 1577 ··· 1588 1591 mutex_init(&vsc8531->phc_lock); 1589 1592 mutex_init(&vsc8531->ts_lock); 1590 1593 skb_queue_head_init(&vsc8531->rx_skbs_list); 1594 + skb_queue_head_init(&vsc8531->ptp->tx_queue); 1591 1595 1592 1596 /* Retrieve the shared load/save GPIO. Request it as non exclusive as 1593 1597 * the same GPIO can be requested by all the PHYs of the same package.
+65 -38
drivers/net/phy/phylink.c
··· 1016 1016 pl->pcs->ops->pcs_an_restart(pl->pcs); 1017 1017 } 1018 1018 1019 + enum inband_type { 1020 + INBAND_NONE, 1021 + INBAND_CISCO_SGMII, 1022 + INBAND_BASEX, 1023 + }; 1024 + 1025 + static enum inband_type phylink_get_inband_type(phy_interface_t interface) 1026 + { 1027 + switch (interface) { 1028 + case PHY_INTERFACE_MODE_SGMII: 1029 + case PHY_INTERFACE_MODE_QSGMII: 1030 + case PHY_INTERFACE_MODE_QUSGMII: 1031 + case PHY_INTERFACE_MODE_USXGMII: 1032 + case PHY_INTERFACE_MODE_10G_QXGMII: 1033 + /* These protocols are designed for use with a PHY which 1034 + * communicates its negotiation result back to the MAC via 1035 + * inband communication. Note: there exist PHYs that run 1036 + * with SGMII but do not send the inband data. 1037 + */ 1038 + return INBAND_CISCO_SGMII; 1039 + 1040 + case PHY_INTERFACE_MODE_1000BASEX: 1041 + case PHY_INTERFACE_MODE_2500BASEX: 1042 + /* 1000base-X is designed for use media-side for Fibre 1043 + * connections, and thus the Autoneg bit needs to be 1044 + * taken into account. We also do this for 2500base-X 1045 + * as well, but drivers may not support this, so may 1046 + * need to override this. 1047 + */ 1048 + return INBAND_BASEX; 1049 + 1050 + default: 1051 + return INBAND_NONE; 1052 + } 1053 + } 1054 + 1019 1055 /** 1020 1056 * phylink_pcs_neg_mode() - helper to determine PCS inband mode 1021 1057 * @pl: a pointer to a &struct phylink returned from phylink_create() ··· 1079 1043 unsigned int pcs_ib_caps = 0; 1080 1044 unsigned int phy_ib_caps = 0; 1081 1045 unsigned int neg_mode, mode; 1082 - enum { 1083 - INBAND_CISCO_SGMII, 1084 - INBAND_BASEX, 1085 - } type; 1046 + enum inband_type type; 1047 + 1048 + type = phylink_get_inband_type(interface); 1049 + if (type == INBAND_NONE) { 1050 + pl->pcs_neg_mode = PHYLINK_PCS_NEG_NONE; 1051 + pl->act_link_an_mode = pl->req_link_an_mode; 1052 + return; 1053 + } 1086 1054 1087 1055 mode = pl->req_link_an_mode; 1088 1056 1089 1057 pl->phy_ib_mode = 0; 1090 - 1091 - switch (interface) { 1092 - case PHY_INTERFACE_MODE_SGMII: 1093 - case PHY_INTERFACE_MODE_QSGMII: 1094 - case PHY_INTERFACE_MODE_QUSGMII: 1095 - case PHY_INTERFACE_MODE_USXGMII: 1096 - case PHY_INTERFACE_MODE_10G_QXGMII: 1097 - /* These protocols are designed for use with a PHY which 1098 - * communicates its negotiation result back to the MAC via 1099 - * inband communication. Note: there exist PHYs that run 1100 - * with SGMII but do not send the inband data. 1101 - */ 1102 - type = INBAND_CISCO_SGMII; 1103 - break; 1104 - 1105 - case PHY_INTERFACE_MODE_1000BASEX: 1106 - case PHY_INTERFACE_MODE_2500BASEX: 1107 - /* 1000base-X is designed for use media-side for Fibre 1108 - * connections, and thus the Autoneg bit needs to be 1109 - * taken into account. We also do this for 2500base-X 1110 - * as well, but drivers may not support this, so may 1111 - * need to override this. 1112 - */ 1113 - type = INBAND_BASEX; 1114 - break; 1115 - 1116 - default: 1117 - pl->pcs_neg_mode = PHYLINK_PCS_NEG_NONE; 1118 - pl->act_link_an_mode = mode; 1119 - return; 1120 - } 1121 1058 1122 1059 if (pcs) 1123 1060 pcs_ib_caps = phylink_pcs_inband_caps(pcs, interface); ··· 2141 2132 __ETHTOOL_LINK_MODE_MASK_NBITS, pl->supported, 2142 2133 __ETHTOOL_LINK_MODE_MASK_NBITS, phy->advertising); 2143 2134 2144 - if (phy_interrupt_is_valid(phy)) 2145 - phy_request_interrupt(phy); 2146 - 2147 2135 if (pl->config->mac_managed_pm) 2148 2136 phy->mac_managed_pm = true; 2149 2137 ··· 2156 2150 if (ret == -EOPNOTSUPP) 2157 2151 ret = 0; 2158 2152 } 2153 + 2154 + if (ret == 0 && phy_interrupt_is_valid(phy)) 2155 + phy_request_interrupt(phy); 2159 2156 2160 2157 return ret; 2161 2158 } ··· 3634 3625 { 3635 3626 __ETHTOOL_DECLARE_LINK_MODE_MASK(support); 3636 3627 struct phylink_link_state config; 3628 + enum inband_type inband_type; 3637 3629 phy_interface_t interface; 3638 3630 int ret; 3639 3631 ··· 3680 3670 3681 3671 phylink_dbg(pl, "optical SFP: chosen %s interface\n", 3682 3672 phy_modes(interface)); 3673 + 3674 + inband_type = phylink_get_inband_type(interface); 3675 + if (inband_type == INBAND_NONE) { 3676 + /* If this is the sole interface, and there is no inband 3677 + * support, clear the advertising mask and Autoneg bit in 3678 + * the support mask. Otherwise, just clear the Autoneg bit 3679 + * in the advertising mask. 3680 + */ 3681 + if (phy_interface_weight(pl->sfp_interfaces) == 1) { 3682 + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3683 + pl->sfp_support); 3684 + linkmode_zero(config.advertising); 3685 + } else { 3686 + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3687 + config.advertising); 3688 + } 3689 + } 3683 3690 3684 3691 if (!phylink_validate_pcs_inband_autoneg(pl, interface, 3685 3692 config.advertising)) {
+3
drivers/net/phy/sfp.c
··· 492 492 SFP_QUIRK("ALCATELLUCENT", "3FE46541AA", sfp_quirk_2500basex, 493 493 sfp_fixup_nokia), 494 494 495 + // FLYPRO SFP-10GT-CS-30M uses Rollball protocol to talk to the PHY. 496 + SFP_QUIRK_F("FLYPRO", "SFP-10GT-CS-30M", sfp_fixup_rollball), 497 + 495 498 // Fiberstore SFP-10G-T doesn't identify as copper, uses the Rollball 496 499 // protocol to talk to the PHY and needs 4 sec wait before probing the 497 500 // PHY.
+3 -3
drivers/net/ppp/ppp_generic.c
··· 1744 1744 */ 1745 1745 if (net_ratelimit()) 1746 1746 netdev_err(ppp->dev, "ppp: compressor dropped pkt\n"); 1747 - kfree_skb(skb); 1748 1747 consume_skb(new_skb); 1749 1748 new_skb = NULL; 1750 1749 } ··· 1844 1845 "down - pkt dropped.\n"); 1845 1846 goto drop; 1846 1847 } 1847 - skb = pad_compress_skb(ppp, skb); 1848 - if (!skb) 1848 + new_skb = pad_compress_skb(ppp, skb); 1849 + if (!new_skb) 1849 1850 goto drop; 1851 + skb = new_skb; 1850 1852 } 1851 1853 1852 1854 /*
+12 -6
drivers/net/vxlan/vxlan_core.c
··· 1445 1445 if (READ_ONCE(f->updated) != now) 1446 1446 WRITE_ONCE(f->updated, now); 1447 1447 1448 + /* Don't override an fdb with nexthop with a learnt entry */ 1449 + if (rcu_access_pointer(f->nh)) 1450 + return SKB_DROP_REASON_VXLAN_ENTRY_EXISTS; 1451 + 1448 1452 if (likely(vxlan_addr_equal(&rdst->remote_ip, src_ip) && 1449 1453 rdst->remote_ifindex == ifindex)) 1450 1454 return SKB_NOT_DROPPED_YET; 1451 1455 1452 1456 /* Don't migrate static entries, drop packets */ 1453 1457 if (f->state & (NUD_PERMANENT | NUD_NOARP)) 1454 - return SKB_DROP_REASON_VXLAN_ENTRY_EXISTS; 1455 - 1456 - /* Don't override an fdb with nexthop with a learnt entry */ 1457 - if (rcu_access_pointer(f->nh)) 1458 1458 return SKB_DROP_REASON_VXLAN_ENTRY_EXISTS; 1459 1459 1460 1460 if (net_ratelimit()) ··· 1877 1877 n = neigh_lookup(&arp_tbl, &tip, dev); 1878 1878 1879 1879 if (n) { 1880 + struct vxlan_rdst *rdst = NULL; 1880 1881 struct vxlan_fdb *f; 1881 1882 struct sk_buff *reply; 1882 1883 ··· 1888 1887 1889 1888 rcu_read_lock(); 1890 1889 f = vxlan_find_mac_tx(vxlan, n->ha, vni); 1891 - if (f && vxlan_addr_any(&(first_remote_rcu(f)->remote_ip))) { 1890 + if (f) 1891 + rdst = first_remote_rcu(f); 1892 + if (rdst && vxlan_addr_any(&rdst->remote_ip)) { 1892 1893 /* bridge-local neighbor */ 1893 1894 neigh_release(n); 1894 1895 rcu_read_unlock(); ··· 2047 2044 n = neigh_lookup(ipv6_stub->nd_tbl, &msg->target, dev); 2048 2045 2049 2046 if (n) { 2047 + struct vxlan_rdst *rdst = NULL; 2050 2048 struct vxlan_fdb *f; 2051 2049 struct sk_buff *reply; 2052 2050 ··· 2057 2053 } 2058 2054 2059 2055 f = vxlan_find_mac_tx(vxlan, n->ha, vni); 2060 - if (f && vxlan_addr_any(&(first_remote_rcu(f)->remote_ip))) { 2056 + if (f) 2057 + rdst = first_remote_rcu(f); 2058 + if (rdst && vxlan_addr_any(&rdst->remote_ip)) { 2061 2059 /* bridge-local neighbor */ 2062 2060 neigh_release(n); 2063 2061 goto out;
+1 -3
drivers/net/vxlan/vxlan_private.h
··· 61 61 return &vn->sock_list[hash_32(ntohs(port), PORT_HASH_BITS)]; 62 62 } 63 63 64 - /* First remote destination for a forwarding entry. 65 - * Guaranteed to be non-NULL because remotes are never deleted. 66 - */ 64 + /* First remote destination for a forwarding entry. */ 67 65 static inline struct vxlan_rdst *first_remote_rcu(struct vxlan_fdb *fdb) 68 66 { 69 67 if (rcu_access_pointer(fdb->nh))
+2
drivers/net/wireless/ath/ath11k/core.h
··· 411 411 bool do_not_send_tmpl; 412 412 struct ath11k_arp_ns_offload arp_ns_offload; 413 413 struct ath11k_rekey_data rekey_data; 414 + u32 num_stations; 415 + bool reinstall_group_keys; 414 416 415 417 struct ath11k_reg_tpc_power_info reg_tpc_info; 416 418
+102 -9
drivers/net/wireless/ath/ath11k/mac.c
··· 4317 4317 return first_errno; 4318 4318 } 4319 4319 4320 + static int ath11k_set_group_keys(struct ath11k_vif *arvif) 4321 + { 4322 + struct ath11k *ar = arvif->ar; 4323 + struct ath11k_base *ab = ar->ab; 4324 + const u8 *addr = arvif->bssid; 4325 + int i, ret, first_errno = 0; 4326 + struct ath11k_peer *peer; 4327 + 4328 + spin_lock_bh(&ab->base_lock); 4329 + peer = ath11k_peer_find(ab, arvif->vdev_id, addr); 4330 + spin_unlock_bh(&ab->base_lock); 4331 + 4332 + if (!peer) 4333 + return -ENOENT; 4334 + 4335 + for (i = 0; i < ARRAY_SIZE(peer->keys); i++) { 4336 + struct ieee80211_key_conf *key = peer->keys[i]; 4337 + 4338 + if (!key || (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 4339 + continue; 4340 + 4341 + ret = ath11k_install_key(arvif, key, SET_KEY, addr, 4342 + WMI_KEY_GROUP); 4343 + if (ret < 0 && first_errno == 0) 4344 + first_errno = ret; 4345 + 4346 + if (ret < 0) 4347 + ath11k_warn(ab, "failed to set group key of idx %d for vdev %d: %d\n", 4348 + i, arvif->vdev_id, ret); 4349 + } 4350 + 4351 + return first_errno; 4352 + } 4353 + 4320 4354 static int ath11k_mac_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 4321 4355 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 4322 4356 struct ieee80211_key_conf *key) ··· 4360 4326 struct ath11k_vif *arvif = ath11k_vif_to_arvif(vif); 4361 4327 struct ath11k_peer *peer; 4362 4328 struct ath11k_sta *arsta; 4329 + bool is_ap_with_no_sta; 4363 4330 const u8 *peer_addr; 4364 4331 int ret = 0; 4365 4332 u32 flags = 0; ··· 4421 4386 else 4422 4387 flags |= WMI_KEY_GROUP; 4423 4388 4424 - ret = ath11k_install_key(arvif, key, cmd, peer_addr, flags); 4425 - if (ret) { 4426 - ath11k_warn(ab, "ath11k_install_key failed (%d)\n", ret); 4427 - goto exit; 4428 - } 4389 + ath11k_dbg(ar->ab, ATH11K_DBG_MAC, 4390 + "%s for peer %pM on vdev %d flags 0x%X, type = %d, num_sta %d\n", 4391 + cmd == SET_KEY ? "SET_KEY" : "DEL_KEY", peer_addr, arvif->vdev_id, 4392 + flags, arvif->vdev_type, arvif->num_stations); 4429 4393 4430 - ret = ath11k_dp_peer_rx_pn_replay_config(arvif, peer_addr, cmd, key); 4431 - if (ret) { 4432 - ath11k_warn(ab, "failed to offload PN replay detection %d\n", ret); 4433 - goto exit; 4394 + /* Allow group key clearing only in AP mode when no stations are 4395 + * associated. There is a known race condition in firmware where 4396 + * group addressed packets may be dropped if the key is cleared 4397 + * and immediately set again during rekey. 4398 + * 4399 + * During GTK rekey, mac80211 issues a clear key (if the old key 4400 + * exists) followed by an install key operation for same key 4401 + * index. This causes ath11k to send two WMI commands in quick 4402 + * succession: one to clear the old key and another to install the 4403 + * new key in the same slot. 4404 + * 4405 + * Under certain conditions—especially under high load or time 4406 + * sensitive scenarios, firmware may process these commands 4407 + * asynchronously in a way that firmware assumes the key is 4408 + * cleared whereas hardware has a valid key. This inconsistency 4409 + * between hardware and firmware leads to group addressed packet 4410 + * drops after rekey. 4411 + * Only setting the same key again can restore a valid key in 4412 + * firmware and allow packets to be transmitted. 4413 + * 4414 + * There is a use case where an AP can transition from Secure mode 4415 + * to open mode without a vdev restart by just deleting all 4416 + * associated peers and clearing key, Hence allow clear key for 4417 + * that case alone. Mark arvif->reinstall_group_keys in such cases 4418 + * and reinstall the same key when the first peer is added, 4419 + * allowing firmware to recover from the race if it had occurred. 4420 + */ 4421 + 4422 + is_ap_with_no_sta = (vif->type == NL80211_IFTYPE_AP && 4423 + !arvif->num_stations); 4424 + if ((flags & WMI_KEY_PAIRWISE) || cmd == SET_KEY || is_ap_with_no_sta) { 4425 + ret = ath11k_install_key(arvif, key, cmd, peer_addr, flags); 4426 + if (ret) { 4427 + ath11k_warn(ab, "ath11k_install_key failed (%d)\n", ret); 4428 + goto exit; 4429 + } 4430 + 4431 + ret = ath11k_dp_peer_rx_pn_replay_config(arvif, peer_addr, cmd, key); 4432 + if (ret) { 4433 + ath11k_warn(ab, "failed to offload PN replay detection %d\n", 4434 + ret); 4435 + goto exit; 4436 + } 4437 + 4438 + if ((flags & WMI_KEY_GROUP) && cmd == SET_KEY && is_ap_with_no_sta) 4439 + arvif->reinstall_group_keys = true; 4434 4440 } 4435 4441 4436 4442 spin_lock_bh(&ab->base_lock); ··· 5070 4994 return -ENOBUFS; 5071 4995 5072 4996 ar->num_stations++; 4997 + arvif->num_stations++; 5073 4998 5074 4999 return 0; 5075 5000 } ··· 5086 5009 return; 5087 5010 5088 5011 ar->num_stations--; 5012 + arvif->num_stations--; 5089 5013 } 5090 5014 5091 5015 static u32 ath11k_mac_ieee80211_sta_bw_to_wmi(struct ath11k *ar, ··· 9616 9538 ath11k_warn(ab, "refusing to associate station: too many connected already (%d)\n", 9617 9539 ar->max_num_stations); 9618 9540 goto exit; 9541 + } 9542 + 9543 + /* Driver allows the DEL KEY followed by SET KEY sequence for 9544 + * group keys for only when there is no clients associated, if at 9545 + * all firmware has entered the race during that window, 9546 + * reinstalling the same key when the first sta connects will allow 9547 + * firmware to recover from the race. 9548 + */ 9549 + if (arvif->num_stations == 1 && arvif->reinstall_group_keys) { 9550 + ath11k_dbg(ab, ATH11K_DBG_MAC, "set group keys on 1st station add for vdev %d\n", 9551 + arvif->vdev_id); 9552 + ret = ath11k_set_group_keys(arvif); 9553 + if (ret) 9554 + goto dec_num_station; 9555 + arvif->reinstall_group_keys = false; 9619 9556 } 9620 9557 9621 9558 arsta->rx_stats = kzalloc(sizeof(*arsta->rx_stats), GFP_KERNEL);
+1
drivers/net/wireless/ath/ath12k/wmi.c
··· 2423 2423 2424 2424 eml_cap = arg->ml.eml_cap; 2425 2425 if (u16_get_bits(eml_cap, IEEE80211_EML_CAP_EMLSR_SUPP)) { 2426 + ml_params->flags |= cpu_to_le32(ATH12K_WMI_FLAG_MLO_EMLSR_SUPPORT); 2426 2427 /* Padding delay */ 2427 2428 eml_pad_delay = ieee80211_emlsr_pad_delay_in_us(eml_cap); 2428 2429 ml_params->emlsr_padding_delay_us = cpu_to_le32(eml_pad_delay);
+2 -4
drivers/net/wireless/broadcom/brcm80211/brcmfmac/btcoex.c
··· 393 393 if (!cfg->btcoex) 394 394 return; 395 395 396 - if (cfg->btcoex->timer_on) { 397 - cfg->btcoex->timer_on = false; 398 - timer_shutdown_sync(&cfg->btcoex->timer); 399 - } 396 + timer_shutdown_sync(&cfg->btcoex->timer); 397 + cfg->btcoex->timer_on = false; 400 398 401 399 cancel_work_sync(&cfg->btcoex->work); 402 400
+24 -1
drivers/net/wireless/intel/iwlwifi/fw/acpi.c
··· 169 169 170 170 BUILD_BUG_ON(ARRAY_SIZE(acpi_dsm_size) != DSM_FUNC_NUM_FUNCS); 171 171 172 - if (WARN_ON(func >= ARRAY_SIZE(acpi_dsm_size))) 172 + if (WARN_ON(func >= ARRAY_SIZE(acpi_dsm_size) || !func)) 173 173 return -EINVAL; 174 174 175 175 expected_size = acpi_dsm_size[func]; ··· 177 177 /* Currently all ACPI DSMs are either 8-bit or 32-bit */ 178 178 if (expected_size != sizeof(u8) && expected_size != sizeof(u32)) 179 179 return -EOPNOTSUPP; 180 + 181 + if (!fwrt->acpi_dsm_funcs_valid) { 182 + ret = iwl_acpi_get_dsm_integer(fwrt->dev, ACPI_DSM_REV, 183 + DSM_FUNC_QUERY, 184 + &iwl_guid, &tmp, 185 + acpi_dsm_size[DSM_FUNC_QUERY]); 186 + if (ret) { 187 + /* always indicate BIT(0) to avoid re-reading */ 188 + fwrt->acpi_dsm_funcs_valid = BIT(0); 189 + return ret; 190 + } 191 + 192 + IWL_DEBUG_RADIO(fwrt, "ACPI DSM validity bitmap 0x%x\n", 193 + (u32)tmp); 194 + /* always indicate BIT(0) to avoid re-reading */ 195 + fwrt->acpi_dsm_funcs_valid = tmp | BIT(0); 196 + } 197 + 198 + if (!(fwrt->acpi_dsm_funcs_valid & BIT(func))) { 199 + IWL_DEBUG_RADIO(fwrt, "ACPI DSM %d not indicated as valid\n", 200 + func); 201 + return -ENODATA; 202 + } 180 203 181 204 ret = iwl_acpi_get_dsm_integer(fwrt->dev, ACPI_DSM_REV, func, 182 205 &iwl_guid, &tmp, expected_size);
+8
drivers/net/wireless/intel/iwlwifi/fw/runtime.h
··· 113 113 * @phy_filters: specific phy filters as read from WPFC BIOS table 114 114 * @ppag_bios_rev: PPAG BIOS revision 115 115 * @ppag_bios_source: see &enum bios_source 116 + * @acpi_dsm_funcs_valid: bitmap indicating which DSM values are valid, 117 + * zero (default initialization) means it hasn't been read yet, 118 + * and BIT(0) is set when it has since function 0 also has this 119 + * bitmap and is always supported 116 120 */ 117 121 struct iwl_fw_runtime { 118 122 struct iwl_trans *trans; ··· 193 189 bool uats_valid; 194 190 u8 uefi_tables_lock_status; 195 191 struct iwl_phy_specific_cfg phy_filters; 192 + 193 + #ifdef CONFIG_ACPI 194 + u32 acpi_dsm_funcs_valid; 195 + #endif 196 196 }; 197 197 198 198 void iwl_fw_runtime_init(struct iwl_fw_runtime *fwrt, struct iwl_trans *trans,
+6
drivers/net/wireless/intel/iwlwifi/fw/uefi.c
··· 747 747 goto out; 748 748 } 749 749 750 + if (!(data->functions[DSM_FUNC_QUERY] & BIT(func))) { 751 + IWL_DEBUG_RADIO(fwrt, "DSM func %d not in 0x%x\n", 752 + func, data->functions[DSM_FUNC_QUERY]); 753 + goto out; 754 + } 755 + 750 756 *value = data->functions[func]; 751 757 752 758 IWL_DEBUG_RADIO(fwrt,
+17 -5
drivers/net/wireless/intel/iwlwifi/pcie/drv.c
··· 673 673 674 674 IWL_DEV_INFO(iwl6005_n_cfg, iwl6005_2agn_sff_name, 675 675 DEVICE(0x0082), SUBDEV_MASKED(0xC000, 0xF000)), 676 + IWL_DEV_INFO(iwl6005_n_cfg, iwl6005_2agn_sff_name, 677 + DEVICE(0x0085), SUBDEV_MASKED(0xC000, 0xF000)), 676 678 IWL_DEV_INFO(iwl6005_n_cfg, iwl6005_2agn_d_name, 677 679 DEVICE(0x0082), SUBDEV(0x4820)), 678 680 IWL_DEV_INFO(iwl6005_n_cfg, iwl6005_2agn_mow1_name, ··· 731 729 DEVICE(0x0083), SUBDEV_MASKED(0x5, 0xF)), 732 730 IWL_DEV_INFO(iwl1000_bg_cfg, iwl1000_bg_name, 733 731 DEVICE(0x0083), SUBDEV_MASKED(0x6, 0xF)), 732 + IWL_DEV_INFO(iwl1000_bgn_cfg, iwl1000_bgn_name, 733 + DEVICE(0x0084), SUBDEV_MASKED(0x5, 0xF)), 734 734 IWL_DEV_INFO(iwl1000_bg_cfg, iwl1000_bg_name, 735 - DEVICE(0x0084), SUBDEV(0x1216)), 736 - IWL_DEV_INFO(iwl1000_bg_cfg, iwl1000_bg_name, 737 - DEVICE(0x0084), SUBDEV(0x1316)), 735 + DEVICE(0x0084), SUBDEV_MASKED(0x6, 0xF)), 738 736 739 737 /* 100 Series WiFi */ 740 738 IWL_DEV_INFO(iwl100_bgn_cfg, iwl100_bgn_name, ··· 966 964 DEVICE(0x24F3), SUBDEV(0x0004)), 967 965 IWL_DEV_INFO(iwl8260_cfg, iwl8260_2n_name, 968 966 DEVICE(0x24F3), SUBDEV(0x0044)), 967 + IWL_DEV_INFO(iwl8260_cfg, iwl8260_2ac_name, 968 + DEVICE(0x24F4)), 969 + IWL_DEV_INFO(iwl8260_cfg, iwl4165_2ac_name, 970 + DEVICE(0x24F5)), 971 + IWL_DEV_INFO(iwl8260_cfg, iwl4165_2ac_name, 972 + DEVICE(0x24F6)), 969 973 IWL_DEV_INFO(iwl8265_cfg, iwl8265_2ac_name, 970 974 DEVICE(0x24FD)), 971 975 IWL_DEV_INFO(iwl8265_cfg, iwl8275_2ac_name, ··· 1230 1222 * Note: MAC (bits 0:7) will be cleared upon suspend even with wowlan, 1231 1223 * but not bits [15:8]. So if we have bits set in lower word, assume 1232 1224 * the device is alive. 1225 + * Alternatively, if the scratch value is 0xFFFFFFFF, then we no longer 1226 + * have access to the device and consider it powered off. 1233 1227 * For older devices, just try silently to grab the NIC. 1234 1228 */ 1235 1229 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1236 - if (!(iwl_read32(trans, CSR_FUNC_SCRATCH) & 1237 - CSR_FUNC_SCRATCH_POWER_OFF_MASK)) 1230 + u32 scratch = iwl_read32(trans, CSR_FUNC_SCRATCH); 1231 + 1232 + if (!(scratch & CSR_FUNC_SCRATCH_POWER_OFF_MASK) || 1233 + scratch == ~0U) 1238 1234 device_was_powered_off = true; 1239 1235 } else { 1240 1236 /*
+2 -1
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/tx.c
··· 2092 2092 break; 2093 2093 } 2094 2094 2095 - if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 2095 + if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_9000 && 2096 + trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 2096 2097 len = DIV_ROUND_UP(len, 4); 2097 2098 2098 2099 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
+6 -3
drivers/net/wireless/marvell/libertas/cfg.c
··· 1151 1151 /* add SSID TLV */ 1152 1152 rcu_read_lock(); 1153 1153 ssid_eid = ieee80211_bss_get_ie(bss, WLAN_EID_SSID); 1154 - if (ssid_eid) 1155 - pos += lbs_add_ssid_tlv(pos, ssid_eid + 2, ssid_eid[1]); 1156 - else 1154 + if (ssid_eid) { 1155 + u32 ssid_len = min(ssid_eid[1], IEEE80211_MAX_SSID_LEN); 1156 + 1157 + pos += lbs_add_ssid_tlv(pos, ssid_eid + 2, ssid_len); 1158 + } else { 1157 1159 lbs_deb_assoc("no SSID\n"); 1160 + } 1158 1161 rcu_read_unlock(); 1159 1162 1160 1163 /* add DS param TLV */
+3 -2
drivers/net/wireless/marvell/mwifiex/cfg80211.c
··· 4673 4673 * additional active scan request for hidden SSIDs on passive channels. 4674 4674 */ 4675 4675 adapter->num_in_chan_stats = 2 * (n_channels_bg + n_channels_a); 4676 - adapter->chan_stats = vmalloc(array_size(sizeof(*adapter->chan_stats), 4677 - adapter->num_in_chan_stats)); 4676 + adapter->chan_stats = kcalloc(adapter->num_in_chan_stats, 4677 + sizeof(*adapter->chan_stats), 4678 + GFP_KERNEL); 4678 4679 4679 4680 if (!adapter->chan_stats) 4680 4681 return -ENOMEM;
+2 -2
drivers/net/wireless/marvell/mwifiex/main.c
··· 642 642 goto done; 643 643 644 644 err_add_intf: 645 - vfree(adapter->chan_stats); 645 + kfree(adapter->chan_stats); 646 646 err_init_chan_scan: 647 647 wiphy_unregister(adapter->wiphy); 648 648 wiphy_free(adapter->wiphy); ··· 1485 1485 wiphy_free(adapter->wiphy); 1486 1486 adapter->wiphy = NULL; 1487 1487 1488 - vfree(adapter->chan_stats); 1488 + kfree(adapter->chan_stats); 1489 1489 mwifiex_free_cmd_buffers(adapter); 1490 1490 } 1491 1491
+42 -1
drivers/net/wireless/mediatek/mt76/mac80211.c
··· 818 818 } 819 819 EXPORT_SYMBOL_GPL(mt76_free_device); 820 820 821 + static void mt76_reset_phy(struct mt76_phy *phy) 822 + { 823 + if (!phy) 824 + return; 825 + 826 + INIT_LIST_HEAD(&phy->tx_list); 827 + } 828 + 829 + void mt76_reset_device(struct mt76_dev *dev) 830 + { 831 + int i; 832 + 833 + rcu_read_lock(); 834 + for (i = 0; i < ARRAY_SIZE(dev->wcid); i++) { 835 + struct mt76_wcid *wcid; 836 + 837 + wcid = rcu_dereference(dev->wcid[i]); 838 + if (!wcid) 839 + continue; 840 + 841 + wcid->sta = 0; 842 + mt76_wcid_cleanup(dev, wcid); 843 + rcu_assign_pointer(dev->wcid[i], NULL); 844 + } 845 + rcu_read_unlock(); 846 + 847 + INIT_LIST_HEAD(&dev->wcid_list); 848 + INIT_LIST_HEAD(&dev->sta_poll_list); 849 + dev->vif_mask = 0; 850 + memset(dev->wcid_mask, 0, sizeof(dev->wcid_mask)); 851 + 852 + mt76_reset_phy(&dev->phy); 853 + for (i = 0; i < ARRAY_SIZE(dev->phys); i++) 854 + mt76_reset_phy(dev->phys[i]); 855 + } 856 + EXPORT_SYMBOL_GPL(mt76_reset_device); 857 + 821 858 struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw, 822 859 struct ieee80211_vif *vif) 823 860 { ··· 1716 1679 skb_queue_splice_tail_init(&wcid->tx_pending, &list); 1717 1680 spin_unlock(&wcid->tx_pending.lock); 1718 1681 1682 + spin_lock(&wcid->tx_offchannel.lock); 1683 + skb_queue_splice_tail_init(&wcid->tx_offchannel, &list); 1684 + spin_unlock(&wcid->tx_offchannel.lock); 1685 + 1719 1686 spin_unlock_bh(&phy->tx_lock); 1720 1687 1721 1688 while ((skb = __skb_dequeue(&list)) != NULL) { ··· 1731 1690 1732 1691 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid) 1733 1692 { 1734 - if (test_bit(MT76_MCU_RESET, &dev->phy.state)) 1693 + if (test_bit(MT76_MCU_RESET, &dev->phy.state) || !wcid->sta) 1735 1694 return; 1736 1695 1737 1696 spin_lock_bh(&dev->sta_poll_lock);
+1
drivers/net/wireless/mediatek/mt76/mt76.h
··· 1243 1243 struct ieee80211_rate *rates, int n_rates); 1244 1244 void mt76_unregister_device(struct mt76_dev *dev); 1245 1245 void mt76_free_device(struct mt76_dev *dev); 1246 + void mt76_reset_device(struct mt76_dev *dev); 1246 1247 void mt76_unregister_phy(struct mt76_phy *phy); 1247 1248 1248 1249 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size,
+5 -7
drivers/net/wireless/mediatek/mt76/mt7915/mac.c
··· 1460 1460 if (i == 10) 1461 1461 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1462 1462 1463 - spin_lock_bh(&dev->mt76.sta_poll_lock); 1464 - while (!list_empty(&dev->mt76.sta_poll_list)) 1465 - list_del_init(dev->mt76.sta_poll_list.next); 1466 - spin_unlock_bh(&dev->mt76.sta_poll_lock); 1467 - 1468 - memset(dev->mt76.wcid_mask, 0, sizeof(dev->mt76.wcid_mask)); 1469 - dev->mt76.vif_mask = 0; 1470 1463 dev->phy.omac_mask = 0; 1471 1464 if (phy2) 1472 1465 phy2->omac_mask = 0; 1466 + 1467 + mt76_reset_device(&dev->mt76); 1468 + 1469 + INIT_LIST_HEAD(&dev->sta_rc_list); 1470 + INIT_LIST_HEAD(&dev->twt_list); 1473 1471 1474 1472 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1475 1473 dev->mt76.global_wcid.idx = i;
+1 -4
drivers/net/wireless/mediatek/mt76/mt7921/main.c
··· 1459 1459 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1460 1460 return -EOPNOTSUPP; 1461 1461 1462 - /* Avoid beacon loss due to the CAC(Channel Availability Check) time 1463 - * of the AP. 1464 - */ 1465 1462 if (!cfg80211_chandef_usable(hw->wiphy, &chsw->chandef, 1466 - IEEE80211_CHAN_RADAR)) 1463 + IEEE80211_CHAN_DISABLED)) 1467 1464 return -EOPNOTSUPP; 1468 1465 1469 1466 return 0;
+1 -1
drivers/net/wireless/mediatek/mt76/mt7925/mac.c
··· 1449 1449 sta = wcid_to_sta(wcid); 1450 1450 1451 1451 if (sta && likely(e->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1452 - mt76_connac2_tx_check_aggr(sta, txwi); 1452 + mt7925_tx_check_aggr(sta, e->skb, wcid); 1453 1453 1454 1454 skb_pull(e->skb, headroom); 1455 1455 mt76_tx_complete_skb(mdev, e->wcid, e->skb);
+6 -1
drivers/net/wireless/mediatek/mt76/mt7925/main.c
··· 1191 1191 struct mt792x_bss_conf *mconf; 1192 1192 struct mt792x_link_sta *mlink; 1193 1193 1194 + if (vif->type == NL80211_IFTYPE_AP) 1195 + break; 1196 + 1194 1197 link_sta = mt792x_sta_to_link_sta(vif, sta, link_id); 1195 1198 if (!link_sta) 1196 1199 continue; ··· 2072 2069 GFP_KERNEL); 2073 2070 mlink = devm_kzalloc(dev->mt76.dev, sizeof(*mlink), 2074 2071 GFP_KERNEL); 2075 - if (!mconf || !mlink) 2072 + if (!mconf || !mlink) { 2073 + mt792x_mutex_release(dev); 2076 2074 return -ENOMEM; 2075 + } 2077 2076 } 2078 2077 2079 2078 mconfs[link_id] = mconf;
+8 -4
drivers/net/wireless/mediatek/mt76/mt7925/mcu.c
··· 1834 1834 struct tlv *tlv; 1835 1835 u16 eml_cap; 1836 1836 1837 + if (!ieee80211_vif_is_mld(vif)) 1838 + return; 1839 + 1837 1840 tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_EHT_MLD, sizeof(*eht_mld)); 1838 1841 eht_mld = (struct sta_rec_eht_mld *)tlv; 1839 1842 eht_mld->mld_type = 0xff; 1840 - 1841 - if (!ieee80211_vif_is_mld(vif)) 1842 - return; 1843 1843 1844 1844 ext_capa = cfg80211_get_iftype_ext_capa(wiphy, 1845 1845 ieee80211_vif_type_p2p(vif)); ··· 1912 1912 struct mt76_dev *dev = phy->dev; 1913 1913 struct mt792x_bss_conf *mconf; 1914 1914 struct sk_buff *skb; 1915 + int conn_state; 1915 1916 1916 1917 mconf = mt792x_vif_to_link(mvif, info->wcid->link_id); 1917 1918 ··· 1921 1920 if (IS_ERR(skb)) 1922 1921 return PTR_ERR(skb); 1923 1922 1923 + conn_state = info->enable ? CONN_STATE_PORT_SECURE : 1924 + CONN_STATE_DISCONNECT; 1925 + 1924 1926 if (info->enable && info->link_sta) { 1925 1927 mt76_connac_mcu_sta_basic_tlv(dev, skb, info->link_conf, 1926 1928 info->link_sta, 1927 - info->enable, info->newly); 1929 + conn_state, info->newly); 1928 1930 mt7925_mcu_sta_phy_tlv(skb, info->vif, info->link_sta); 1929 1931 mt7925_mcu_sta_ht_tlv(skb, info->link_sta); 1930 1932 mt7925_mcu_sta_vht_tlv(skb, info->link_sta);
+38 -22
drivers/net/wireless/mediatek/mt76/mt7996/mac.c
··· 62 62 int i; 63 63 64 64 wcid = mt76_wcid_ptr(dev, idx); 65 - if (!wcid) 65 + if (!wcid || !wcid->sta) 66 66 return NULL; 67 67 68 68 if (!mt7996_band_valid(dev, band_idx)) ··· 903 903 IEEE80211_TX_CTRL_MLO_LINK); 904 904 905 905 mvif = vif ? (struct mt7996_vif *)vif->drv_priv : NULL; 906 - if (mvif) 907 - mlink = rcu_dereference(mvif->mt76.link[link_id]); 906 + if (mvif) { 907 + if (wcid->offchannel) 908 + mlink = rcu_dereference(mvif->mt76.offchannel_link); 909 + if (!mlink) 910 + mlink = rcu_dereference(mvif->mt76.link[link_id]); 911 + } 908 912 909 913 if (mlink) { 910 914 omac_idx = mlink->omac_idx; ··· 1247 1243 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); 1248 1244 wcid = mt76_wcid_ptr(dev, idx); 1249 1245 sta = wcid_to_sta(wcid); 1250 - if (!sta) 1246 + if (!sta) { 1247 + link_sta = NULL; 1251 1248 goto next; 1249 + } 1252 1250 1253 1251 link_sta = rcu_dereference(sta->link[wcid->link_id]); 1254 1252 if (!link_sta) ··· 1700 1694 static void 1701 1695 mt7996_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1702 1696 { 1703 - struct ieee80211_hw *hw = priv; 1697 + struct ieee80211_bss_conf *link_conf; 1698 + struct mt7996_phy *phy = priv; 1699 + struct mt7996_dev *dev = phy->dev; 1700 + unsigned int link_id; 1701 + 1704 1702 1705 1703 switch (vif->type) { 1706 1704 case NL80211_IFTYPE_MESH_POINT: 1707 1705 case NL80211_IFTYPE_ADHOC: 1708 1706 case NL80211_IFTYPE_AP: 1709 - mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf); 1710 1707 break; 1711 1708 default: 1712 - break; 1709 + return; 1713 1710 } 1711 + 1712 + for_each_vif_active_link(vif, link_conf, link_id) { 1713 + struct mt7996_vif_link *link; 1714 + 1715 + link = mt7996_vif_link(dev, vif, link_id); 1716 + if (!link || link->phy != phy) 1717 + continue; 1718 + 1719 + mt7996_mcu_add_beacon(dev->mt76.hw, vif, link_conf); 1720 + } 1721 + } 1722 + 1723 + void mt7996_mac_update_beacons(struct mt7996_phy *phy) 1724 + { 1725 + ieee80211_iterate_active_interfaces(phy->mt76->hw, 1726 + IEEE80211_IFACE_ITER_RESUME_ALL, 1727 + mt7996_update_vif_beacon, phy); 1714 1728 } 1715 1729 1716 1730 static void ··· 1738 1712 { 1739 1713 struct mt76_phy *phy2, *phy3; 1740 1714 1741 - ieee80211_iterate_active_interfaces(dev->mt76.hw, 1742 - IEEE80211_IFACE_ITER_RESUME_ALL, 1743 - mt7996_update_vif_beacon, dev->mt76.hw); 1715 + mt7996_mac_update_beacons(&dev->phy); 1744 1716 1745 1717 phy2 = dev->mt76.phys[MT_BAND1]; 1746 - if (!phy2) 1747 - return; 1748 - 1749 - ieee80211_iterate_active_interfaces(phy2->hw, 1750 - IEEE80211_IFACE_ITER_RESUME_ALL, 1751 - mt7996_update_vif_beacon, phy2->hw); 1718 + if (phy2) 1719 + mt7996_mac_update_beacons(phy2->priv); 1752 1720 1753 1721 phy3 = dev->mt76.phys[MT_BAND2]; 1754 - if (!phy3) 1755 - return; 1756 - 1757 - ieee80211_iterate_active_interfaces(phy3->hw, 1758 - IEEE80211_IFACE_ITER_RESUME_ALL, 1759 - mt7996_update_vif_beacon, phy3->hw); 1722 + if (phy3) 1723 + mt7996_mac_update_beacons(phy3->priv); 1760 1724 } 1761 1725 1762 1726 void mt7996_tx_token_put(struct mt7996_dev *dev)
+5
drivers/net/wireless/mediatek/mt76/mt7996/main.c
··· 516 516 struct mt7996_phy *phy = mphy->priv; 517 517 int ret; 518 518 519 + if (mphy->offchannel) 520 + mt7996_mac_update_beacons(phy); 521 + 519 522 ret = mt7996_mcu_set_chan_info(phy, UNI_CHANNEL_SWITCH); 520 523 if (ret) 521 524 goto out; ··· 536 533 537 534 mt7996_mac_reset_counters(phy); 538 535 phy->noise = 0; 536 + if (!mphy->offchannel) 537 + mt7996_mac_update_beacons(phy); 539 538 540 539 out: 541 540 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
+10 -5
drivers/net/wireless/mediatek/mt76/mt7996/mcu.c
··· 1879 1879 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 1880 1880 void *data, u16 version) 1881 1881 { 1882 + struct uni_header hdr = {}; 1882 1883 struct ra_fixed_rate *req; 1883 - struct uni_header hdr; 1884 1884 struct sk_buff *skb; 1885 1885 struct tlv *tlv; 1886 1886 int len; ··· 2755 2755 struct ieee80211_bss_conf *link_conf) 2756 2756 { 2757 2757 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2758 - struct mt76_vif_link *mlink = mt76_vif_conf_link(&dev->mt76, vif, link_conf); 2758 + struct mt7996_vif_link *link = mt7996_vif_conf_link(dev, vif, link_conf); 2759 + struct mt76_vif_link *mlink = link ? &link->mt76 : NULL; 2759 2760 struct ieee80211_mutable_offsets offs; 2760 2761 struct ieee80211_tx_info *info; 2761 2762 struct sk_buff *skb, *rskb; 2762 2763 struct tlv *tlv; 2763 2764 struct bss_bcn_content_tlv *bcn; 2764 2765 int len, extra_len = 0; 2766 + bool enabled = link_conf->enable_beacon; 2765 2767 2766 2768 if (link_conf->nontransmitted) 2767 2769 return 0; ··· 2771 2769 if (!mlink) 2772 2770 return -EINVAL; 2773 2771 2772 + if (link->phy && link->phy->mt76->offchannel) 2773 + enabled = false; 2774 + 2774 2775 rskb = __mt7996_mcu_alloc_bss_req(&dev->mt76, mlink, 2775 2776 MT7996_MAX_BSS_OFFLOAD_SIZE); 2776 2777 if (IS_ERR(rskb)) 2777 2778 return PTR_ERR(rskb); 2778 2779 2779 2780 skb = ieee80211_beacon_get_template(hw, vif, &offs, link_conf->link_id); 2780 - if (link_conf->enable_beacon && !skb) { 2781 + if (enabled && !skb) { 2781 2782 dev_kfree_skb(rskb); 2782 2783 return -EINVAL; 2783 2784 } ··· 2799 2794 len = ALIGN(sizeof(*bcn) + MT_TXD_SIZE + extra_len, 4); 2800 2795 tlv = mt7996_mcu_add_uni_tlv(rskb, UNI_BSS_INFO_BCN_CONTENT, len); 2801 2796 bcn = (struct bss_bcn_content_tlv *)tlv; 2802 - bcn->enable = link_conf->enable_beacon; 2797 + bcn->enable = enabled; 2803 2798 if (!bcn->enable) 2804 2799 goto out; 2805 2800 ··· 3377 3372 { 3378 3373 struct { 3379 3374 u8 __rsv[4]; 3380 - } __packed hdr; 3375 + } __packed hdr = {}; 3381 3376 struct hdr_trans_blacklist *req_blacklist; 3382 3377 struct hdr_trans_en *req_en; 3383 3378 struct sk_buff *skb;
+1
drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h
··· 732 732 struct sk_buff *skb, struct mt76_wcid *wcid, 733 733 struct ieee80211_key_conf *key, int pid, 734 734 enum mt76_txq_id qid, u32 changed); 735 + void mt7996_mac_update_beacons(struct mt7996_phy *phy); 735 736 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 736 737 void mt7996_mac_work(struct work_struct *work); 737 738 void mt7996_mac_reset_work(struct work_struct *work);
+6 -6
drivers/net/wireless/mediatek/mt76/tx.c
··· 332 332 struct mt76_wcid *wcid, struct sk_buff *skb) 333 333 { 334 334 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 335 + struct ieee80211_hdr *hdr = (void *)skb->data; 335 336 struct sk_buff_head *head; 336 337 337 338 if (mt76_testmode_enabled(phy)) { ··· 350 349 info->hw_queue |= FIELD_PREP(MT_TX_HW_QUEUE_PHY, phy->band_idx); 351 350 352 351 if ((info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) || 353 - (info->control.flags & IEEE80211_TX_CTRL_DONT_USE_RATE_MASK)) 352 + ((info->control.flags & IEEE80211_TX_CTRL_DONT_USE_RATE_MASK) && 353 + ieee80211_is_probe_req(hdr->frame_control))) 354 354 head = &wcid->tx_offchannel; 355 355 else 356 356 head = &wcid->tx_pending; ··· 646 644 static void mt76_txq_schedule_pending(struct mt76_phy *phy) 647 645 { 648 646 LIST_HEAD(tx_list); 647 + int ret = 0; 649 648 650 649 if (list_empty(&phy->tx_list)) 651 650 return; ··· 658 655 list_splice_init(&phy->tx_list, &tx_list); 659 656 while (!list_empty(&tx_list)) { 660 657 struct mt76_wcid *wcid; 661 - int ret; 662 658 663 659 wcid = list_first_entry(&tx_list, struct mt76_wcid, tx_list); 664 660 list_del_init(&wcid->tx_list); 665 661 666 662 spin_unlock(&phy->tx_lock); 667 - ret = mt76_txq_schedule_pending_wcid(phy, wcid, &wcid->tx_offchannel); 663 + if (ret >= 0) 664 + ret = mt76_txq_schedule_pending_wcid(phy, wcid, &wcid->tx_offchannel); 668 665 if (ret >= 0 && !phy->offchannel) 669 666 ret = mt76_txq_schedule_pending_wcid(phy, wcid, &wcid->tx_pending); 670 667 spin_lock(&phy->tx_lock); ··· 673 670 !skb_queue_empty(&wcid->tx_offchannel) && 674 671 list_empty(&wcid->tx_list)) 675 672 list_add_tail(&wcid->tx_list, &phy->tx_list); 676 - 677 - if (ret < 0) 678 - break; 679 673 } 680 674 spin_unlock(&phy->tx_lock); 681 675
+28 -11
drivers/net/wireless/microchip/wilc1000/wlan_cfg.c
··· 41 41 }; 42 42 43 43 static const struct wilc_cfg_str g_cfg_str[] = { 44 - {WID_FIRMWARE_VERSION, NULL}, 45 - {WID_MAC_ADDR, NULL}, 46 - {WID_ASSOC_RES_INFO, NULL}, 47 - {WID_NIL, NULL} 44 + {WID_FIRMWARE_VERSION, 0, NULL}, 45 + {WID_MAC_ADDR, 0, NULL}, 46 + {WID_ASSOC_RES_INFO, 0, NULL}, 47 + {WID_NIL, 0, NULL} 48 48 }; 49 49 50 50 #define WILC_RESP_MSG_TYPE_CONFIG_REPLY 'R' ··· 147 147 148 148 switch (FIELD_GET(WILC_WID_TYPE, wid)) { 149 149 case WID_CHAR: 150 + len = 3; 151 + if (len + 2 > size) 152 + return; 153 + 150 154 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) 151 155 i++; 152 156 153 157 if (cfg->b[i].id == wid) 154 158 cfg->b[i].val = info[4]; 155 159 156 - len = 3; 157 160 break; 158 161 159 162 case WID_SHORT: 163 + len = 4; 164 + if (len + 2 > size) 165 + return; 166 + 160 167 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) 161 168 i++; 162 169 163 170 if (cfg->hw[i].id == wid) 164 171 cfg->hw[i].val = get_unaligned_le16(&info[4]); 165 172 166 - len = 4; 167 173 break; 168 174 169 175 case WID_INT: 176 + len = 6; 177 + if (len + 2 > size) 178 + return; 179 + 170 180 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) 171 181 i++; 172 182 173 183 if (cfg->w[i].id == wid) 174 184 cfg->w[i].val = get_unaligned_le32(&info[4]); 175 185 176 - len = 6; 177 186 break; 178 187 179 188 case WID_STR: 189 + len = 2 + get_unaligned_le16(&info[2]); 190 + 180 191 while (cfg->s[i].id != WID_NIL && cfg->s[i].id != wid) 181 192 i++; 182 193 183 - if (cfg->s[i].id == wid) 184 - memcpy(cfg->s[i].str, &info[2], 185 - get_unaligned_le16(&info[2]) + 2); 194 + if (cfg->s[i].id == wid) { 195 + if (len > cfg->s[i].len || (len + 2 > size)) 196 + return; 186 197 187 - len = 2 + get_unaligned_le16(&info[2]); 198 + memcpy(cfg->s[i].str, &info[2], 199 + len); 200 + } 201 + 188 202 break; 189 203 190 204 default: ··· 398 384 /* store the string cfg parameters */ 399 385 wl->cfg.s[i].id = WID_FIRMWARE_VERSION; 400 386 wl->cfg.s[i].str = str_vals->firmware_version; 387 + wl->cfg.s[i].len = sizeof(str_vals->firmware_version); 401 388 i++; 402 389 wl->cfg.s[i].id = WID_MAC_ADDR; 403 390 wl->cfg.s[i].str = str_vals->mac_address; 391 + wl->cfg.s[i].len = sizeof(str_vals->mac_address); 404 392 i++; 405 393 wl->cfg.s[i].id = WID_ASSOC_RES_INFO; 406 394 wl->cfg.s[i].str = str_vals->assoc_rsp; 395 + wl->cfg.s[i].len = sizeof(str_vals->assoc_rsp); 407 396 i++; 408 397 wl->cfg.s[i].id = WID_NIL; 409 398 wl->cfg.s[i].str = NULL;
+3 -2
drivers/net/wireless/microchip/wilc1000/wlan_cfg.h
··· 24 24 25 25 struct wilc_cfg_str { 26 26 u16 id; 27 + u16 len; 27 28 u8 *str; 28 29 }; 29 30 30 31 struct wilc_cfg_str_vals { 31 - u8 mac_address[7]; 32 - u8 firmware_version[129]; 32 + u8 mac_address[8]; 33 + u8 firmware_version[130]; 33 34 u8 assoc_rsp[WILC_MAX_ASSOC_RESP_FRAME_SIZE]; 34 35 }; 35 36
+2 -2
drivers/net/wireless/ralink/rt2x00/Kconfig
··· 66 66 select RT2X00_LIB_PCI 67 67 select RT2X00_LIB_FIRMWARE 68 68 select RT2X00_LIB_CRYPTO 69 - select CRC_CCITT 70 69 select EEPROM_93CX6 71 70 help 72 71 This adds support for rt27xx/rt28xx/rt30xx wireless chipset family. ··· 141 142 select RT2X00_LIB_USB 142 143 select RT2X00_LIB_FIRMWARE 143 144 select RT2X00_LIB_CRYPTO 144 - select CRC_CCITT 145 145 help 146 146 This adds support for rt27xx/rt28xx/rt30xx wireless chipset family. 147 147 Supported chips: RT2770, RT2870 & RT3070, RT3071 & RT3072 ··· 215 217 216 218 config RT2800_LIB 217 219 tristate 220 + select CRC_CCITT 218 221 219 222 config RT2800_LIB_MMIO 220 223 tristate ··· 224 225 225 226 config RT2X00_LIB_MMIO 226 227 tristate 228 + select RT2X00_LIB 227 229 228 230 config RT2X00_LIB_PCI 229 231 tristate
+1 -1
drivers/net/wireless/st/cw1200/sta.c
··· 1291 1291 rcu_read_lock(); 1292 1292 ssidie = ieee80211_bss_get_ie(bss, WLAN_EID_SSID); 1293 1293 if (ssidie) { 1294 - join.ssid_len = ssidie[1]; 1294 + join.ssid_len = min(ssidie[1], IEEE80211_MAX_SSID_LEN); 1295 1295 memcpy(join.ssid, &ssidie[2], join.ssid_len); 1296 1296 } 1297 1297 rcu_read_unlock();
+4 -1
drivers/of/of_numa.c
··· 59 59 r = -EINVAL; 60 60 } 61 61 62 - for (i = 0; !r && !of_address_to_resource(np, i, &rsrc); i++) 62 + for (i = 0; !r && !of_address_to_resource(np, i, &rsrc); i++) { 63 63 r = numa_add_memblk(nid, rsrc.start, rsrc.end + 1); 64 + if (!r) 65 + node_set(nid, numa_nodes_parsed); 66 + } 64 67 65 68 if (!i || r) { 66 69 of_node_put(np);
+1 -2
drivers/ptp/ptp_ocp.c
··· 4557 4557 ptp_ocp_debugfs_remove_device(bp); 4558 4558 ptp_ocp_detach_sysfs(bp); 4559 4559 ptp_ocp_attr_group_del(bp); 4560 - if (timer_pending(&bp->watchdog)) 4561 - timer_delete_sync(&bp->watchdog); 4560 + timer_delete_sync(&bp->watchdog); 4562 4561 if (bp->ts0) 4563 4562 ptp_ocp_unregister_ext(bp->ts0); 4564 4563 if (bp->ts1)
+1 -1
drivers/regulator/qcom-pm8008-regulator.c
··· 96 96 97 97 uV = le16_to_cpu(val) * 1000; 98 98 99 - return (uV - preg->desc.min_uV) / preg->desc.uV_step; 99 + return regulator_map_voltage_linear_range(rdev, uV, INT_MAX); 100 100 } 101 101 102 102 static const struct regulator_ops pm8008_regulator_ops = {
+7 -5
drivers/soc/qcom/mdt_loader.c
··· 39 39 if (phend > fw->size) 40 40 return false; 41 41 42 - if (ehdr->e_shentsize != sizeof(struct elf32_shdr)) 43 - return false; 42 + if (ehdr->e_shentsize || ehdr->e_shnum) { 43 + if (ehdr->e_shentsize != sizeof(struct elf32_shdr)) 44 + return false; 44 45 45 - shend = size_add(size_mul(sizeof(struct elf32_shdr), ehdr->e_shnum), ehdr->e_shoff); 46 - if (shend > fw->size) 47 - return false; 46 + shend = size_add(size_mul(sizeof(struct elf32_shdr), ehdr->e_shnum), ehdr->e_shoff); 47 + if (shend > fw->size) 48 + return false; 49 + } 48 50 49 51 return true; 50 52 }
+20 -3
drivers/soc/qcom/ubwc_config.c
··· 12 12 13 13 #include <linux/soc/qcom/ubwc.h> 14 14 15 + static const struct qcom_ubwc_cfg_data no_ubwc_data = { 16 + /* no UBWC, no HBB */ 17 + }; 18 + 15 19 static const struct qcom_ubwc_cfg_data msm8937_data = { 16 20 .ubwc_enc_version = UBWC_1_0, 17 21 .ubwc_dec_version = UBWC_1_0, ··· 219 215 }; 220 216 221 217 static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { 218 + { .compatible = "qcom,apq8016", .data = &no_ubwc_data }, 219 + { .compatible = "qcom,apq8026", .data = &no_ubwc_data }, 220 + { .compatible = "qcom,apq8074", .data = &no_ubwc_data }, 222 221 { .compatible = "qcom,apq8096", .data = &msm8998_data }, 223 - { .compatible = "qcom,msm8917", .data = &msm8937_data }, 222 + { .compatible = "qcom,msm8226", .data = &no_ubwc_data }, 223 + { .compatible = "qcom,msm8916", .data = &no_ubwc_data }, 224 + { .compatible = "qcom,msm8917", .data = &no_ubwc_data }, 224 225 { .compatible = "qcom,msm8937", .data = &msm8937_data }, 226 + { .compatible = "qcom,msm8929", .data = &no_ubwc_data }, 227 + { .compatible = "qcom,msm8939", .data = &no_ubwc_data }, 225 228 { .compatible = "qcom,msm8953", .data = &msm8937_data }, 226 - { .compatible = "qcom,msm8956", .data = &msm8937_data }, 227 - { .compatible = "qcom,msm8976", .data = &msm8937_data }, 229 + { .compatible = "qcom,msm8956", .data = &no_ubwc_data }, 230 + { .compatible = "qcom,msm8974", .data = &no_ubwc_data }, 231 + { .compatible = "qcom,msm8976", .data = &no_ubwc_data }, 228 232 { .compatible = "qcom,msm8996", .data = &msm8998_data }, 229 233 { .compatible = "qcom,msm8998", .data = &msm8998_data }, 230 234 { .compatible = "qcom,qcm2290", .data = &qcm2290_data, }, ··· 245 233 { .compatible = "qcom,sc7280", .data = &sc7280_data, }, 246 234 { .compatible = "qcom,sc8180x", .data = &sc8180x_data, }, 247 235 { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, }, 236 + { .compatible = "qcom,sda660", .data = &msm8937_data }, 237 + { .compatible = "qcom,sdm450", .data = &msm8937_data }, 248 238 { .compatible = "qcom,sdm630", .data = &msm8937_data }, 239 + { .compatible = "qcom,sdm632", .data = &msm8937_data }, 249 240 { .compatible = "qcom,sdm636", .data = &msm8937_data }, 250 241 { .compatible = "qcom,sdm660", .data = &msm8937_data }, 251 242 { .compatible = "qcom,sdm670", .data = &sdm670_data, }, ··· 261 246 { .compatible = "qcom,sm6375", .data = &sm6350_data, }, 262 247 { .compatible = "qcom,sm7125", .data = &sc7180_data }, 263 248 { .compatible = "qcom,sm7150", .data = &sm7150_data, }, 249 + { .compatible = "qcom,sm7225", .data = &sm6350_data, }, 250 + { .compatible = "qcom,sm7325", .data = &sc7280_data, }, 264 251 { .compatible = "qcom,sm8150", .data = &sm8150_data, }, 265 252 { .compatible = "qcom,sm8250", .data = &sm8250_data, }, 266 253 { .compatible = "qcom,sm8350", .data = &sm8350_data, },
+2 -2
drivers/tee/optee/ffa_abi.c
··· 657 657 * with a matching configuration. 658 658 */ 659 659 660 - static bool optee_ffa_api_is_compatbile(struct ffa_device *ffa_dev, 660 + static bool optee_ffa_api_is_compatible(struct ffa_device *ffa_dev, 661 661 const struct ffa_ops *ops) 662 662 { 663 663 const struct ffa_msg_ops *msg_ops = ops->msg_ops; ··· 908 908 ffa_ops = ffa_dev->ops; 909 909 notif_ops = ffa_ops->notifier_ops; 910 910 911 - if (!optee_ffa_api_is_compatbile(ffa_dev, ffa_ops)) 911 + if (!optee_ffa_api_is_compatible(ffa_dev, ffa_ops)) 912 912 return -EINVAL; 913 913 914 914 if (!optee_ffa_exchange_caps(ffa_dev, ffa_ops, &sec_caps,
+10 -4
drivers/tee/tee_shm.c
··· 230 230 pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL); 231 231 if (!pages) { 232 232 rc = -ENOMEM; 233 - goto err; 233 + goto err_pages; 234 234 } 235 235 236 236 for (i = 0; i < nr_pages; i++) ··· 243 243 rc = shm_register(shm->ctx, shm, pages, nr_pages, 244 244 (unsigned long)shm->kaddr); 245 245 if (rc) 246 - goto err; 246 + goto err_kfree; 247 247 } 248 248 249 249 return 0; 250 - err: 250 + err_kfree: 251 + kfree(pages); 252 + err_pages: 251 253 free_pages_exact(shm->kaddr, shm->size); 252 254 shm->kaddr = NULL; 253 255 return rc; ··· 562 560 */ 563 561 void tee_shm_put(struct tee_shm *shm) 564 562 { 565 - struct tee_device *teedev = shm->ctx->teedev; 563 + struct tee_device *teedev; 566 564 bool do_release = false; 567 565 566 + if (!shm || !shm->ctx || !shm->ctx->teedev) 567 + return; 568 + 569 + teedev = shm->ctx->teedev; 568 570 mutex_lock(&teedev->mutex); 569 571 if (refcount_dec_and_test(&shm->refcount)) { 570 572 /*
+1 -1
fs/btrfs/btrfs_inode.h
··· 248 248 u64 new_delalloc_bytes; 249 249 /* 250 250 * The offset of the last dir index key that was logged. 251 - * This is used only for directories. 251 + * This is used only for directories. Protected by 'log_mutex'. 252 252 */ 253 253 u64 last_dir_index_offset; 254 254 };
+25 -25
fs/btrfs/inode.c
··· 6805 6805 struct fscrypt_name fname; 6806 6806 u64 index; 6807 6807 int ret; 6808 - int drop_inode = 0; 6809 6808 6810 6809 /* do not allow sys_link's with other subvols of the same device */ 6811 6810 if (btrfs_root_id(root) != btrfs_root_id(BTRFS_I(inode)->root)) ··· 6836 6837 6837 6838 /* There are several dir indexes for this inode, clear the cache. */ 6838 6839 BTRFS_I(inode)->dir_index = 0ULL; 6839 - inc_nlink(inode); 6840 6840 inode_inc_iversion(inode); 6841 6841 inode_set_ctime_current(inode); 6842 - ihold(inode); 6843 6842 set_bit(BTRFS_INODE_COPY_EVERYTHING, &BTRFS_I(inode)->runtime_flags); 6844 6843 6845 6844 ret = btrfs_add_link(trans, BTRFS_I(dir), BTRFS_I(inode), 6846 6845 &fname.disk_name, 1, index); 6846 + if (ret) 6847 + goto fail; 6847 6848 6849 + /* Link added now we update the inode item with the new link count. */ 6850 + inc_nlink(inode); 6851 + ret = btrfs_update_inode(trans, BTRFS_I(inode)); 6848 6852 if (ret) { 6849 - drop_inode = 1; 6850 - } else { 6851 - struct dentry *parent = dentry->d_parent; 6852 - 6853 - ret = btrfs_update_inode(trans, BTRFS_I(inode)); 6854 - if (ret) 6855 - goto fail; 6856 - if (inode->i_nlink == 1) { 6857 - /* 6858 - * If new hard link count is 1, it's a file created 6859 - * with open(2) O_TMPFILE flag. 6860 - */ 6861 - ret = btrfs_orphan_del(trans, BTRFS_I(inode)); 6862 - if (ret) 6863 - goto fail; 6864 - } 6865 - d_instantiate(dentry, inode); 6866 - btrfs_log_new_name(trans, old_dentry, NULL, 0, parent); 6853 + btrfs_abort_transaction(trans, ret); 6854 + goto fail; 6867 6855 } 6856 + 6857 + if (inode->i_nlink == 1) { 6858 + /* 6859 + * If the new hard link count is 1, it's a file created with the 6860 + * open(2) O_TMPFILE flag. 6861 + */ 6862 + ret = btrfs_orphan_del(trans, BTRFS_I(inode)); 6863 + if (ret) { 6864 + btrfs_abort_transaction(trans, ret); 6865 + goto fail; 6866 + } 6867 + } 6868 + 6869 + /* Grab reference for the new dentry passed to d_instantiate(). */ 6870 + ihold(inode); 6871 + d_instantiate(dentry, inode); 6872 + btrfs_log_new_name(trans, old_dentry, NULL, 0, dentry->d_parent); 6868 6873 6869 6874 fail: 6870 6875 fscrypt_free_filename(&fname); 6871 6876 if (trans) 6872 6877 btrfs_end_transaction(trans); 6873 - if (drop_inode) { 6874 - inode_dec_link_count(inode); 6875 - iput(inode); 6876 - } 6877 6878 btrfs_btree_balance_dirty(fs_info); 6878 6879 return ret; 6879 6880 } ··· 7829 7830 ei->last_sub_trans = 0; 7830 7831 ei->logged_trans = 0; 7831 7832 ei->delalloc_bytes = 0; 7833 + /* new_delalloc_bytes and last_dir_index_offset are in a union. */ 7832 7834 ei->new_delalloc_bytes = 0; 7833 7835 ei->defrag_bytes = 0; 7834 7836 ei->disk_i_size = 0;
+53 -25
fs/btrfs/tree-log.c
··· 3340 3340 return 0; 3341 3341 } 3342 3342 3343 + static bool mark_inode_as_not_logged(const struct btrfs_trans_handle *trans, 3344 + struct btrfs_inode *inode) 3345 + { 3346 + bool ret = false; 3347 + 3348 + /* 3349 + * Do this only if ->logged_trans is still 0 to prevent races with 3350 + * concurrent logging as we may see the inode not logged when 3351 + * inode_logged() is called but it gets logged after inode_logged() did 3352 + * not find it in the log tree and we end up setting ->logged_trans to a 3353 + * value less than trans->transid after the concurrent logging task has 3354 + * set it to trans->transid. As a consequence, subsequent rename, unlink 3355 + * and link operations may end up not logging new names and removing old 3356 + * names from the log. 3357 + */ 3358 + spin_lock(&inode->lock); 3359 + if (inode->logged_trans == 0) 3360 + inode->logged_trans = trans->transid - 1; 3361 + else if (inode->logged_trans == trans->transid) 3362 + ret = true; 3363 + spin_unlock(&inode->lock); 3364 + 3365 + return ret; 3366 + } 3367 + 3343 3368 /* 3344 3369 * Check if an inode was logged in the current transaction. This correctly deals 3345 3370 * with the case where the inode was logged but has a logged_trans of 0, which ··· 3382 3357 struct btrfs_key key; 3383 3358 int ret; 3384 3359 3385 - if (inode->logged_trans == trans->transid) 3360 + /* 3361 + * Quick lockless call, since once ->logged_trans is set to the current 3362 + * transaction, we never set it to a lower value anywhere else. 3363 + */ 3364 + if (data_race(inode->logged_trans) == trans->transid) 3386 3365 return 1; 3387 3366 3388 3367 /* 3389 - * If logged_trans is not 0, then we know the inode logged was not logged 3390 - * in this transaction, so we can return false right away. 3368 + * If logged_trans is not 0 and not trans->transid, then we know the 3369 + * inode was not logged in this transaction, so we can return false 3370 + * right away. We take the lock to avoid a race caused by load/store 3371 + * tearing with a concurrent btrfs_log_inode() call or a concurrent task 3372 + * in this function further below - an update to trans->transid can be 3373 + * teared into two 32 bits updates for example, in which case we could 3374 + * see a positive value that is not trans->transid and assume the inode 3375 + * was not logged when it was. 3391 3376 */ 3392 - if (inode->logged_trans > 0) 3377 + spin_lock(&inode->lock); 3378 + if (inode->logged_trans == trans->transid) { 3379 + spin_unlock(&inode->lock); 3380 + return 1; 3381 + } else if (inode->logged_trans > 0) { 3382 + spin_unlock(&inode->lock); 3393 3383 return 0; 3384 + } 3385 + spin_unlock(&inode->lock); 3394 3386 3395 3387 /* 3396 3388 * If no log tree was created for this root in this transaction, then ··· 3416 3374 * transaction's ID, to avoid the search below in a future call in case 3417 3375 * a log tree gets created after this. 3418 3376 */ 3419 - if (!test_bit(BTRFS_ROOT_HAS_LOG_TREE, &inode->root->state)) { 3420 - inode->logged_trans = trans->transid - 1; 3421 - return 0; 3422 - } 3377 + if (!test_bit(BTRFS_ROOT_HAS_LOG_TREE, &inode->root->state)) 3378 + return mark_inode_as_not_logged(trans, inode); 3423 3379 3424 3380 /* 3425 3381 * We have a log tree and the inode's logged_trans is 0. We can't tell ··· 3471 3431 * Set logged_trans to a value greater than 0 and less then the 3472 3432 * current transaction to avoid doing the search in future calls. 3473 3433 */ 3474 - inode->logged_trans = trans->transid - 1; 3475 - return 0; 3434 + return mark_inode_as_not_logged(trans, inode); 3476 3435 } 3477 3436 3478 3437 /* ··· 3479 3440 * the current transacion's ID, to avoid future tree searches as long as 3480 3441 * the inode is not evicted again. 3481 3442 */ 3443 + spin_lock(&inode->lock); 3482 3444 inode->logged_trans = trans->transid; 3483 - 3484 - /* 3485 - * If it's a directory, then we must set last_dir_index_offset to the 3486 - * maximum possible value, so that the next attempt to log the inode does 3487 - * not skip checking if dir index keys found in modified subvolume tree 3488 - * leaves have been logged before, otherwise it would result in attempts 3489 - * to insert duplicate dir index keys in the log tree. This must be done 3490 - * because last_dir_index_offset is an in-memory only field, not persisted 3491 - * in the inode item or any other on-disk structure, so its value is lost 3492 - * once the inode is evicted. 3493 - */ 3494 - if (S_ISDIR(inode->vfs_inode.i_mode)) 3495 - inode->last_dir_index_offset = (u64)-1; 3445 + spin_unlock(&inode->lock); 3496 3446 3497 3447 return 1; 3498 3448 } ··· 4073 4045 4074 4046 /* 4075 4047 * If the inode was logged before and it was evicted, then its 4076 - * last_dir_index_offset is (u64)-1, so we don't the value of the last index 4048 + * last_dir_index_offset is 0, so we don't know the value of the last index 4077 4049 * key offset. If that's the case, search for it and update the inode. This 4078 4050 * is to avoid lookups in the log tree every time we try to insert a dir index 4079 4051 * key from a leaf changed in the current transaction, and to allow us to always ··· 4089 4061 4090 4062 lockdep_assert_held(&inode->log_mutex); 4091 4063 4092 - if (inode->last_dir_index_offset != (u64)-1) 4064 + if (inode->last_dir_index_offset != 0) 4093 4065 return 0; 4094 4066 4095 4067 if (!ctx->logged_before) {
+4
fs/efivarfs/super.c
··· 152 152 { 153 153 int guid = len - EFI_VARIABLE_GUID_LEN; 154 154 155 + /* Parallel lookups may produce a temporary invalid filename */ 156 + if (guid <= 0) 157 + return 1; 158 + 155 159 if (name->len != len) 156 160 return 1; 157 161
+3
fs/ocfs2/inode.c
··· 1281 1281 * the journal is flushed before journal shutdown. Thus it is safe to 1282 1282 * have inodes get cleaned up after journal shutdown. 1283 1283 */ 1284 + if (!osb->journal) 1285 + return; 1286 + 1284 1287 jbd2_journal_release_jbd_inode(osb->journal->j_journal, 1285 1288 &oi->ip_jinode); 1286 1289 }
+21 -17
fs/proc/generic.c
··· 367 367 .setattr = proc_notify_change, 368 368 }; 369 369 370 + static void pde_set_flags(struct proc_dir_entry *pde) 371 + { 372 + const struct proc_ops *proc_ops = pde->proc_ops; 373 + 374 + if (!proc_ops) 375 + return; 376 + 377 + if (proc_ops->proc_flags & PROC_ENTRY_PERMANENT) 378 + pde->flags |= PROC_ENTRY_PERMANENT; 379 + if (proc_ops->proc_read_iter) 380 + pde->flags |= PROC_ENTRY_proc_read_iter; 381 + #ifdef CONFIG_COMPAT 382 + if (proc_ops->proc_compat_ioctl) 383 + pde->flags |= PROC_ENTRY_proc_compat_ioctl; 384 + #endif 385 + if (proc_ops->proc_lseek) 386 + pde->flags |= PROC_ENTRY_proc_lseek; 387 + } 388 + 370 389 /* returns the registered entry, or frees dp and returns NULL on failure */ 371 390 struct proc_dir_entry *proc_register(struct proc_dir_entry *dir, 372 391 struct proc_dir_entry *dp) 373 392 { 374 393 if (proc_alloc_inum(&dp->low_ino)) 375 394 goto out_free_entry; 395 + 396 + pde_set_flags(dp); 376 397 377 398 write_lock(&proc_subdir_lock); 378 399 dp->parent = dir; ··· 582 561 return p; 583 562 } 584 563 585 - static void pde_set_flags(struct proc_dir_entry *pde) 586 - { 587 - if (pde->proc_ops->proc_flags & PROC_ENTRY_PERMANENT) 588 - pde->flags |= PROC_ENTRY_PERMANENT; 589 - if (pde->proc_ops->proc_read_iter) 590 - pde->flags |= PROC_ENTRY_proc_read_iter; 591 - #ifdef CONFIG_COMPAT 592 - if (pde->proc_ops->proc_compat_ioctl) 593 - pde->flags |= PROC_ENTRY_proc_compat_ioctl; 594 - #endif 595 - if (pde->proc_ops->proc_lseek) 596 - pde->flags |= PROC_ENTRY_proc_lseek; 597 - } 598 - 599 564 struct proc_dir_entry *proc_create_data(const char *name, umode_t mode, 600 565 struct proc_dir_entry *parent, 601 566 const struct proc_ops *proc_ops, void *data) ··· 592 585 if (!p) 593 586 return NULL; 594 587 p->proc_ops = proc_ops; 595 - pde_set_flags(p); 596 588 return proc_register(parent, p); 597 589 } 598 590 EXPORT_SYMBOL(proc_create_data); ··· 642 636 p->proc_ops = &proc_seq_ops; 643 637 p->seq_ops = ops; 644 638 p->state_size = state_size; 645 - pde_set_flags(p); 646 639 return proc_register(parent, p); 647 640 } 648 641 EXPORT_SYMBOL(proc_create_seq_private); ··· 672 667 return NULL; 673 668 p->proc_ops = &proc_single_ops; 674 669 p->single_show = show; 675 - pde_set_flags(p); 676 670 return proc_register(parent, p); 677 671 } 678 672 EXPORT_SYMBOL(proc_create_single_data);
+14
fs/smb/client/cifsfs.c
··· 1358 1358 truncate_setsize(target_inode, new_size); 1359 1359 fscache_resize_cookie(cifs_inode_cookie(target_inode), 1360 1360 new_size); 1361 + } else if (rc == -EOPNOTSUPP) { 1362 + /* 1363 + * copy_file_range syscall man page indicates EINVAL 1364 + * is returned e.g when "fd_in and fd_out refer to the 1365 + * same file and the source and target ranges overlap." 1366 + * Test generic/157 was what showed these cases where 1367 + * we need to remap EOPNOTSUPP to EINVAL 1368 + */ 1369 + if (off >= src_inode->i_size) { 1370 + rc = -EINVAL; 1371 + } else if (src_inode == target_inode) { 1372 + if (off + len > destoff) 1373 + rc = -EINVAL; 1374 + } 1361 1375 } 1362 1376 if (rc == 0 && new_size > target_cifsi->netfs.zero_point) 1363 1377 target_cifsi->netfs.zero_point = new_size;
+5 -2
fs/smb/client/smb2inode.c
··· 207 207 server = cifs_pick_channel(ses); 208 208 209 209 vars = kzalloc(sizeof(*vars), GFP_ATOMIC); 210 - if (vars == NULL) 211 - return -ENOMEM; 210 + if (vars == NULL) { 211 + rc = -ENOMEM; 212 + goto out; 213 + } 212 214 rqst = &vars->rqst[0]; 213 215 rsp_iov = &vars->rsp_iov[0]; 214 216 ··· 866 864 smb2_should_replay(tcon, &retries, &cur_sleep)) 867 865 goto replay_again; 868 866 867 + out: 869 868 if (cfile) 870 869 cifsFileInfo_put(cfile); 871 870
+14 -11
fs/smb/server/smb2pdu.c
··· 2951 2951 } 2952 2952 2953 2953 ksmbd_debug(SMB, "converted name = %s\n", name); 2954 - if (strchr(name, ':')) { 2955 - if (!test_share_config_flag(work->tcon->share_conf, 2956 - KSMBD_SHARE_FLAG_STREAMS)) { 2957 - rc = -EBADF; 2958 - goto err_out2; 2959 - } 2960 - rc = parse_stream_name(name, &stream_name, &s_type); 2961 - if (rc < 0) 2962 - goto err_out2; 2963 - } 2964 2954 2965 2955 if (posix_ctxt == false) { 2956 + if (strchr(name, ':')) { 2957 + if (!test_share_config_flag(work->tcon->share_conf, 2958 + KSMBD_SHARE_FLAG_STREAMS)) { 2959 + rc = -EBADF; 2960 + goto err_out2; 2961 + } 2962 + rc = parse_stream_name(name, &stream_name, &s_type); 2963 + if (rc < 0) 2964 + goto err_out2; 2965 + } 2966 + 2966 2967 rc = ksmbd_validate_filename(name); 2967 2968 if (rc < 0) 2968 2969 goto err_out2; ··· 3443 3442 3444 3443 fp->attrib_only = !(req->DesiredAccess & ~(FILE_READ_ATTRIBUTES_LE | 3445 3444 FILE_WRITE_ATTRIBUTES_LE | FILE_SYNCHRONIZE_LE)); 3445 + 3446 + fp->is_posix_ctxt = posix_ctxt; 3446 3447 3447 3448 /* fp should be searchable through ksmbd_inode.m_fp_list 3448 3449 * after daccess, saccess, attrib_only, and stream are ··· 5991 5988 if (IS_ERR(new_name)) 5992 5989 return PTR_ERR(new_name); 5993 5990 5994 - if (strchr(new_name, ':')) { 5991 + if (fp->is_posix_ctxt == false && strchr(new_name, ':')) { 5995 5992 int s_type; 5996 5993 char *xattr_stream_name, *stream_name = NULL; 5997 5994 size_t xattr_stream_size;
+2
fs/smb/server/vfs_cache.h
··· 112 112 bool is_durable; 113 113 bool is_persistent; 114 114 bool is_resilient; 115 + 116 + bool is_posix_ctxt; 115 117 }; 116 118 117 119 static inline void set_ctx_actor(struct dir_context *ctx,
+1
fs/xfs/Kconfig
··· 105 105 config XFS_RT 106 106 bool "XFS Realtime subvolume support" 107 107 depends on XFS_FS 108 + default BLK_DEV_ZONED 108 109 help 109 110 If you say Y here you will be able to mount and use XFS filesystems 110 111 which contain a realtime subvolume. The realtime subvolume is a
+7
fs/xfs/libxfs/xfs_attr_remote.c
··· 435 435 0, &bp, &xfs_attr3_rmt_buf_ops); 436 436 if (xfs_metadata_is_sick(error)) 437 437 xfs_dirattr_mark_sick(args->dp, XFS_ATTR_FORK); 438 + /* 439 + * ENODATA from disk implies a disk medium failure; 440 + * ENODATA for xattrs means attribute not found, so 441 + * disambiguate that here. 442 + */ 443 + if (error == -ENODATA) 444 + error = -EIO; 438 445 if (error) 439 446 return error; 440 447
+6
fs/xfs/libxfs/xfs_da_btree.c
··· 2833 2833 &bp, ops); 2834 2834 if (xfs_metadata_is_sick(error)) 2835 2835 xfs_dirattr_mark_sick(dp, whichfork); 2836 + /* 2837 + * ENODATA from disk implies a disk medium failure; ENODATA for 2838 + * xattrs means attribute not found, so disambiguate that here. 2839 + */ 2840 + if (error == -ENODATA && whichfork == XFS_ATTR_FORK) 2841 + error = -EIO; 2836 2842 if (error) 2837 2843 goto out_free; 2838 2844
+3
fs/xfs/xfs_aops.c
··· 760 760 { 761 761 struct xfs_inode *ip = XFS_I(file_inode(swap_file)); 762 762 763 + if (xfs_is_zoned_inode(ip)) 764 + return -EINVAL; 765 + 763 766 /* 764 767 * Swap file activation can race against concurrent shared extent 765 768 * removal in files that have been cloned. If this happens,
+2 -43
fs/xfs/xfs_zone_alloc.c
··· 374 374 return 0; 375 375 } 376 376 377 - /* 378 - * Check if the zone containing the data just before the offset we are 379 - * writing to is still open and has space. 380 - */ 381 - static struct xfs_open_zone * 382 - xfs_last_used_zone( 383 - struct iomap_ioend *ioend) 384 - { 385 - struct xfs_inode *ip = XFS_I(ioend->io_inode); 386 - struct xfs_mount *mp = ip->i_mount; 387 - xfs_fileoff_t offset_fsb = XFS_B_TO_FSB(mp, ioend->io_offset); 388 - struct xfs_rtgroup *rtg = NULL; 389 - struct xfs_open_zone *oz = NULL; 390 - struct xfs_iext_cursor icur; 391 - struct xfs_bmbt_irec got; 392 - 393 - xfs_ilock(ip, XFS_ILOCK_SHARED); 394 - if (!xfs_iext_lookup_extent_before(ip, &ip->i_df, &offset_fsb, 395 - &icur, &got)) { 396 - xfs_iunlock(ip, XFS_ILOCK_SHARED); 397 - return NULL; 398 - } 399 - xfs_iunlock(ip, XFS_ILOCK_SHARED); 400 - 401 - rtg = xfs_rtgroup_grab(mp, xfs_rtb_to_rgno(mp, got.br_startblock)); 402 - if (!rtg) 403 - return NULL; 404 - 405 - xfs_ilock(rtg_rmap(rtg), XFS_ILOCK_SHARED); 406 - oz = READ_ONCE(rtg->rtg_open_zone); 407 - if (oz && (oz->oz_is_gc || !atomic_inc_not_zero(&oz->oz_ref))) 408 - oz = NULL; 409 - xfs_iunlock(rtg_rmap(rtg), XFS_ILOCK_SHARED); 410 - 411 - xfs_rtgroup_rele(rtg); 412 - return oz; 413 - } 414 - 415 377 static struct xfs_group * 416 378 xfs_find_free_zone( 417 379 struct xfs_mount *mp, ··· 880 918 goto out_error; 881 919 882 920 /* 883 - * If we don't have a cached zone in this write context, see if the 884 - * last extent before the one we are writing to points to an active 885 - * zone. If so, just continue writing to it. 921 + * If we don't have a locally cached zone in this write context, see if 922 + * the inode is still associated with a zone and use that if so. 886 923 */ 887 - if (!*oz && ioend->io_offset) 888 - *oz = xfs_last_used_zone(ioend); 889 924 if (!*oz) 890 925 *oz = xfs_cached_zone(mp, ip); 891 926
+6
fs/xfs/xfs_zone_space_resv.c
··· 10 10 #include "xfs_mount.h" 11 11 #include "xfs_inode.h" 12 12 #include "xfs_rtbitmap.h" 13 + #include "xfs_icache.h" 13 14 #include "xfs_zone_alloc.h" 14 15 #include "xfs_zone_priv.h" 15 16 #include "xfs_zones.h" ··· 231 230 232 231 error = xfs_dec_freecounter(mp, XC_FREE_RTEXTENTS, count_fsb, 233 232 flags & XFS_ZR_RESERVED); 233 + if (error == -ENOSPC && !(flags & XFS_ZR_NOWAIT)) { 234 + xfs_inodegc_flush(mp); 235 + error = xfs_dec_freecounter(mp, XC_FREE_RTEXTENTS, count_fsb, 236 + flags & XFS_ZR_RESERVED); 237 + } 234 238 if (error == -ENOSPC && (flags & XFS_ZR_GREEDY) && count_fsb > 1) 235 239 error = xfs_zoned_reserve_extents_greedy(mp, &count_fsb, flags); 236 240 if (error)
+5 -5
include/drm/drm_gpuvm.h
··· 103 103 } va; 104 104 105 105 /** 106 - * @gem: structure containing the &drm_gem_object and it's offset 106 + * @gem: structure containing the &drm_gem_object and its offset 107 107 */ 108 108 struct { 109 109 /** ··· 843 843 } va; 844 844 845 845 /** 846 - * @gem: structure containing the &drm_gem_object and it's offset 846 + * @gem: structure containing the &drm_gem_object and its offset 847 847 */ 848 848 struct { 849 849 /** ··· 1189 1189 1190 1190 /** 1191 1191 * @sm_step_unmap: called from &drm_gpuvm_sm_map and 1192 - * &drm_gpuvm_sm_unmap to unmap an existent mapping 1192 + * &drm_gpuvm_sm_unmap to unmap an existing mapping 1193 1193 * 1194 - * This callback is called when existent mapping needs to be unmapped. 1194 + * This callback is called when existing mapping needs to be unmapped. 1195 1195 * This is the case when either a newly requested mapping encloses an 1196 - * existent mapping or an unmap of an existent mapping is requested. 1196 + * existing mapping or an unmap of an existing mapping is requested. 1197 1197 * 1198 1198 * The &priv pointer matches the one the driver passed to 1199 1199 * &drm_gpuvm_sm_map or &drm_gpuvm_sm_unmap, respectively.
+2 -1
include/linux/kexec.h
··· 460 460 461 461 /* List of defined/legal kexec file flags */ 462 462 #define KEXEC_FILE_FLAGS (KEXEC_FILE_UNLOAD | KEXEC_FILE_ON_CRASH | \ 463 - KEXEC_FILE_NO_INITRAMFS | KEXEC_FILE_DEBUG) 463 + KEXEC_FILE_NO_INITRAMFS | KEXEC_FILE_DEBUG | \ 464 + KEXEC_FILE_NO_CMA) 464 465 465 466 /* flag to track if kexec reboot is in progress */ 466 467 extern bool kexec_in_progress;
+29
include/linux/pgalloc.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + #ifndef _LINUX_PGALLOC_H 3 + #define _LINUX_PGALLOC_H 4 + 5 + #include <linux/pgtable.h> 6 + #include <asm/pgalloc.h> 7 + 8 + /* 9 + * {pgd,p4d}_populate_kernel() are defined as macros to allow 10 + * compile-time optimization based on the configured page table levels. 11 + * Without this, linking may fail because callers (e.g., KASAN) may rely 12 + * on calls to these functions being optimized away when passing symbols 13 + * that exist only for certain page table levels. 14 + */ 15 + #define pgd_populate_kernel(addr, pgd, p4d) \ 16 + do { \ 17 + pgd_populate(&init_mm, pgd, p4d); \ 18 + if (ARCH_PAGE_TABLE_SYNC_MASK & PGTBL_PGD_MODIFIED) \ 19 + arch_sync_kernel_mappings(addr, addr); \ 20 + } while (0) 21 + 22 + #define p4d_populate_kernel(addr, p4d, pud) \ 23 + do { \ 24 + p4d_populate(&init_mm, p4d, pud); \ 25 + if (ARCH_PAGE_TABLE_SYNC_MASK & PGTBL_P4D_MODIFIED) \ 26 + arch_sync_kernel_mappings(addr, addr); \ 27 + } while (0) 28 + 29 + #endif /* _LINUX_PGALLOC_H */
+21 -4
include/linux/pgtable.h
··· 1467 1467 } 1468 1468 #endif 1469 1469 1470 + /* 1471 + * Architectures can set this mask to a combination of PGTBL_P?D_MODIFIED values 1472 + * and let generic vmalloc, ioremap and page table update code know when 1473 + * arch_sync_kernel_mappings() needs to be called. 1474 + */ 1475 + #ifndef ARCH_PAGE_TABLE_SYNC_MASK 1476 + #define ARCH_PAGE_TABLE_SYNC_MASK 0 1477 + #endif 1478 + 1479 + /* 1480 + * There is no default implementation for arch_sync_kernel_mappings(). It is 1481 + * relied upon the compiler to optimize calls out if ARCH_PAGE_TABLE_SYNC_MASK 1482 + * is 0. 1483 + */ 1484 + void arch_sync_kernel_mappings(unsigned long start, unsigned long end); 1485 + 1470 1486 #endif /* CONFIG_MMU */ 1471 1487 1472 1488 /* ··· 1954 1938 /* 1955 1939 * Page Table Modification bits for pgtbl_mod_mask. 1956 1940 * 1957 - * These are used by the p?d_alloc_track*() set of functions an in the generic 1958 - * vmalloc/ioremap code to track at which page-table levels entries have been 1959 - * modified. Based on that the code can better decide when vmalloc and ioremap 1960 - * mapping changes need to be synchronized to other page-tables in the system. 1941 + * These are used by the p?d_alloc_track*() and p*d_populate_kernel() 1942 + * functions in the generic vmalloc, ioremap and page table update code 1943 + * to track at which page-table levels entries have been modified. 1944 + * Based on that the code can better decide when page table changes need 1945 + * to be synchronized to other page-tables in the system. 1961 1946 */ 1962 1947 #define __PGTBL_PGD_MODIFIED 0 1963 1948 #define __PGTBL_P4D_MODIFIED 1
+5
include/linux/phy.h
··· 169 169 return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX); 170 170 } 171 171 172 + static inline unsigned int phy_interface_weight(const unsigned long *intf) 173 + { 174 + return bitmap_weight(intf, PHY_INTERFACE_MODE_MAX); 175 + } 176 + 172 177 static inline void phy_interface_and(unsigned long *dst, const unsigned long *a, 173 178 const unsigned long *b) 174 179 {
-16
include/linux/vmalloc.h
··· 220 220 struct page **pages, unsigned int page_shift); 221 221 222 222 /* 223 - * Architectures can set this mask to a combination of PGTBL_P?D_MODIFIED values 224 - * and let generic vmalloc and ioremap code know when arch_sync_kernel_mappings() 225 - * needs to be called. 226 - */ 227 - #ifndef ARCH_PAGE_TABLE_SYNC_MASK 228 - #define ARCH_PAGE_TABLE_SYNC_MASK 0 229 - #endif 230 - 231 - /* 232 - * There is no default implementation for arch_sync_kernel_mappings(). It is 233 - * relied upon the compiler to optimize calls out if ARCH_PAGE_TABLE_SYNC_MASK 234 - * is 0. 235 - */ 236 - void arch_sync_kernel_mappings(unsigned long start, unsigned long end); 237 - 238 - /* 239 223 * Lowlevel-APIs (not for driver use!) 240 224 */ 241 225
+13 -4
include/net/sock.h
··· 291 291 * @sk_ack_backlog: current listen backlog 292 292 * @sk_max_ack_backlog: listen backlog set in listen() 293 293 * @sk_uid: user id of owner 294 + * @sk_ino: inode number (zero if orphaned) 294 295 * @sk_prefer_busy_poll: prefer busypolling over softirq processing 295 296 * @sk_busy_poll_budget: napi processing budget when busypolling 296 297 * @sk_priority: %SO_PRIORITY setting ··· 528 527 u32 sk_ack_backlog; 529 528 u32 sk_max_ack_backlog; 530 529 kuid_t sk_uid; 530 + unsigned long sk_ino; 531 531 spinlock_t sk_peer_lock; 532 532 int sk_bind_phc; 533 533 struct pid *sk_peer_pid; ··· 2065 2063 static inline void sk_set_socket(struct sock *sk, struct socket *sock) 2066 2064 { 2067 2065 sk->sk_socket = sock; 2066 + if (sock) { 2067 + WRITE_ONCE(sk->sk_uid, SOCK_INODE(sock)->i_uid); 2068 + WRITE_ONCE(sk->sk_ino, SOCK_INODE(sock)->i_ino); 2069 + } 2068 2070 } 2069 2071 2070 2072 static inline wait_queue_head_t *sk_sleep(struct sock *sk) ··· 2090 2084 sk_set_socket(sk, NULL); 2091 2085 sk->sk_wq = NULL; 2092 2086 /* Note: sk_uid is unchanged. */ 2087 + WRITE_ONCE(sk->sk_ino, 0); 2093 2088 write_unlock_bh(&sk->sk_callback_lock); 2094 2089 } 2095 2090 ··· 2101 2094 rcu_assign_pointer(sk->sk_wq, &parent->wq); 2102 2095 parent->sk = sk; 2103 2096 sk_set_socket(sk, parent); 2104 - WRITE_ONCE(sk->sk_uid, SOCK_INODE(parent)->i_uid); 2105 2097 security_sock_graft(sk, parent); 2106 2098 write_unlock_bh(&sk->sk_callback_lock); 2099 + } 2100 + 2101 + static inline unsigned long sock_i_ino(const struct sock *sk) 2102 + { 2103 + /* Paired with WRITE_ONCE() in sock_graft() and sock_orphan() */ 2104 + return READ_ONCE(sk->sk_ino); 2107 2105 } 2108 2106 2109 2107 static inline kuid_t sk_uid(const struct sock *sk) ··· 2116 2104 /* Paired with WRITE_ONCE() in sockfs_setattr() */ 2117 2105 return READ_ONCE(sk->sk_uid); 2118 2106 } 2119 - 2120 - unsigned long __sock_i_ino(struct sock *sk); 2121 - unsigned long sock_i_ino(struct sock *sk); 2122 2107 2123 2108 static inline kuid_t sock_net_uid(const struct net *net, const struct sock *sk) 2124 2109 {
+2
include/uapi/linux/netfilter/nf_tables.h
··· 1784 1784 * enum nft_device_attributes - nf_tables device netlink attributes 1785 1785 * 1786 1786 * @NFTA_DEVICE_NAME: name of this device (NLA_STRING) 1787 + * @NFTA_DEVICE_PREFIX: device name prefix, a simple wildcard (NLA_STRING) 1787 1788 */ 1788 1789 enum nft_devices_attributes { 1789 1790 NFTA_DEVICE_UNSPEC, 1790 1791 NFTA_DEVICE_NAME, 1792 + NFTA_DEVICE_PREFIX, 1791 1793 __NFTA_DEVICE_MAX 1792 1794 }; 1793 1795 #define NFTA_DEVICE_MAX (__NFTA_DEVICE_MAX - 1)
+5 -4
init/Kconfig
··· 117 117 118 118 config CC_HAS_COUNTED_BY 119 119 bool 120 - # clang needs to be at least 19.1.3 to avoid __bdos miscalculations 121 - # https://github.com/llvm/llvm-project/pull/110497 122 - # https://github.com/llvm/llvm-project/pull/112636 123 - default y if CC_IS_CLANG && CLANG_VERSION >= 190103 120 + # clang needs to be at least 20.1.0 to avoid potential crashes 121 + # when building structures that contain __counted_by 122 + # https://github.com/ClangBuiltLinux/linux/issues/2114 123 + # https://github.com/llvm/llvm-project/commit/160fb1121cdf703c3ef5e61fb26c5659eb581489 124 + default y if CC_IS_CLANG && CLANG_VERSION >= 200100 124 125 # supported since gcc 15.1.0 125 126 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108896 126 127 default y if CC_IS_GCC && GCC_VERSION >= 150100
+13 -7
io_uring/kbuf.c
··· 36 36 { 37 37 while (len) { 38 38 struct io_uring_buf *buf; 39 - u32 this_len; 39 + u32 buf_len, this_len; 40 40 41 41 buf = io_ring_head_to_buf(bl->buf_ring, bl->head, bl->mask); 42 - this_len = min_t(int, len, buf->len); 43 - buf->len -= this_len; 44 - if (buf->len) { 42 + buf_len = READ_ONCE(buf->len); 43 + this_len = min_t(u32, len, buf_len); 44 + buf_len -= this_len; 45 + /* Stop looping for invalid buffer length of 0 */ 46 + if (buf_len || !this_len) { 45 47 buf->addr += this_len; 48 + buf->len = buf_len; 46 49 return false; 47 50 } 51 + buf->len = 0; 48 52 bl->head++; 49 53 len -= this_len; 50 54 } ··· 163 159 __u16 tail, head = bl->head; 164 160 struct io_uring_buf *buf; 165 161 void __user *ret; 162 + u32 buf_len; 166 163 167 164 tail = smp_load_acquire(&br->tail); 168 165 if (unlikely(tail == head)) ··· 173 168 req->flags |= REQ_F_BL_EMPTY; 174 169 175 170 buf = io_ring_head_to_buf(br, head, bl->mask); 176 - if (*len == 0 || *len > buf->len) 177 - *len = buf->len; 171 + buf_len = READ_ONCE(buf->len); 172 + if (*len == 0 || *len > buf_len) 173 + *len = buf_len; 178 174 req->flags |= REQ_F_BUFFER_RING | REQ_F_BUFFERS_COMMIT; 179 175 req->buf_list = bl; 180 176 req->buf_index = buf->bid; ··· 271 265 272 266 req->buf_index = buf->bid; 273 267 do { 274 - u32 len = buf->len; 268 + u32 len = READ_ONCE(buf->len); 275 269 276 270 /* truncate end piece, if needed, for non partial buffers */ 277 271 if (len > arg->max_len) {
+12 -6
kernel/sched/deadline.c
··· 1496 1496 } 1497 1497 1498 1498 if (unlikely(is_dl_boosted(dl_se) || !start_dl_timer(dl_se))) { 1499 - if (dl_server(dl_se)) 1500 - enqueue_dl_entity(dl_se, ENQUEUE_REPLENISH); 1501 - else 1499 + if (dl_server(dl_se)) { 1500 + replenish_dl_new_period(dl_se, rq); 1501 + start_dl_timer(dl_se); 1502 + } else { 1502 1503 enqueue_task_dl(rq, dl_task_of(dl_se), ENQUEUE_REPLENISH); 1504 + } 1503 1505 } 1504 1506 1505 1507 if (!is_leftmost(dl_se, &rq->dl)) ··· 1613 1611 static bool dl_server_stopped(struct sched_dl_entity *dl_se) 1614 1612 { 1615 1613 if (!dl_se->dl_server_active) 1616 - return false; 1614 + return true; 1617 1615 1618 1616 if (dl_se->dl_server_idle) { 1619 1617 dl_server_stop(dl_se); ··· 1851 1849 u64 deadline = dl_se->deadline; 1852 1850 1853 1851 dl_rq->dl_nr_running++; 1854 - add_nr_running(rq_of_dl_rq(dl_rq), 1); 1852 + 1853 + if (!dl_server(dl_se)) 1854 + add_nr_running(rq_of_dl_rq(dl_rq), 1); 1855 1855 1856 1856 inc_dl_deadline(dl_rq, deadline); 1857 1857 } ··· 1863 1859 { 1864 1860 WARN_ON(!dl_rq->dl_nr_running); 1865 1861 dl_rq->dl_nr_running--; 1866 - sub_nr_running(rq_of_dl_rq(dl_rq), 1); 1862 + 1863 + if (!dl_server(dl_se)) 1864 + sub_nr_running(rq_of_dl_rq(dl_rq), 1); 1867 1865 1868 1866 dec_dl_deadline(dl_rq, dl_se->deadline); 1869 1867 }
+2 -4
kernel/sched/debug.c
··· 376 376 return -EINVAL; 377 377 } 378 378 379 - if (rq->cfs.h_nr_queued) { 380 - update_rq_clock(rq); 381 - dl_server_stop(&rq->fair_server); 382 - } 379 + update_rq_clock(rq); 380 + dl_server_stop(&rq->fair_server); 383 381 384 382 retval = dl_server_apply_params(&rq->fair_server, runtime, period, 0); 385 383 if (retval)
+2
kernel/sched/topology.c
··· 2201 2201 goto unlock; 2202 2202 2203 2203 hop_masks = bsearch(&k, k.masks, sched_domains_numa_levels, sizeof(k.masks[0]), hop_cmp); 2204 + if (!hop_masks) 2205 + goto unlock; 2204 2206 hop = hop_masks - k.masks; 2205 2207 2206 2208 ret = hop ?
+3 -3
lib/ubsan.c
··· 333 333 void __ubsan_handle_divrem_overflow(void *_data, void *lhs, void *rhs) 334 334 { 335 335 struct overflow_data *data = _data; 336 - char rhs_val_str[VALUE_LENGTH]; 336 + char lhs_val_str[VALUE_LENGTH]; 337 337 338 338 if (suppress_report(&data->location)) 339 339 return; 340 340 341 341 ubsan_prologue(&data->location, "division-overflow"); 342 342 343 - val_to_string(rhs_val_str, sizeof(rhs_val_str), data->type, rhs); 343 + val_to_string(lhs_val_str, sizeof(lhs_val_str), data->type, lhs); 344 344 345 345 if (type_is_signed(data->type) && get_signed_val(data->type, rhs) == -1) 346 346 pr_err("division of %s by -1 cannot be represented in type %s\n", 347 - rhs_val_str, data->type->type_name); 347 + lhs_val_str, data->type->type_name); 348 348 else 349 349 pr_err("division by zero\n"); 350 350
+2 -2
mm/damon/core.c
··· 2073 2073 2074 2074 if (quota->ms) { 2075 2075 if (quota->total_charged_ns) 2076 - throughput = quota->total_charged_sz * 1000000 / 2077 - quota->total_charged_ns; 2076 + throughput = mult_frac(quota->total_charged_sz, 1000000, 2077 + quota->total_charged_ns); 2078 2078 else 2079 2079 throughput = PAGE_SIZE * 1024; 2080 2080 esz = min(throughput * quota->ms, esz);
+6 -6
mm/kasan/init.c
··· 13 13 #include <linux/mm.h> 14 14 #include <linux/pfn.h> 15 15 #include <linux/slab.h> 16 + #include <linux/pgalloc.h> 16 17 17 18 #include <asm/page.h> 18 - #include <asm/pgalloc.h> 19 19 20 20 #include "kasan.h" 21 21 ··· 191 191 pud_t *pud; 192 192 pmd_t *pmd; 193 193 194 - p4d_populate(&init_mm, p4d, 194 + p4d_populate_kernel(addr, p4d, 195 195 lm_alias(kasan_early_shadow_pud)); 196 196 pud = pud_offset(p4d, addr); 197 197 pud_populate(&init_mm, pud, ··· 212 212 } else { 213 213 p = early_alloc(PAGE_SIZE, NUMA_NO_NODE); 214 214 pud_init(p); 215 - p4d_populate(&init_mm, p4d, p); 215 + p4d_populate_kernel(addr, p4d, p); 216 216 } 217 217 } 218 218 zero_pud_populate(p4d, addr, next); ··· 251 251 * puds,pmds, so pgd_populate(), pud_populate() 252 252 * is noops. 253 253 */ 254 - pgd_populate(&init_mm, pgd, 254 + pgd_populate_kernel(addr, pgd, 255 255 lm_alias(kasan_early_shadow_p4d)); 256 256 p4d = p4d_offset(pgd, addr); 257 - p4d_populate(&init_mm, p4d, 257 + p4d_populate_kernel(addr, p4d, 258 258 lm_alias(kasan_early_shadow_pud)); 259 259 pud = pud_offset(p4d, addr); 260 260 pud_populate(&init_mm, pud, ··· 273 273 if (!p) 274 274 return -ENOMEM; 275 275 } else { 276 - pgd_populate(&init_mm, pgd, 276 + pgd_populate_kernel(addr, pgd, 277 277 early_alloc(PAGE_SIZE, NUMA_NO_NODE)); 278 278 } 279 279 }
+2
mm/kasan/kasan_test_c.c
··· 1578 1578 1579 1579 ptr = kmalloc(size, GFP_KERNEL | __GFP_ZERO); 1580 1580 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr); 1581 + OPTIMIZER_HIDE_VAR(ptr); 1581 1582 1582 1583 src = kmalloc(KASAN_GRANULE_SIZE, GFP_KERNEL | __GFP_ZERO); 1583 1584 strscpy(src, "f0cacc1a0000000", KASAN_GRANULE_SIZE); 1585 + OPTIMIZER_HIDE_VAR(src); 1584 1586 1585 1587 /* 1586 1588 * Make sure that strscpy() does not trigger KASAN if it overreads into
+14 -8
mm/kasan/shadow.c
··· 305 305 pte_t pte; 306 306 int index; 307 307 308 - if (likely(!pte_none(ptep_get(ptep)))) 309 - return 0; 308 + arch_leave_lazy_mmu_mode(); 310 309 311 310 index = PFN_DOWN(addr - data->start); 312 311 page = data->pages[index]; ··· 318 319 data->pages[index] = NULL; 319 320 } 320 321 spin_unlock(&init_mm.page_table_lock); 322 + 323 + arch_enter_lazy_mmu_mode(); 321 324 322 325 return 0; 323 326 } ··· 462 461 static int kasan_depopulate_vmalloc_pte(pte_t *ptep, unsigned long addr, 463 462 void *unused) 464 463 { 465 - unsigned long page; 464 + pte_t pte; 465 + int none; 466 466 467 - page = (unsigned long)__va(pte_pfn(ptep_get(ptep)) << PAGE_SHIFT); 467 + arch_leave_lazy_mmu_mode(); 468 468 469 469 spin_lock(&init_mm.page_table_lock); 470 - 471 - if (likely(!pte_none(ptep_get(ptep)))) { 470 + pte = ptep_get(ptep); 471 + none = pte_none(pte); 472 + if (likely(!none)) 472 473 pte_clear(&init_mm, addr, ptep); 473 - free_page(page); 474 - } 475 474 spin_unlock(&init_mm.page_table_lock); 475 + 476 + if (likely(!none)) 477 + __free_page(pfn_to_page(pte_pfn(pte))); 478 + 479 + arch_enter_lazy_mmu_mode(); 476 480 477 481 return 0; 478 482 }
+20 -7
mm/kmemleak.c
··· 437 437 else if (untagged_objp == untagged_ptr || alias) 438 438 return object; 439 439 else { 440 + /* 441 + * Printk deferring due to the kmemleak_lock held. 442 + * This is done to avoid deadlock. 443 + */ 444 + printk_deferred_enter(); 440 445 kmemleak_warn("Found object by alias at 0x%08lx\n", 441 446 ptr); 442 447 dump_object_info(object); 448 + printk_deferred_exit(); 443 449 break; 444 450 } 445 451 } ··· 742 736 else if (untagged_objp + parent->size <= untagged_ptr) 743 737 link = &parent->rb_node.rb_right; 744 738 else { 739 + /* 740 + * Printk deferring due to the kmemleak_lock held. 741 + * This is done to avoid deadlock. 742 + */ 743 + printk_deferred_enter(); 745 744 kmemleak_stop("Cannot insert 0x%lx into the object search tree (overlaps existing)\n", 746 745 ptr); 747 746 /* ··· 754 743 * be freed while the kmemleak_lock is held. 755 744 */ 756 745 dump_object_info(parent); 746 + printk_deferred_exit(); 757 747 return -EEXIST; 758 748 } 759 749 } ··· 868 856 869 857 raw_spin_lock_irqsave(&kmemleak_lock, flags); 870 858 object = __find_and_remove_object(ptr, 1, objflags); 871 - if (!object) { 872 - #ifdef DEBUG 873 - kmemleak_warn("Partially freeing unknown object at 0x%08lx (size %zu)\n", 874 - ptr, size); 875 - #endif 859 + if (!object) 876 860 goto unlock; 877 - } 878 861 879 862 /* 880 863 * Create one or two objects that may result from the memory block ··· 889 882 890 883 unlock: 891 884 raw_spin_unlock_irqrestore(&kmemleak_lock, flags); 892 - if (object) 885 + if (object) { 893 886 __delete_object(object); 887 + } else { 888 + #ifdef DEBUG 889 + kmemleak_warn("Partially freeing unknown object at 0x%08lx (size %zu)\n", 890 + ptr, size); 891 + #endif 892 + } 894 893 895 894 out: 896 895 if (object_l)
+3 -3
mm/percpu.c
··· 3108 3108 #endif /* BUILD_EMBED_FIRST_CHUNK */ 3109 3109 3110 3110 #ifdef BUILD_PAGE_FIRST_CHUNK 3111 - #include <asm/pgalloc.h> 3111 + #include <linux/pgalloc.h> 3112 3112 3113 3113 #ifndef P4D_TABLE_SIZE 3114 3114 #define P4D_TABLE_SIZE PAGE_SIZE ··· 3134 3134 3135 3135 if (pgd_none(*pgd)) { 3136 3136 p4d = memblock_alloc_or_panic(P4D_TABLE_SIZE, P4D_TABLE_SIZE); 3137 - pgd_populate(&init_mm, pgd, p4d); 3137 + pgd_populate_kernel(addr, pgd, p4d); 3138 3138 } 3139 3139 3140 3140 p4d = p4d_offset(pgd, addr); 3141 3141 if (p4d_none(*p4d)) { 3142 3142 pud = memblock_alloc_or_panic(PUD_TABLE_SIZE, PUD_TABLE_SIZE); 3143 - p4d_populate(&init_mm, p4d, pud); 3143 + p4d_populate_kernel(addr, p4d, pud); 3144 3144 } 3145 3145 3146 3146 pud = pud_offset(p4d, addr);
+26 -11
mm/slub.c
··· 962 962 } 963 963 964 964 #ifdef CONFIG_STACKDEPOT 965 - static noinline depot_stack_handle_t set_track_prepare(void) 965 + static noinline depot_stack_handle_t set_track_prepare(gfp_t gfp_flags) 966 966 { 967 967 depot_stack_handle_t handle; 968 968 unsigned long entries[TRACK_ADDRS_COUNT]; 969 969 unsigned int nr_entries; 970 970 971 971 nr_entries = stack_trace_save(entries, ARRAY_SIZE(entries), 3); 972 - handle = stack_depot_save(entries, nr_entries, GFP_NOWAIT); 972 + handle = stack_depot_save(entries, nr_entries, gfp_flags); 973 973 974 974 return handle; 975 975 } 976 976 #else 977 - static inline depot_stack_handle_t set_track_prepare(void) 977 + static inline depot_stack_handle_t set_track_prepare(gfp_t gfp_flags) 978 978 { 979 979 return 0; 980 980 } ··· 996 996 } 997 997 998 998 static __always_inline void set_track(struct kmem_cache *s, void *object, 999 - enum track_item alloc, unsigned long addr) 999 + enum track_item alloc, unsigned long addr, gfp_t gfp_flags) 1000 1000 { 1001 - depot_stack_handle_t handle = set_track_prepare(); 1001 + depot_stack_handle_t handle = set_track_prepare(gfp_flags); 1002 1002 1003 1003 set_track_update(s, object, alloc, addr, handle); 1004 1004 } ··· 1140 1140 return; 1141 1141 1142 1142 slab_bug(s, reason); 1143 - print_trailer(s, slab, object); 1143 + if (!object || !check_valid_pointer(s, slab, object)) { 1144 + print_slab_info(slab); 1145 + pr_err("Invalid pointer 0x%p\n", object); 1146 + } else { 1147 + print_trailer(s, slab, object); 1148 + } 1144 1149 add_taint(TAINT_BAD_PAGE, LOCKDEP_NOW_UNRELIABLE); 1145 1150 1146 1151 WARN_ON(1); ··· 1926 1921 static inline void slab_pad_check(struct kmem_cache *s, struct slab *slab) {} 1927 1922 static inline int check_object(struct kmem_cache *s, struct slab *slab, 1928 1923 void *object, u8 val) { return 1; } 1929 - static inline depot_stack_handle_t set_track_prepare(void) { return 0; } 1924 + static inline depot_stack_handle_t set_track_prepare(gfp_t gfp_flags) { return 0; } 1930 1925 static inline void set_track(struct kmem_cache *s, void *object, 1931 - enum track_item alloc, unsigned long addr) {} 1926 + enum track_item alloc, unsigned long addr, gfp_t gfp_flags) {} 1932 1927 static inline void add_full(struct kmem_cache *s, struct kmem_cache_node *n, 1933 1928 struct slab *slab) {} 1934 1929 static inline void remove_full(struct kmem_cache *s, struct kmem_cache_node *n, ··· 3881 3876 * For debug caches here we had to go through 3882 3877 * alloc_single_from_partial() so just store the 3883 3878 * tracking info and return the object. 3879 + * 3880 + * Due to disabled preemption we need to disallow 3881 + * blocking. The flags are further adjusted by 3882 + * gfp_nested_mask() in stack_depot itself. 3884 3883 */ 3885 3884 if (s->flags & SLAB_STORE_USER) 3886 - set_track(s, freelist, TRACK_ALLOC, addr); 3885 + set_track(s, freelist, TRACK_ALLOC, addr, 3886 + gfpflags & ~(__GFP_DIRECT_RECLAIM)); 3887 3887 3888 3888 return freelist; 3889 3889 } ··· 3920 3910 goto new_objects; 3921 3911 3922 3912 if (s->flags & SLAB_STORE_USER) 3923 - set_track(s, freelist, TRACK_ALLOC, addr); 3913 + set_track(s, freelist, TRACK_ALLOC, addr, 3914 + gfpflags & ~(__GFP_DIRECT_RECLAIM)); 3924 3915 3925 3916 return freelist; 3926 3917 } ··· 4432 4421 unsigned long flags; 4433 4422 depot_stack_handle_t handle = 0; 4434 4423 4424 + /* 4425 + * We cannot use GFP_NOWAIT as there are callsites where waking up 4426 + * kswapd could deadlock 4427 + */ 4435 4428 if (s->flags & SLAB_STORE_USER) 4436 - handle = set_track_prepare(); 4429 + handle = set_track_prepare(__GFP_NOWARN); 4437 4430 4438 4431 spin_lock_irqsave(&n->list_lock, flags); 4439 4432
+3 -8
mm/sparse-vmemmap.c
··· 27 27 #include <linux/spinlock.h> 28 28 #include <linux/vmalloc.h> 29 29 #include <linux/sched.h> 30 + #include <linux/pgalloc.h> 30 31 31 32 #include <asm/dma.h> 32 - #include <asm/pgalloc.h> 33 33 #include <asm/tlbflush.h> 34 34 35 35 #include "hugetlb_vmemmap.h" ··· 229 229 if (!p) 230 230 return NULL; 231 231 pud_init(p); 232 - p4d_populate(&init_mm, p4d, p); 232 + p4d_populate_kernel(addr, p4d, p); 233 233 } 234 234 return p4d; 235 235 } ··· 241 241 void *p = vmemmap_alloc_block_zero(PAGE_SIZE, node); 242 242 if (!p) 243 243 return NULL; 244 - pgd_populate(&init_mm, pgd, p); 244 + pgd_populate_kernel(addr, pgd, p); 245 245 } 246 246 return pgd; 247 247 } ··· 577 577 578 578 if (r < 0) 579 579 return NULL; 580 - 581 - if (system_state == SYSTEM_BOOTING) 582 - memmap_boot_pages_add(DIV_ROUND_UP(end - start, PAGE_SIZE)); 583 - else 584 - memmap_pages_add(DIV_ROUND_UP(end - start, PAGE_SIZE)); 585 580 586 581 return pfn_to_page(pfn); 587 582 }
+9 -6
mm/sparse.c
··· 454 454 */ 455 455 sparsemap_buf = memmap_alloc(size, section_map_size(), addr, nid, true); 456 456 sparsemap_buf_end = sparsemap_buf + size; 457 - #ifndef CONFIG_SPARSEMEM_VMEMMAP 458 - memmap_boot_pages_add(DIV_ROUND_UP(size, PAGE_SIZE)); 459 - #endif 460 457 } 461 458 462 459 static void __init sparse_buffer_fini(void) ··· 564 567 sparse_buffer_fini(); 565 568 goto failed; 566 569 } 570 + memmap_boot_pages_add(DIV_ROUND_UP(PAGES_PER_SECTION * sizeof(struct page), 571 + PAGE_SIZE)); 567 572 sparse_init_early_section(nid, map, pnum, 0); 568 573 } 569 574 } ··· 679 680 unsigned long start = (unsigned long) pfn_to_page(pfn); 680 681 unsigned long end = start + nr_pages * sizeof(struct page); 681 682 682 - memmap_pages_add(-1L * (DIV_ROUND_UP(end - start, PAGE_SIZE))); 683 683 vmemmap_free(start, end, altmap); 684 684 } 685 685 static void free_map_bootmem(struct page *memmap) ··· 854 856 * The memmap of early sections is always fully populated. See 855 857 * section_activate() and pfn_valid() . 856 858 */ 857 - if (!section_is_early) 859 + if (!section_is_early) { 860 + memmap_pages_add(-1L * (DIV_ROUND_UP(nr_pages * sizeof(struct page), PAGE_SIZE))); 858 861 depopulate_section_memmap(pfn, nr_pages, altmap); 859 - else if (memmap) 862 + } else if (memmap) { 863 + memmap_boot_pages_add(-1L * (DIV_ROUND_UP(nr_pages * sizeof(struct page), 864 + PAGE_SIZE))); 860 865 free_map_bootmem(memmap); 866 + } 861 867 862 868 if (empty) 863 869 ms->section_mem_map = (unsigned long)NULL; ··· 906 904 section_deactivate(pfn, nr_pages, altmap); 907 905 return ERR_PTR(-ENOMEM); 908 906 } 907 + memmap_pages_add(DIV_ROUND_UP(nr_pages * sizeof(struct page), PAGE_SIZE)); 909 908 910 909 return memmap; 911 910 }
+7 -2
mm/userfaultfd.c
··· 1453 1453 folio_unlock(src_folio); 1454 1454 folio_put(src_folio); 1455 1455 } 1456 - if (dst_pte) 1457 - pte_unmap(dst_pte); 1456 + /* 1457 + * Unmap in reverse order (LIFO) to maintain proper kmap_local 1458 + * index ordering when CONFIG_HIGHPTE is enabled. We mapped dst_pte 1459 + * first, then src_pte, so we must unmap src_pte first, then dst_pte. 1460 + */ 1458 1461 if (src_pte) 1459 1462 pte_unmap(src_pte); 1463 + if (dst_pte) 1464 + pte_unmap(dst_pte); 1460 1465 mmu_notifier_invalidate_range_end(&range); 1461 1466 if (si) 1462 1467 put_swap_device(si);
+4 -2
net/atm/resources.c
··· 112 112 113 113 if (atm_proc_dev_register(dev) < 0) { 114 114 pr_err("atm_proc_dev_register failed for dev %s\n", type); 115 - goto out_fail; 115 + mutex_unlock(&atm_dev_mutex); 116 + kfree(dev); 117 + return NULL; 116 118 } 117 119 118 120 if (atm_register_sysfs(dev, parent) < 0) { ··· 130 128 return dev; 131 129 132 130 out_fail: 133 - kfree(dev); 131 + put_device(&dev->class_dev); 134 132 dev = NULL; 135 133 goto out; 136 134 }
+4
net/ax25/ax25_in.c
··· 433 433 int ax25_kiss_rcv(struct sk_buff *skb, struct net_device *dev, 434 434 struct packet_type *ptype, struct net_device *orig_dev) 435 435 { 436 + skb = skb_share_check(skb, GFP_ATOMIC); 437 + if (!skb) 438 + return NET_RX_DROP; 439 + 436 440 skb_orphan(skb); 437 441 438 442 if (!net_eq(dev_net(dev), &init_net)) {
+6 -1
net/batman-adv/network-coding.c
··· 1687 1687 1688 1688 coding_len = ntohs(coded_packet_tmp.coded_len); 1689 1689 1690 - if (coding_len > skb->len) 1690 + /* ensure dst buffer is large enough (payload only) */ 1691 + if (coding_len + h_size > skb->len) 1692 + return NULL; 1693 + 1694 + /* ensure src buffer is large enough (payload only) */ 1695 + if (coding_len + h_size > nc_packet->skb->len) 1691 1696 return NULL; 1692 1697 1693 1698 /* Here the magic is reversed:
+3
net/bluetooth/l2cap_sock.c
··· 1422 1422 if (!sk) 1423 1423 return 0; 1424 1424 1425 + lock_sock_nested(sk, L2CAP_NESTING_PARENT); 1425 1426 l2cap_sock_cleanup_listen(sk); 1427 + release_sock(sk); 1428 + 1426 1429 bt_sock_unlink(&l2cap_sk_list, sk); 1427 1430 1428 1431 err = l2cap_sock_shutdown(sock, SHUT_RDWR);
-3
net/bridge/br_netfilter_hooks.c
··· 626 626 break; 627 627 } 628 628 629 - ct = container_of(nfct, struct nf_conn, ct_general); 630 - WARN_ON_ONCE(!nf_ct_is_confirmed(ct)); 631 - 632 629 return ret; 633 630 } 634 631 #endif
+2
net/core/gen_estimator.c
··· 90 90 rate = (b_packets - est->last_packets) << (10 - est->intvl_log); 91 91 rate = (rate >> est->ewma_log) - (est->avpps >> est->ewma_log); 92 92 93 + preempt_disable_nested(); 93 94 write_seqcount_begin(&est->seq); 94 95 est->avbps += brate; 95 96 est->avpps += rate; 96 97 write_seqcount_end(&est->seq); 98 + preempt_enable_nested(); 97 99 98 100 est->last_bytes = b_bytes; 99 101 est->last_packets = b_packets;
-22
net/core/sock.c
··· 2787 2787 EXPORT_SYMBOL(sock_pfree); 2788 2788 #endif /* CONFIG_INET */ 2789 2789 2790 - unsigned long __sock_i_ino(struct sock *sk) 2791 - { 2792 - unsigned long ino; 2793 - 2794 - read_lock(&sk->sk_callback_lock); 2795 - ino = sk->sk_socket ? SOCK_INODE(sk->sk_socket)->i_ino : 0; 2796 - read_unlock(&sk->sk_callback_lock); 2797 - return ino; 2798 - } 2799 - EXPORT_SYMBOL(__sock_i_ino); 2800 - 2801 - unsigned long sock_i_ino(struct sock *sk) 2802 - { 2803 - unsigned long ino; 2804 - 2805 - local_bh_disable(); 2806 - ino = __sock_i_ino(sk); 2807 - local_bh_enable(); 2808 - return ino; 2809 - } 2810 - EXPORT_SYMBOL(sock_i_ino); 2811 - 2812 2790 /* 2813 2791 * Allocate a skb from the socket's send buffer. 2814 2792 */
+3 -4
net/ipv4/devinet.c
··· 340 340 341 341 static int __init inet_blackhole_dev_init(void) 342 342 { 343 - int err = 0; 343 + struct in_device *in_dev; 344 344 345 345 rtnl_lock(); 346 - if (!inetdev_init(blackhole_netdev)) 347 - err = -ENOMEM; 346 + in_dev = inetdev_init(blackhole_netdev); 348 347 rtnl_unlock(); 349 348 350 - return err; 349 + return PTR_ERR_OR_ZERO(in_dev); 351 350 } 352 351 late_initcall(inet_blackhole_dev_init); 353 352
+4 -2
net/ipv4/icmp.c
··· 801 801 struct sk_buff *cloned_skb = NULL; 802 802 struct ip_options opts = { 0 }; 803 803 enum ip_conntrack_info ctinfo; 804 + enum ip_conntrack_dir dir; 804 805 struct nf_conn *ct; 805 806 __be32 orig_ip; 806 807 807 808 ct = nf_ct_get(skb_in, &ctinfo); 808 - if (!ct || !(ct->status & IPS_SRC_NAT)) { 809 + if (!ct || !(READ_ONCE(ct->status) & IPS_NAT_MASK)) { 809 810 __icmp_send(skb_in, type, code, info, &opts); 810 811 return; 811 812 } ··· 821 820 goto out; 822 821 823 822 orig_ip = ip_hdr(skb_in)->saddr; 824 - ip_hdr(skb_in)->saddr = ct->tuplehash[0].tuple.src.u3.ip; 823 + dir = CTINFO2DIR(ctinfo); 824 + ip_hdr(skb_in)->saddr = ct->tuplehash[dir].tuple.src.u3.ip; 825 825 __icmp_send(skb_in, type, code, info, &opts); 826 826 ip_hdr(skb_in)->saddr = orig_ip; 827 827 out:
+2 -4
net/ipv6/exthdrs.c
··· 494 494 495 495 idev = __in6_dev_get(skb->dev); 496 496 497 - accept_rpl_seg = net->ipv6.devconf_all->rpl_seg_enabled; 498 - if (accept_rpl_seg > idev->cnf.rpl_seg_enabled) 499 - accept_rpl_seg = idev->cnf.rpl_seg_enabled; 500 - 497 + accept_rpl_seg = min(READ_ONCE(net->ipv6.devconf_all->rpl_seg_enabled), 498 + READ_ONCE(idev->cnf.rpl_seg_enabled)); 501 499 if (!accept_rpl_seg) { 502 500 kfree_skb(skb); 503 501 return -1;
+4 -2
net/ipv6/ip6_icmp.c
··· 54 54 struct inet6_skb_parm parm = { 0 }; 55 55 struct sk_buff *cloned_skb = NULL; 56 56 enum ip_conntrack_info ctinfo; 57 + enum ip_conntrack_dir dir; 57 58 struct in6_addr orig_ip; 58 59 struct nf_conn *ct; 59 60 60 61 ct = nf_ct_get(skb_in, &ctinfo); 61 - if (!ct || !(ct->status & IPS_SRC_NAT)) { 62 + if (!ct || !(READ_ONCE(ct->status) & IPS_NAT_MASK)) { 62 63 __icmpv6_send(skb_in, type, code, info, &parm); 63 64 return; 64 65 } ··· 74 73 goto out; 75 74 76 75 orig_ip = ipv6_hdr(skb_in)->saddr; 77 - ipv6_hdr(skb_in)->saddr = ct->tuplehash[0].tuple.src.u3.in6; 76 + dir = CTINFO2DIR(ctinfo); 77 + ipv6_hdr(skb_in)->saddr = ct->tuplehash[dir].tuple.src.u3.in6; 78 78 __icmpv6_send(skb_in, type, code, info, &parm); 79 79 ipv6_hdr(skb_in)->saddr = orig_ip; 80 80 out:
+15 -17
net/ipv6/tcp_ipv6.c
··· 1429 1429 ireq = inet_rsk(req); 1430 1430 1431 1431 if (sk_acceptq_is_full(sk)) 1432 - goto out_overflow; 1432 + goto exit_overflow; 1433 1433 1434 1434 if (!dst) { 1435 1435 dst = inet6_csk_route_req(sk, &fl6, req, IPPROTO_TCP); 1436 1436 if (!dst) 1437 - goto out; 1437 + goto exit; 1438 1438 } 1439 1439 1440 1440 newsk = tcp_create_openreq_child(sk, req, skb); 1441 1441 if (!newsk) 1442 - goto out_nonewsk; 1442 + goto exit_nonewsk; 1443 1443 1444 1444 /* 1445 1445 * No need to charge this sock to the relevant IPv6 refcnt debug socks ··· 1523 1523 const union tcp_md5_addr *addr; 1524 1524 1525 1525 addr = (union tcp_md5_addr *)&newsk->sk_v6_daddr; 1526 - if (tcp_md5_key_copy(newsk, addr, AF_INET6, 128, l3index, key)) { 1527 - inet_csk_prepare_forced_close(newsk); 1528 - tcp_done(newsk); 1529 - goto out; 1530 - } 1526 + if (tcp_md5_key_copy(newsk, addr, AF_INET6, 128, l3index, key)) 1527 + goto put_and_exit; 1531 1528 } 1532 1529 } 1533 1530 #endif 1534 1531 #ifdef CONFIG_TCP_AO 1535 1532 /* Copy over tcp_ao_info if any */ 1536 1533 if (tcp_ao_copy_all_matching(sk, newsk, req, skb, AF_INET6)) 1537 - goto out; /* OOM */ 1534 + goto put_and_exit; /* OOM */ 1538 1535 #endif 1539 1536 1540 - if (__inet_inherit_port(sk, newsk) < 0) { 1541 - inet_csk_prepare_forced_close(newsk); 1542 - tcp_done(newsk); 1543 - goto out; 1544 - } 1537 + if (__inet_inherit_port(sk, newsk) < 0) 1538 + goto put_and_exit; 1545 1539 *own_req = inet_ehash_nolisten(newsk, req_to_sk(req_unhash), 1546 1540 &found_dup_sk); 1547 1541 if (*own_req) { ··· 1562 1568 1563 1569 return newsk; 1564 1570 1565 - out_overflow: 1571 + exit_overflow: 1566 1572 __NET_INC_STATS(sock_net(sk), LINUX_MIB_LISTENOVERFLOWS); 1567 - out_nonewsk: 1573 + exit_nonewsk: 1568 1574 dst_release(dst); 1569 - out: 1575 + exit: 1570 1576 tcp_listendrop(sk); 1571 1577 return NULL; 1578 + put_and_exit: 1579 + inet_csk_prepare_forced_close(newsk); 1580 + tcp_done(newsk); 1581 + goto exit; 1572 1582 } 1573 1583 1574 1584 INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
+1 -1
net/mac80211/driver-ops.h
··· 1416 1416 struct ieee80211_sub_if_data *sdata, 1417 1417 struct cfg80211_ftm_responder_stats *ftm_stats) 1418 1418 { 1419 - u32 ret = -EOPNOTSUPP; 1419 + int ret = -EOPNOTSUPP; 1420 1420 1421 1421 might_sleep(); 1422 1422 lockdep_assert_wiphy(local->hw.wiphy);
+6 -1
net/mac80211/main.c
··· 1111 1111 int result, i; 1112 1112 enum nl80211_band band; 1113 1113 int channels, max_bitrates; 1114 - bool supp_ht, supp_vht, supp_he, supp_eht; 1114 + bool supp_ht, supp_vht, supp_he, supp_eht, supp_s1g; 1115 1115 struct cfg80211_chan_def dflt_chandef = {}; 1116 1116 1117 1117 if (ieee80211_hw_check(hw, QUEUE_CONTROL) && ··· 1227 1227 supp_vht = false; 1228 1228 supp_he = false; 1229 1229 supp_eht = false; 1230 + supp_s1g = false; 1230 1231 for (band = 0; band < NUM_NL80211_BANDS; band++) { 1231 1232 const struct ieee80211_sband_iftype_data *iftd; 1232 1233 struct ieee80211_supported_band *sband; ··· 1275 1274 max_bitrates = sband->n_bitrates; 1276 1275 supp_ht = supp_ht || sband->ht_cap.ht_supported; 1277 1276 supp_vht = supp_vht || sband->vht_cap.vht_supported; 1277 + supp_s1g = supp_s1g || sband->s1g_cap.s1g; 1278 1278 1279 1279 for_each_sband_iftype_data(sband, i, iftd) { 1280 1280 u8 he_40_mhz_cap; ··· 1407 1405 if (supp_vht) 1408 1406 local->scan_ies_len += 1409 1407 2 + sizeof(struct ieee80211_vht_cap); 1408 + 1409 + if (supp_s1g) 1410 + local->scan_ies_len += 2 + sizeof(struct ieee80211_s1g_cap); 1410 1411 1411 1412 /* 1412 1413 * HE cap element is variable in size - set len to allow max size */
+8
net/mac80211/mlme.c
··· 1189 1189 "required MCSes not supported, disabling EHT\n"); 1190 1190 } 1191 1191 1192 + if (conn->mode >= IEEE80211_CONN_MODE_EHT && 1193 + channel->band != NL80211_BAND_2GHZ && 1194 + conn->bw_limit == IEEE80211_CONN_BW_LIMIT_40) { 1195 + conn->mode = IEEE80211_CONN_MODE_HE; 1196 + link_id_info(sdata, link_id, 1197 + "required bandwidth not supported, disabling EHT\n"); 1198 + } 1199 + 1192 1200 /* the mode can only decrease, so this must terminate */ 1193 1201 if (ap_mode != conn->mode) { 1194 1202 kfree(elems);
+25 -5
net/mac80211/tests/chan-mode.c
··· 2 2 /* 3 3 * KUnit tests for channel mode functions 4 4 * 5 - * Copyright (C) 2024 Intel Corporation 5 + * Copyright (C) 2024-2025 Intel Corporation 6 6 */ 7 7 #include <net/cfg80211.h> 8 8 #include <kunit/test.h> ··· 28 28 u8 vht_basic_mcs_1_4, vht_basic_mcs_5_8; 29 29 u8 he_basic_mcs_1_4, he_basic_mcs_5_8; 30 30 u8 eht_mcs7_min_nss; 31 + u16 eht_disabled_subchannels; 32 + u8 eht_bw; 33 + enum ieee80211_conn_bw_limit conn_bw_limit; 34 + enum ieee80211_conn_bw_limit expected_bw_limit; 31 35 int error; 32 36 } determine_chan_mode_cases[] = { 33 37 { ··· 132 128 .conn_mode = IEEE80211_CONN_MODE_EHT, 133 129 .eht_mcs7_min_nss = 0x15, 134 130 .error = EINVAL, 131 + }, { 132 + .desc = "80 MHz EHT is downgraded to 40 MHz HE due to puncturing", 133 + .conn_mode = IEEE80211_CONN_MODE_EHT, 134 + .expected_mode = IEEE80211_CONN_MODE_HE, 135 + .conn_bw_limit = IEEE80211_CONN_BW_LIMIT_80, 136 + .expected_bw_limit = IEEE80211_CONN_BW_LIMIT_40, 137 + .eht_disabled_subchannels = 0x08, 138 + .eht_bw = IEEE80211_EHT_OPER_CHAN_WIDTH_80MHZ, 135 139 } 136 140 }; 137 141 KUNIT_ARRAY_PARAM_DESC(determine_chan_mode, determine_chan_mode_cases, desc) ··· 150 138 struct t_sdata *t_sdata = T_SDATA(test); 151 139 struct ieee80211_conn_settings conn = { 152 140 .mode = params->conn_mode, 153 - .bw_limit = IEEE80211_CONN_BW_LIMIT_20, 141 + .bw_limit = params->conn_bw_limit, 154 142 }; 155 143 struct cfg80211_bss cbss = { 156 144 .channel = &t_sdata->band_5ghz.channels[0], ··· 203 191 0x7f, 0x01, 0x00, 0x88, 0x88, 0x88, 0x00, 0x00, 204 192 0x00, 205 193 /* EHT Operation */ 206 - WLAN_EID_EXTENSION, 0x09, WLAN_EID_EXT_EHT_OPERATION, 207 - 0x01, params->eht_mcs7_min_nss ? params->eht_mcs7_min_nss : 0x11, 208 - 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 194 + WLAN_EID_EXTENSION, 0x0b, WLAN_EID_EXT_EHT_OPERATION, 195 + 0x03, params->eht_mcs7_min_nss ? params->eht_mcs7_min_nss : 0x11, 196 + 0x00, 0x00, 0x00, params->eht_bw, 197 + params->eht_bw == IEEE80211_EHT_OPER_CHAN_WIDTH_80MHZ ? 42 : 36, 198 + 0x00, 199 + u16_get_bits(params->eht_disabled_subchannels, 0xff), 200 + u16_get_bits(params->eht_disabled_subchannels, 0xff00), 209 201 }; 210 202 struct ieee80211_chan_req chanreq = {}; 211 203 struct cfg80211_chan_def ap_chandef = {}; 212 204 struct ieee802_11_elems *elems; 205 + 206 + /* To force EHT downgrade to HE on punctured 80 MHz downgraded to 40 MHz */ 207 + set_bit(IEEE80211_HW_DISALLOW_PUNCTURING, t_sdata->local.hw.flags); 213 208 214 209 if (params->strict) 215 210 set_bit(IEEE80211_HW_STRICT, t_sdata->local.hw.flags); ··· 256 237 } else { 257 238 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, elems); 258 239 KUNIT_ASSERT_EQ(test, conn.mode, params->expected_mode); 240 + KUNIT_ASSERT_EQ(test, conn.bw_limit, params->expected_bw_limit); 259 241 } 260 242 } 261 243
+1 -1
net/mctp/af_mctp.c
··· 425 425 return 0; 426 426 } 427 427 428 - return -EINVAL; 428 + return -ENOPROTOOPT; 429 429 } 430 430 431 431 /* helpers for reading/writing the tag ioc, handling compatibility across the
+19 -16
net/mctp/route.c
··· 378 378 static void mctp_flow_prepare_output(struct sk_buff *skb, struct mctp_dev *dev) {} 379 379 #endif 380 380 381 + /* takes ownership of skb, both in success and failure cases */ 381 382 static int mctp_frag_queue(struct mctp_sk_key *key, struct sk_buff *skb) 382 383 { 383 384 struct mctp_hdr *hdr = mctp_hdr(skb); ··· 388 387 & MCTP_HDR_SEQ_MASK; 389 388 390 389 if (!key->reasm_head) { 391 - /* Since we're manipulating the shared frag_list, ensure it isn't 392 - * shared with any other SKBs. 390 + /* Since we're manipulating the shared frag_list, ensure it 391 + * isn't shared with any other SKBs. In the cloned case, 392 + * this will free the skb; callers can no longer access it 393 + * safely. 393 394 */ 394 395 key->reasm_head = skb_unshare(skb, GFP_ATOMIC); 395 396 if (!key->reasm_head) ··· 405 402 exp_seq = (key->last_seq + 1) & MCTP_HDR_SEQ_MASK; 406 403 407 404 if (this_seq != exp_seq) 408 - return -EINVAL; 405 + goto err_free; 409 406 410 407 if (key->reasm_head->len + skb->len > mctp_message_maxlen) 411 - return -EINVAL; 408 + goto err_free; 412 409 413 410 skb->next = NULL; 414 411 skb->sk = NULL; ··· 422 419 key->reasm_head->truesize += skb->truesize; 423 420 424 421 return 0; 422 + 423 + err_free: 424 + kfree_skb(skb); 425 + return -EINVAL; 425 426 } 426 427 427 428 static int mctp_dst_input(struct mctp_dst *dst, struct sk_buff *skb) ··· 539 532 * key isn't observable yet 540 533 */ 541 534 mctp_frag_queue(key, skb); 535 + skb = NULL; 542 536 543 537 /* if the key_add fails, we've raced with another 544 538 * SOM packet with the same src, dest and tag. There's 545 539 * no way to distinguish future packets, so all we 546 - * can do is drop; we'll free the skb on exit from 547 - * this function. 540 + * can do is drop. 548 541 */ 549 542 rc = mctp_key_add(key, msk); 550 - if (!rc) { 543 + if (!rc) 551 544 trace_mctp_key_acquire(key); 552 - skb = NULL; 553 - } 554 545 555 546 /* we don't need to release key->lock on exit, so 556 547 * clean up here and suppress the unlock via ··· 566 561 key = NULL; 567 562 } else { 568 563 rc = mctp_frag_queue(key, skb); 569 - if (!rc) 570 - skb = NULL; 564 + skb = NULL; 571 565 } 572 566 } 573 567 ··· 576 572 */ 577 573 578 574 /* we need to be continuing an existing reassembly... */ 579 - if (!key->reasm_head) 575 + if (!key->reasm_head) { 580 576 rc = -EINVAL; 581 - else 577 + } else { 582 578 rc = mctp_frag_queue(key, skb); 579 + skb = NULL; 580 + } 583 581 584 582 if (rc) 585 583 goto out_unlock; 586 - 587 - /* we've queued; the queue owns the skb now */ 588 - skb = NULL; 589 584 590 585 /* end of message? deliver to socket, and we're done with 591 586 * the reassembly/response key
-1
net/mptcp/protocol.c
··· 3574 3574 write_lock_bh(&sk->sk_callback_lock); 3575 3575 rcu_assign_pointer(sk->sk_wq, &parent->wq); 3576 3576 sk_set_socket(sk, parent); 3577 - WRITE_ONCE(sk->sk_uid, SOCK_INODE(parent)->i_uid); 3578 3577 write_unlock_bh(&sk->sk_callback_lock); 3579 3578 } 3580 3579
+2 -2
net/netfilter/nf_conntrack_helper.c
··· 368 368 (cur->tuple.src.l3num == NFPROTO_UNSPEC || 369 369 cur->tuple.src.l3num == me->tuple.src.l3num) && 370 370 cur->tuple.dst.protonum == me->tuple.dst.protonum) { 371 - ret = -EEXIST; 371 + ret = -EBUSY; 372 372 goto out; 373 373 } 374 374 } ··· 379 379 hlist_for_each_entry(cur, &nf_ct_helper_hash[h], hnode) { 380 380 if (nf_ct_tuple_src_mask_cmp(&cur->tuple, &me->tuple, 381 381 &mask)) { 382 - ret = -EEXIST; 382 + ret = -EBUSY; 383 383 goto out; 384 384 } 385 385 }
+31 -11
net/netfilter/nf_tables_api.c
··· 1951 1951 return -ENOSPC; 1952 1952 } 1953 1953 1954 + static bool hook_is_prefix(struct nft_hook *hook) 1955 + { 1956 + return strlen(hook->ifname) >= hook->ifnamelen; 1957 + } 1958 + 1959 + static int nft_nla_put_hook_dev(struct sk_buff *skb, struct nft_hook *hook) 1960 + { 1961 + int attr = hook_is_prefix(hook) ? NFTA_DEVICE_PREFIX : NFTA_DEVICE_NAME; 1962 + 1963 + return nla_put_string(skb, attr, hook->ifname); 1964 + } 1965 + 1954 1966 static int nft_dump_basechain_hook(struct sk_buff *skb, 1955 1967 const struct net *net, int family, 1956 1968 const struct nft_base_chain *basechain, ··· 1994 1982 if (!first) 1995 1983 first = hook; 1996 1984 1997 - if (nla_put(skb, NFTA_DEVICE_NAME, 1998 - hook->ifnamelen, hook->ifname)) 1985 + if (nft_nla_put_hook_dev(skb, hook)) 1999 1986 goto nla_put_failure; 2000 1987 n++; 2001 1988 } 2002 1989 nla_nest_end(skb, nest_devs); 2003 1990 2004 1991 if (n == 1 && 2005 - nla_put(skb, NFTA_HOOK_DEV, 2006 - first->ifnamelen, first->ifname)) 1992 + !hook_is_prefix(first) && 1993 + nla_put_string(skb, NFTA_HOOK_DEV, first->ifname)) 2007 1994 goto nla_put_failure; 2008 1995 } 2009 1996 nla_nest_end(skb, nest); ··· 2313 2302 } 2314 2303 2315 2304 static struct nft_hook *nft_netdev_hook_alloc(struct net *net, 2316 - const struct nlattr *attr) 2305 + const struct nlattr *attr, 2306 + bool prefix) 2317 2307 { 2318 2308 struct nf_hook_ops *ops; 2319 2309 struct net_device *dev; ··· 2331 2319 if (err < 0) 2332 2320 goto err_hook_free; 2333 2321 2334 - hook->ifnamelen = nla_len(attr); 2322 + /* include the terminating NUL-char when comparing non-prefixes */ 2323 + hook->ifnamelen = strlen(hook->ifname) + !prefix; 2335 2324 2336 2325 /* nf_tables_netdev_event() is called under rtnl_mutex, this is 2337 2326 * indirectly serializing all the other holders of the commit_mutex with ··· 2379 2366 struct nft_hook *hook, *next; 2380 2367 const struct nlattr *tmp; 2381 2368 int rem, n = 0, err; 2369 + bool prefix; 2382 2370 2383 2371 nla_for_each_nested(tmp, attr, rem) { 2384 - if (nla_type(tmp) != NFTA_DEVICE_NAME) { 2372 + switch (nla_type(tmp)) { 2373 + case NFTA_DEVICE_NAME: 2374 + prefix = false; 2375 + break; 2376 + case NFTA_DEVICE_PREFIX: 2377 + prefix = true; 2378 + break; 2379 + default: 2385 2380 err = -EINVAL; 2386 2381 goto err_hook; 2387 2382 } 2388 2383 2389 - hook = nft_netdev_hook_alloc(net, tmp); 2384 + hook = nft_netdev_hook_alloc(net, tmp, prefix); 2390 2385 if (IS_ERR(hook)) { 2391 2386 NL_SET_BAD_ATTR(extack, tmp); 2392 2387 err = PTR_ERR(hook); ··· 2440 2419 int err; 2441 2420 2442 2421 if (tb[NFTA_HOOK_DEV]) { 2443 - hook = nft_netdev_hook_alloc(net, tb[NFTA_HOOK_DEV]); 2422 + hook = nft_netdev_hook_alloc(net, tb[NFTA_HOOK_DEV], false); 2444 2423 if (IS_ERR(hook)) { 2445 2424 NL_SET_BAD_ATTR(extack, tb[NFTA_HOOK_DEV]); 2446 2425 return PTR_ERR(hook); ··· 9470 9449 9471 9450 list_for_each_entry_rcu(hook, hook_list, list, 9472 9451 lockdep_commit_lock_is_held(net)) { 9473 - if (nla_put(skb, NFTA_DEVICE_NAME, 9474 - hook->ifnamelen, hook->ifname)) 9452 + if (nft_nla_put_hook_dev(skb, hook)) 9475 9453 goto nla_put_failure; 9476 9454 } 9477 9455 nla_nest_end(skb, nest_devs);
+1 -1
net/netlink/diag.c
··· 168 168 NETLINK_CB(cb->skb).portid, 169 169 cb->nlh->nlmsg_seq, 170 170 NLM_F_MULTI, 171 - __sock_i_ino(sk)) < 0) { 171 + sock_i_ino(sk)) < 0) { 172 172 ret = 1; 173 173 break; 174 174 }
-2
net/smc/smc_clc.c
··· 426 426 { 427 427 struct smc_clc_msg_hdr *hdr = &dclc->hdr; 428 428 429 - if (hdr->typev1 != SMC_TYPE_R && hdr->typev1 != SMC_TYPE_D) 430 - return false; 431 429 if (hdr->version == SMC_V1) { 432 430 if (ntohs(hdr->length) != sizeof(struct smc_clc_msg_decline)) 433 431 return false;
+3
net/smc/smc_ib.c
··· 742 742 unsigned int i; 743 743 bool ret = false; 744 744 745 + if (!lnk->smcibdev->ibdev->dma_device) 746 + return ret; 747 + 745 748 /* for now there is just one DMA address */ 746 749 for_each_sg(buf_slot->sgt[lnk->link_idx].sgl, sg, 747 750 buf_slot->sgt[lnk->link_idx].nents, i) {
+2 -1
net/wireless/scan.c
··· 1916 1916 */ 1917 1917 1918 1918 f = rcu_access_pointer(new->pub.beacon_ies); 1919 - kfree_rcu((struct cfg80211_bss_ies *)f, rcu_head); 1919 + if (!new->pub.hidden_beacon_bss) 1920 + kfree_rcu((struct cfg80211_bss_ies *)f, rcu_head); 1920 1921 return false; 1921 1922 } 1922 1923
+4 -1
net/wireless/sme.c
··· 900 900 if (!wdev->u.client.ssid_len) { 901 901 rcu_read_lock(); 902 902 for_each_valid_link(cr, link) { 903 + u32 ssid_len; 904 + 903 905 ssid = ieee80211_bss_get_elem(cr->links[link].bss, 904 906 WLAN_EID_SSID); 905 907 906 908 if (!ssid || !ssid->datalen) 907 909 continue; 908 910 909 - memcpy(wdev->u.client.ssid, ssid->data, ssid->datalen); 911 + ssid_len = min(ssid->datalen, IEEE80211_MAX_SSID_LEN); 912 + memcpy(wdev->u.client.ssid, ssid->data, ssid_len); 910 913 wdev->u.client.ssid_len = ssid->datalen; 911 914 break; 912 915 }
+1
rust/kernel/mm/virt.rs
··· 209 209 /// 210 210 /// For the duration of 'a, the referenced vma must be undergoing initialization in an 211 211 /// `f_ops->mmap()` hook. 212 + #[repr(transparent)] 212 213 pub struct VmaNew { 213 214 vma: VmaRef, 214 215 }
+8 -4
scripts/Makefile.kasan
··· 86 86 hwasan-use-short-granules=0 \ 87 87 hwasan-inline-all-checks=0 88 88 89 - # Instrument memcpy/memset/memmove calls by using instrumented __hwasan_mem*(). 90 - ifeq ($(call clang-min-version, 150000)$(call gcc-min-version, 130000),y) 91 - kasan_params += hwasan-kernel-mem-intrinsic-prefix=1 92 - endif 89 + # Instrument memcpy/memset/memmove calls by using instrumented __(hw)asan_mem*(). 90 + ifdef CONFIG_CC_HAS_KASAN_MEMINTRINSIC_PREFIX 91 + ifdef CONFIG_CC_IS_GCC 92 + kasan_params += asan-kernel-mem-intrinsic-prefix=1 93 + else 94 + kasan_params += hwasan-kernel-mem-intrinsic-prefix=1 95 + endif 96 + endif # CONFIG_CC_HAS_KASAN_MEMINTRINSIC_PREFIX 93 97 94 98 endif # CONFIG_KASAN_SW_TAGS 95 99
+1 -1
sound/firewire/motu/motu-hwdep.c
··· 111 111 events = 0; 112 112 spin_unlock_irq(&motu->lock); 113 113 114 - return events | EPOLLOUT; 114 + return events; 115 115 } 116 116 117 117 static int hwdep_get_info(struct snd_motu *motu, void __user *arg)
+1
sound/hda/codecs/hdmi/hdmi.c
··· 1582 1582 static const struct snd_pci_quirk force_connect_list[] = { 1583 1583 SND_PCI_QUIRK(0x103c, 0x83e2, "HP EliteDesk 800 G4", 1), 1584 1584 SND_PCI_QUIRK(0x103c, 0x83ef, "HP MP9 G4 Retail System AMS", 1), 1585 + SND_PCI_QUIRK(0x103c, 0x845a, "HP EliteDesk 800 G4 DM 65W", 1), 1585 1586 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1586 1587 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1587 1588 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
+17
sound/hda/codecs/hdmi/nvhdmi.c
··· 198 198 HDA_CODEC_ID_MODEL(0x10de0098, "GPU 98 HDMI/DP", MODEL_GENERIC), 199 199 HDA_CODEC_ID_MODEL(0x10de0099, "GPU 99 HDMI/DP", MODEL_GENERIC), 200 200 HDA_CODEC_ID_MODEL(0x10de009a, "GPU 9a HDMI/DP", MODEL_GENERIC), 201 + HDA_CODEC_ID_MODEL(0x10de009b, "GPU 9b HDMI/DP", MODEL_GENERIC), 202 + HDA_CODEC_ID_MODEL(0x10de009c, "GPU 9c HDMI/DP", MODEL_GENERIC), 201 203 HDA_CODEC_ID_MODEL(0x10de009d, "GPU 9d HDMI/DP", MODEL_GENERIC), 202 204 HDA_CODEC_ID_MODEL(0x10de009e, "GPU 9e HDMI/DP", MODEL_GENERIC), 203 205 HDA_CODEC_ID_MODEL(0x10de009f, "GPU 9f HDMI/DP", MODEL_GENERIC), 204 206 HDA_CODEC_ID_MODEL(0x10de00a0, "GPU a0 HDMI/DP", MODEL_GENERIC), 207 + HDA_CODEC_ID_MODEL(0x10de00a1, "GPU a1 HDMI/DP", MODEL_GENERIC), 205 208 HDA_CODEC_ID_MODEL(0x10de00a3, "GPU a3 HDMI/DP", MODEL_GENERIC), 206 209 HDA_CODEC_ID_MODEL(0x10de00a4, "GPU a4 HDMI/DP", MODEL_GENERIC), 207 210 HDA_CODEC_ID_MODEL(0x10de00a5, "GPU a5 HDMI/DP", MODEL_GENERIC), 208 211 HDA_CODEC_ID_MODEL(0x10de00a6, "GPU a6 HDMI/DP", MODEL_GENERIC), 209 212 HDA_CODEC_ID_MODEL(0x10de00a7, "GPU a7 HDMI/DP", MODEL_GENERIC), 213 + HDA_CODEC_ID_MODEL(0x10de00a8, "GPU a8 HDMI/DP", MODEL_GENERIC), 214 + HDA_CODEC_ID_MODEL(0x10de00a9, "GPU a9 HDMI/DP", MODEL_GENERIC), 215 + HDA_CODEC_ID_MODEL(0x10de00aa, "GPU aa HDMI/DP", MODEL_GENERIC), 216 + HDA_CODEC_ID_MODEL(0x10de00ab, "GPU ab HDMI/DP", MODEL_GENERIC), 217 + HDA_CODEC_ID_MODEL(0x10de00ad, "GPU ad HDMI/DP", MODEL_GENERIC), 218 + HDA_CODEC_ID_MODEL(0x10de00ae, "GPU ae HDMI/DP", MODEL_GENERIC), 219 + HDA_CODEC_ID_MODEL(0x10de00af, "GPU af HDMI/DP", MODEL_GENERIC), 220 + HDA_CODEC_ID_MODEL(0x10de00b0, "GPU b0 HDMI/DP", MODEL_GENERIC), 221 + HDA_CODEC_ID_MODEL(0x10de00b1, "GPU b1 HDMI/DP", MODEL_GENERIC), 222 + HDA_CODEC_ID_MODEL(0x10de00c0, "GPU c0 HDMI/DP", MODEL_GENERIC), 223 + HDA_CODEC_ID_MODEL(0x10de00c1, "GPU c1 HDMI/DP", MODEL_GENERIC), 224 + HDA_CODEC_ID_MODEL(0x10de00c3, "GPU c3 HDMI/DP", MODEL_GENERIC), 225 + HDA_CODEC_ID_MODEL(0x10de00c4, "GPU c4 HDMI/DP", MODEL_GENERIC), 226 + HDA_CODEC_ID_MODEL(0x10de00c5, "GPU c5 HDMI/DP", MODEL_GENERIC), 210 227 {} /* terminator */ 211 228 }; 212 229 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_nvhdmi);
+2
sound/hda/codecs/hdmi/tegrahdmi.c
··· 299 299 HDA_CODEC_ID_MODEL(0x10de002f, "Tegra194 HDMI/DP2", MODEL_TEGRA), 300 300 HDA_CODEC_ID_MODEL(0x10de0030, "Tegra194 HDMI/DP3", MODEL_TEGRA), 301 301 HDA_CODEC_ID_MODEL(0x10de0031, "Tegra234 HDMI/DP", MODEL_TEGRA234), 302 + HDA_CODEC_ID_MODEL(0x10de0033, "SoC 33 HDMI/DP", MODEL_TEGRA234), 302 303 HDA_CODEC_ID_MODEL(0x10de0034, "Tegra264 HDMI/DP", MODEL_TEGRA234), 304 + HDA_CODEC_ID_MODEL(0x10de0035, "SoC 35 HDMI/DP", MODEL_TEGRA234), 303 305 {} /* terminator */ 304 306 }; 305 307 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_tegrahdmi);
+2
sound/hda/codecs/realtek/alc269.c
··· 7147 7147 SND_PCI_QUIRK(0x1d05, 0x121b, "TongFang GMxAGxx", ALC269_FIXUP_NO_SHUTUP), 7148 7148 SND_PCI_QUIRK(0x1d05, 0x1387, "TongFang GMxIXxx", ALC2XX_FIXUP_HEADSET_MIC), 7149 7149 SND_PCI_QUIRK(0x1d05, 0x1409, "TongFang GMxIXxx", ALC2XX_FIXUP_HEADSET_MIC), 7150 + SND_PCI_QUIRK(0x1d05, 0x300f, "TongFang X6AR5xxY", ALC2XX_FIXUP_HEADSET_MIC), 7151 + SND_PCI_QUIRK(0x1d05, 0x3019, "TongFang X6FR5xxY", ALC2XX_FIXUP_HEADSET_MIC), 7150 7152 SND_PCI_QUIRK(0x1d17, 0x3288, "Haier Boyue G42", ALC269VC_FIXUP_ACER_VCOPPERBOX_PINS), 7151 7153 SND_PCI_QUIRK(0x1d72, 0x1602, "RedmiBook", ALC255_FIXUP_XIAOMI_HEADSET_MIC), 7152 7154 SND_PCI_QUIRK(0x1d72, 0x1701, "XiaomiNotebook Pro", ALC298_FIXUP_DELL1_MIC_NO_PRESENCE),
+6 -3
sound/hda/codecs/side-codecs/tas2781_hda_i2c.c
··· 300 300 { 301 301 efi_guid_t efi_guid = tasdev_fct_efi_guid[LENOVO]; 302 302 char *vars[TASDEV_CALIB_N] = { 303 - "R0_%d", "InvR0_%d", "R0_Low_%d", "Power_%d", "TLim_%d" 303 + "R0_%d", "R0_Low_%d", "InvR0_%d", "Power_%d", "TLim_%d" 304 304 }; 305 305 efi_char16_t efi_name[TAS2563_CAL_VAR_NAME_MAX]; 306 306 unsigned long max_size = TAS2563_CAL_DATA_SIZE; ··· 310 310 struct cali_reg *r = &cd->cali_reg_array; 311 311 unsigned int offset = 0; 312 312 unsigned char *data; 313 + __be32 bedata; 313 314 efi_status_t status; 314 315 unsigned int attr; 315 316 int ret, i, j, k; ··· 328 327 data[offset] = i; 329 328 offset++; 330 329 for (j = 0; j < TASDEV_CALIB_N; ++j) { 331 - ret = snprintf(var8, sizeof(var8), vars[j], i); 332 - 330 + /* EFI name for calibration started with 1, not 0 */ 331 + ret = snprintf(var8, sizeof(var8), vars[j], i + 1); 333 332 if (ret < 0 || ret >= sizeof(var8) - 1) { 334 333 dev_err(p->dev, "%s: Read %s failed\n", 335 334 __func__, var8); ··· 352 351 i, j, status); 353 352 return -EINVAL; 354 353 } 354 + bedata = cpu_to_be32(*(uint32_t *)&data[offset]); 355 + memcpy(&data[offset], &bedata, sizeof(bedata)); 355 356 offset += TAS2563_CAL_DATA_SIZE; 356 357 } 357 358 }
+23 -3
sound/hda/core/intel-dsp-config.c
··· 116 116 .flags = FLAG_SST, 117 117 .device = PCI_DEVICE_ID_INTEL_HDA_FCL, 118 118 }, 119 + #else /* AVS disabled; force to legacy as SOF doesn't work for SKL or KBL */ 120 + { 121 + .device = PCI_DEVICE_ID_INTEL_HDA_SKL_LP, 122 + }, 123 + { 124 + .device = PCI_DEVICE_ID_INTEL_HDA_KBL_LP, 125 + }, 119 126 #endif 120 127 #if IS_ENABLED(CONFIG_SND_SOC_SOF_APOLLOLAKE) 121 128 { ··· 174 167 175 168 /* 176 169 * CoffeeLake, CannonLake, CometLake, IceLake, TigerLake, AlderLake, 177 - * RaptorLake use legacy HDAudio driver except for Google Chromebooks 178 - * and when DMICs are present. Two cases are required since Coreboot 179 - * does not expose NHLT tables. 170 + * RaptorLake, MeteorLake use legacy HDAudio driver except for Google 171 + * Chromebooks and when DMICs are present. Two cases are required since 172 + * Coreboot does not expose NHLT tables. 180 173 * 181 174 * When the Chromebook quirk is not present, it's based on information 182 175 * that no such device exists. When the quirk is present, it could be ··· 523 516 /* Meteor Lake */ 524 517 #if IS_ENABLED(CONFIG_SND_SOC_SOF_METEORLAKE) 525 518 /* Meteorlake-P */ 519 + { 520 + .flags = FLAG_SOF, 521 + .device = PCI_DEVICE_ID_INTEL_HDA_MTL, 522 + .dmi_table = (const struct dmi_system_id []) { 523 + { 524 + .ident = "Google Chromebooks", 525 + .matches = { 526 + DMI_MATCH(DMI_SYS_VENDOR, "Google"), 527 + } 528 + }, 529 + {} 530 + } 531 + }, 526 532 { 527 533 .flags = FLAG_SOF | FLAG_SOF_ONLY_IF_DMIC_OR_SOUNDWIRE, 528 534 .device = PCI_DEVICE_ID_INTEL_HDA_MTL,
+1 -1
sound/soc/codecs/idt821034.c
··· 1067 1067 1068 1068 ret = idt821034_set_slic_conf(idt821034, ch, slic_conf); 1069 1069 if (ret) { 1070 - dev_err(&idt821034->spi->dev, "dir in gpio %d (%u, 0x%x) failed (%d)\n", 1070 + dev_err(&idt821034->spi->dev, "dir out gpio %d (%u, 0x%x) failed (%d)\n", 1071 1071 offset, ch, mask, ret); 1072 1072 } 1073 1073
+1 -1
sound/soc/renesas/rcar/core.c
··· 597 597 598 598 dev_dbg(dev, "%s is connected to io (%s)\n", 599 599 rsnd_mod_name(mod), 600 - snd_pcm_direction_name(io->substream->stream)); 600 + rsnd_io_is_play(io) ? "Playback" : "Capture"); 601 601 602 602 return 0; 603 603 }
+15 -10
sound/soc/soc-core.c
··· 369 369 *snd_soc_lookup_component_nolocked(struct device *dev, const char *driver_name) 370 370 { 371 371 struct snd_soc_component *component; 372 - struct snd_soc_component *found_component; 373 372 374 - found_component = NULL; 375 373 for_each_component(component) { 376 - if ((dev == component->dev) && 377 - (!driver_name || 378 - (driver_name == component->driver->name) || 379 - (strcmp(component->driver->name, driver_name) == 0))) { 380 - found_component = component; 381 - break; 382 - } 374 + if (dev != component->dev) 375 + continue; 376 + 377 + if (!driver_name) 378 + return component; 379 + 380 + if (!component->driver->name) 381 + continue; 382 + 383 + if (component->driver->name == driver_name) 384 + return component; 385 + 386 + if (strcmp(component->driver->name, driver_name) == 0) 387 + return component; 383 388 } 384 389 385 - return found_component; 390 + return NULL; 386 391 } 387 392 EXPORT_SYMBOL_GPL(snd_soc_lookup_component_nolocked); 388 393
+1
sound/soc/sof/intel/ptl.c
··· 143 143 .read_sdw_lcount = hda_sdw_check_lcount_ext, 144 144 .check_sdw_irq = lnl_dsp_check_sdw_irq, 145 145 .check_sdw_wakeen_irq = lnl_sdw_check_wakeen_irq, 146 + .sdw_process_wakeen = hda_sdw_process_wakeen_common, 146 147 .check_ipc_irq = mtl_dsp_check_ipc_irq, 147 148 .cl_init = mtl_dsp_cl_init, 148 149 .power_down_dsp = mtl_power_down_dsp,
+8 -4
sound/usb/format.c
··· 327 327 max_rate = combine_quad(&fmt[6]); 328 328 329 329 switch (max_rate) { 330 + case 192000: 331 + if (rate == 176400 || rate == 192000) 332 + return true; 333 + fallthrough; 334 + case 96000: 335 + if (rate == 88200 || rate == 96000) 336 + return true; 337 + fallthrough; 330 338 case 48000: 331 339 return (rate == 44100 || rate == 48000); 332 - case 96000: 333 - return (rate == 88200 || rate == 96000); 334 - case 192000: 335 - return (rate == 176400 || rate == 192000); 336 340 default: 337 341 usb_audio_info(chip, 338 342 "%u:%d : unexpected max rate: %u\n",
+3 -5
sound/usb/mixer_quirks.c
··· 4608 4608 if (unitid == 7 && cval->control == UAC_FU_VOLUME) 4609 4609 snd_dragonfly_quirk_db_scale(mixer, cval, kctl); 4610 4610 break; 4611 + } 4612 + 4611 4613 /* lowest playback value is muted on some devices */ 4612 - case USB_ID(0x0d8c, 0x000c): /* C-Media */ 4613 - case USB_ID(0x0d8c, 0x0014): /* C-Media */ 4614 - case USB_ID(0x19f7, 0x0003): /* RODE NT-USB */ 4614 + if (mixer->chip->quirk_flags & QUIRK_FLAG_MIXER_MIN_MUTE) 4615 4615 if (strstr(kctl->id.name, "Playback")) 4616 4616 cval->min_mute = 1; 4617 - break; 4618 - } 4619 4617 4620 4618 /* ALSA-ify some Plantronics headset control names */ 4621 4619 if (USB_ID_VENDOR(mixer->chip->usb_id) == 0x047f &&
+20 -2
sound/usb/quirks.c
··· 2199 2199 QUIRK_FLAG_SET_IFACE_FIRST), 2200 2200 DEVICE_FLG(0x0556, 0x0014, /* Phoenix Audio TMX320VC */ 2201 2201 QUIRK_FLAG_GET_SAMPLE_RATE), 2202 + DEVICE_FLG(0x0572, 0x1b08, /* Conexant Systems (Rockwell), Inc. */ 2203 + QUIRK_FLAG_MIXER_MIN_MUTE), 2204 + DEVICE_FLG(0x0572, 0x1b09, /* Conexant Systems (Rockwell), Inc. */ 2205 + QUIRK_FLAG_MIXER_MIN_MUTE), 2202 2206 DEVICE_FLG(0x05a3, 0x9420, /* ELP HD USB Camera */ 2203 2207 QUIRK_FLAG_GET_SAMPLE_RATE), 2204 2208 DEVICE_FLG(0x05a7, 0x1020, /* Bose Companion 5 */ ··· 2245 2241 QUIRK_FLAG_CTL_MSG_DELAY_1M), 2246 2242 DEVICE_FLG(0x0b0e, 0x0349, /* Jabra 550a */ 2247 2243 QUIRK_FLAG_CTL_MSG_DELAY_1M), 2244 + DEVICE_FLG(0x0bda, 0x498a, /* Realtek Semiconductor Corp. */ 2245 + QUIRK_FLAG_MIXER_MIN_MUTE), 2248 2246 DEVICE_FLG(0x0c45, 0x6340, /* Sonix HD USB Camera */ 2249 2247 QUIRK_FLAG_GET_SAMPLE_RATE), 2250 2248 DEVICE_FLG(0x0c45, 0x636b, /* Microdia JP001 USB Camera */ 2251 2249 QUIRK_FLAG_GET_SAMPLE_RATE), 2252 - DEVICE_FLG(0x0d8c, 0x0014, /* USB Audio Device */ 2253 - QUIRK_FLAG_CTL_MSG_DELAY_1M), 2250 + DEVICE_FLG(0x0d8c, 0x000c, /* C-Media */ 2251 + QUIRK_FLAG_MIXER_MIN_MUTE), 2252 + DEVICE_FLG(0x0d8c, 0x0014, /* C-Media */ 2253 + QUIRK_FLAG_CTL_MSG_DELAY_1M | QUIRK_FLAG_MIXER_MIN_MUTE), 2254 2254 DEVICE_FLG(0x0ecb, 0x205c, /* JBL Quantum610 Wireless */ 2255 2255 QUIRK_FLAG_FIXED_RATE), 2256 2256 DEVICE_FLG(0x0ecb, 0x2069, /* JBL Quantum810 Wireless */ ··· 2263 2255 QUIRK_FLAG_SHARE_MEDIA_DEVICE | QUIRK_FLAG_ALIGN_TRANSFER), 2264 2256 DEVICE_FLG(0x1101, 0x0003, /* Audioengine D1 */ 2265 2257 QUIRK_FLAG_GET_SAMPLE_RATE), 2258 + DEVICE_FLG(0x12d1, 0x3a07, /* Huawei Technologies Co., Ltd. */ 2259 + QUIRK_FLAG_MIXER_MIN_MUTE), 2266 2260 DEVICE_FLG(0x1224, 0x2a25, /* Jieli Technology USB PHY 2.0 */ 2267 2261 QUIRK_FLAG_GET_SAMPLE_RATE | QUIRK_FLAG_MIC_RES_16), 2268 2262 DEVICE_FLG(0x1395, 0x740a, /* Sennheiser DECT */ ··· 2303 2293 QUIRK_FLAG_ITF_USB_DSD_DAC | QUIRK_FLAG_CTL_MSG_DELAY), 2304 2294 DEVICE_FLG(0x1901, 0x0191, /* GE B850V3 CP2114 audio interface */ 2305 2295 QUIRK_FLAG_GET_SAMPLE_RATE), 2296 + DEVICE_FLG(0x19f7, 0x0003, /* RODE NT-USB */ 2297 + QUIRK_FLAG_MIXER_MIN_MUTE), 2306 2298 DEVICE_FLG(0x19f7, 0x0035, /* RODE NT-USB+ */ 2307 2299 QUIRK_FLAG_GET_SAMPLE_RATE), 2308 2300 DEVICE_FLG(0x1bcf, 0x2281, /* HD Webcam */ ··· 2355 2343 QUIRK_FLAG_IGNORE_CTL_ERROR), 2356 2344 DEVICE_FLG(0x2912, 0x30c8, /* Audioengine D1 */ 2357 2345 QUIRK_FLAG_GET_SAMPLE_RATE), 2346 + DEVICE_FLG(0x2a70, 0x1881, /* OnePlus Technology (Shenzhen) Co., Ltd. BE02T */ 2347 + QUIRK_FLAG_MIXER_MIN_MUTE), 2358 2348 DEVICE_FLG(0x2b53, 0x0023, /* Fiero SC-01 (firmware v1.0.0 @ 48 kHz) */ 2359 2349 QUIRK_FLAG_GENERIC_IMPLICIT_FB), 2360 2350 DEVICE_FLG(0x2b53, 0x0024, /* Fiero SC-01 (firmware v1.0.0 @ 96 kHz) */ ··· 2367 2353 QUIRK_FLAG_CTL_MSG_DELAY_1M), 2368 2354 DEVICE_FLG(0x2d95, 0x8021, /* VIVO USB-C-XE710 HEADSET */ 2369 2355 QUIRK_FLAG_CTL_MSG_DELAY_1M), 2356 + DEVICE_FLG(0x2d99, 0x0026, /* HECATE G2 GAMING HEADSET */ 2357 + QUIRK_FLAG_MIXER_MIN_MUTE), 2370 2358 DEVICE_FLG(0x2fc6, 0xf0b7, /* iBasso DC07 Pro */ 2371 2359 QUIRK_FLAG_CTL_MSG_DELAY_1M), 2372 2360 DEVICE_FLG(0x30be, 0x0101, /* Schiit Hel */ 2373 2361 QUIRK_FLAG_IGNORE_CTL_ERROR), 2362 + DEVICE_FLG(0x339b, 0x3a07, /* Synaptics HONOR USB-C HEADSET */ 2363 + QUIRK_FLAG_MIXER_MIN_MUTE), 2374 2364 DEVICE_FLG(0x413c, 0xa506, /* Dell AE515 sound bar */ 2375 2365 QUIRK_FLAG_GET_SAMPLE_RATE), 2376 2366 DEVICE_FLG(0x534d, 0x0021, /* MacroSilicon MS2100/MS2106 */
+4
sound/usb/usbaudio.h
··· 196 196 * for the given endpoint. 197 197 * QUIRK_FLAG_MIC_RES_16 and QUIRK_FLAG_MIC_RES_384 198 198 * Set the fixed resolution for Mic Capture Volume (mostly for webcams) 199 + * QUIRK_FLAG_MIXER_MIN_MUTE 200 + * Set minimum volume control value as mute for devices where the lowest 201 + * playback value represents muted state instead of minimum audible volume 199 202 */ 200 203 201 204 #define QUIRK_FLAG_GET_SAMPLE_RATE (1U << 0) ··· 225 222 #define QUIRK_FLAG_FIXED_RATE (1U << 21) 226 223 #define QUIRK_FLAG_MIC_RES_16 (1U << 22) 227 224 #define QUIRK_FLAG_MIC_RES_384 (1U << 23) 225 + #define QUIRK_FLAG_MIXER_MIN_MUTE (1U << 24) 228 226 229 227 #endif /* __USBAUDIO_H */
-3
tools/arch/arm64/include/asm/sysreg.h
··· 1080 1080 1081 1081 #define ARM64_FEATURE_FIELD_BITS 4 1082 1082 1083 - /* Defined for compatibility only, do not add new users. */ 1084 - #define ARM64_FEATURE_MASK(x) (x##_MASK) 1085 - 1086 1083 #ifdef __ASSEMBLY__ 1087 1084 1088 1085 .macro mrs_s, rt, sreg
+1 -1
tools/net/ynl/pyynl/ynl_gen_c.py
··· 830 830 'ynl_attr_for_each_nested(attr2, attr) {', 831 831 '\tif (ynl_attr_validate(yarg, attr2))', 832 832 '\t\treturn YNL_PARSE_CB_ERROR;', 833 - f'\t{var}->_count.{self.c_name}++;', 833 + f'\tn_{self.c_name}++;', 834 834 '}'] 835 835 return get_lines, None, local_vars 836 836
+2 -3
tools/testing/selftests/arm64/fp/fp-ptrace.c
··· 1187 1187 if (!vl) 1188 1188 return; 1189 1189 1190 - iov.iov_len = SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, SVE_PT_REGS_SVE); 1190 + iov.iov_len = SVE_PT_SIZE(vq, SVE_PT_REGS_SVE); 1191 1191 iov.iov_base = malloc(iov.iov_len); 1192 1192 if (!iov.iov_base) { 1193 1193 ksft_print_msg("Failed allocating %lu byte SVE write buffer\n", ··· 1234 1234 if (!vl) 1235 1235 return; 1236 1236 1237 - iov.iov_len = SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, 1238 - SVE_PT_REGS_FPSIMD); 1237 + iov.iov_len = SVE_PT_SIZE(vq, SVE_PT_REGS_FPSIMD); 1239 1238 iov.iov_base = malloc(iov.iov_len); 1240 1239 if (!iov.iov_base) { 1241 1240 ksft_print_msg("Failed allocating %lu byte SVE write buffer\n",
+2 -2
tools/testing/selftests/drivers/net/hw/csum.py
··· 17 17 ip_args = f"-{ipver} -S {cfg.remote_addr_v[ipver]} -D {cfg.addr_v[ipver]}" 18 18 19 19 rx_cmd = f"{cfg.bin_local} -i {cfg.ifname} -n 100 {ip_args} -r 1 -R {extra_args}" 20 - tx_cmd = f"{cfg.bin_remote} -i {cfg.ifname} -n 100 {ip_args} -r 1 -T {extra_args}" 20 + tx_cmd = f"{cfg.bin_remote} -i {cfg.remote_ifname} -n 100 {ip_args} -r 1 -T {extra_args}" 21 21 22 22 with bkg(rx_cmd, exit_wait=True): 23 23 wait_port_listen(34000, proto="udp") ··· 37 37 if extra_args != "-U -Z": 38 38 extra_args += " -r 1" 39 39 40 - rx_cmd = f"{cfg.bin_remote} -i {cfg.ifname} -L 1 -n 100 {ip_args} -R {extra_args}" 40 + rx_cmd = f"{cfg.bin_remote} -i {cfg.remote_ifname} -L 1 -n 100 {ip_args} -R {extra_args}" 41 41 tx_cmd = f"{cfg.bin_local} -i {cfg.ifname} -L 1 -n 100 {ip_args} -T {extra_args}" 42 42 43 43 with bkg(rx_cmd, host=cfg.remote, exit_wait=True):
+2 -2
tools/testing/selftests/kselftest_harness.h
··· 751 751 for (; _metadata->trigger; _metadata->trigger = \ 752 752 __bail(_assert, _metadata)) 753 753 754 - #define is_signed_type(var) (!!(((__typeof__(var))(-1)) < (__typeof__(var))1)) 754 + #define is_signed_var(var) (!!(((__typeof__(var))(-1)) < (__typeof__(var))1)) 755 755 756 756 #define __EXPECT(_expected, _expected_str, _seen, _seen_str, _t, _assert) do { \ 757 757 /* Avoid multiple evaluation of the cases */ \ ··· 759 759 __typeof__(_seen) __seen = (_seen); \ 760 760 if (!(__exp _t __seen)) { \ 761 761 /* Report with actual signedness to avoid weird output. */ \ 762 - switch (is_signed_type(__exp) * 2 + is_signed_type(__seen)) { \ 762 + switch (is_signed_var(__exp) * 2 + is_signed_var(__seen)) { \ 763 763 case 0: { \ 764 764 uintmax_t __exp_print = (uintmax_t)__exp; \ 765 765 uintmax_t __seen_print = (uintmax_t)__seen; \
+1
tools/testing/selftests/kvm/Makefile.kvm
··· 169 169 TEST_GEN_PROGS_arm64 += arm64/vgic_lpi_stress 170 170 TEST_GEN_PROGS_arm64 += arm64/vpmu_counter_access 171 171 TEST_GEN_PROGS_arm64 += arm64/no-vgic-v3 172 + TEST_GEN_PROGS_arm64 += arm64/kvm-uuid 172 173 TEST_GEN_PROGS_arm64 += access_tracking_perf_test 173 174 TEST_GEN_PROGS_arm64 += arch_timer 174 175 TEST_GEN_PROGS_arm64 += coalesced_io_test
+1 -1
tools/testing/selftests/kvm/arm64/aarch32_id_regs.c
··· 146 146 147 147 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 148 148 149 - el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val); 149 + el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val); 150 150 return el0 == ID_AA64PFR0_EL1_EL0_IMP; 151 151 } 152 152
+6 -6
tools/testing/selftests/kvm/arm64/debug-exceptions.c
··· 116 116 117 117 /* Reset all bcr/bvr/wcr/wvr registers */ 118 118 dfr0 = read_sysreg(id_aa64dfr0_el1); 119 - brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), dfr0); 119 + brps = FIELD_GET(ID_AA64DFR0_EL1_BRPs, dfr0); 120 120 for (i = 0; i <= brps; i++) { 121 121 write_dbgbcr(i, 0); 122 122 write_dbgbvr(i, 0); 123 123 } 124 - wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), dfr0); 124 + wrps = FIELD_GET(ID_AA64DFR0_EL1_WRPs, dfr0); 125 125 for (i = 0; i <= wrps; i++) { 126 126 write_dbgwcr(i, 0); 127 127 write_dbgwvr(i, 0); ··· 418 418 419 419 static int debug_version(uint64_t id_aa64dfr0) 420 420 { 421 - return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), id_aa64dfr0); 421 + return FIELD_GET(ID_AA64DFR0_EL1_DebugVer, id_aa64dfr0); 422 422 } 423 423 424 424 static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) ··· 539 539 int b, w, c; 540 540 541 541 /* Number of breakpoints */ 542 - brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), aa64dfr0) + 1; 542 + brp_num = FIELD_GET(ID_AA64DFR0_EL1_BRPs, aa64dfr0) + 1; 543 543 __TEST_REQUIRE(brp_num >= 2, "At least two breakpoints are required"); 544 544 545 545 /* Number of watchpoints */ 546 - wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), aa64dfr0) + 1; 546 + wrp_num = FIELD_GET(ID_AA64DFR0_EL1_WRPs, aa64dfr0) + 1; 547 547 548 548 /* Number of context aware breakpoints */ 549 - ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), aa64dfr0) + 1; 549 + ctx_brp_num = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, aa64dfr0) + 1; 550 550 551 551 pr_debug("%s brp_num:%d, wrp_num:%d, ctx_brp_num:%d\n", __func__, 552 552 brp_num, wrp_num, ctx_brp_num);
+70
tools/testing/selftests/kvm/arm64/kvm-uuid.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + 3 + // Check that nobody has tampered with KVM's UID 4 + 5 + #include <errno.h> 6 + #include <linux/arm-smccc.h> 7 + #include <asm/kvm.h> 8 + #include <kvm_util.h> 9 + 10 + #include "processor.h" 11 + 12 + /* 13 + * Do NOT redefine these constants, or try to replace them with some 14 + * "common" version. They are hardcoded here to detect any potential 15 + * breakage happening in the rest of the kernel. 16 + * 17 + * KVM UID value: 28b46fb6-2ec5-11e9-a9ca-4b564d003a74 18 + */ 19 + #define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0 0xb66fb428U 20 + #define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1 0xe911c52eU 21 + #define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_2 0x564bcaa9U 22 + #define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_3 0x743a004dU 23 + 24 + static void guest_code(void) 25 + { 26 + struct arm_smccc_res res = {}; 27 + 28 + smccc_hvc(ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID, 0, 0, 0, 0, 0, 0, 0, &res); 29 + 30 + __GUEST_ASSERT(res.a0 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0 && 31 + res.a1 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1 && 32 + res.a2 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_2 && 33 + res.a3 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_3, 34 + "Unexpected KVM-specific UID %lx %lx %lx %lx\n", res.a0, res.a1, res.a2, res.a3); 35 + GUEST_DONE(); 36 + } 37 + 38 + int main (int argc, char *argv[]) 39 + { 40 + struct kvm_vcpu *vcpu; 41 + struct kvm_vm *vm; 42 + struct ucall uc; 43 + bool guest_done = false; 44 + 45 + vm = vm_create_with_one_vcpu(&vcpu, guest_code); 46 + 47 + while (!guest_done) { 48 + vcpu_run(vcpu); 49 + 50 + switch (get_ucall(vcpu, &uc)) { 51 + case UCALL_SYNC: 52 + break; 53 + case UCALL_DONE: 54 + guest_done = true; 55 + break; 56 + case UCALL_ABORT: 57 + REPORT_GUEST_ASSERT(uc); 58 + break; 59 + case UCALL_PRINTF: 60 + printf("%s", uc.buffer); 61 + break; 62 + default: 63 + TEST_FAIL("Unexpected guest exit"); 64 + } 65 + } 66 + 67 + kvm_vm_free(vm); 68 + 69 + return 0; 70 + }
+2 -2
tools/testing/selftests/kvm/arm64/no-vgic-v3.c
··· 54 54 * Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having 55 55 * hidden the feature at runtime without any other userspace action. 56 56 */ 57 - __GUEST_ASSERT(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 57 + __GUEST_ASSERT(FIELD_GET(ID_AA64PFR0_EL1_GIC, 58 58 read_sysreg(id_aa64pfr0_el1)) == 0, 59 59 "GICv3 wrongly advertised"); 60 60 ··· 165 165 166 166 vm = vm_create_with_one_vcpu(&vcpu, NULL); 167 167 pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 168 - __TEST_REQUIRE(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), pfr0), 168 + __TEST_REQUIRE(FIELD_GET(ID_AA64PFR0_EL1_GIC, pfr0), 169 169 "GICv3 not supported."); 170 170 kvm_vm_free(vm); 171 171
+3 -3
tools/testing/selftests/kvm/arm64/page_fault_test.c
··· 95 95 uint64_t isar0 = read_sysreg(id_aa64isar0_el1); 96 96 uint64_t atomic; 97 97 98 - atomic = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC), isar0); 98 + atomic = FIELD_GET(ID_AA64ISAR0_EL1_ATOMIC, isar0); 99 99 return atomic >= 2; 100 100 } 101 101 102 102 static bool guest_check_dc_zva(void) 103 103 { 104 104 uint64_t dczid = read_sysreg(dczid_el0); 105 - uint64_t dzp = FIELD_GET(ARM64_FEATURE_MASK(DCZID_EL0_DZP), dczid); 105 + uint64_t dzp = FIELD_GET(DCZID_EL0_DZP, dczid); 106 106 107 107 return dzp == 0; 108 108 } ··· 195 195 uint64_t hadbs, tcr; 196 196 197 197 /* Skip if HA is not supported. */ 198 - hadbs = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS), mmfr1); 198 + hadbs = FIELD_GET(ID_AA64MMFR1_EL1_HAFDBS, mmfr1); 199 199 if (hadbs == 0) 200 200 return false; 201 201
+5 -4
tools/testing/selftests/kvm/arm64/set_id_regs.c
··· 243 243 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1); 244 244 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); 245 245 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); 246 + GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1); 246 247 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); 247 248 GUEST_REG_SYNC(SYS_CTR_EL0); 248 249 GUEST_REG_SYNC(SYS_MIDR_EL1); ··· 595 594 */ 596 595 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 597 596 598 - mte = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), val); 599 - mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val); 597 + mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val); 598 + mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 600 599 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 || 601 600 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) { 602 601 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n"); ··· 613 612 } 614 613 615 614 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); 616 - mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val); 615 + mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val); 617 616 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI) 618 617 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n"); 619 618 else ··· 775 774 776 775 /* Check for AARCH64 only system */ 777 776 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); 778 - el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val); 777 + el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val); 779 778 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP); 780 779 781 780 ksft_print_header();
+1 -1
tools/testing/selftests/kvm/arm64/vpmu_counter_access.c
··· 441 441 442 442 /* Make sure that PMUv3 support is indicated in the ID register */ 443 443 dfr0 = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1)); 444 - pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), dfr0); 444 + pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer, dfr0); 445 445 TEST_ASSERT(pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && 446 446 pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP, 447 447 "Unexpected PMUVER (0x%x) on the vCPU with PMUv3", pmuver);
+3 -3
tools/testing/selftests/kvm/lib/arm64/processor.c
··· 573 573 err = ioctl(vcpu_fd, KVM_GET_ONE_REG, &reg); 574 574 TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); 575 575 576 - gran = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN4), val); 576 + gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN4, val); 577 577 *ipa4k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN4_NI, 578 578 ID_AA64MMFR0_EL1_TGRAN4_52_BIT); 579 579 580 - gran = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN64), val); 580 + gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN64, val); 581 581 *ipa64k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN64_NI, 582 582 ID_AA64MMFR0_EL1_TGRAN64_IMP); 583 583 584 - gran = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN16), val); 584 + gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN16, val); 585 585 *ipa16k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN16_NI, 586 586 ID_AA64MMFR0_EL1_TGRAN16_52_BIT); 587 587
+2 -2
tools/testing/selftests/mm/cow.c
··· 1554 1554 } 1555 1555 1556 1556 /* Read from the page to populate the shared zeropage. */ 1557 - FORCE_READ(mem); 1558 - FORCE_READ(smem); 1557 + FORCE_READ(*mem); 1558 + FORCE_READ(*smem); 1559 1559 1560 1560 fn(mem, smem, pagesize); 1561 1561 munmap:
+1 -1
tools/testing/selftests/mm/guard-regions.c
··· 145 145 if (write) 146 146 *ptr = 'x'; 147 147 else 148 - FORCE_READ(ptr); 148 + FORCE_READ(*ptr); 149 149 } 150 150 151 151 signal_jump_set = false;
+3 -1
tools/testing/selftests/mm/hugetlb-madvise.c
··· 50 50 unsigned long i; 51 51 52 52 for (i = 0; i < nr_pages; i++) { 53 + unsigned long *addr2 = 54 + ((unsigned long *)(addr + (i * huge_page_size))); 53 55 /* Prevent the compiler from optimizing out the entire loop: */ 54 - FORCE_READ(((unsigned long *)(addr + (i * huge_page_size)))); 56 + FORCE_READ(*addr2); 55 57 } 56 58 } 57 59
+1 -1
tools/testing/selftests/mm/migration.c
··· 110 110 * the memory access actually happens and prevents the compiler 111 111 * from optimizing away this entire loop. 112 112 */ 113 - FORCE_READ((uint64_t *)ptr); 113 + FORCE_READ(*(uint64_t *)ptr); 114 114 } 115 115 116 116 return NULL;
+1 -1
tools/testing/selftests/mm/pagemap_ioctl.c
··· 1525 1525 1526 1526 ret = madvise(mem, hpage_size, MADV_HUGEPAGE); 1527 1527 if (!ret) { 1528 - FORCE_READ(mem); 1528 + FORCE_READ(*mem); 1529 1529 1530 1530 ret = pagemap_ioctl(mem, hpage_size, &vec, 1, 0, 1531 1531 0, PAGE_IS_PFNZERO, 0, 0, PAGE_IS_PFNZERO);
+5 -2
tools/testing/selftests/mm/split_huge_page_test.c
··· 439 439 } 440 440 madvise(*addr, fd_size, MADV_HUGEPAGE); 441 441 442 - for (size_t i = 0; i < fd_size; i++) 443 - FORCE_READ((*addr + i)); 442 + for (size_t i = 0; i < fd_size; i++) { 443 + char *addr2 = *addr + i; 444 + 445 + FORCE_READ(*addr2); 446 + } 444 447 445 448 if (!check_huge_file(*addr, fd_size / pmd_pagesize, pmd_pagesize)) { 446 449 ksft_print_msg("No large pagecache folio generated, please provide a filesystem supporting large folio\n");
+1 -1
tools/testing/selftests/mm/vm_util.h
··· 23 23 * anything with it in order to trigger a read page fault. We therefore must use 24 24 * volatile to stop the compiler from optimising this away. 25 25 */ 26 - #define FORCE_READ(x) (*(volatile typeof(x) *)x) 26 + #define FORCE_READ(x) (*(const volatile typeof(x) *)&(x)) 27 27 28 28 extern unsigned int __page_size; 29 29 extern unsigned int __page_shift;
+1
tools/testing/selftests/net/Makefile
··· 99 99 TEST_GEN_PROGS += bind_timewait 100 100 TEST_PROGS += test_vxlan_mdb.sh 101 101 TEST_PROGS += test_bridge_neigh_suppress.sh 102 + TEST_PROGS += test_vxlan_nh.sh 102 103 TEST_PROGS += test_vxlan_nolocalbypass.sh 103 104 TEST_PROGS += test_bridge_backup_port.sh 104 105 TEST_PROGS += test_neigh.sh
+2 -2
tools/testing/selftests/net/bind_bhash.c
··· 75 75 int *array = (int *)arg; 76 76 77 77 for (i = 0; i < MAX_CONNECTIONS; i++) { 78 - sock_fd = bind_socket(SO_REUSEADDR | SO_REUSEPORT, setup_addr); 78 + sock_fd = bind_socket(SO_REUSEPORT, setup_addr); 79 79 if (sock_fd < 0) { 80 80 ret = sock_fd; 81 81 pthread_exit(&ret); ··· 103 103 104 104 setup_addr = use_v6 ? setup_addr_v6 : setup_addr_v4; 105 105 106 - listener_fd = bind_socket(SO_REUSEADDR | SO_REUSEPORT, setup_addr); 106 + listener_fd = bind_socket(SO_REUSEPORT, setup_addr); 107 107 if (listen(listener_fd, 100) < 0) { 108 108 perror("listen failed"); 109 109 return -1;
+1 -1
tools/testing/selftests/net/netfilter/conntrack_clash.sh
··· 99 99 local entries 100 100 local cre 101 101 102 - if ! ip netns exec "$ns" ./udpclash $daddr $dport;then 102 + if ! ip netns exec "$ns" timeout 30 ./udpclash $daddr $dport;then 103 103 echo "INFO: did not receive expected number of replies for $daddr:$dport" 104 104 ip netns exec "$ctns" conntrack -S 105 105 # don't fail: check if clash resolution triggered after all.
+3 -2
tools/testing/selftests/net/netfilter/conntrack_resize.sh
··· 187 187 [ -x udpclash ] || return 188 188 189 189 while [ $now -lt $end ]; do 190 - ip netns exec "$ns" ./udpclash 127.0.0.1 $((RANDOM%65536)) > /dev/null 2>&1 190 + ip netns exec "$ns" timeout 30 ./udpclash 127.0.0.1 $((RANDOM%65536)) > /dev/null 2>&1 191 191 192 192 now=$(date +%s) 193 193 done ··· 277 277 insert_flood() 278 278 { 279 279 local n="$1" 280 + local timeout="$2" 280 281 local r=0 281 282 282 283 r=$((RANDOM%$insert_count)) ··· 303 302 read tainted_then < /proc/sys/kernel/tainted 304 303 305 304 for n in "$nsclient1" "$nsclient2";do 306 - insert_flood "$n" & 305 + insert_flood "$n" "$timeout" & 307 306 done 308 307 309 308 # resize table constantly while flood/insert/dump/flushs
+76 -37
tools/testing/selftests/net/netfilter/nft_flowtable.sh
··· 20 20 SOCAT_TIMEOUT=60 21 21 22 22 nsin="" 23 + nsin_small="" 23 24 ns1out="" 24 25 ns2out="" 25 26 ··· 37 36 38 37 cleanup_all_ns 39 38 40 - rm -f "$nsin" "$ns1out" "$ns2out" 39 + rm -f "$nsin" "$nsin_small" "$ns1out" "$ns2out" 41 40 42 41 [ "$log_netns" -eq 0 ] && sysctl -q net.netfilter.nf_log_all_netns="$log_netns" 43 42 } ··· 73 72 rmtu=2000 74 73 75 74 filesize=$((2 * 1024 * 1024)) 75 + filesize_small=$((filesize / 16)) 76 76 77 77 usage(){ 78 78 echo "nft_flowtable.sh [OPTIONS]" ··· 91 89 o) omtu=$OPTARG;; 92 90 l) lmtu=$OPTARG;; 93 91 r) rmtu=$OPTARG;; 94 - s) filesize=$OPTARG;; 92 + s) 93 + filesize=$OPTARG 94 + filesize_small=$((OPTARG / 16)) 95 + ;; 95 96 *) usage;; 96 97 esac 97 98 done ··· 220 215 fi 221 216 222 217 nsin=$(mktemp) 218 + nsin_small=$(mktemp) 223 219 ns1out=$(mktemp) 224 220 ns2out=$(mktemp) 225 221 ··· 271 265 check_dscp() 272 266 { 273 267 local what=$1 268 + local pmtud="$2" 274 269 local ok=1 275 270 276 271 local counter ··· 284 277 local pc4z=${counter%*bytes*} 285 278 local pc4z=${pc4z#*packets} 286 279 280 + local failmsg="FAIL: pmtu $pmtu: $what counters do not match, expected" 281 + 287 282 case "$what" in 288 283 "dscp_none") 289 284 if [ "$pc4" -gt 0 ] || [ "$pc4z" -eq 0 ]; then 290 - echo "FAIL: dscp counters do not match, expected dscp3 == 0, dscp0 > 0, but got $pc4,$pc4z" 1>&2 285 + echo "$failmsg dscp3 == 0, dscp0 > 0, but got $pc4,$pc4z" 1>&2 291 286 ret=1 292 287 ok=0 293 288 fi 294 289 ;; 295 290 "dscp_fwd") 296 291 if [ "$pc4" -eq 0 ] || [ "$pc4z" -eq 0 ]; then 297 - echo "FAIL: dscp counters do not match, expected dscp3 and dscp0 > 0 but got $pc4,$pc4z" 1>&2 292 + echo "$failmsg dscp3 and dscp0 > 0 but got $pc4,$pc4z" 1>&2 298 293 ret=1 299 294 ok=0 300 295 fi 301 296 ;; 302 297 "dscp_ingress") 303 298 if [ "$pc4" -eq 0 ] || [ "$pc4z" -gt 0 ]; then 304 - echo "FAIL: dscp counters do not match, expected dscp3 > 0, dscp0 == 0 but got $pc4,$pc4z" 1>&2 299 + echo "$failmsg dscp3 > 0, dscp0 == 0 but got $pc4,$pc4z" 1>&2 305 300 ret=1 306 301 ok=0 307 302 fi 308 303 ;; 309 304 "dscp_egress") 310 305 if [ "$pc4" -eq 0 ] || [ "$pc4z" -gt 0 ]; then 311 - echo "FAIL: dscp counters do not match, expected dscp3 > 0, dscp0 == 0 but got $pc4,$pc4z" 1>&2 306 + echo "$failmsg dscp3 > 0, dscp0 == 0 but got $pc4,$pc4z" 1>&2 312 307 ret=1 313 308 ok=0 314 309 fi 315 310 ;; 316 311 *) 317 - echo "FAIL: Unknown DSCP check" 1>&2 312 + echo "$failmsg: Unknown DSCP check" 1>&2 318 313 ret=1 319 314 ok=0 320 315 esac ··· 328 319 329 320 check_transfer() 330 321 { 331 - in=$1 332 - out=$2 333 - what=$3 322 + local in=$1 323 + local out=$2 324 + local what=$3 334 325 335 326 if ! cmp "$in" "$out" > /dev/null 2>&1; then 336 327 echo "FAIL: file mismatch for $what" 1>&2 ··· 351 342 { 352 343 local nsa=$1 353 344 local nsb=$2 354 - local dstip=$3 355 - local dstport=$4 345 + local pmtu=$3 346 + local dstip=$4 347 + local dstport=$5 356 348 local lret=0 349 + local socatc 350 + local socatl 351 + local infile="$nsin" 357 352 358 - timeout "$SOCAT_TIMEOUT" ip netns exec "$nsb" socat -4 TCP-LISTEN:12345,reuseaddr STDIO < "$nsin" > "$ns2out" & 353 + if [ $pmtu -eq 0 ]; then 354 + infile="$nsin_small" 355 + fi 356 + 357 + timeout "$SOCAT_TIMEOUT" ip netns exec "$nsb" socat -4 TCP-LISTEN:12345,reuseaddr STDIO < "$infile" > "$ns2out" & 359 358 lpid=$! 360 359 361 360 busywait 1000 listener_ready 362 361 363 - timeout "$SOCAT_TIMEOUT" ip netns exec "$nsa" socat -4 TCP:"$dstip":"$dstport" STDIO < "$nsin" > "$ns1out" 362 + timeout "$SOCAT_TIMEOUT" ip netns exec "$nsa" socat -4 TCP:"$dstip":"$dstport" STDIO < "$infile" > "$ns1out" 363 + socatc=$? 364 364 365 365 wait $lpid 366 + socatl=$? 366 367 367 - if ! check_transfer "$nsin" "$ns2out" "ns1 -> ns2"; then 368 + if [ $socatl -ne 0 ] || [ $socatc -ne 0 ];then 369 + rc=1 370 + fi 371 + 372 + if ! check_transfer "$infile" "$ns2out" "ns1 -> ns2"; then 368 373 lret=1 369 374 ret=1 370 375 fi 371 376 372 - if ! check_transfer "$nsin" "$ns1out" "ns1 <- ns2"; then 377 + if ! check_transfer "$infile" "$ns1out" "ns1 <- ns2"; then 373 378 lret=1 374 379 ret=1 375 380 fi ··· 393 370 394 371 test_tcp_forwarding() 395 372 { 396 - test_tcp_forwarding_ip "$1" "$2" 10.0.2.99 12345 373 + local pmtu="$3" 374 + 375 + test_tcp_forwarding_ip "$1" "$2" "$pmtu" 10.0.2.99 12345 397 376 398 377 return $? 399 378 } 400 379 401 380 test_tcp_forwarding_set_dscp() 402 381 { 403 - check_dscp "dscp_none" 382 + local pmtu="$3" 404 383 405 384 ip netns exec "$nsr1" nft -f - <<EOF 406 385 table netdev dscpmangle { ··· 413 388 } 414 389 EOF 415 390 if [ $? -eq 0 ]; then 416 - test_tcp_forwarding_ip "$1" "$2" 10.0.2.99 12345 417 - check_dscp "dscp_ingress" 391 + test_tcp_forwarding_ip "$1" "$2" "$3" 10.0.2.99 12345 392 + check_dscp "dscp_ingress" "$pmtu" 418 393 419 394 ip netns exec "$nsr1" nft delete table netdev dscpmangle 420 395 else ··· 430 405 } 431 406 EOF 432 407 if [ $? -eq 0 ]; then 433 - test_tcp_forwarding_ip "$1" "$2" 10.0.2.99 12345 434 - check_dscp "dscp_egress" 408 + test_tcp_forwarding_ip "$1" "$2" "$pmtu" 10.0.2.99 12345 409 + check_dscp "dscp_egress" "$pmtu" 435 410 436 - ip netns exec "$nsr1" nft flush table netdev dscpmangle 411 + ip netns exec "$nsr1" nft delete table netdev dscpmangle 437 412 else 438 413 echo "SKIP: Could not load netdev:egress for veth1" 439 414 fi ··· 441 416 # partial. If flowtable really works, then both dscp-is-0 and dscp-is-cs3 442 417 # counters should have seen packets (before and after ft offload kicks in). 443 418 ip netns exec "$nsr1" nft -a insert rule inet filter forward ip dscp set cs3 444 - test_tcp_forwarding_ip "$1" "$2" 10.0.2.99 12345 445 - check_dscp "dscp_fwd" 419 + test_tcp_forwarding_ip "$1" "$2" "$pmtu" 10.0.2.99 12345 420 + check_dscp "dscp_fwd" "$pmtu" 446 421 } 447 422 448 423 test_tcp_forwarding_nat() 449 424 { 425 + local nsa="$1" 426 + local nsb="$2" 427 + local pmtu="$3" 428 + local what="$4" 450 429 local lret 451 - local pmtu 452 430 453 - test_tcp_forwarding_ip "$1" "$2" 10.0.2.99 12345 431 + [ "$pmtu" -eq 0 ] && what="$what (pmtu disabled)" 432 + 433 + test_tcp_forwarding_ip "$nsa" "$nsb" "$pmtu" 10.0.2.99 12345 454 434 lret=$? 455 - 456 - pmtu=$3 457 - what=$4 458 435 459 436 if [ "$lret" -eq 0 ] ; then 460 437 if [ "$pmtu" -eq 1 ] ;then 461 - check_counters "flow offload for ns1/ns2 with masquerade and pmtu discovery $what" 438 + check_counters "flow offload for ns1/ns2 with masquerade $what" 462 439 else 463 440 echo "PASS: flow offload for ns1/ns2 with masquerade $what" 464 441 fi 465 442 466 - test_tcp_forwarding_ip "$1" "$2" 10.6.6.6 1666 443 + test_tcp_forwarding_ip "$1" "$2" "$pmtu" 10.6.6.6 1666 467 444 lret=$? 468 445 if [ "$pmtu" -eq 1 ] ;then 469 - check_counters "flow offload for ns1/ns2 with dnat and pmtu discovery $what" 446 + check_counters "flow offload for ns1/ns2 with dnat $what" 470 447 elif [ "$lret" -eq 0 ] ; then 471 448 echo "PASS: flow offload for ns1/ns2 with dnat $what" 472 449 fi 450 + else 451 + echo "FAIL: flow offload for ns1/ns2 with dnat $what" 473 452 fi 474 453 475 454 return $lret 476 455 } 477 456 478 457 make_file "$nsin" "$filesize" 458 + make_file "$nsin_small" "$filesize_small" 479 459 480 460 # First test: 481 461 # No PMTU discovery, nsr1 is expected to fragment packets from ns1 to ns2 as needed. 482 462 # Due to MTU mismatch in both directions, all packets (except small packets like pure 483 463 # acks) have to be handled by normal forwarding path. Therefore, packet counters 484 464 # are not checked. 485 - if test_tcp_forwarding "$ns1" "$ns2"; then 465 + if test_tcp_forwarding "$ns1" "$ns2" 0; then 486 466 echo "PASS: flow offloaded for ns1/ns2" 487 467 else 488 468 echo "FAIL: flow offload for ns1/ns2:" 1>&2 ··· 519 489 } 520 490 EOF 521 491 492 + check_dscp "dscp_none" "0" 522 493 if ! test_tcp_forwarding_set_dscp "$ns1" "$ns2" 0 ""; then 523 - echo "FAIL: flow offload for ns1/ns2 with dscp update" 1>&2 494 + echo "FAIL: flow offload for ns1/ns2 with dscp update and no pmtu discovery" 1>&2 524 495 exit 0 525 496 fi 526 497 ··· 543 512 # are lower than file size and packets were forwarded via flowtable layer. 544 513 # For earlier tests (large mtus), packets cannot be handled via flowtable 545 514 # (except pure acks and other small packets). 515 + ip netns exec "$nsr1" nft reset counters table inet filter >/dev/null 516 + ip netns exec "$ns2" nft reset counters table inet filter >/dev/null 517 + 518 + if ! test_tcp_forwarding_set_dscp "$ns1" "$ns2" 1 ""; then 519 + echo "FAIL: flow offload for ns1/ns2 with dscp update and pmtu discovery" 1>&2 520 + exit 0 521 + fi 522 + 546 523 ip netns exec "$nsr1" nft reset counters table inet filter >/dev/null 547 524 548 525 if ! test_tcp_forwarding_nat "$ns1" "$ns2" 1 ""; then ··· 683 644 ip -net "$ns2" route add default via 10.0.2.1 684 645 ip -net "$ns2" route add default via dead:2::1 685 646 686 - if test_tcp_forwarding "$ns1" "$ns2"; then 647 + if test_tcp_forwarding "$ns1" "$ns2" 1; then 687 648 check_counters "ipsec tunnel mode for ns1/ns2" 688 649 else 689 650 echo "FAIL: ipsec tunnel mode for ns1/ns2" ··· 707 668 fi 708 669 709 670 echo "re-run with random mtus and file size: -o $o -l $l -r $r -s $filesize" 710 - $0 -o "$o" -l "$l" -r "$r" -s "$filesize" 671 + $0 -o "$o" -l "$l" -r "$r" -s "$filesize" || ret=1 711 672 fi 712 673 713 674 exit $ret
+1 -1
tools/testing/selftests/net/netfilter/udpclash.c
··· 29 29 int sockfd; 30 30 }; 31 31 32 - static int wait = 1; 32 + static volatile int wait = 1; 33 33 34 34 static void *thread_main(void *varg) 35 35 {
+223
tools/testing/selftests/net/test_vxlan_nh.sh
··· 1 + #!/bin/bash 2 + # SPDX-License-Identifier: GPL-2.0 3 + 4 + source lib.sh 5 + TESTS=" 6 + basic_tx_ipv4 7 + basic_tx_ipv6 8 + learning 9 + proxy_ipv4 10 + proxy_ipv6 11 + " 12 + VERBOSE=0 13 + 14 + ################################################################################ 15 + # Utilities 16 + 17 + run_cmd() 18 + { 19 + local cmd="$1" 20 + local out 21 + local stderr="2>/dev/null" 22 + 23 + if [ "$VERBOSE" = "1" ]; then 24 + echo "COMMAND: $cmd" 25 + stderr= 26 + fi 27 + 28 + out=$(eval "$cmd" "$stderr") 29 + rc=$? 30 + if [ "$VERBOSE" -eq 1 ] && [ -n "$out" ]; then 31 + echo " $out" 32 + fi 33 + 34 + return $rc 35 + } 36 + 37 + ################################################################################ 38 + # Cleanup 39 + 40 + exit_cleanup_all() 41 + { 42 + cleanup_all_ns 43 + exit "${EXIT_STATUS}" 44 + } 45 + 46 + ################################################################################ 47 + # Tests 48 + 49 + nh_stats_get() 50 + { 51 + ip -n "$ns1" -s -j nexthop show id 10 | jq ".[][\"group_stats\"][][\"packets\"]" 52 + } 53 + 54 + tc_stats_get() 55 + { 56 + tc_rule_handle_stats_get "dev dummy1 egress" 101 ".packets" "-n $ns1" 57 + } 58 + 59 + basic_tx_common() 60 + { 61 + local af_str=$1; shift 62 + local proto=$1; shift 63 + local local_addr=$1; shift 64 + local plen=$1; shift 65 + local remote_addr=$1; shift 66 + 67 + RET=0 68 + 69 + # Test basic Tx functionality. Check that stats are incremented on 70 + # both the FDB nexthop group and the egress device. 71 + 72 + run_cmd "ip -n $ns1 link add name dummy1 up type dummy" 73 + run_cmd "ip -n $ns1 route add $remote_addr/$plen dev dummy1" 74 + run_cmd "tc -n $ns1 qdisc add dev dummy1 clsact" 75 + run_cmd "tc -n $ns1 filter add dev dummy1 egress proto $proto pref 1 handle 101 flower ip_proto udp dst_ip $remote_addr dst_port 4789 action pass" 76 + 77 + run_cmd "ip -n $ns1 address add $local_addr/$plen dev lo" 78 + 79 + run_cmd "ip -n $ns1 nexthop add id 1 via $remote_addr fdb" 80 + run_cmd "ip -n $ns1 nexthop add id 10 group 1 fdb" 81 + 82 + run_cmd "ip -n $ns1 link add name vx0 up type vxlan id 10010 local $local_addr dstport 4789" 83 + run_cmd "bridge -n $ns1 fdb add 00:11:22:33:44:55 dev vx0 self static nhid 10" 84 + 85 + run_cmd "ip netns exec $ns1 mausezahn vx0 -a own -b 00:11:22:33:44:55 -c 1 -q" 86 + 87 + busywait "$BUSYWAIT_TIMEOUT" until_counter_is "== 1" nh_stats_get > /dev/null 88 + check_err $? "FDB nexthop group stats did not increase" 89 + 90 + busywait "$BUSYWAIT_TIMEOUT" until_counter_is "== 1" tc_stats_get > /dev/null 91 + check_err $? "tc filter stats did not increase" 92 + 93 + log_test "VXLAN FDB nexthop: $af_str basic Tx" 94 + } 95 + 96 + basic_tx_ipv4() 97 + { 98 + basic_tx_common "IPv4" ipv4 192.0.2.1 32 192.0.2.2 99 + } 100 + 101 + basic_tx_ipv6() 102 + { 103 + basic_tx_common "IPv6" ipv6 2001:db8:1::1 128 2001:db8:1::2 104 + } 105 + 106 + learning() 107 + { 108 + RET=0 109 + 110 + # When learning is enabled on the VXLAN device, an incoming packet 111 + # might try to refresh an FDB entry that points to an FDB nexthop group 112 + # instead of an ordinary remote destination. Check that the kernel does 113 + # not crash in this situation. 114 + 115 + run_cmd "ip -n $ns1 address add 192.0.2.1/32 dev lo" 116 + run_cmd "ip -n $ns1 address add 192.0.2.2/32 dev lo" 117 + 118 + run_cmd "ip -n $ns1 nexthop add id 1 via 192.0.2.3 fdb" 119 + run_cmd "ip -n $ns1 nexthop add id 10 group 1 fdb" 120 + 121 + run_cmd "ip -n $ns1 link add name vx0 up type vxlan id 10010 local 192.0.2.1 dstport 12345 localbypass" 122 + run_cmd "ip -n $ns1 link add name vx1 up type vxlan id 10020 local 192.0.2.2 dstport 54321 learning" 123 + 124 + run_cmd "bridge -n $ns1 fdb add 00:11:22:33:44:55 dev vx0 self static dst 192.0.2.2 port 54321 vni 10020" 125 + run_cmd "bridge -n $ns1 fdb add 00:aa:bb:cc:dd:ee dev vx1 self static nhid 10" 126 + 127 + run_cmd "ip netns exec $ns1 mausezahn vx0 -a 00:aa:bb:cc:dd:ee -b 00:11:22:33:44:55 -c 1 -q" 128 + 129 + log_test "VXLAN FDB nexthop: learning" 130 + } 131 + 132 + proxy_common() 133 + { 134 + local af_str=$1; shift 135 + local local_addr=$1; shift 136 + local plen=$1; shift 137 + local remote_addr=$1; shift 138 + local neigh_addr=$1; shift 139 + local ping_cmd=$1; shift 140 + 141 + RET=0 142 + 143 + # When the "proxy" option is enabled on the VXLAN device, the device 144 + # will suppress ARP requests and IPv6 Neighbor Solicitation messages if 145 + # it is able to reply on behalf of the remote host. That is, if a 146 + # matching and valid neighbor entry is configured on the VXLAN device 147 + # whose MAC address is not behind the "any" remote (0.0.0.0 / ::). The 148 + # FDB entry for the neighbor's MAC address might point to an FDB 149 + # nexthop group instead of an ordinary remote destination. Check that 150 + # the kernel does not crash in this situation. 151 + 152 + run_cmd "ip -n $ns1 address add $local_addr/$plen dev lo" 153 + 154 + run_cmd "ip -n $ns1 nexthop add id 1 via $remote_addr fdb" 155 + run_cmd "ip -n $ns1 nexthop add id 10 group 1 fdb" 156 + 157 + run_cmd "ip -n $ns1 link add name vx0 up type vxlan id 10010 local $local_addr dstport 4789 proxy" 158 + 159 + run_cmd "ip -n $ns1 neigh add $neigh_addr lladdr 00:11:22:33:44:55 nud perm dev vx0" 160 + 161 + run_cmd "bridge -n $ns1 fdb add 00:11:22:33:44:55 dev vx0 self static nhid 10" 162 + 163 + run_cmd "ip netns exec $ns1 $ping_cmd" 164 + 165 + log_test "VXLAN FDB nexthop: $af_str proxy" 166 + } 167 + 168 + proxy_ipv4() 169 + { 170 + proxy_common "IPv4" 192.0.2.1 32 192.0.2.2 192.0.2.3 \ 171 + "arping -b -c 1 -s 192.0.2.1 -I vx0 192.0.2.3" 172 + } 173 + 174 + proxy_ipv6() 175 + { 176 + proxy_common "IPv6" 2001:db8:1::1 128 2001:db8:1::2 2001:db8:1::3 \ 177 + "ndisc6 -r 1 -s 2001:db8:1::1 -w 1 2001:db8:1::3 vx0" 178 + } 179 + 180 + ################################################################################ 181 + # Usage 182 + 183 + usage() 184 + { 185 + cat <<EOF 186 + usage: ${0##*/} OPTS 187 + 188 + -t <test> Test(s) to run (default: all) 189 + (options: $TESTS) 190 + -p Pause on fail 191 + -v Verbose mode (show commands and output) 192 + EOF 193 + } 194 + 195 + ################################################################################ 196 + # Main 197 + 198 + while getopts ":t:pvh" opt; do 199 + case $opt in 200 + t) TESTS=$OPTARG;; 201 + p) PAUSE_ON_FAIL=yes;; 202 + v) VERBOSE=$((VERBOSE + 1));; 203 + h) usage; exit 0;; 204 + *) usage; exit 1;; 205 + esac 206 + done 207 + 208 + require_command mausezahn 209 + require_command arping 210 + require_command ndisc6 211 + require_command jq 212 + 213 + if ! ip nexthop help 2>&1 | grep -q "stats"; then 214 + echo "SKIP: iproute2 ip too old, missing nexthop stats support" 215 + exit "$ksft_skip" 216 + fi 217 + 218 + trap exit_cleanup_all EXIT 219 + 220 + for t in $TESTS 221 + do 222 + setup_ns ns1; $t; cleanup_all_ns; 223 + done
+5 -5
tools/testing/selftests/ublk/file_backed.c
··· 20 20 struct io_uring_sqe *sqe[1]; 21 21 22 22 ublk_io_alloc_sqes(t, sqe, 1); 23 - io_uring_prep_fsync(sqe[0], 1 /*fds[1]*/, IORING_FSYNC_DATASYNC); 23 + io_uring_prep_fsync(sqe[0], ublk_get_registered_fd(q, 1) /*fds[1]*/, IORING_FSYNC_DATASYNC); 24 24 io_uring_sqe_set_flags(sqe[0], IOSQE_FIXED_FILE); 25 25 /* bit63 marks us as tgt io */ 26 26 sqe[0]->user_data = build_user_data(tag, ublk_op, 0, q->q_id, 1); ··· 42 42 if (!sqe[0]) 43 43 return -ENOMEM; 44 44 45 - io_uring_prep_rw(op, sqe[0], 1 /*fds[1]*/, 45 + io_uring_prep_rw(op, sqe[0], ublk_get_registered_fd(q, 1) /*fds[1]*/, 46 46 addr, 47 47 iod->nr_sectors << 9, 48 48 iod->start_sector << 9); ··· 56 56 57 57 ublk_io_alloc_sqes(t, sqe, 3); 58 58 59 - io_uring_prep_buf_register(sqe[0], 0, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 59 + io_uring_prep_buf_register(sqe[0], q, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 60 60 sqe[0]->flags |= IOSQE_CQE_SKIP_SUCCESS | IOSQE_IO_HARDLINK; 61 61 sqe[0]->user_data = build_user_data(tag, 62 62 ublk_cmd_op_nr(sqe[0]->cmd_op), 0, q->q_id, 1); 63 63 64 - io_uring_prep_rw(op, sqe[1], 1 /*fds[1]*/, 0, 64 + io_uring_prep_rw(op, sqe[1], ublk_get_registered_fd(q, 1) /*fds[1]*/, 0, 65 65 iod->nr_sectors << 9, 66 66 iod->start_sector << 9); 67 67 sqe[1]->buf_index = tag; 68 68 sqe[1]->flags |= IOSQE_FIXED_FILE | IOSQE_IO_HARDLINK; 69 69 sqe[1]->user_data = build_user_data(tag, ublk_op, 0, q->q_id, 1); 70 70 71 - io_uring_prep_buf_unregister(sqe[2], 0, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 71 + io_uring_prep_buf_unregister(sqe[2], q, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 72 72 sqe[2]->user_data = build_user_data(tag, ublk_cmd_op_nr(sqe[2]->cmd_op), 0, q->q_id, 1); 73 73 74 74 return 2;
+31 -7
tools/testing/selftests/ublk/kublk.c
··· 432 432 } 433 433 } 434 434 435 - static int ublk_queue_init(struct ublk_queue *q, unsigned extra_flags) 435 + static int ublk_queue_init(struct ublk_queue *q, unsigned long long extra_flags) 436 436 { 437 437 struct ublk_dev *dev = q->dev; 438 438 int depth = dev->dev_info.queue_depth; ··· 445 445 q->q_depth = depth; 446 446 q->flags = dev->dev_info.flags; 447 447 q->flags |= extra_flags; 448 + 449 + /* Cache fd in queue for fast path access */ 450 + q->ublk_fd = dev->fds[0]; 448 451 449 452 cmd_buf_size = ublk_queue_cmd_buf_sz(q); 450 453 off = UBLKSRV_CMD_BUF_OFFSET + q->q_id * ublk_queue_max_cmd_buf_sz(); ··· 484 481 return -ENOMEM; 485 482 } 486 483 487 - static int ublk_thread_init(struct ublk_thread *t) 484 + static int ublk_thread_init(struct ublk_thread *t, unsigned long long extra_flags) 488 485 { 489 486 struct ublk_dev *dev = t->dev; 487 + unsigned long long flags = dev->dev_info.flags | extra_flags; 490 488 int ring_depth = dev->tgt.sq_depth, cq_depth = dev->tgt.cq_depth; 491 489 int ret; 492 490 ··· 516 512 517 513 io_uring_register_ring_fd(&t->ring); 518 514 519 - ret = io_uring_register_files(&t->ring, dev->fds, dev->nr_fds); 515 + if (flags & UBLKS_Q_NO_UBLK_FIXED_FD) { 516 + /* Register only backing files starting from index 1, exclude ublk control device */ 517 + if (dev->nr_fds > 1) { 518 + ret = io_uring_register_files(&t->ring, &dev->fds[1], dev->nr_fds - 1); 519 + } else { 520 + /* No backing files to register, skip file registration */ 521 + ret = 0; 522 + } 523 + } else { 524 + ret = io_uring_register_files(&t->ring, dev->fds, dev->nr_fds); 525 + } 520 526 if (ret) { 521 527 ublk_err("ublk dev %d thread %d register files failed %d\n", 522 528 t->dev->dev_info.dev_id, t->idx, ret); ··· 640 626 641 627 /* These fields should be written once, never change */ 642 628 ublk_set_sqe_cmd_op(sqe[0], cmd_op); 643 - sqe[0]->fd = 0; /* dev->fds[0] */ 629 + sqe[0]->fd = ublk_get_registered_fd(q, 0); /* dev->fds[0] */ 644 630 sqe[0]->opcode = IORING_OP_URING_CMD; 645 - sqe[0]->flags = IOSQE_FIXED_FILE; 631 + if (q->flags & UBLKS_Q_NO_UBLK_FIXED_FD) 632 + sqe[0]->flags = 0; /* Use raw FD, not fixed file */ 633 + else 634 + sqe[0]->flags = IOSQE_FIXED_FILE; 646 635 sqe[0]->rw_flags = 0; 647 636 cmd->tag = io->tag; 648 637 cmd->q_id = q->q_id; ··· 849 832 unsigned idx; 850 833 sem_t *ready; 851 834 cpu_set_t *affinity; 835 + unsigned long long extra_flags; 852 836 }; 853 837 854 838 static void *ublk_io_handler_fn(void *data) ··· 862 844 t->dev = info->dev; 863 845 t->idx = info->idx; 864 846 865 - ret = ublk_thread_init(t); 847 + ret = ublk_thread_init(t, info->extra_flags); 866 848 if (ret) { 867 849 ublk_err("ublk dev %d thread %u init failed\n", 868 850 dev_id, t->idx); ··· 952 934 953 935 if (ctx->auto_zc_fallback) 954 936 extra_flags = UBLKS_Q_AUTO_BUF_REG_FALLBACK; 937 + if (ctx->no_ublk_fixed_fd) 938 + extra_flags |= UBLKS_Q_NO_UBLK_FIXED_FD; 955 939 956 940 for (i = 0; i < dinfo->nr_hw_queues; i++) { 957 941 dev->q[i].dev = dev; ··· 971 951 tinfo[i].dev = dev; 972 952 tinfo[i].idx = i; 973 953 tinfo[i].ready = &ready; 954 + tinfo[i].extra_flags = extra_flags; 974 955 975 956 /* 976 957 * If threads are not tied 1:1 to queues, setting thread ··· 1492 1471 printf("%s %s -t [null|loop|stripe|fault_inject] [-q nr_queues] [-d depth] [-n dev_id]\n", 1493 1472 exe, recovery ? "recover" : "add"); 1494 1473 printf("\t[--foreground] [--quiet] [-z] [--auto_zc] [--auto_zc_fallback] [--debug_mask mask] [-r 0|1 ] [-g]\n"); 1495 - printf("\t[-e 0|1 ] [-i 0|1]\n"); 1474 + printf("\t[-e 0|1 ] [-i 0|1] [--no_ublk_fixed_fd]\n"); 1496 1475 printf("\t[--nthreads threads] [--per_io_tasks]\n"); 1497 1476 printf("\t[target options] [backfile1] [backfile2] ...\n"); 1498 1477 printf("\tdefault: nr_queues=2(max 32), depth=128(max 1024), dev_id=-1(auto allocation)\n"); ··· 1555 1534 { "size", 1, NULL, 's'}, 1556 1535 { "nthreads", 1, NULL, 0 }, 1557 1536 { "per_io_tasks", 0, NULL, 0 }, 1537 + { "no_ublk_fixed_fd", 0, NULL, 0 }, 1558 1538 { 0, 0, 0, 0 } 1559 1539 }; 1560 1540 const struct ublk_tgt_ops *ops = NULL; ··· 1635 1613 ctx.nthreads = strtol(optarg, NULL, 10); 1636 1614 if (!strcmp(longopts[option_idx].name, "per_io_tasks")) 1637 1615 ctx.per_io_tasks = 1; 1616 + if (!strcmp(longopts[option_idx].name, "no_ublk_fixed_fd")) 1617 + ctx.no_ublk_fixed_fd = 1; 1638 1618 break; 1639 1619 case '?': 1640 1620 /*
+31 -14
tools/testing/selftests/ublk/kublk.h
··· 77 77 unsigned int recovery:1; 78 78 unsigned int auto_zc_fallback:1; 79 79 unsigned int per_io_tasks:1; 80 + unsigned int no_ublk_fixed_fd:1; 80 81 81 82 int _evtfd; 82 83 int _shmid; ··· 167 166 168 167 /* borrow one bit of ublk uapi flags, which may never be used */ 169 168 #define UBLKS_Q_AUTO_BUF_REG_FALLBACK (1ULL << 63) 169 + #define UBLKS_Q_NO_UBLK_FIXED_FD (1ULL << 62) 170 170 __u64 flags; 171 + int ublk_fd; /* cached ublk char device fd */ 171 172 struct ublk_io ios[UBLK_QUEUE_DEPTH]; 172 173 }; 173 174 ··· 276 273 return nr_sqes; 277 274 } 278 275 279 - static inline void io_uring_prep_buf_register(struct io_uring_sqe *sqe, 280 - int dev_fd, int tag, int q_id, __u64 index) 276 + static inline int ublk_get_registered_fd(struct ublk_queue *q, int fd_index) 277 + { 278 + if (q->flags & UBLKS_Q_NO_UBLK_FIXED_FD) { 279 + if (fd_index == 0) 280 + /* Return the raw ublk FD for index 0 */ 281 + return q->ublk_fd; 282 + /* Adjust index for backing files (index 1 becomes 0, etc.) */ 283 + return fd_index - 1; 284 + } 285 + return fd_index; 286 + } 287 + 288 + static inline void __io_uring_prep_buf_reg_unreg(struct io_uring_sqe *sqe, 289 + struct ublk_queue *q, int tag, int q_id, __u64 index) 281 290 { 282 291 struct ublksrv_io_cmd *cmd = (struct ublksrv_io_cmd *)sqe->cmd; 292 + int dev_fd = ublk_get_registered_fd(q, 0); 283 293 284 294 io_uring_prep_read(sqe, dev_fd, 0, 0, 0); 285 295 sqe->opcode = IORING_OP_URING_CMD; 286 - sqe->flags |= IOSQE_FIXED_FILE; 287 - sqe->cmd_op = UBLK_U_IO_REGISTER_IO_BUF; 296 + if (q->flags & UBLKS_Q_NO_UBLK_FIXED_FD) 297 + sqe->flags &= ~IOSQE_FIXED_FILE; 298 + else 299 + sqe->flags |= IOSQE_FIXED_FILE; 288 300 289 301 cmd->tag = tag; 290 302 cmd->addr = index; 291 303 cmd->q_id = q_id; 292 304 } 293 305 294 - static inline void io_uring_prep_buf_unregister(struct io_uring_sqe *sqe, 295 - int dev_fd, int tag, int q_id, __u64 index) 306 + static inline void io_uring_prep_buf_register(struct io_uring_sqe *sqe, 307 + struct ublk_queue *q, int tag, int q_id, __u64 index) 296 308 { 297 - struct ublksrv_io_cmd *cmd = (struct ublksrv_io_cmd *)sqe->cmd; 309 + __io_uring_prep_buf_reg_unreg(sqe, q, tag, q_id, index); 310 + sqe->cmd_op = UBLK_U_IO_REGISTER_IO_BUF; 311 + } 298 312 299 - io_uring_prep_read(sqe, dev_fd, 0, 0, 0); 300 - sqe->opcode = IORING_OP_URING_CMD; 301 - sqe->flags |= IOSQE_FIXED_FILE; 313 + static inline void io_uring_prep_buf_unregister(struct io_uring_sqe *sqe, 314 + struct ublk_queue *q, int tag, int q_id, __u64 index) 315 + { 316 + __io_uring_prep_buf_reg_unreg(sqe, q, tag, q_id, index); 302 317 sqe->cmd_op = UBLK_U_IO_UNREGISTER_IO_BUF; 303 - 304 - cmd->tag = tag; 305 - cmd->addr = index; 306 - cmd->q_id = q_id; 307 318 } 308 319 309 320 static inline void *ublk_get_sqe_cmd(const struct io_uring_sqe *sqe)
+2 -2
tools/testing/selftests/ublk/null.c
··· 63 63 64 64 ublk_io_alloc_sqes(t, sqe, 3); 65 65 66 - io_uring_prep_buf_register(sqe[0], 0, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 66 + io_uring_prep_buf_register(sqe[0], q, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 67 67 sqe[0]->user_data = build_user_data(tag, 68 68 ublk_cmd_op_nr(sqe[0]->cmd_op), 0, q->q_id, 1); 69 69 sqe[0]->flags |= IOSQE_CQE_SKIP_SUCCESS | IOSQE_IO_HARDLINK; ··· 71 71 __setup_nop_io(tag, iod, sqe[1], q->q_id); 72 72 sqe[1]->flags |= IOSQE_IO_HARDLINK; 73 73 74 - io_uring_prep_buf_unregister(sqe[2], 0, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 74 + io_uring_prep_buf_unregister(sqe[2], q, tag, q->q_id, ublk_get_io(q, tag)->buf_index); 75 75 sqe[2]->user_data = build_user_data(tag, ublk_cmd_op_nr(sqe[2]->cmd_op), 0, q->q_id, 1); 76 76 77 77 // buf register is marked as IOSQE_CQE_SKIP_SUCCESS
+2 -2
tools/testing/selftests/ublk/stripe.c
··· 142 142 ublk_io_alloc_sqes(t, sqe, s->nr + extra); 143 143 144 144 if (zc) { 145 - io_uring_prep_buf_register(sqe[0], 0, tag, q->q_id, io->buf_index); 145 + io_uring_prep_buf_register(sqe[0], q, tag, q->q_id, io->buf_index); 146 146 sqe[0]->flags |= IOSQE_CQE_SKIP_SUCCESS | IOSQE_IO_HARDLINK; 147 147 sqe[0]->user_data = build_user_data(tag, 148 148 ublk_cmd_op_nr(sqe[0]->cmd_op), 0, q->q_id, 1); ··· 168 168 if (zc) { 169 169 struct io_uring_sqe *unreg = sqe[s->nr + 1]; 170 170 171 - io_uring_prep_buf_unregister(unreg, 0, tag, q->q_id, io->buf_index); 171 + io_uring_prep_buf_unregister(unreg, q, tag, q->q_id, io->buf_index); 172 172 unreg->user_data = build_user_data( 173 173 tag, ublk_cmd_op_nr(unreg->cmd_op), 0, q->q_id, 1); 174 174 }
+3 -3
tools/testing/selftests/ublk/test_stress_04.sh
··· 28 28 _create_backfile 1 128M 29 29 _create_backfile 2 128M 30 30 31 - ublk_io_and_kill_daemon 8G -t null -q 4 -z & 32 - ublk_io_and_kill_daemon 256M -t loop -q 4 -z "${UBLK_BACKFILES[0]}" & 31 + ublk_io_and_kill_daemon 8G -t null -q 4 -z --no_ublk_fixed_fd & 32 + ublk_io_and_kill_daemon 256M -t loop -q 4 -z --no_ublk_fixed_fd "${UBLK_BACKFILES[0]}" & 33 33 ublk_io_and_kill_daemon 256M -t stripe -q 4 -z "${UBLK_BACKFILES[1]}" "${UBLK_BACKFILES[2]}" & 34 34 35 35 if _have_feature "AUTO_BUF_REG"; then 36 36 ublk_io_and_kill_daemon 8G -t null -q 4 --auto_zc & 37 37 ublk_io_and_kill_daemon 256M -t loop -q 4 --auto_zc "${UBLK_BACKFILES[0]}" & 38 - ublk_io_and_kill_daemon 256M -t stripe -q 4 --auto_zc "${UBLK_BACKFILES[1]}" "${UBLK_BACKFILES[2]}" & 38 + ublk_io_and_kill_daemon 256M -t stripe -q 4 --auto_zc --no_ublk_fixed_fd "${UBLK_BACKFILES[1]}" "${UBLK_BACKFILES[2]}" & 39 39 ublk_io_and_kill_daemon 8G -t null -q 4 -z --auto_zc --auto_zc_fallback & 40 40 fi 41 41