Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-misc-next-2026-03-05' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v7.1:
Cross-subsystem Changes:
dma-buf:
- Prepare for compile-time concurrency analysis
Core Changes:
buddy:
- Improve assert testing
sched:
- Fix race condition in drm_sched_fini()
- Mark slow tests
Driver Changes:
bridge:
- waveshare-dsi: Fix register and attach; Support 1..4 DSI lanes plus DT bindings
gma500:
- Use DRM client buffer for fbdev framebuffer
gud:
- Test for imported buffers with helper
imagination:
- Fix power domain handling
ivpu:
- Update boot API to v3.29.4
- Limit per-user number of doorbells and contexts
nouveau:
- Test for imported buffers with helper
panel:
- panel-edp: Fix timings for BOE NV140WUM-N64
panfrost:
- Test for imported buffers with helper
panthor:
- Test for imported buffers with helper
vc4:
- Test for imported buffers with helper
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20260305081140.GA171266@linux.fritz.box
+388
-371
+88
-6
drivers/accel/ivpu/ivpu_drv.c
+88
-6
drivers/accel/ivpu/ivpu_drv.c
···
67
67
module_param_named(force_snoop, ivpu_force_snoop, bool, 0444);
68
68
MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access");
69
69
70
+
static struct ivpu_user_limits *ivpu_user_limits_alloc(struct ivpu_device *vdev, uid_t uid)
71
+
{
72
+
struct ivpu_user_limits *limits;
73
+
74
+
limits = kzalloc_obj(*limits);
75
+
if (!limits)
76
+
return ERR_PTR(-ENOMEM);
77
+
78
+
kref_init(&limits->ref);
79
+
atomic_set(&limits->db_count, 0);
80
+
limits->vdev = vdev;
81
+
limits->uid = uid;
82
+
83
+
/* Allow root user to allocate all contexts */
84
+
if (uid == 0) {
85
+
limits->max_ctx_count = ivpu_get_context_count(vdev);
86
+
limits->max_db_count = ivpu_get_doorbell_count(vdev);
87
+
} else {
88
+
limits->max_ctx_count = ivpu_get_context_count(vdev) / 2;
89
+
limits->max_db_count = ivpu_get_doorbell_count(vdev) / 2;
90
+
}
91
+
92
+
hash_add(vdev->user_limits, &limits->hash_node, uid);
93
+
94
+
return limits;
95
+
}
96
+
97
+
static struct ivpu_user_limits *ivpu_user_limits_get(struct ivpu_device *vdev)
98
+
{
99
+
struct ivpu_user_limits *limits;
100
+
uid_t uid = current_uid().val;
101
+
102
+
guard(mutex)(&vdev->user_limits_lock);
103
+
104
+
hash_for_each_possible(vdev->user_limits, limits, hash_node, uid) {
105
+
if (limits->uid == uid) {
106
+
if (kref_read(&limits->ref) >= limits->max_ctx_count) {
107
+
ivpu_dbg(vdev, IOCTL, "User %u exceeded max ctx count %u\n", uid,
108
+
limits->max_ctx_count);
109
+
return ERR_PTR(-EMFILE);
110
+
}
111
+
112
+
kref_get(&limits->ref);
113
+
return limits;
114
+
}
115
+
}
116
+
117
+
return ivpu_user_limits_alloc(vdev, uid);
118
+
}
119
+
120
+
static void ivpu_user_limits_release(struct kref *ref)
121
+
{
122
+
struct ivpu_user_limits *limits = container_of(ref, struct ivpu_user_limits, ref);
123
+
struct ivpu_device *vdev = limits->vdev;
124
+
125
+
lockdep_assert_held(&vdev->user_limits_lock);
126
+
drm_WARN_ON(&vdev->drm, atomic_read(&limits->db_count));
127
+
hash_del(&limits->hash_node);
128
+
kfree(limits);
129
+
}
130
+
131
+
static void ivpu_user_limits_put(struct ivpu_device *vdev, struct ivpu_user_limits *limits)
132
+
{
133
+
guard(mutex)(&vdev->user_limits_lock);
134
+
kref_put(&limits->ref, ivpu_user_limits_release);
135
+
}
136
+
70
137
struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
71
138
{
72
139
struct ivpu_device *vdev = file_priv->vdev;
···
177
110
mutex_unlock(&vdev->context_list_lock);
178
111
pm_runtime_put_autosuspend(vdev->drm.dev);
179
112
113
+
ivpu_user_limits_put(vdev, file_priv->user_limits);
180
114
mutex_destroy(&file_priv->ms_lock);
181
115
mutex_destroy(&file_priv->lock);
182
116
kfree(file_priv);
···
237
169
args->value = ivpu_hw_dpu_max_freq_get(vdev);
238
170
break;
239
171
case DRM_IVPU_PARAM_NUM_CONTEXTS:
240
-
args->value = ivpu_get_context_count(vdev);
172
+
args->value = file_priv->user_limits->max_ctx_count;
241
173
break;
242
174
case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
243
175
args->value = vdev->hw->ranges.user.start;
···
299
231
{
300
232
struct ivpu_device *vdev = to_ivpu_device(dev);
301
233
struct ivpu_file_priv *file_priv;
234
+
struct ivpu_user_limits *limits;
302
235
u32 ctx_id;
303
236
int idx, ret;
304
237
305
238
if (!drm_dev_enter(dev, &idx))
306
239
return -ENODEV;
307
240
241
+
limits = ivpu_user_limits_get(vdev);
242
+
if (IS_ERR(limits)) {
243
+
ret = PTR_ERR(limits);
244
+
goto err_dev_exit;
245
+
}
246
+
308
247
file_priv = kzalloc_obj(*file_priv);
309
248
if (!file_priv) {
310
249
ret = -ENOMEM;
311
-
goto err_dev_exit;
250
+
goto err_user_limits_put;
312
251
}
313
252
314
253
INIT_LIST_HEAD(&file_priv->ms_instance_list);
315
254
316
255
file_priv->vdev = vdev;
317
256
file_priv->bound = true;
257
+
file_priv->user_limits = limits;
318
258
kref_init(&file_priv->ref);
319
259
mutex_init(&file_priv->lock);
320
260
mutex_init(&file_priv->ms_lock);
···
360
284
mutex_destroy(&file_priv->ms_lock);
361
285
mutex_destroy(&file_priv->lock);
362
286
kfree(file_priv);
287
+
err_user_limits_put:
288
+
ivpu_user_limits_put(vdev, limits);
363
289
err_dev_exit:
364
290
drm_dev_exit(idx);
365
291
return ret;
···
421
343
ivpu_ipc_consumer_del(vdev, &cons);
422
344
423
345
if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
424
-
ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n",
425
-
ipc_hdr.data_addr);
346
+
ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n", ipc_hdr.data_addr);
426
347
return -EIO;
427
348
}
428
349
···
530
453
}
531
454
532
455
static const struct file_operations ivpu_fops = {
533
-
.owner = THIS_MODULE,
456
+
.owner = THIS_MODULE,
534
457
DRM_ACCEL_FOPS,
535
458
#ifdef CONFIG_PROC_FS
536
459
.show_fdinfo = drm_show_fdinfo,
···
669
592
xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
670
593
xa_init_flags(&vdev->db_xa, XA_FLAGS_ALLOC1);
671
594
INIT_LIST_HEAD(&vdev->bo_list);
595
+
hash_init(vdev->user_limits);
672
596
673
597
vdev->db_limit.min = IVPU_MIN_DB;
674
598
vdev->db_limit.max = IVPU_MAX_DB;
675
599
676
600
ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock);
601
+
if (ret)
602
+
goto err_xa_destroy;
603
+
604
+
ret = drmm_mutex_init(&vdev->drm, &vdev->user_limits_lock);
677
605
if (ret)
678
606
goto err_xa_destroy;
679
607
···
799
717
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
800
718
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_WCL) },
801
719
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NVL) },
802
-
{ }
720
+
{}
803
721
};
804
722
MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
805
723
+22
-4
drivers/accel/ivpu/ivpu_drv.h
+22
-4
drivers/accel/ivpu/ivpu_drv.h
···
12
12
#include <drm/drm_mm.h>
13
13
#include <drm/drm_print.h>
14
14
15
+
#include <linux/hashtable.h>
15
16
#include <linux/pci.h>
16
17
#include <linux/xarray.h>
17
18
#include <uapi/drm/ivpu_accel.h>
···
44
43
/* SSID 1 is used by the VPU to represent reserved context */
45
44
#define IVPU_RESERVED_CONTEXT_MMU_SSID 1
46
45
#define IVPU_USER_CONTEXT_MIN_SSID 2
47
-
#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
46
+
#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 128)
48
47
49
48
#define IVPU_MIN_DB 1
50
49
#define IVPU_MAX_DB 255
51
50
52
51
#define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
53
52
#define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
54
-
55
-
#define IVPU_NUM_PRIORITIES 4
56
-
#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
57
53
58
54
#define IVPU_CMDQ_MIN_ID 1
59
55
#define IVPU_CMDQ_MAX_ID 255
···
121
123
struct ivpu_ipc_info;
122
124
struct ivpu_pm_info;
123
125
126
+
struct ivpu_user_limits {
127
+
struct hlist_node hash_node;
128
+
struct ivpu_device *vdev;
129
+
struct kref ref;
130
+
u32 max_ctx_count;
131
+
u32 max_db_count;
132
+
u32 uid;
133
+
atomic_t db_count;
134
+
};
135
+
124
136
struct ivpu_device {
125
137
struct drm_device drm;
126
138
void __iomem *regb;
···
150
142
struct mutex context_list_lock; /* Protects user context addition/removal */
151
143
struct xarray context_xa;
152
144
struct xa_limit context_xa_limit;
145
+
DECLARE_HASHTABLE(user_limits, 8);
146
+
struct mutex user_limits_lock; /* Protects user_limits */
153
147
154
148
struct xarray db_xa;
155
149
struct xa_limit db_limit;
···
199
189
struct list_head ms_instance_list;
200
190
struct ivpu_bo *ms_info_bo;
201
191
struct xa_limit job_limit;
192
+
struct ivpu_user_limits *user_limits;
202
193
u32 job_id_next;
203
194
struct xa_limit cmdq_limit;
204
195
u32 cmdq_id_next;
···
295
284
struct xa_limit ctx_limit = vdev->context_xa_limit;
296
285
297
286
return (ctx_limit.max - ctx_limit.min + 1);
287
+
}
288
+
289
+
static inline u32 ivpu_get_doorbell_count(struct ivpu_device *vdev)
290
+
{
291
+
struct xa_limit db_limit = vdev->db_limit;
292
+
293
+
return (db_limit.max - db_limit.min + 1);
298
294
}
299
295
300
296
static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
+26
-10
drivers/accel/ivpu/ivpu_job.c
+26
-10
drivers/accel/ivpu/ivpu_job.c
···
173
173
ret = xa_alloc_cyclic(&file_priv->cmdq_xa, &cmdq->id, cmdq, file_priv->cmdq_limit,
174
174
&file_priv->cmdq_id_next, GFP_KERNEL);
175
175
if (ret < 0) {
176
-
ivpu_err(vdev, "Failed to allocate command queue ID: %d\n", ret);
176
+
ivpu_dbg(vdev, IOCTL, "Failed to allocate command queue ID: %d\n", ret);
177
177
goto err_free_cmdq;
178
178
}
179
179
···
215
215
216
216
static int ivpu_register_db(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
217
217
{
218
+
struct ivpu_user_limits *limits = file_priv->user_limits;
218
219
struct ivpu_device *vdev = file_priv->vdev;
219
220
int ret;
221
+
222
+
if (atomic_inc_return(&limits->db_count) > limits->max_db_count) {
223
+
ivpu_dbg(vdev, IOCTL, "Maximum number of %u doorbells for uid %u reached\n",
224
+
limits->max_db_count, limits->uid);
225
+
ret = -EBUSY;
226
+
goto err_dec_db_count;
227
+
}
220
228
221
229
ret = xa_alloc_cyclic(&vdev->db_xa, &cmdq->db_id, NULL, vdev->db_limit, &vdev->db_next,
222
230
GFP_KERNEL);
223
231
if (ret < 0) {
224
-
ivpu_err(vdev, "Failed to allocate doorbell ID: %d\n", ret);
225
-
return ret;
232
+
ivpu_dbg(vdev, IOCTL, "Failed to allocate doorbell ID: %d\n", ret);
233
+
goto err_dec_db_count;
226
234
}
227
235
228
236
if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
···
239
231
else
240
232
ret = ivpu_jsm_register_db(vdev, file_priv->ctx.id, cmdq->db_id,
241
233
cmdq->mem->vpu_addr, ivpu_bo_size(cmdq->mem));
242
-
243
-
if (!ret) {
244
-
ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n",
245
-
cmdq->db_id, cmdq->id, file_priv->ctx.id, cmdq->priority);
246
-
} else {
234
+
if (ret) {
247
235
xa_erase(&vdev->db_xa, cmdq->db_id);
248
236
cmdq->db_id = 0;
237
+
goto err_dec_db_count;
249
238
}
250
239
240
+
ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n",
241
+
cmdq->db_id, cmdq->id, file_priv->ctx.id, cmdq->priority);
242
+
return 0;
243
+
244
+
err_dec_db_count:
245
+
atomic_dec(&limits->db_count);
251
246
return ret;
252
247
}
253
248
···
309
298
}
310
299
311
300
xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);
301
+
atomic_dec(&file_priv->user_limits->db_count);
312
302
cmdq->db_id = 0;
313
303
314
304
return 0;
···
325
313
326
314
static void ivpu_cmdq_destroy(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq)
327
315
{
316
+
lockdep_assert_held(&file_priv->lock);
328
317
ivpu_cmdq_unregister(file_priv, cmdq);
329
318
xa_erase(&file_priv->cmdq_xa, cmdq->id);
330
319
ivpu_cmdq_free(file_priv, cmdq);
···
393
380
mutex_lock(&file_priv->lock);
394
381
395
382
xa_for_each(&file_priv->cmdq_xa, cmdq_id, cmdq) {
396
-
xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);
397
-
cmdq->db_id = 0;
383
+
if (cmdq->db_id) {
384
+
xa_erase(&file_priv->vdev->db_xa, cmdq->db_id);
385
+
atomic_dec(&file_priv->user_limits->db_count);
386
+
cmdq->db_id = 0;
387
+
}
398
388
}
399
389
400
390
mutex_unlock(&file_priv->lock);
+93
-118
drivers/accel/ivpu/vpu_boot_api.h
+93
-118
drivers/accel/ivpu/vpu_boot_api.h
···
1
1
/* SPDX-License-Identifier: MIT */
2
2
/*
3
-
* Copyright (c) 2020-2024, Intel Corporation.
3
+
* Copyright (c) 2020-2025, Intel Corporation.
4
+
*/
5
+
6
+
/**
7
+
* @addtogroup Boot
8
+
* @{
9
+
*/
10
+
11
+
/**
12
+
* @file
13
+
* @brief Boot API public header file.
4
14
*/
5
15
6
16
#ifndef VPU_BOOT_API_H
7
17
#define VPU_BOOT_API_H
8
18
9
-
/*
19
+
/**
10
20
* The below values will be used to construct the version info this way:
11
21
* fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
12
22
* VPU_BOOT_API_VER_MINOR;
···
26
16
* partial info a build error will be generated.
27
17
*/
28
18
29
-
/*
19
+
/**
30
20
* Major version changes that break backward compatibility.
31
21
* Major version must start from 1 and can only be incremented.
32
22
*/
33
23
#define VPU_BOOT_API_VER_MAJOR 3
34
24
35
-
/*
25
+
/**
36
26
* Minor version changes when API backward compatibility is preserved.
37
27
* Resets to 0 if Major version is incremented.
38
28
*/
39
-
#define VPU_BOOT_API_VER_MINOR 28
29
+
#define VPU_BOOT_API_VER_MINOR 29
40
30
41
-
/*
31
+
/**
42
32
* API header changed (field names, documentation, formatting) but API itself has not been changed
43
33
*/
44
-
#define VPU_BOOT_API_VER_PATCH 3
34
+
#define VPU_BOOT_API_VER_PATCH 4
45
35
46
-
/*
36
+
/**
47
37
* Index in the API version table
48
38
* Must be unique for each API
49
39
*/
···
51
41
52
42
#pragma pack(push, 4)
53
43
54
-
/*
44
+
/**
55
45
* Firmware image header format
56
46
*/
57
47
#define VPU_FW_HEADER_SIZE 4096
···
71
61
u32 firmware_version_size;
72
62
u64 boot_params_load_address;
73
63
u32 api_version[VPU_FW_API_VER_NUM];
74
-
/* Size of memory require for firmware execution */
64
+
/** Size of memory require for firmware execution */
75
65
u32 runtime_size;
76
66
u32 shave_nn_fw_size;
77
-
/*
67
+
/**
78
68
* Size of primary preemption buffer, assuming a 2-job submission queue.
79
69
* NOTE: host driver is expected to adapt size accordingly to actual
80
70
* submission queue size and device capabilities.
81
71
*/
82
72
u32 preemption_buffer_1_size;
83
-
/*
73
+
/**
84
74
* Size of secondary preemption buffer, assuming a 2-job submission queue.
85
75
* NOTE: host driver is expected to adapt size accordingly to actual
86
76
* submission queue size and device capabilities.
87
77
*/
88
78
u32 preemption_buffer_2_size;
89
-
/*
79
+
/**
90
80
* Maximum preemption buffer size that the FW can use: no need for the host
91
81
* driver to allocate more space than that specified by these fields.
92
82
* A value of 0 means no declared limit.
93
83
*/
94
84
u32 preemption_buffer_1_max_size;
95
85
u32 preemption_buffer_2_max_size;
96
-
/* Space reserved for future preemption-related fields. */
86
+
/** Space reserved for future preemption-related fields. */
97
87
u32 preemption_reserved[4];
98
-
/* FW image read only section start address, 4KB aligned */
88
+
/** FW image read only section start address, 4KB aligned */
99
89
u64 ro_section_start_address;
100
-
/* FW image read only section size, 4KB aligned */
90
+
/** FW image read only section size, 4KB aligned */
101
91
u32 ro_section_size;
102
92
u32 reserved;
103
93
};
104
94
105
-
/*
95
+
/**
106
96
* Firmware boot parameters format
107
97
*/
108
-
109
-
#define VPU_BOOT_PLL_COUNT 3
110
-
#define VPU_BOOT_PLL_OUT_COUNT 4
111
98
112
99
/** Values for boot_type field */
113
100
#define VPU_BOOT_TYPE_COLDBOOT 0
···
173
166
#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
174
167
#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23
175
168
176
-
/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
169
+
/** VPU 30xx HW component IDs are sequential, so define first and last IDs. */
177
170
#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
178
171
#define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15
179
172
···
182
175
u8 cfg;
183
176
};
184
177
185
-
struct vpu_warm_boot_section {
186
-
u32 src;
187
-
u32 dst;
188
-
u32 size;
189
-
u32 core_id;
190
-
u32 is_clear_op;
191
-
};
192
-
193
-
/*
178
+
/**
194
179
* When HW scheduling mode is enabled, a present period is defined.
195
180
* It will be used by VPU to swap between normal and focus priorities
196
181
* to prevent starving of normal priority band (when implemented).
···
205
206
* Enum for dvfs_mode boot param.
206
207
*/
207
208
enum vpu_governor {
208
-
VPU_GOV_DEFAULT = 0, /* Default Governor for the system */
209
-
VPU_GOV_MAX_PERFORMANCE = 1, /* Maximum performance governor */
210
-
VPU_GOV_ON_DEMAND = 2, /* On Demand frequency control governor */
211
-
VPU_GOV_POWER_SAVE = 3, /* Power save governor */
212
-
VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /* On Demand priority based governor */
209
+
VPU_GOV_DEFAULT = 0, /** Default Governor for the system */
210
+
VPU_GOV_MAX_PERFORMANCE = 1, /** Maximum performance governor */
211
+
VPU_GOV_ON_DEMAND = 2, /** On Demand frequency control governor */
212
+
VPU_GOV_POWER_SAVE = 3, /** Power save governor */
213
+
VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /** On Demand priority based governor */
213
214
};
214
215
215
216
struct vpu_boot_params {
216
217
u32 magic;
217
218
u32 vpu_id;
218
219
u32 vpu_count;
219
-
u32 pad0[5];
220
-
/* Clock frequencies: 0x20 - 0xFF */
220
+
u32 reserved_0[5];
221
+
/** Clock frequencies: 0x20 - 0xFF */
221
222
u32 frequency;
222
-
u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
223
+
u32 reserved_1[12];
223
224
u32 perf_clk_frequency;
224
-
u32 pad1[42];
225
-
/* Memory regions: 0x100 - 0x1FF */
225
+
u32 reserved_2[42];
226
+
/** Memory regions: 0x100 - 0x1FF */
226
227
u64 ipc_header_area_start;
227
228
u32 ipc_header_area_size;
228
229
u64 shared_region_base;
···
233
234
u32 global_aliased_pio_size;
234
235
u32 autoconfig;
235
236
struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
236
-
u64 global_memory_allocator_base;
237
-
u32 global_memory_allocator_size;
237
+
u32 reserved_3[3];
238
238
/**
239
239
* ShaveNN FW section VPU base address
240
240
* On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
241
241
*/
242
242
u64 shave_nn_fw_base;
243
-
u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
244
-
u32 pad2[43];
245
-
/* IRQ re-direct numbers: 0x200 - 0x2FF */
243
+
u64 save_restore_ret_address; /** stores the address of FW's restore entry point */
244
+
u32 reserved_4[43];
245
+
/** IRQ re-direct numbers: 0x200 - 0x2FF */
246
246
s32 watchdog_irq_mss;
247
247
s32 watchdog_irq_nce;
248
-
/* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
248
+
/** ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
249
249
u32 host_to_vpu_irq;
250
-
/* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
250
+
/** VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
251
251
u32 job_done_irq;
252
-
/* VPU -> ARM IRQ line to use to request MMU update. */
253
-
u32 mmu_update_request_irq;
254
-
/* ARM -> VPU IRQ line to use to notify of MMU update completion. */
255
-
u32 mmu_update_done_irq;
256
-
/* ARM -> VPU IRQ line to use to request power level change. */
257
-
u32 set_power_level_irq;
258
-
/* VPU -> ARM IRQ line to use to notify of power level change completion. */
259
-
u32 set_power_level_done_irq;
260
-
/* VPU -> ARM IRQ line to use to notify of VPU idle state change */
261
-
u32 set_vpu_idle_update_irq;
262
-
/* VPU -> ARM IRQ line to use to request counter reset. */
263
-
u32 metric_query_event_irq;
264
-
/* ARM -> VPU IRQ line to use to notify of counter reset completion. */
265
-
u32 metric_query_event_done_irq;
266
-
/* VPU -> ARM IRQ line to use to notify of preemption completion. */
267
-
u32 preemption_done_irq;
268
-
/* Padding. */
269
-
u32 pad3[52];
270
-
/* Silicon information: 0x300 - 0x3FF */
252
+
/** Padding. */
253
+
u32 reserved_5[60];
254
+
/** Silicon information: 0x300 - 0x3FF */
271
255
u32 host_version_id;
272
256
u32 si_stepping;
273
257
u64 device_id;
···
276
294
u32 crit_tracing_buff_size;
277
295
u64 verbose_tracing_buff_addr;
278
296
u32 verbose_tracing_buff_size;
279
-
u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
297
+
u64 verbose_tracing_sw_component_mask; /** TO BE REMOVED */
280
298
/**
281
299
* Mask of destinations to which logging messages are delivered; bitwise OR
282
300
* of values defined in vpu_trace_destination enum.
···
290
308
/** Mask of trace message formats supported by the driver */
291
309
u64 tracing_buff_message_format_mask;
292
310
u64 trace_reserved_1[2];
293
-
/**
294
-
* Period at which the VPU reads the temp sensor values into MMIO, on
295
-
* platforms where that is necessary (in ms). 0 to disable reads.
296
-
*/
297
-
u32 temp_sensor_period_ms;
311
+
u32 reserved_6;
298
312
/** PLL ratio for efficient clock frequency */
299
313
u32 pn_freq_pll_ratio;
300
314
/**
···
325
347
* 1: IPC message required to save state on D0i3 entry flow.
326
348
*/
327
349
u32 d0i3_delayed_entry;
328
-
/* Time spent by VPU in D0i3 state */
350
+
/** Time spent by VPU in D0i3 state */
329
351
u64 d0i3_residency_time_us;
330
-
/* Value of VPU perf counter at the time of entering D0i3 state . */
352
+
/** Value of VPU perf counter at the time of entering D0i3 state . */
331
353
u64 d0i3_entry_vpu_ts;
332
-
/*
354
+
/**
333
355
* The system time of the host operating system in microseconds.
334
356
* E.g the number of microseconds since 1st of January 1970, or whatever
335
357
* date the host operating system uses to maintain system time.
···
337
359
* The KMD is required to update this value on every VPU reset.
338
360
*/
339
361
u64 system_time_us;
340
-
u32 pad4[2];
341
-
/*
362
+
u32 reserved_7[2];
363
+
/**
342
364
* The delta between device monotonic time and the current value of the
343
365
* HW timestamp register, in ticks. Written by the firmware during boot.
344
366
* Can be used by the KMD to calculate device time.
345
367
*/
346
368
u64 device_time_delta_ticks;
347
-
u32 pad7[14];
348
-
/* Warm boot information: 0x400 - 0x43F */
349
-
u32 warm_boot_sections_count;
350
-
u32 warm_boot_start_address_reference;
351
-
u32 warm_boot_section_info_address_offset;
352
-
u32 pad5[13];
353
-
/* Power States transitions timestamps: 0x440 - 0x46F*/
354
-
struct {
355
-
/* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
369
+
u32 reserved_8[30];
370
+
/** Power States transitions timestamps: 0x440 - 0x46F*/
371
+
struct power_states_timestamps {
372
+
/** VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
356
373
u64 vpu_active_state_requested;
357
-
/* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
374
+
/** VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
358
375
u64 vpu_active_state_achieved;
359
-
/* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
376
+
/** VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
360
377
u64 vpu_idle_state_requested;
361
-
/* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
378
+
/** VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
362
379
u64 vpu_idle_state_achieved;
363
-
/* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
380
+
/** VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
364
381
u64 vpu_standby_state_requested;
365
-
/* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
382
+
/** VPU_IDLE -> VPU_STANDBY transition completed timestamp */
366
383
u64 vpu_standby_state_achieved;
367
384
} power_states_timestamps;
368
-
/* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
385
+
/** VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
369
386
u32 vpu_scheduling_mode;
370
-
/* Present call period in milliseconds. */
387
+
/** Present call period in milliseconds. */
371
388
u32 vpu_focus_present_timer_ms;
372
-
/* VPU ECC Signaling */
389
+
/** VPU ECC Signaling */
373
390
u32 vpu_uses_ecc_mca_signal;
374
-
/* Values defined by POWER_PROFILE* macros */
391
+
/** Values defined by POWER_PROFILE* macros */
375
392
u32 power_profile;
376
-
/* Microsecond value for DCT active cycle */
393
+
/** Microsecond value for DCT active cycle */
377
394
u32 dct_active_us;
378
-
/* Microsecond value for DCT inactive cycle */
395
+
/** Microsecond value for DCT inactive cycle */
379
396
u32 dct_inactive_us;
380
-
/* Unused/reserved: 0x488 - 0xFFF */
381
-
u32 pad6[734];
397
+
/** Unused/reserved: 0x488 - 0xFFF */
398
+
u32 reserved_9[734];
382
399
};
383
400
384
-
/* Magic numbers set between host and vpu to detect corruption of tracing init */
401
+
/** Magic numbers set between host and vpu to detect corruption of tracing init */
385
402
#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
386
403
387
-
/* Tracing buffer message format definitions */
404
+
/** Tracing buffer message format definitions */
388
405
#define VPU_TRACING_FORMAT_STRING 0
389
406
#define VPU_TRACING_FORMAT_MIPI 2
390
-
/*
407
+
/**
391
408
* Header of the tracing buffer.
392
409
* The below defined header will be stored at the beginning of
393
410
* each allocated tracing buffer, followed by a series of 256b
···
394
421
* @see VPU_TRACING_BUFFER_CANARY
395
422
*/
396
423
u32 host_canary_start;
397
-
/* offset from start of buffer for trace entries */
424
+
/** offset from start of buffer for trace entries */
398
425
u32 read_index;
399
-
/* keeps track of wrapping on the reader side */
426
+
/** keeps track of wrapping on the reader side */
400
427
u32 read_wrap_count;
401
428
u32 pad_to_cache_line_size_0[13];
402
-
/* End of first cache line */
429
+
/** End of first cache line */
403
430
404
431
/**
405
432
* Magic number set by host to detect corruption
406
433
* @see VPU_TRACING_BUFFER_CANARY
407
434
*/
408
435
u32 vpu_canary_start;
409
-
/* offset from start of buffer from write start */
436
+
/** offset from start of buffer from write start */
410
437
u32 write_index;
411
-
/* counter for buffer wrapping */
438
+
/** counter for buffer wrapping */
412
439
u32 wrap_count;
413
-
/* legacy field - do not use */
440
+
/** legacy field - do not use */
414
441
u32 reserved_0;
415
442
/**
416
-
* Size of the log buffer include this header (@header_size) and space
417
-
* reserved for all messages. If @alignment` is greater that 0 the @Size
418
-
* must be multiple of @Alignment.
443
+
* Size of the log buffer including this header (`header_size`) and space
444
+
* reserved for all messages. If `alignment` is greater than 0, the `size`
445
+
* must be a multiple of `alignment`.
419
446
*/
420
447
u32 size;
421
-
/* Header version */
448
+
/** Header version */
422
449
u16 header_version;
423
-
/* Header size */
450
+
/** Header size */
424
451
u16 header_size;
425
-
/*
452
+
/**
426
453
* Format of the messages in the trace buffer
427
454
* 0 - null terminated string
428
455
* 1 - size + null terminated string
429
456
* 2 - MIPI-SysT encoding
430
457
*/
431
458
u32 format;
432
-
/*
459
+
/**
433
460
* Message alignment
434
461
* 0 - messages are place 1 after another
435
462
* n - every message starts and multiple on offset
436
463
*/
437
-
u32 alignment; /* 64, 128, 256 */
438
-
/* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
464
+
u32 alignment; /** 64, 128, 256 */
465
+
/** Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
439
466
char name[16];
440
467
u32 pad_to_cache_line_size_1[4];
441
-
/* End of second cache line */
468
+
/** End of second cache line */
442
469
};
443
470
444
471
#pragma pack(pop)
445
472
446
473
#endif
474
+
475
+
///@}
+4
-1
drivers/dma-buf/dma-resv.c
+4
-1
drivers/dma-buf/dma-resv.c
···
790
790
mmap_read_lock(mm);
791
791
ww_acquire_init(&ctx, &reservation_ww_class);
792
792
ret = dma_resv_lock(&obj, &ctx);
793
-
if (ret == -EDEADLK)
793
+
if (ret) {
794
+
/* Only EDEADLK from the error injection is possible here */
795
+
WARN_ON(ret != -EDEADLK);
794
796
dma_resv_lock_slow(&obj, &ctx);
797
+
}
795
798
fs_reclaim_acquire(GFP_KERNEL);
796
799
/* for unmap_mapping_range on trylocked buffer objects in shrinkers */
797
800
i_mmap_lock_write(&mapping);
+28
-8
drivers/gpu/buddy.c
+28
-8
drivers/gpu/buddy.c
···
3
3
* Copyright © 2021 Intel Corporation
4
4
*/
5
5
6
-
#include <kunit/test-bug.h>
7
-
6
+
#include <linux/bug.h>
8
7
#include <linux/export.h>
9
8
#include <linux/kmemleak.h>
10
9
#include <linux/module.h>
11
10
#include <linux/sizes.h>
12
11
13
12
#include <linux/gpu_buddy.h>
13
+
14
+
/**
15
+
* gpu_buddy_assert - assert a condition in the buddy allocator
16
+
* @condition: condition expected to be true
17
+
*
18
+
* When CONFIG_KUNIT is enabled, evaluates @condition and, if false, triggers
19
+
* a WARN_ON() and also calls kunit_fail_current_test() so that any running
20
+
* kunit test is properly marked as failed. The stringified condition is
21
+
* included in the failure message for easy identification.
22
+
*
23
+
* When CONFIG_KUNIT is not enabled, this reduces to WARN_ON() so production
24
+
* builds retain the same warning semantics as before.
25
+
*/
26
+
#if IS_ENABLED(CONFIG_KUNIT)
27
+
#include <kunit/test-bug.h>
28
+
#define gpu_buddy_assert(condition) do { \
29
+
if (WARN_ON(!(condition))) \
30
+
kunit_fail_current_test("gpu_buddy_assert(" #condition ")"); \
31
+
} while (0)
32
+
#else
33
+
#define gpu_buddy_assert(condition) WARN_ON(!(condition))
34
+
#endif
14
35
15
36
static struct kmem_cache *slab_blocks;
16
37
···
289
268
if (!gpu_buddy_block_is_free(buddy))
290
269
continue;
291
270
292
-
WARN_ON(gpu_buddy_block_is_clear(block) ==
293
-
gpu_buddy_block_is_clear(buddy));
271
+
gpu_buddy_assert(gpu_buddy_block_is_clear(block) !=
272
+
gpu_buddy_block_is_clear(buddy));
294
273
295
274
/*
296
275
* Advance to the next node when the current node is the buddy,
···
436
415
start = gpu_buddy_block_offset(mm->roots[i]);
437
416
__force_merge(mm, start, start + size, order);
438
417
439
-
if (WARN_ON(!gpu_buddy_block_is_free(mm->roots[i])))
440
-
kunit_fail_current_test("buddy_fini() root");
418
+
gpu_buddy_assert(gpu_buddy_block_is_free(mm->roots[i]));
441
419
442
420
gpu_block_free(mm, mm->roots[i]);
443
421
···
444
424
size -= root_size;
445
425
}
446
426
447
-
WARN_ON(mm->avail != mm->size);
427
+
gpu_buddy_assert(mm->avail == mm->size);
448
428
449
429
for_each_free_tree(i)
450
430
kfree(mm->free_trees[i]);
···
561
541
{
562
542
struct gpu_buddy_block *block, *on;
563
543
564
-
WARN_ON(mark_dirty && mark_clear);
544
+
gpu_buddy_assert(!(mark_dirty && mark_clear));
565
545
566
546
list_for_each_entry_safe(block, on, objects, link) {
567
547
if (mark_clear)
+2
-1
drivers/gpu/drm/drm_client.c
+2
-1
drivers/gpu/drm/drm_client.c
···
204
204
}
205
205
EXPORT_SYMBOL(drm_client_buffer_delete);
206
206
207
-
static struct drm_client_buffer *
207
+
struct drm_client_buffer *
208
208
drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height,
209
209
u32 format, u32 handle, u32 pitch)
210
210
{
···
265
265
kfree(buffer);
266
266
return ERR_PTR(ret);
267
267
}
268
+
EXPORT_SYMBOL(drm_client_buffer_create);
268
269
269
270
/**
270
271
* drm_client_buffer_vmap_local - Map DRM client buffer into address space
+50
-51
drivers/gpu/drm/gma500/fbdev.c
+50
-51
drivers/gpu/drm/gma500/fbdev.c
···
72
72
static void psb_fbdev_fb_destroy(struct fb_info *info)
73
73
{
74
74
struct drm_fb_helper *fb_helper = info->par;
75
-
struct drm_framebuffer *fb = fb_helper->fb;
76
-
struct drm_gem_object *obj = fb->obj[0];
77
75
78
76
drm_fb_helper_fini(fb_helper);
79
77
80
-
drm_framebuffer_unregister_private(fb);
81
-
drm_framebuffer_cleanup(fb);
82
-
kfree(fb);
83
-
84
-
drm_gem_object_put(obj);
85
-
78
+
drm_client_buffer_delete(fb_helper->buffer);
86
79
drm_client_release(&fb_helper->client);
87
80
}
88
81
···
98
105
int psb_fbdev_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
99
106
struct drm_fb_helper_surface_size *sizes)
100
107
{
101
-
struct drm_device *dev = fb_helper->dev;
108
+
struct drm_client_dev *client = &fb_helper->client;
109
+
struct drm_device *dev = client->dev;
110
+
struct drm_file *file = client->file;
102
111
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
103
112
struct pci_dev *pdev = to_pci_dev(dev->dev);
104
113
struct fb_info *info = fb_helper->info;
105
-
struct drm_framebuffer *fb;
106
-
struct drm_mode_fb_cmd2 mode_cmd = { };
107
-
int size;
108
-
int ret;
114
+
u32 fourcc, pitch;
115
+
u64 size;
116
+
const struct drm_format_info *format;
117
+
struct drm_client_buffer *buffer;
109
118
struct psb_gem_object *backing;
110
119
struct drm_gem_object *obj;
111
-
u32 bpp, depth;
120
+
u32 handle;
121
+
int ret;
112
122
113
123
/* No 24-bit packed mode */
114
124
if (sizes->surface_bpp == 24) {
115
125
sizes->surface_bpp = 32;
116
126
sizes->surface_depth = 24;
117
127
}
118
-
bpp = sizes->surface_bpp;
119
-
depth = sizes->surface_depth;
120
128
121
-
/*
122
-
* If the mode does not fit in 32 bit then switch to 16 bit to get
123
-
* a console on full resolution. The X mode setting server will
124
-
* allocate its own 32-bit GEM framebuffer.
125
-
*/
126
-
size = ALIGN(sizes->surface_width * DIV_ROUND_UP(bpp, 8), 64) *
127
-
sizes->surface_height;
128
-
size = ALIGN(size, PAGE_SIZE);
129
-
130
-
if (size > dev_priv->vram_stolen_size) {
131
-
sizes->surface_bpp = 16;
132
-
sizes->surface_depth = 16;
133
-
}
134
-
bpp = sizes->surface_bpp;
135
-
depth = sizes->surface_depth;
136
-
137
-
mode_cmd.width = sizes->surface_width;
138
-
mode_cmd.height = sizes->surface_height;
139
-
mode_cmd.pitches[0] = ALIGN(mode_cmd.width * DIV_ROUND_UP(bpp, 8), 64);
140
-
mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
141
-
142
-
size = mode_cmd.pitches[0] * mode_cmd.height;
143
-
size = ALIGN(size, PAGE_SIZE);
129
+
try_psb_gem_create:
130
+
fourcc = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth);
131
+
format = drm_get_format_info(dev, fourcc, DRM_FORMAT_MOD_LINEAR);
132
+
pitch = ALIGN(drm_format_info_min_pitch(format, 0, sizes->surface_width), SZ_64);
133
+
size = ALIGN(pitch * sizes->surface_height, PAGE_SIZE);
144
134
145
135
/* Allocate the framebuffer in the GTT with stolen page backing */
146
136
backing = psb_gem_create(dev, size, "fb", true, PAGE_SIZE);
147
-
if (IS_ERR(backing))
148
-
return PTR_ERR(backing);
137
+
if (IS_ERR(backing)) {
138
+
ret = PTR_ERR(backing);
139
+
if (ret == -EBUSY && sizes->surface_bpp > 16) {
140
+
/*
141
+
* If the mode does not fit in 32 bit then switch to 16 bit to
142
+
* get a console on full resolution. User-space compositors will
143
+
* allocate their own 32-bit framebuffers.
144
+
*/
145
+
sizes->surface_bpp = 16;
146
+
sizes->surface_depth = 16;
147
+
goto try_psb_gem_create;
148
+
}
149
+
return ret;
150
+
}
149
151
obj = &backing->base;
150
152
151
-
fb = psb_framebuffer_create(dev,
152
-
drm_get_format_info(dev, mode_cmd.pixel_format,
153
-
mode_cmd.modifier[0]),
154
-
&mode_cmd, obj);
155
-
if (IS_ERR(fb)) {
156
-
ret = PTR_ERR(fb);
153
+
ret = drm_gem_handle_create(file, obj, &handle);
154
+
if (ret)
157
155
goto err_drm_gem_object_put;
156
+
157
+
buffer = drm_client_buffer_create(client, sizes->surface_width, sizes->surface_height,
158
+
fourcc, handle, pitch);
159
+
if (IS_ERR(buffer)) {
160
+
ret = PTR_ERR(buffer);
161
+
goto err_drm_gem_handle_delete;
158
162
}
159
163
160
164
fb_helper->funcs = &psb_fbdev_fb_helper_funcs;
161
-
fb_helper->fb = fb;
165
+
fb_helper->buffer = buffer;
166
+
fb_helper->fb = buffer->fb;
162
167
163
168
info->fbops = &psb_fbdev_fb_ops;
164
169
165
170
/* Accessed stolen memory directly */
166
171
info->screen_base = dev_priv->vram_addr + backing->offset;
167
-
info->screen_size = size;
172
+
info->screen_size = obj->size;
168
173
169
174
drm_fb_helper_fill_info(info, fb_helper, sizes);
170
175
171
176
info->fix.smem_start = dev_priv->stolen_base + backing->offset;
172
-
info->fix.smem_len = size;
177
+
info->fix.smem_len = obj->size;
173
178
info->fix.ywrapstep = 0;
174
179
info->fix.ypanstep = 0;
175
180
info->fix.mmio_start = pci_resource_start(pdev, 0);
···
177
186
178
187
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
179
188
180
-
dev_dbg(dev->dev, "allocated %dx%d fb\n", fb->width, fb->height);
189
+
dev_dbg(dev->dev, "allocated %dx%d fb\n", buffer->fb->width, buffer->fb->height);
190
+
191
+
/* The handle is only needed for creating the framebuffer.*/
192
+
drm_gem_handle_delete(file, handle);
193
+
194
+
/* The framebuffer still holds a references on the GEM object. */
195
+
drm_gem_object_put(obj);
181
196
182
197
return 0;
183
198
199
+
err_drm_gem_handle_delete:
200
+
drm_gem_handle_delete(file, handle);
184
201
err_drm_gem_object_put:
185
202
drm_gem_object_put(obj);
186
203
return ret;
+9
-95
drivers/gpu/drm/gma500/framebuffer.c
+9
-95
drivers/gpu/drm/gma500/framebuffer.c
···
12
12
#include "framebuffer.h"
13
13
#include "psb_drv.h"
14
14
15
-
static const struct drm_framebuffer_funcs psb_fb_funcs = {
16
-
.destroy = drm_gem_fb_destroy,
17
-
.create_handle = drm_gem_fb_create_handle,
18
-
};
19
-
20
-
/**
21
-
* psb_framebuffer_init - initialize a framebuffer
22
-
* @dev: our DRM device
23
-
* @fb: framebuffer to set up
24
-
* @mode_cmd: mode description
25
-
* @obj: backing object
26
-
*
27
-
* Configure and fill in the boilerplate for our frame buffer. Return
28
-
* 0 on success or an error code if we fail.
29
-
*/
30
-
static int psb_framebuffer_init(struct drm_device *dev,
31
-
struct drm_framebuffer *fb,
32
-
const struct drm_format_info *info,
33
-
const struct drm_mode_fb_cmd2 *mode_cmd,
34
-
struct drm_gem_object *obj)
15
+
static struct drm_framebuffer *
16
+
psb_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp,
17
+
const struct drm_format_info *info,
18
+
const struct drm_mode_fb_cmd2 *cmd)
35
19
{
36
-
int ret;
37
-
38
20
/*
39
21
* Reject unknown formats, YUV formats, and formats with more than
40
22
* 4 bytes per pixel.
41
23
*/
42
24
if (!info->depth || info->cpp[0] > 4)
43
-
return -EINVAL;
44
-
45
-
if (mode_cmd->pitches[0] & 63)
46
-
return -EINVAL;
47
-
48
-
drm_helper_mode_fill_fb_struct(dev, fb, info, mode_cmd);
49
-
fb->obj[0] = obj;
50
-
ret = drm_framebuffer_init(dev, fb, &psb_fb_funcs);
51
-
if (ret) {
52
-
dev_err(dev->dev, "framebuffer init failed: %d\n", ret);
53
-
return ret;
54
-
}
55
-
return 0;
56
-
}
57
-
58
-
/**
59
-
* psb_framebuffer_create - create a framebuffer backed by gt
60
-
* @dev: our DRM device
61
-
* @info: pixel format information
62
-
* @mode_cmd: the description of the requested mode
63
-
* @obj: the backing object
64
-
*
65
-
* Create a framebuffer object backed by the gt, and fill in the
66
-
* boilerplate required
67
-
*
68
-
* TODO: review object references
69
-
*/
70
-
struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev,
71
-
const struct drm_format_info *info,
72
-
const struct drm_mode_fb_cmd2 *mode_cmd,
73
-
struct drm_gem_object *obj)
74
-
{
75
-
struct drm_framebuffer *fb;
76
-
int ret;
77
-
78
-
fb = kzalloc_obj(*fb);
79
-
if (!fb)
80
-
return ERR_PTR(-ENOMEM);
81
-
82
-
ret = psb_framebuffer_init(dev, fb, info, mode_cmd, obj);
83
-
if (ret) {
84
-
kfree(fb);
85
-
return ERR_PTR(ret);
86
-
}
87
-
return fb;
88
-
}
89
-
90
-
/**
91
-
* psb_user_framebuffer_create - create framebuffer
92
-
* @dev: our DRM device
93
-
* @filp: client file
94
-
* @cmd: mode request
95
-
*
96
-
* Create a new framebuffer backed by a userspace GEM object
97
-
*/
98
-
static struct drm_framebuffer *psb_user_framebuffer_create
99
-
(struct drm_device *dev, struct drm_file *filp,
100
-
const struct drm_format_info *info,
101
-
const struct drm_mode_fb_cmd2 *cmd)
102
-
{
103
-
struct drm_gem_object *obj;
104
-
struct drm_framebuffer *fb;
25
+
return ERR_PTR(-EINVAL);
105
26
106
27
/*
107
-
* Find the GEM object and thus the gtt range object that is
108
-
* to back this space
28
+
* Pitch must be aligned to 64 bytes.
109
29
*/
110
-
obj = drm_gem_object_lookup(filp, cmd->handles[0]);
111
-
if (obj == NULL)
112
-
return ERR_PTR(-ENOENT);
30
+
if (cmd->pitches[0] & 63)
31
+
return ERR_PTR(-EINVAL);
113
32
114
-
/* Let the core code do all the work */
115
-
fb = psb_framebuffer_create(dev, info, cmd, obj);
116
-
if (IS_ERR(fb))
117
-
drm_gem_object_put(obj);
118
-
119
-
return fb;
33
+
return drm_gem_fb_create(dev, filp, info, cmd);
120
34
}
121
35
122
36
static const struct drm_mode_config_funcs psb_mode_funcs = {
-6
drivers/gpu/drm/gma500/psb_drv.h
-6
drivers/gpu/drm/gma500/psb_drv.h
···
592
592
extern void psb_modeset_init(struct drm_device *dev);
593
593
extern void psb_modeset_cleanup(struct drm_device *dev);
594
594
595
-
/* framebuffer */
596
-
struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev,
597
-
const struct drm_format_info *info,
598
-
const struct drm_mode_fb_cmd2 *mode_cmd,
599
-
struct drm_gem_object *obj);
600
-
601
595
/* fbdev */
602
596
#if defined(CONFIG_DRM_FBDEV_EMULATION)
603
597
int psb_fbdev_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
+1
-1
drivers/gpu/drm/gud/gud_pipe.c
+1
-1
drivers/gpu/drm/gud/gud_pipe.c
···
447
447
}
448
448
449
449
/* Imported buffers are assumed to be WriteCombined with uncached reads */
450
-
gud_flush_damage(gdrm, fb, src, !fb->obj[0]->import_attach, damage);
450
+
gud_flush_damage(gdrm, fb, src, !drm_gem_is_imported(fb->obj[0]), damage);
451
451
}
452
452
453
453
int gud_plane_atomic_check(struct drm_plane *plane,
+35
-17
drivers/gpu/drm/imagination/pvr_power.c
+35
-17
drivers/gpu/drm/imagination/pvr_power.c
···
598
598
struct drm_device *drm_dev = from_pvr_device(pvr_dev);
599
599
struct device *dev = drm_dev->dev;
600
600
601
-
struct device_link **domain_links __free(kfree) = NULL;
602
601
struct dev_pm_domain_list *domains = NULL;
602
+
struct device_link **domain_links = NULL;
603
603
int domain_count;
604
604
int link_count;
605
605
···
608
608
609
609
domain_count = of_count_phandle_with_args(dev->of_node, "power-domains",
610
610
"#power-domain-cells");
611
-
if (domain_count < 0)
612
-
return domain_count;
611
+
if (domain_count < 0) {
612
+
err = domain_count;
613
+
goto out;
614
+
}
613
615
614
-
if (domain_count <= 1)
615
-
return 0;
616
+
if (domain_count <= 1) {
617
+
err = 0;
618
+
goto out;
619
+
}
616
620
617
621
if (domain_count > ARRAY_SIZE(ROGUE_PD_NAMES)) {
618
622
drm_err(drm_dev, "%s() only supports %zu domains on Rogue",
619
623
__func__, ARRAY_SIZE(ROGUE_PD_NAMES));
620
-
return -EOPNOTSUPP;
624
+
err = -EOPNOTSUPP;
625
+
goto out;
621
626
}
622
627
623
628
link_count = domain_count - 1;
624
629
625
630
domain_links = kzalloc_objs(*domain_links, link_count);
626
-
if (!domain_links)
627
-
return -ENOMEM;
631
+
if (!domain_links) {
632
+
err = -ENOMEM;
633
+
goto out;
634
+
}
628
635
629
636
const struct dev_pm_domain_attach_data pd_attach_data = {
630
637
.pd_names = ROGUE_PD_NAMES,
···
641
634
642
635
err = dev_pm_domain_attach_list(dev, &pd_attach_data, &domains);
643
636
if (err < 0)
644
-
return err;
637
+
goto err_free_links;
645
638
646
639
for (i = 0; i < link_count; i++) {
647
640
struct device_link *link;
···
657
650
domain_links[i] = link;
658
651
}
659
652
660
-
pvr_dev->power = (struct pvr_device_power){
661
-
.domains = domains,
662
-
.domain_links = no_free_ptr(domain_links),
663
-
};
664
-
665
-
return 0;
653
+
err = 0;
654
+
goto out;
666
655
667
656
err_unlink:
668
657
while (--i >= 0)
669
658
device_link_del(domain_links[i]);
659
+
660
+
dev_pm_domain_detach_list(domains);
661
+
domains = NULL;
662
+
663
+
err_free_links:
664
+
kfree(domain_links);
665
+
domain_links = NULL;
666
+
667
+
out:
668
+
pvr_dev->power = (struct pvr_device_power){
669
+
.domains = domains,
670
+
.domain_links = domain_links,
671
+
};
670
672
671
673
return err;
672
674
}
···
684
668
{
685
669
struct pvr_device_power *pvr_power = &pvr_dev->power;
686
670
687
-
int i = (int)pvr_power->domains->num_pds - 1;
671
+
if (!pvr_power->domains)
672
+
goto out;
688
673
689
-
while (--i >= 0)
674
+
for (int i = (int)pvr_power->domains->num_pds - 2; i >= 0; --i)
690
675
device_link_del(pvr_power->domain_links[i]);
691
676
692
677
dev_pm_domain_detach_list(pvr_power->domains);
693
678
694
679
kfree(pvr_power->domain_links);
695
680
681
+
out:
696
682
*pvr_power = (struct pvr_device_power){ 0 };
697
683
}
+1
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+8
-1
drivers/gpu/drm/panel/panel-edp.c
+8
-1
drivers/gpu/drm/panel/panel-edp.c
···
1814
1814
.enable = 200,
1815
1815
};
1816
1816
1817
+
static const struct panel_delay delay_200_500_e200_d100 = {
1818
+
.hpd_absent = 200,
1819
+
.unprepare = 500,
1820
+
.enable = 200,
1821
+
.disable = 100,
1822
+
};
1823
+
1817
1824
static const struct panel_delay delay_200_500_e200_d200 = {
1818
1825
.hpd_absent = 200,
1819
1826
.unprepare = 500,
···
2021
2014
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c93, &delay_200_500_e200, "Unknown"),
2022
2015
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cb6, &delay_200_500_e200, "NT116WHM-N44"),
2023
2016
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cf2, &delay_200_500_e200, "NV156FHM-N4S"),
2024
-
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cf6, &delay_200_500_e200, "NV140WUM-N64"),
2017
+
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cf6, &delay_200_500_e200_d100, "NV140WUM-N64"),
2025
2018
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cfa, &delay_200_500_e50, "NV116WHM-A4D"),
2026
2019
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0d45, &delay_200_500_e80, "NV116WHM-N4B"),
2027
2020
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0d73, &delay_200_500_e80, "NE140WUM-N6S"),
+1
-1
drivers/gpu/drm/panfrost/panfrost_gem.c
+1
-1
drivers/gpu/drm/panfrost/panfrost_gem.c
···
702
702
resident_size,
703
703
drm_vma_node_start(&bo->base.base.vma_node));
704
704
705
-
if (bo->base.base.import_attach)
705
+
if (drm_gem_is_imported(&bo->base.base))
706
706
gem_state_flags |= PANFROST_DEBUGFS_GEM_STATE_FLAG_IMPORTED;
707
707
if (bo->base.base.dma_buf)
708
708
gem_state_flags |= PANFROST_DEBUGFS_GEM_STATE_FLAG_EXPORTED;
+1
-1
drivers/gpu/drm/panthor/panthor_gem.c
+1
-1
drivers/gpu/drm/panthor/panthor_gem.c
···
666
666
resident_size,
667
667
drm_vma_node_start(&bo->base.base.vma_node));
668
668
669
-
if (bo->base.base.import_attach)
669
+
if (drm_gem_is_imported(&bo->base.base))
670
670
gem_state_flags |= PANTHOR_DEBUGFS_GEM_STATE_FLAG_IMPORTED;
671
671
if (bo->base.base.dma_buf)
672
672
gem_state_flags |= PANTHOR_DEBUGFS_GEM_STATE_FLAG_EXPORTED;
+1
-37
drivers/gpu/drm/scheduler/sched_main.c
+1
-37
drivers/gpu/drm/scheduler/sched_main.c
···
1418
1418
*/
1419
1419
void drm_sched_fini(struct drm_gpu_scheduler *sched)
1420
1420
{
1421
-
struct drm_sched_entity *s_entity;
1422
1421
int i;
1423
1422
1424
1423
drm_sched_wqueue_stop(sched);
1425
1424
1426
-
for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) {
1427
-
struct drm_sched_rq *rq = sched->sched_rq[i];
1428
-
1429
-
spin_lock(&rq->lock);
1430
-
list_for_each_entry(s_entity, &rq->entities, list) {
1431
-
/*
1432
-
* Prevents reinsertion and marks job_queue as idle,
1433
-
* it will be removed from the rq in drm_sched_entity_fini()
1434
-
* eventually
1435
-
*
1436
-
* FIXME:
1437
-
* This lacks the proper spin_lock(&s_entity->lock) and
1438
-
* is, therefore, a race condition. Most notably, it
1439
-
* can race with drm_sched_entity_push_job(). The lock
1440
-
* cannot be taken here, however, because this would
1441
-
* lead to lock inversion -> deadlock.
1442
-
*
1443
-
* The best solution probably is to enforce the life
1444
-
* time rule of all entities having to be torn down
1445
-
* before their scheduler. Then, however, locking could
1446
-
* be dropped alltogether from this function.
1447
-
*
1448
-
* For now, this remains a potential race in all
1449
-
* drivers that keep entities alive for longer than
1450
-
* the scheduler.
1451
-
*
1452
-
* The READ_ONCE() is there to make the lockless read
1453
-
* (warning about the lockless write below) slightly
1454
-
* less broken...
1455
-
*/
1456
-
if (!READ_ONCE(s_entity->stopped))
1457
-
dev_warn(sched->dev, "Tearing down scheduler with active entities!\n");
1458
-
s_entity->stopped = true;
1459
-
}
1460
-
spin_unlock(&rq->lock);
1425
+
for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++)
1461
1426
kfree(sched->sched_rq[i]);
1462
-
}
1463
1427
1464
1428
/* Wakeup everyone stuck in drm_sched_entity_flush for this scheduler */
1465
1429
wake_up_all(&sched->job_scheduled);
+2
-2
drivers/gpu/drm/scheduler/tests/tests_basic.c
+2
-2
drivers/gpu/drm/scheduler/tests/tests_basic.c
···
421
421
422
422
static struct kunit_case drm_sched_priority_tests[] = {
423
423
KUNIT_CASE(drm_sched_priorities),
424
-
KUNIT_CASE(drm_sched_change_priority),
424
+
KUNIT_CASE_SLOW(drm_sched_change_priority),
425
425
{}
426
426
};
427
427
···
546
546
}
547
547
548
548
static struct kunit_case drm_sched_credits_tests[] = {
549
-
KUNIT_CASE(drm_sched_test_credits),
549
+
KUNIT_CASE_SLOW(drm_sched_test_credits),
550
550
{}
551
551
};
552
552
+1
-1
drivers/gpu/drm/vc4/vc4_bo.c
+1
-1
drivers/gpu/drm/vc4/vc4_bo.c
+1
-1
drivers/gpu/drm/vc4/vc4_gem.c
+1
-1
drivers/gpu/drm/vc4/vc4_gem.c
···
1250
1250
/* Not sure it's safe to purge imported BOs. Let's just assume it's
1251
1251
* not until proven otherwise.
1252
1252
*/
1253
-
if (gem_obj->import_attach) {
1253
+
if (drm_gem_is_imported(gem_obj)) {
1254
1254
DRM_DEBUG("madvise not supported on imported BOs\n");
1255
1255
ret = -EINVAL;
1256
1256
goto out_put_gem;
+1
-1
drivers/gpu/tests/gpu_buddy_test.c
+1
-1
drivers/gpu/tests/gpu_buddy_test.c
···
910
910
KUNIT_CASE(gpu_test_buddy_alloc_contiguous),
911
911
KUNIT_CASE(gpu_test_buddy_alloc_clear),
912
912
KUNIT_CASE(gpu_test_buddy_alloc_range_bias),
913
-
KUNIT_CASE(gpu_test_buddy_fragmentation_performance),
913
+
KUNIT_CASE_SLOW(gpu_test_buddy_fragmentation_performance),
914
914
KUNIT_CASE(gpu_test_buddy_alloc_exceeds_max_order),
915
915
{}
916
916
};
+3
include/drm/drm_client.h
+3
include/drm/drm_client.h
···
196
196
};
197
197
198
198
struct drm_client_buffer *
199
+
drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height,
200
+
u32 format, u32 handle, u32 pitch);
201
+
struct drm_client_buffer *
199
202
drm_client_buffer_create_dumb(struct drm_client_dev *client, u32 width, u32 height, u32 format);
200
203
void drm_client_buffer_delete(struct drm_client_buffer *buffer);
201
204
int drm_client_buffer_flush(struct drm_client_buffer *buffer, struct drm_rect *rect);