Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-06-20' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Bit of an uptick in fixes for rc3, msm and amdgpu leading the way,
with i915/xe/nouveau with a few each and then some scattered misc
bits, nothing looks too crazy:
msm:
- Display:
- Fixed DP output on SDM845
- Fixed 10nm DSI PLL init
- GPU:
- SUBMIT ioctl error path leak fixes
- drm half of stall-on-fault fixes
- a7xx: Missing CP_RESET_CONTEXT_STATE
- Skip GPU component bind if GPU is not in the device table
i915:
- Fix MIPI vtotal programming off by one on Broxton
- Fix PMU code for GCOV and AutoFDO enabled build
xe:
- A workaround update
- Fix memset on iomem
- Fix early wedge on GuC Load failure
amdgpu:
- DP tunneling fix
- LTTPR fix
- DSC fix
- DML2.x ABGR16161616 fix
- RMCM fix
- Backlight fixes
- GFX11 kicker support
- SDMA reset fixes
- VCN 5.0.1 fix
- Reset fix
- Misc small fixes
amdkfd:
- SDMA reset fix
- Fix race in GWS scheduling
nouveau:
- update docs reference
- fix backlight name buffer size
- fix UAF in r535 gsp rpc msg
- fix undefined shift
mgag200:
- drop export header
ast:
- drop export header
malidp:
- drop informational error
ssd130x:
- fix clear columns
etnaviv:
- scheduler locking fix
v3d:
- null pointer crash fix"
* tag 'drm-fixes-2025-06-20' of https://gitlab.freedesktop.org/drm/kernel: (50 commits)
drm/xe: Fix early wedge on GuC load failure
drm/xe: Fix memset on iomem
drm/xe/bmg: Update Wa_16023588340
drm/amdgpu/sdma5.2: init engine reset mutex
drm/amdkfd: Fix race in GWS queue scheduling
drm/amdgpu/sdma5: init engine reset mutex
drm/amdgpu: switch job hw_fence to amdgpu_fence
drm/amdgpu: Fix SDMA UTC_L1 handling during start/stop sequences
drm/amdgpu: Release reset locks during failures
drm/amd/display: Check dce_hwseq before dereferencing it
drm/amdgpu: VCN v5_0_1 to prevent FW checking RB during DPG pause
drm/amdgpu: Use logical instance ID for SDMA v4_4_2 queue operations
drm/amdgpu: Fix SDMA engine reset with logical instance ID
drm/amdgpu: add kicker fws loading for gfx11/smu13/psp13
drm/amdgpu: Add kicker device detection
drm/amd/display: Export full brightness range to userspace
drm/amd/display: Only read ACPI backlight caps once
drm/amd/display: Fix RMCM programming seq errors
drm/amd/display: Fix mpv playback corruption on weston
drm/amd/display: Add more checks for DSC / HUBP ONO guarantees
...
+599
-201
+1
-1
Documentation/gpu/nouveau.rst
+1
-1
Documentation/gpu/nouveau.rst
···
25
25
GSP Support
26
26
------------------------
27
27
28
-
.. kernel-doc:: drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
28
+
.. kernel-doc:: drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
29
29
:doc: GSP message queue element
30
30
31
31
.. kernel-doc:: drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+56
-26
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+56
-26
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
6019
6019
return ret;
6020
6020
}
6021
6021
6022
-
static int amdgpu_device_halt_activities(struct amdgpu_device *adev,
6023
-
struct amdgpu_job *job,
6024
-
struct amdgpu_reset_context *reset_context,
6025
-
struct list_head *device_list,
6026
-
struct amdgpu_hive_info *hive,
6027
-
bool need_emergency_restart)
6022
+
static int amdgpu_device_recovery_prepare(struct amdgpu_device *adev,
6023
+
struct list_head *device_list,
6024
+
struct amdgpu_hive_info *hive)
6028
6025
{
6029
-
struct list_head *device_list_handle = NULL;
6030
6026
struct amdgpu_device *tmp_adev = NULL;
6031
-
int i, r = 0;
6027
+
int r;
6032
6028
6033
6029
/*
6034
6030
* Build list of devices to reset.
···
6041
6045
}
6042
6046
if (!list_is_first(&adev->reset_list, device_list))
6043
6047
list_rotate_to_front(&adev->reset_list, device_list);
6044
-
device_list_handle = device_list;
6045
6048
} else {
6046
6049
list_add_tail(&adev->reset_list, device_list);
6047
-
device_list_handle = device_list;
6048
6050
}
6049
6051
6050
6052
if (!amdgpu_sriov_vf(adev) && (!adev->pcie_reset_ctx.occurs_dpc)) {
6051
-
r = amdgpu_device_health_check(device_list_handle);
6053
+
r = amdgpu_device_health_check(device_list);
6052
6054
if (r)
6053
6055
return r;
6054
6056
}
6055
6057
6056
-
/* We need to lock reset domain only once both for XGMI and single device */
6057
-
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
6058
-
reset_list);
6058
+
return 0;
6059
+
}
6060
+
6061
+
static void amdgpu_device_recovery_get_reset_lock(struct amdgpu_device *adev,
6062
+
struct list_head *device_list)
6063
+
{
6064
+
struct amdgpu_device *tmp_adev = NULL;
6065
+
6066
+
if (list_empty(device_list))
6067
+
return;
6068
+
tmp_adev =
6069
+
list_first_entry(device_list, struct amdgpu_device, reset_list);
6059
6070
amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
6071
+
}
6072
+
6073
+
static void amdgpu_device_recovery_put_reset_lock(struct amdgpu_device *adev,
6074
+
struct list_head *device_list)
6075
+
{
6076
+
struct amdgpu_device *tmp_adev = NULL;
6077
+
6078
+
if (list_empty(device_list))
6079
+
return;
6080
+
tmp_adev =
6081
+
list_first_entry(device_list, struct amdgpu_device, reset_list);
6082
+
amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
6083
+
}
6084
+
6085
+
static int amdgpu_device_halt_activities(
6086
+
struct amdgpu_device *adev, struct amdgpu_job *job,
6087
+
struct amdgpu_reset_context *reset_context,
6088
+
struct list_head *device_list, struct amdgpu_hive_info *hive,
6089
+
bool need_emergency_restart)
6090
+
{
6091
+
struct amdgpu_device *tmp_adev = NULL;
6092
+
int i, r = 0;
6060
6093
6061
6094
/* block all schedulers and reset given job's ring */
6062
-
list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
6063
-
6095
+
list_for_each_entry(tmp_adev, device_list, reset_list) {
6064
6096
amdgpu_device_set_mp1_state(tmp_adev);
6065
6097
6066
6098
/*
···
6276
6252
amdgpu_ras_set_error_query_ready(tmp_adev, true);
6277
6253
6278
6254
}
6279
-
6280
-
tmp_adev = list_first_entry(device_list, struct amdgpu_device,
6281
-
reset_list);
6282
-
amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
6283
-
6284
6255
}
6285
6256
6286
6257
···
6343
6324
reset_context->hive = hive;
6344
6325
INIT_LIST_HEAD(&device_list);
6345
6326
6327
+
if (amdgpu_device_recovery_prepare(adev, &device_list, hive))
6328
+
goto end_reset;
6329
+
6330
+
/* We need to lock reset domain only once both for XGMI and single device */
6331
+
amdgpu_device_recovery_get_reset_lock(adev, &device_list);
6332
+
6346
6333
r = amdgpu_device_halt_activities(adev, job, reset_context, &device_list,
6347
6334
hive, need_emergency_restart);
6348
6335
if (r)
6349
-
goto end_reset;
6336
+
goto reset_unlock;
6350
6337
6351
6338
if (need_emergency_restart)
6352
6339
goto skip_sched_resume;
···
6362
6337
*
6363
6338
* job->base holds a reference to parent fence
6364
6339
*/
6365
-
if (job && dma_fence_is_signaled(&job->hw_fence)) {
6340
+
if (job && dma_fence_is_signaled(&job->hw_fence.base)) {
6366
6341
job_signaled = true;
6367
6342
dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
6368
6343
goto skip_hw_reset;
···
6370
6345
6371
6346
r = amdgpu_device_asic_reset(adev, &device_list, reset_context);
6372
6347
if (r)
6373
-
goto end_reset;
6348
+
goto reset_unlock;
6374
6349
skip_hw_reset:
6375
6350
r = amdgpu_device_sched_resume(&device_list, reset_context, job_signaled);
6376
6351
if (r)
6377
-
goto end_reset;
6352
+
goto reset_unlock;
6378
6353
skip_sched_resume:
6379
6354
amdgpu_device_gpu_resume(adev, &device_list, need_emergency_restart);
6355
+
reset_unlock:
6356
+
amdgpu_device_recovery_put_reset_lock(adev, &device_list);
6380
6357
end_reset:
6381
6358
if (hive) {
6382
6359
mutex_unlock(&hive->hive_lock);
···
6790
6763
memset(&reset_context, 0, sizeof(reset_context));
6791
6764
INIT_LIST_HEAD(&device_list);
6792
6765
6766
+
amdgpu_device_recovery_prepare(adev, &device_list, hive);
6767
+
amdgpu_device_recovery_get_reset_lock(adev, &device_list);
6793
6768
r = amdgpu_device_halt_activities(adev, NULL, &reset_context, &device_list,
6794
6769
hive, false);
6795
6770
if (hive) {
···
6909
6880
if (hive) {
6910
6881
list_for_each_entry(tmp_adev, &device_list, reset_list)
6911
6882
amdgpu_device_unset_mp1_state(tmp_adev);
6912
-
amdgpu_device_unlock_reset_domain(adev->reset_domain);
6913
6883
}
6884
+
amdgpu_device_recovery_put_reset_lock(adev, &device_list);
6914
6885
}
6915
6886
6916
6887
if (hive) {
···
6956
6927
6957
6928
amdgpu_device_sched_resume(&device_list, NULL, NULL);
6958
6929
amdgpu_device_gpu_resume(adev, &device_list, false);
6930
+
amdgpu_device_recovery_put_reset_lock(adev, &device_list);
6959
6931
adev->pcie_reset_ctx.occurs_dpc = false;
6960
6932
6961
6933
if (hive) {
+7
-23
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+7
-23
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
···
41
41
#include "amdgpu_trace.h"
42
42
#include "amdgpu_reset.h"
43
43
44
-
/*
45
-
* Fences mark an event in the GPUs pipeline and are used
46
-
* for GPU/CPU synchronization. When the fence is written,
47
-
* it is expected that all buffers associated with that fence
48
-
* are no longer in use by the associated ring on the GPU and
49
-
* that the relevant GPU caches have been flushed.
50
-
*/
51
-
52
-
struct amdgpu_fence {
53
-
struct dma_fence base;
54
-
55
-
/* RB, DMA, etc. */
56
-
struct amdgpu_ring *ring;
57
-
ktime_t start_timestamp;
58
-
};
59
-
60
44
static struct kmem_cache *amdgpu_fence_slab;
61
45
62
46
int amdgpu_fence_slab_init(void)
···
135
151
am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
136
152
if (am_fence == NULL)
137
153
return -ENOMEM;
138
-
fence = &am_fence->base;
139
-
am_fence->ring = ring;
140
154
} else {
141
155
/* take use of job-embedded fence */
142
-
fence = &job->hw_fence;
156
+
am_fence = &job->hw_fence;
143
157
}
158
+
fence = &am_fence->base;
159
+
am_fence->ring = ring;
144
160
145
161
seq = ++ring->fence_drv.sync_seq;
146
162
if (job && job->job_run_counter) {
···
702
718
* it right here or we won't be able to track them in fence_drv
703
719
* and they will remain unsignaled during sa_bo free.
704
720
*/
705
-
job = container_of(old, struct amdgpu_job, hw_fence);
721
+
job = container_of(old, struct amdgpu_job, hw_fence.base);
706
722
if (!job->base.s_fence && !dma_fence_is_signaled(old))
707
723
dma_fence_signal(old);
708
724
RCU_INIT_POINTER(*ptr, NULL);
···
764
780
765
781
static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
766
782
{
767
-
struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
783
+
struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence.base);
768
784
769
785
return (const char *)to_amdgpu_ring(job->base.sched)->name;
770
786
}
···
794
810
*/
795
811
static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
796
812
{
797
-
struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
813
+
struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence.base);
798
814
799
815
if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
800
816
amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
···
829
845
struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
830
846
831
847
/* free job if fence has a parent job */
832
-
kfree(container_of(f, struct amdgpu_job, hw_fence));
848
+
kfree(container_of(f, struct amdgpu_job, hw_fence.base));
833
849
}
834
850
835
851
/**
+6
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+6
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
···
272
272
/* Check if any fences where initialized */
273
273
if (job->base.s_fence && job->base.s_fence->finished.ops)
274
274
f = &job->base.s_fence->finished;
275
-
else if (job->hw_fence.ops)
276
-
f = &job->hw_fence;
275
+
else if (job->hw_fence.base.ops)
276
+
f = &job->hw_fence.base;
277
277
else
278
278
f = NULL;
279
279
···
290
290
amdgpu_sync_free(&job->explicit_sync);
291
291
292
292
/* only put the hw fence if has embedded fence */
293
-
if (!job->hw_fence.ops)
293
+
if (!job->hw_fence.base.ops)
294
294
kfree(job);
295
295
else
296
-
dma_fence_put(&job->hw_fence);
296
+
dma_fence_put(&job->hw_fence.base);
297
297
}
298
298
299
299
void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
···
322
322
if (job->gang_submit != &job->base.s_fence->scheduled)
323
323
dma_fence_put(job->gang_submit);
324
324
325
-
if (!job->hw_fence.ops)
325
+
if (!job->hw_fence.base.ops)
326
326
kfree(job);
327
327
else
328
-
dma_fence_put(&job->hw_fence);
328
+
dma_fence_put(&job->hw_fence.base);
329
329
}
330
330
331
331
struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+12
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+12
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
3522
3522
uint8_t *ucode_array_start_addr;
3523
3523
int err = 0;
3524
3524
3525
-
err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
3526
-
"amdgpu/%s_sos.bin", chip_name);
3525
+
if (amdgpu_is_kicker_fw(adev))
3526
+
err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
3527
+
"amdgpu/%s_sos_kicker.bin", chip_name);
3528
+
else
3529
+
err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
3530
+
"amdgpu/%s_sos.bin", chip_name);
3527
3531
if (err)
3528
3532
goto out;
3529
3533
···
3803
3799
struct amdgpu_device *adev = psp->adev;
3804
3800
int err;
3805
3801
3806
-
err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
3807
-
"amdgpu/%s_ta.bin", chip_name);
3802
+
if (amdgpu_is_kicker_fw(adev))
3803
+
err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
3804
+
"amdgpu/%s_ta_kicker.bin", chip_name);
3805
+
else
3806
+
err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
3807
+
"amdgpu/%s_ta.bin", chip_name);
3808
3808
if (err)
3809
3809
return err;
3810
3810
+16
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+16
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
···
127
127
struct dma_fence **fences;
128
128
};
129
129
130
+
/*
131
+
* Fences mark an event in the GPUs pipeline and are used
132
+
* for GPU/CPU synchronization. When the fence is written,
133
+
* it is expected that all buffers associated with that fence
134
+
* are no longer in use by the associated ring on the GPU and
135
+
* that the relevant GPU caches have been flushed.
136
+
*/
137
+
138
+
struct amdgpu_fence {
139
+
struct dma_fence base;
140
+
141
+
/* RB, DMA, etc. */
142
+
struct amdgpu_ring *ring;
143
+
ktime_t start_timestamp;
144
+
};
145
+
130
146
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
131
147
132
148
void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
+6
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+6
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
···
540
540
case IP_VERSION(4, 4, 2):
541
541
case IP_VERSION(4, 4, 4):
542
542
case IP_VERSION(4, 4, 5):
543
-
/* For SDMA 4.x, use the existing DPM interface for backward compatibility */
544
-
r = amdgpu_dpm_reset_sdma(adev, 1 << instance_id);
543
+
/* For SDMA 4.x, use the existing DPM interface for backward compatibility,
544
+
* we need to convert the logical instance ID to physical instance ID before reset.
545
+
*/
546
+
r = amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id));
545
547
break;
546
548
case IP_VERSION(5, 0, 0):
547
549
case IP_VERSION(5, 0, 1):
···
570
568
/**
571
569
* amdgpu_sdma_reset_engine - Reset a specific SDMA engine
572
570
* @adev: Pointer to the AMDGPU device
573
-
* @instance_id: ID of the SDMA engine instance to reset
571
+
* @instance_id: Logical ID of the SDMA engine instance to reset
574
572
*
575
573
* Returns: 0 on success, or a negative error code on failure.
576
574
*/
···
603
601
/* Perform the SDMA reset for the specified instance */
604
602
ret = amdgpu_sdma_soft_reset(adev, instance_id);
605
603
if (ret) {
606
-
dev_err(adev->dev, "Failed to reset SDMA instance %u\n", instance_id);
604
+
dev_err(adev->dev, "Failed to reset SDMA logical instance %u\n", instance_id);
607
605
goto exit;
608
606
}
609
607
+17
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+17
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
···
30
30
31
31
#define AMDGPU_UCODE_NAME_MAX (128)
32
32
33
+
static const struct kicker_device kicker_device_list[] = {
34
+
{0x744B, 0x00},
35
+
};
36
+
33
37
static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
34
38
{
35
39
DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
···
1389
1385
}
1390
1386
}
1391
1387
return NULL;
1388
+
}
1389
+
1390
+
bool amdgpu_is_kicker_fw(struct amdgpu_device *adev)
1391
+
{
1392
+
int i;
1393
+
1394
+
for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) {
1395
+
if (adev->pdev->device == kicker_device_list[i].device &&
1396
+
adev->pdev->revision == kicker_device_list[i].revision)
1397
+
return true;
1398
+
}
1399
+
1400
+
return false;
1392
1401
}
1393
1402
1394
1403
void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
···
605
605
uint32_t pldm_version;
606
606
};
607
607
608
+
struct kicker_device{
609
+
unsigned short device;
610
+
u8 revision;
611
+
};
612
+
608
613
void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
609
614
void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
610
615
void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
···
637
632
const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
638
633
639
634
void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
635
+
bool amdgpu_is_kicker_fw(struct amdgpu_device *adev);
640
636
641
637
#endif
+5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+5
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
···
85
85
MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
86
86
MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
87
87
MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
88
+
MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_kicker.bin");
88
89
MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin");
89
90
MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
90
91
MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
···
760
759
err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
761
760
AMDGPU_UCODE_REQUIRED,
762
761
"amdgpu/gc_11_0_0_rlc_1.bin");
762
+
else if (amdgpu_is_kicker_fw(adev))
763
+
err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
764
+
AMDGPU_UCODE_REQUIRED,
765
+
"amdgpu/%s_rlc_kicker.bin", ucode_prefix);
763
766
else
764
767
err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
765
768
AMDGPU_UCODE_REQUIRED,
+7
-2
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+7
-2
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
···
32
32
#include "gc/gc_11_0_0_sh_mask.h"
33
33
34
34
MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin");
35
+
MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu_kicker.bin");
35
36
MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin");
36
37
MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin");
37
38
MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");
···
52
51
DRM_DEBUG("\n");
53
52
54
53
amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
55
-
err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
56
-
"amdgpu/%s_imu.bin", ucode_prefix);
54
+
if (amdgpu_is_kicker_fw(adev))
55
+
err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
56
+
"amdgpu/%s_imu_kicker.bin", ucode_prefix);
57
+
else
58
+
err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
59
+
"amdgpu/%s_imu.bin", ucode_prefix);
57
60
if (err)
58
61
goto out;
59
62
+2
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+2
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
···
42
42
MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43
43
MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44
44
MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
45
+
MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin");
45
46
MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
47
+
MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin");
46
48
MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
47
49
MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
48
50
MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
+7
-3
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+7
-3
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
···
490
490
{
491
491
struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
492
492
u32 doorbell_offset, doorbell;
493
-
u32 rb_cntl, ib_cntl;
493
+
u32 rb_cntl, ib_cntl, sdma_cntl;
494
494
int i;
495
495
496
496
for_each_inst(i, inst_mask) {
···
502
502
ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
503
503
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
504
504
WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
505
+
sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL);
506
+
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0);
507
+
WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl);
505
508
506
509
if (sdma[i]->use_doorbell) {
507
510
doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
···
998
995
/* set utc l1 enable flag always to 1 */
999
996
temp = RREG32_SDMA(i, regSDMA_CNTL);
1000
997
temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
998
+
WREG32_SDMA(i, regSDMA_CNTL, temp);
1001
999
1002
1000
if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) {
1003
1001
/* enable context empty interrupt during initialization */
···
1674
1670
static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
1675
1671
{
1676
1672
struct amdgpu_device *adev = ring->adev;
1677
-
u32 id = GET_INST(SDMA0, ring->me);
1673
+
u32 id = ring->me;
1678
1674
int r;
1679
1675
1680
1676
if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
···
1690
1686
static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
1691
1687
{
1692
1688
struct amdgpu_device *adev = ring->adev;
1693
-
u32 instance_id = GET_INST(SDMA0, ring->me);
1689
+
u32 instance_id = ring->me;
1694
1690
u32 inst_mask;
1695
1691
uint64_t rptr;
1696
1692
+1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+1
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+1
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+5
-1
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+5
-1
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
···
669
669
if (indirect)
670
670
amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
671
671
672
+
/* resetting ring, fw should not check RB ring */
673
+
fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
674
+
672
675
/* Pause dpg */
673
676
vcn_v5_0_1_pause_dpg_mode(vinst, &state);
674
677
···
684
681
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
685
682
tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
686
683
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
687
-
fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
684
+
688
685
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
689
686
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
690
687
···
695
692
tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
696
693
tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
697
694
WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
695
+
/* resetting done, fw can check RB ring */
698
696
fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
699
697
700
698
WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
···
240
240
241
241
packet->bitfields2.engine_sel =
242
242
engine_sel__mes_map_queues__compute_vi;
243
-
packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;
243
+
packet->bitfields2.gws_control_queue = q->properties.is_gws ? 1 : 0;
244
244
packet->bitfields2.extended_engine_sel =
245
245
extended_engine_sel__mes_map_queues__legacy_engine_sel;
246
246
packet->bitfields2.queue_type =
+4
-2
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+4
-2
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
···
510
510
dev->node_props.capability |=
511
511
HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
512
512
513
+
if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0) &&
514
+
(dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
515
+
dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
516
+
513
517
sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",
514
518
dev->node_props.max_engine_clk_fcompute);
515
519
···
2012
2008
if (!amdgpu_sriov_vf(dev->gpu->adev))
2013
2009
dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
2014
2010
2015
-
if (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
2016
-
dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
2017
2011
} else {
2018
2012
dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
2019
2013
HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
+35
-22
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+35
-22
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
4718
4718
return 1;
4719
4719
}
4720
4720
4721
-
static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
4722
-
uint32_t *brightness)
4721
+
/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */
4722
+
static inline u32 scale_input_to_fw(int min, int max, u64 input)
4723
4723
{
4724
+
return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min);
4725
+
}
4726
+
4727
+
/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */
4728
+
static inline u32 scale_fw_to_input(int min, int max, u64 input)
4729
+
{
4730
+
return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL);
4731
+
}
4732
+
4733
+
static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,
4734
+
unsigned int min, unsigned int max,
4735
+
uint32_t *user_brightness)
4736
+
{
4737
+
u32 brightness = scale_input_to_fw(min, max, *user_brightness);
4724
4738
u8 prev_signal = 0, prev_lum = 0;
4725
4739
int i = 0;
4726
4740
···
4745
4731
return;
4746
4732
4747
4733
/* choose start to run less interpolation steps */
4748
-
if (caps->luminance_data[caps->data_points/2].input_signal > *brightness)
4734
+
if (caps->luminance_data[caps->data_points/2].input_signal > brightness)
4749
4735
i = caps->data_points/2;
4750
4736
do {
4751
4737
u8 signal = caps->luminance_data[i].input_signal;
···
4756
4742
* brightness < signal: interpolate between previous and current luminance numerator
4757
4743
* brightness > signal: find next data point
4758
4744
*/
4759
-
if (*brightness > signal) {
4745
+
if (brightness > signal) {
4760
4746
prev_signal = signal;
4761
4747
prev_lum = lum;
4762
4748
i++;
4763
4749
continue;
4764
4750
}
4765
-
if (*brightness < signal)
4751
+
if (brightness < signal)
4766
4752
lum = prev_lum + DIV_ROUND_CLOSEST((lum - prev_lum) *
4767
-
(*brightness - prev_signal),
4753
+
(brightness - prev_signal),
4768
4754
signal - prev_signal);
4769
-
*brightness = DIV_ROUND_CLOSEST(lum * *brightness, 101);
4755
+
*user_brightness = scale_fw_to_input(min, max,
4756
+
DIV_ROUND_CLOSEST(lum * brightness, 101));
4770
4757
return;
4771
4758
} while (i < caps->data_points);
4772
4759
}
···
4780
4765
if (!get_brightness_range(caps, &min, &max))
4781
4766
return brightness;
4782
4767
4783
-
convert_custom_brightness(caps, &brightness);
4768
+
convert_custom_brightness(caps, min, max, &brightness);
4784
4769
4785
-
// Rescale 0..255 to min..max
4786
-
return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4787
-
AMDGPU_MAX_BL_LEVEL);
4770
+
// Rescale 0..max to min..max
4771
+
return min + DIV_ROUND_CLOSEST_ULL((u64)(max - min) * brightness, max);
4788
4772
}
4789
4773
4790
4774
static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
···
4796
4782
4797
4783
if (brightness < min)
4798
4784
return 0;
4799
-
// Rescale min..max to 0..255
4800
-
return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4785
+
// Rescale min..max to 0..max
4786
+
return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min),
4801
4787
max - min);
4802
4788
}
4803
4789
···
4922
4908
struct drm_device *drm = aconnector->base.dev;
4923
4909
struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4924
4910
struct backlight_properties props = { 0 };
4925
-
struct amdgpu_dm_backlight_caps caps = { 0 };
4911
+
struct amdgpu_dm_backlight_caps *caps;
4926
4912
char bl_name[16];
4927
4913
int min, max;
4928
4914
···
4936
4922
return;
4937
4923
}
4938
4924
4939
-
amdgpu_acpi_get_backlight_caps(&caps);
4940
-
if (caps.caps_valid && get_brightness_range(&caps, &min, &max)) {
4925
+
caps = &dm->backlight_caps[aconnector->bl_idx];
4926
+
if (get_brightness_range(caps, &min, &max)) {
4941
4927
if (power_supply_is_system_supplied() > 0)
4942
-
props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps.ac_level, 100);
4928
+
props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->ac_level, 100);
4943
4929
else
4944
-
props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps.dc_level, 100);
4930
+
props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->dc_level, 100);
4945
4931
/* min is zero, so max needs to be adjusted */
4946
4932
props.max_brightness = max - min;
4947
4933
drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
4948
-
caps.ac_level, caps.dc_level);
4934
+
caps->ac_level, caps->dc_level);
4949
4935
} else
4950
-
props.brightness = AMDGPU_MAX_BL_LEVEL;
4936
+
props.brightness = props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4951
4937
4952
-
if (caps.data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
4938
+
if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
4953
4939
drm_info(drm, "Using custom brightness curve\n");
4954
-
props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4955
4940
props.type = BACKLIGHT_RAW;
4956
4941
4957
4942
snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
+33
drivers/gpu/drm/amd/display/dc/core/dc.c
+33
drivers/gpu/drm/amd/display/dc/core/dc.c
···
241
241
DC_LOG_DC("BIOS object table - end");
242
242
243
243
/* Create a link for each usb4 dpia port */
244
+
dc->lowest_dpia_link_index = MAX_LINKS;
244
245
for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
245
246
struct link_init_data link_init_params = {0};
246
247
struct dc_link *link;
···
254
253
255
254
link = dc->link_srv->create_link(&link_init_params);
256
255
if (link) {
256
+
if (dc->lowest_dpia_link_index > dc->link_count)
257
+
dc->lowest_dpia_link_index = dc->link_count;
258
+
257
259
dc->links[dc->link_count] = link;
258
260
link->dc = dc;
259
261
++dc->link_count;
···
6379
6375
return dc->res_pool->funcs->get_det_buffer_size(context);
6380
6376
else
6381
6377
return 0;
6378
+
}
6379
+
/**
6380
+
***********************************************************************************************
6381
+
* dc_get_host_router_index: Get index of host router from a dpia link
6382
+
*
6383
+
* This function return a host router index of the target link. If the target link is dpia link.
6384
+
*
6385
+
* @param [in] link: target link
6386
+
* @param [out] host_router_index: host router index of the target link
6387
+
*
6388
+
* @return: true if the host router index is found and valid.
6389
+
*
6390
+
***********************************************************************************************
6391
+
*/
6392
+
bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index)
6393
+
{
6394
+
struct dc *dc = link->ctx->dc;
6395
+
6396
+
if (link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
6397
+
return false;
6398
+
6399
+
if (link->link_index < dc->lowest_dpia_link_index)
6400
+
return false;
6401
+
6402
+
*host_router_index = (link->link_index - dc->lowest_dpia_link_index) / dc->caps.num_of_dpias_per_host_router;
6403
+
if (*host_router_index < dc->caps.num_of_host_routers)
6404
+
return true;
6405
+
else
6406
+
return false;
6382
6407
}
6383
6408
6384
6409
bool dc_is_cursor_limit_pending(struct dc *dc)
+7
-1
drivers/gpu/drm/amd/display/dc/dc.h
+7
-1
drivers/gpu/drm/amd/display/dc/dc.h
···
66
66
#define MAX_STREAMS 6
67
67
#define MIN_VIEWPORT_SIZE 12
68
68
#define MAX_NUM_EDP 2
69
-
#define MAX_HOST_ROUTERS_NUM 2
69
+
#define MAX_HOST_ROUTERS_NUM 3
70
+
#define MAX_DPIA_PER_HOST_ROUTER 2
70
71
71
72
/* Display Core Interfaces */
72
73
struct dc_versions {
···
306
305
/* Conservative limit for DCC cases which require ODM4:1 to support*/
307
306
uint32_t dcc_plane_width_limit;
308
307
struct dc_scl_caps scl_caps;
308
+
uint8_t num_of_host_routers;
309
+
uint8_t num_of_dpias_per_host_router;
309
310
};
310
311
311
312
struct dc_bug_wa {
···
1606
1603
1607
1604
uint8_t link_count;
1608
1605
struct dc_link *links[MAX_LINKS];
1606
+
uint8_t lowest_dpia_link_index;
1609
1607
struct link_service *link_srv;
1610
1608
1611
1609
struct dc_state *current_state;
···
2598
2594
struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
2599
2595
2600
2596
unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);
2597
+
2598
+
bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index);
2601
2599
2602
2600
/* DSC Interfaces */
2603
2601
#include "dc_dsc.h"
+2
-2
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+2
-2
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
···
1172
1172
union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
1173
1173
union dp_alpm_lttpr_cap alpm;
1174
1174
uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
1175
-
uint8_t lttpr_ieee_oui[3];
1176
-
uint8_t lttpr_device_id[6];
1175
+
uint8_t lttpr_ieee_oui[3]; // Always read from closest LTTPR to host
1176
+
uint8_t lttpr_device_id[6]; // Always read from closest LTTPR to host
1177
1177
};
1178
1178
1179
1179
struct dc_dongle_dfp_cap_ext {
+1
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
+1
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
···
788
788
plane->pixel_format = dml2_420_10;
789
789
break;
790
790
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
791
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
791
792
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
792
793
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
793
794
plane->pixel_format = dml2_444_64;
+4
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+4
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
···
4685
4685
//the tdlut is fetched during the 2 row times of prefetch.
4686
4686
if (p->setup_for_tdlut) {
4687
4687
*p->tdlut_groups_per_2row_ub = (unsigned int)math_ceil2((double) *p->tdlut_bytes_per_frame / *p->tdlut_bytes_per_group, 1);
4688
-
*p->tdlut_opt_time = (*p->tdlut_bytes_per_frame - p->cursor_buffer_size * 1024) / tdlut_drain_rate;
4688
+
if (*p->tdlut_bytes_per_frame > p->cursor_buffer_size * 1024)
4689
+
*p->tdlut_opt_time = (*p->tdlut_bytes_per_frame - p->cursor_buffer_size * 1024) / tdlut_drain_rate;
4690
+
else
4691
+
*p->tdlut_opt_time = 0;
4689
4692
*p->tdlut_drain_time = p->cursor_buffer_size * 1024 / tdlut_drain_rate;
4690
4693
*p->tdlut_bytes_to_deliver = (unsigned int) (p->cursor_buffer_size * 1024.0);
4691
4694
}
+1
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+1
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
···
953
953
out->SourcePixelFormat[location] = dml_420_10;
954
954
break;
955
955
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
956
+
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
956
957
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
957
958
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
958
959
out->SourcePixelFormat[location] = dml_444_64;
+1
-1
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+1
-1
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
···
1225
1225
return;
1226
1226
1227
1227
if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1228
-
if (!link->skip_implict_edp_power_control)
1228
+
if (!link->skip_implict_edp_power_control && hws)
1229
1229
hws->funcs.edp_backlight_control(link, false);
1230
1230
link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1231
1231
}
+28
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+28
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
···
1047
1047
if (dc->caps.sequential_ono) {
1048
1048
update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;
1049
1049
update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;
1050
+
1051
+
/* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */
1052
+
if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&
1053
+
pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {
1054
+
for (j = 0; j < dc->res_pool->pipe_count; ++j) {
1055
+
update_state->pg_pipe_res_update[PG_HUBP][j] = false;
1056
+
update_state->pg_pipe_res_update[PG_DPP][j] = false;
1057
+
}
1058
+
}
1050
1059
}
1051
1060
}
1052
1061
···
1202
1193
update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
1203
1194
1204
1195
if (dc->caps.sequential_ono) {
1196
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
1197
+
struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
1198
+
1199
+
if (new_pipe->stream_res.dsc && !new_pipe->top_pipe &&
1200
+
update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {
1201
+
update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;
1202
+
update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;
1203
+
1204
+
/* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */
1205
+
if (new_pipe->plane_res.hubp &&
1206
+
new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {
1207
+
for (j = 0; j < dc->res_pool->pipe_count; ++j) {
1208
+
update_state->pg_pipe_res_update[PG_HUBP][j] = true;
1209
+
update_state->pg_pipe_res_update[PG_DPP][j] = true;
1210
+
}
1211
+
}
1212
+
}
1213
+
}
1214
+
1205
1215
for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1206
1216
if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
1207
1217
update_state->pg_pipe_res_update[PG_DPP][i]) {
+31
-7
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+31
-7
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
···
385
385
bool dp_is_lttpr_present(struct dc_link *link)
386
386
{
387
387
/* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
388
-
return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
388
+
uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
389
+
bool is_lttpr_present = (lttpr_count > 0 &&
389
390
link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
390
391
link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
392
+
393
+
if (lttpr_count > 0 && !is_lttpr_present)
394
+
DC_LOG_ERROR("LTTPR count is nonzero but invalid lane count reported. Assuming no LTTPR present.\n");
395
+
396
+
return is_lttpr_present;
391
397
}
392
398
393
399
/* in DP compliance test, DPR-120 may have
···
1557
1551
uint8_t lttpr_dpcd_data[10] = {0};
1558
1552
enum dc_status status;
1559
1553
bool is_lttpr_present;
1554
+
uint32_t lttpr_count;
1555
+
uint32_t closest_lttpr_offset;
1560
1556
1561
1557
/* Logic to determine LTTPR support*/
1562
1558
bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
···
1610
1602
lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES -
1611
1603
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1612
1604
1605
+
lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1606
+
1613
1607
/* If this chip cap is set, at least one retimer must exist in the chain
1614
1608
* Override count to 1 if we receive a known bad count (0 or an invalid value) */
1615
1609
if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1616
-
(dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1610
+
lttpr_count == 0) {
1617
1611
/* If you see this message consistently, either the host platform has FIXED_VS flag
1618
1612
* incorrectly configured or the sink device is returning an invalid count.
1619
1613
*/
1620
1614
DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",
1621
1615
link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1622
1616
link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1617
+
lttpr_count = 1;
1623
1618
DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1624
1619
}
1625
1620
1626
-
/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1627
1621
is_lttpr_present = dp_is_lttpr_present(link);
1628
1622
1629
1623
DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
···
1633
1623
if (is_lttpr_present) {
1634
1624
CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1635
1625
1636
-
core_link_read_dpcd(link, DP_LTTPR_IEEE_OUI, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
1637
-
CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), "LTTPR IEEE OUI: ");
1626
+
// Identify closest LTTPR to determine if workarounds required for known embedded LTTPR
1627
+
closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count);
1638
1628
1639
-
core_link_read_dpcd(link, DP_LTTPR_DEVICE_ID, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id));
1640
-
CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), "LTTPR Device ID: ");
1629
+
core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset),
1630
+
link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
1631
+
core_link_read_dpcd(link, (DP_LTTPR_DEVICE_ID + closest_lttpr_offset),
1632
+
link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id));
1633
+
1634
+
if (lttpr_count > 1) {
1635
+
CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui),
1636
+
"Closest LTTPR To Host's IEEE OUI: ");
1637
+
CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id),
1638
+
"Closest LTTPR To Host's LTTPR Device ID: ");
1639
+
} else {
1640
+
CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui),
1641
+
"LTTPR IEEE OUI: ");
1642
+
CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id),
1643
+
"LTTPR Device ID: ");
1644
+
}
1641
1645
}
1642
1646
1643
1647
return status;
+3
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
···
1954
1954
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1955
1955
dc->caps.color.mpc.ocsc = 1;
1956
1956
1957
+
dc->caps.num_of_host_routers = 2;
1958
+
dc->caps.num_of_dpias_per_host_router = 2;
1959
+
1957
1960
/* Use pipe context based otg sync logic */
1958
1961
dc->config.use_pipe_ctx_sync_logic = true;
1959
1962
dc->config.disable_hbr_audio_dp2 = true;
+3
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
···
1894
1894
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1895
1895
dc->caps.color.mpc.ocsc = 1;
1896
1896
1897
+
dc->caps.num_of_host_routers = 2;
1898
+
dc->caps.num_of_dpias_per_host_router = 2;
1899
+
1897
1900
/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1898
1901
* to provide some margin.
1899
1902
* It's expected for furture ASIC to have equal or higher value, in order to
+3
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
···
1866
1866
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1867
1867
dc->caps.color.mpc.ocsc = 1;
1868
1868
1869
+
dc->caps.num_of_host_routers = 2;
1870
+
dc->caps.num_of_dpias_per_host_router = 2;
1871
+
1869
1872
/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1870
1873
* to provide some margin.
1871
1874
* It's expected for furture ASIC to have equal or higher value, in order to
+3
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
···
1867
1867
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1868
1868
dc->caps.color.mpc.ocsc = 1;
1869
1869
1870
+
dc->caps.num_of_host_routers = 2;
1871
+
dc->caps.num_of_dpias_per_host_router = 2;
1872
+
1870
1873
/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1871
1874
* to provide some margin.
1872
1875
* It's expected for furture ASIC to have equal or higher value, in order to
+9
-3
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+9
-3
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
···
58
58
59
59
MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60
60
MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61
+
MODULE_FIRMWARE("amdgpu/smu_13_0_0_kicker.bin");
61
62
MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62
63
MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63
64
···
93
92
int smu_v13_0_init_microcode(struct smu_context *smu)
94
93
{
95
94
struct amdgpu_device *adev = smu->adev;
96
-
char ucode_prefix[15];
95
+
char ucode_prefix[30];
97
96
int err = 0;
98
97
const struct smc_firmware_header_v1_0 *hdr;
99
98
const struct common_firmware_header *header;
···
104
103
return 0;
105
104
106
105
amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
107
-
err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
108
-
"amdgpu/%s.bin", ucode_prefix);
106
+
107
+
if (amdgpu_is_kicker_fw(adev))
108
+
err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
109
+
"amdgpu/%s_kicker.bin", ucode_prefix);
110
+
else
111
+
err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
112
+
"amdgpu/%s.bin", ucode_prefix);
109
113
if (err)
110
114
goto out;
111
115
+1
-1
drivers/gpu/drm/arm/malidp_planes.c
+1
-1
drivers/gpu/drm/arm/malidp_planes.c
-1
drivers/gpu/drm/ast/ast_mode.c
-1
drivers/gpu/drm/ast/ast_mode.c
+2
-2
drivers/gpu/drm/i915/display/vlv_dsi.c
+2
-2
drivers/gpu/drm/i915/display/vlv_dsi.c
···
1056
1056
BXT_MIPI_TRANS_VACTIVE(port));
1057
1057
adjusted_mode->crtc_vtotal =
1058
1058
intel_de_read(display,
1059
-
BXT_MIPI_TRANS_VTOTAL(port));
1059
+
BXT_MIPI_TRANS_VTOTAL(port)) + 1;
1060
1060
1061
1061
hactive = adjusted_mode->crtc_hdisplay;
1062
1062
hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));
···
1260
1260
intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port),
1261
1261
adjusted_mode->crtc_vdisplay);
1262
1262
intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port),
1263
-
adjusted_mode->crtc_vtotal);
1263
+
adjusted_mode->crtc_vtotal - 1);
1264
1264
}
1265
1265
1266
1266
intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port),
+2
-2
drivers/gpu/drm/i915/i915_pmu.c
+2
-2
drivers/gpu/drm/i915/i915_pmu.c
···
112
112
{
113
113
unsigned int bit = config_bit(config);
114
114
115
-
if (__builtin_constant_p(config))
115
+
if (__builtin_constant_p(bit))
116
116
BUILD_BUG_ON(bit >
117
117
BITS_PER_TYPE(typeof_member(struct i915_pmu,
118
118
enable)) - 1);
···
121
121
BITS_PER_TYPE(typeof_member(struct i915_pmu,
122
122
enable)) - 1);
123
123
124
-
return BIT(config_bit(config));
124
+
return BIT(bit);
125
125
}
126
126
127
127
static bool is_engine_event(struct perf_event *event)
-1
drivers/gpu/drm/mgag200/mgag200_ddc.c
-1
drivers/gpu/drm/mgag200/mgag200_ddc.c
-5
drivers/gpu/drm/msm/adreno/a2xx_gpummu.c
-5
drivers/gpu/drm/msm/adreno/a2xx_gpummu.c
···
71
71
return 0;
72
72
}
73
73
74
-
static void a2xx_gpummu_resume_translation(struct msm_mmu *mmu)
75
-
{
76
-
}
77
-
78
74
static void a2xx_gpummu_destroy(struct msm_mmu *mmu)
79
75
{
80
76
struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
···
86
90
.map = a2xx_gpummu_map,
87
91
.unmap = a2xx_gpummu_unmap,
88
92
.destroy = a2xx_gpummu_destroy,
89
-
.resume_translation = a2xx_gpummu_resume_translation,
90
93
};
91
94
92
95
struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu)
+2
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+2
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+18
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+18
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
130
130
OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
131
131
OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
132
132
OUT_RING(ring, submit->seqno - 1);
133
+
134
+
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
135
+
OUT_RING(ring, CP_SET_THREAD_BOTH);
136
+
137
+
/* Reset state used to synchronize BR and BV */
138
+
OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1);
139
+
OUT_RING(ring,
140
+
CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS |
141
+
CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE |
142
+
CP_RESET_CONTEXT_STATE_0_CLEAR_BV_BR_COUNTER |
143
+
CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS);
144
+
145
+
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
146
+
OUT_RING(ring, CP_SET_THREAD_BR);
133
147
}
134
148
135
149
if (!sysprof) {
···
225
211
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
226
212
struct msm_ringbuffer *ring = submit->ring;
227
213
unsigned int i, ibs = 0;
214
+
215
+
adreno_check_and_reenable_stall(adreno_gpu);
228
216
229
217
a6xx_set_pagetable(a6xx_gpu, ring, submit);
230
218
···
350
334
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
351
335
struct msm_ringbuffer *ring = submit->ring;
352
336
unsigned int i, ibs = 0;
337
+
338
+
adreno_check_and_reenable_stall(adreno_gpu);
353
339
354
340
/*
355
341
* Toggle concurrent binning for pagetable switch and set the thread to
+29
-10
drivers/gpu/drm/msm/adreno/adreno_device.c
+29
-10
drivers/gpu/drm/msm/adreno/adreno_device.c
···
137
137
return NULL;
138
138
}
139
139
140
-
static int find_chipid(struct device *dev, uint32_t *chipid)
140
+
static int find_chipid(struct device_node *node, uint32_t *chipid)
141
141
{
142
-
struct device_node *node = dev->of_node;
143
142
const char *compat;
144
143
int ret;
145
144
···
172
173
/* and if that fails, fall back to legacy "qcom,chipid" property: */
173
174
ret = of_property_read_u32(node, "qcom,chipid", chipid);
174
175
if (ret) {
175
-
DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
176
+
DRM_ERROR("%pOF: could not parse qcom,chipid: %d\n",
177
+
node, ret);
176
178
return ret;
177
179
}
178
180
179
-
dev_warn(dev, "Using legacy qcom,chipid binding!\n");
181
+
pr_warn("%pOF: Using legacy qcom,chipid binding!\n", node);
180
182
181
183
return 0;
184
+
}
185
+
186
+
bool adreno_has_gpu(struct device_node *node)
187
+
{
188
+
const struct adreno_info *info;
189
+
uint32_t chip_id;
190
+
int ret;
191
+
192
+
ret = find_chipid(node, &chip_id);
193
+
if (ret)
194
+
return false;
195
+
196
+
info = adreno_info(chip_id);
197
+
if (!info) {
198
+
pr_warn("%pOF: Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
199
+
node, ADRENO_CHIPID_ARGS(chip_id));
200
+
return false;
201
+
}
202
+
203
+
return true;
182
204
}
183
205
184
206
static int adreno_bind(struct device *dev, struct device *master, void *data)
···
211
191
struct msm_gpu *gpu;
212
192
int ret;
213
193
214
-
ret = find_chipid(dev, &config.chip_id);
215
-
if (ret)
194
+
ret = find_chipid(dev->of_node, &config.chip_id);
195
+
/* We shouldn't have gotten this far if we can't parse the chip_id */
196
+
if (WARN_ON(ret))
216
197
return ret;
217
198
218
199
dev->platform_data = &config;
219
200
priv->gpu_pdev = to_platform_device(dev);
220
201
221
202
info = adreno_info(config.chip_id);
222
-
if (!info) {
223
-
dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
224
-
ADRENO_CHIPID_ARGS(config.chip_id));
203
+
/* We shouldn't have gotten this far if we don't recognize the GPU: */
204
+
if (WARN_ON(!info))
225
205
return -ENXIO;
226
-
}
227
206
228
207
config.info = info;
229
208
+43
-11
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+43
-11
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
259
259
return BIT(ttbr1_cfg->ias) - ADRENO_VM_START;
260
260
}
261
261
262
+
void adreno_check_and_reenable_stall(struct adreno_gpu *adreno_gpu)
263
+
{
264
+
struct msm_gpu *gpu = &adreno_gpu->base;
265
+
struct msm_drm_private *priv = gpu->dev->dev_private;
266
+
unsigned long flags;
267
+
268
+
/*
269
+
* Wait until the cooldown period has passed and we would actually
270
+
* collect a crashdump to re-enable stall-on-fault.
271
+
*/
272
+
spin_lock_irqsave(&priv->fault_stall_lock, flags);
273
+
if (!priv->stall_enabled &&
274
+
ktime_after(ktime_get(), priv->stall_reenable_time) &&
275
+
!READ_ONCE(gpu->crashstate)) {
276
+
priv->stall_enabled = true;
277
+
278
+
gpu->aspace->mmu->funcs->set_stall(gpu->aspace->mmu, true);
279
+
}
280
+
spin_unlock_irqrestore(&priv->fault_stall_lock, flags);
281
+
}
282
+
262
283
#define ARM_SMMU_FSR_TF BIT(1)
263
284
#define ARM_SMMU_FSR_PF BIT(3)
264
285
#define ARM_SMMU_FSR_EF BIT(4)
286
+
#define ARM_SMMU_FSR_SS BIT(30)
265
287
266
288
int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
267
289
struct adreno_smmu_fault_info *info, const char *block,
268
290
u32 scratch[4])
269
291
{
292
+
struct msm_drm_private *priv = gpu->dev->dev_private;
270
293
const char *type = "UNKNOWN";
271
-
bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
294
+
bool do_devcoredump = info && (info->fsr & ARM_SMMU_FSR_SS) &&
295
+
!READ_ONCE(gpu->crashstate);
296
+
unsigned long irq_flags;
272
297
273
298
/*
274
-
* If we aren't going to be resuming later from fault_worker, then do
275
-
* it now.
299
+
* In case there is a subsequent storm of pagefaults, disable
300
+
* stall-on-fault for at least half a second.
276
301
*/
277
-
if (!do_devcoredump) {
278
-
gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
302
+
spin_lock_irqsave(&priv->fault_stall_lock, irq_flags);
303
+
if (priv->stall_enabled) {
304
+
priv->stall_enabled = false;
305
+
306
+
gpu->aspace->mmu->funcs->set_stall(gpu->aspace->mmu, false);
279
307
}
308
+
priv->stall_reenable_time = ktime_add_ms(ktime_get(), 500);
309
+
spin_unlock_irqrestore(&priv->fault_stall_lock, irq_flags);
280
310
281
311
/*
282
312
* Print a default message if we couldn't get the data from the
···
334
304
scratch[0], scratch[1], scratch[2], scratch[3]);
335
305
336
306
if (do_devcoredump) {
307
+
struct msm_gpu_fault_info fault_info = {};
308
+
337
309
/* Turn off the hangcheck timer to keep it from bothering us */
338
310
timer_delete(&gpu->hangcheck_timer);
339
311
340
-
gpu->fault_info.ttbr0 = info->ttbr0;
341
-
gpu->fault_info.iova = iova;
342
-
gpu->fault_info.flags = flags;
343
-
gpu->fault_info.type = type;
344
-
gpu->fault_info.block = block;
312
+
fault_info.ttbr0 = info->ttbr0;
313
+
fault_info.iova = iova;
314
+
fault_info.flags = flags;
315
+
fault_info.type = type;
316
+
fault_info.block = block;
345
317
346
-
kthread_queue_work(gpu->worker, &gpu->fault_work);
318
+
msm_gpu_fault_crashstate_capture(gpu, &fault_info);
347
319
}
348
320
349
321
return 0;
+2
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+2
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+9
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+9
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
···
94
94
timing->vsync_polarity = 0;
95
95
}
96
96
97
-
/* for DP/EDP, Shift timings to align it to bottom right */
98
-
if (phys_enc->hw_intf->cap->type == INTF_DP) {
97
+
timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
98
+
timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
99
+
100
+
/*
101
+
* For DP/EDP, Shift timings to align it to bottom right.
102
+
* wide_bus_en is set for everything excluding SDM845 &
103
+
* porch changes cause DisplayPort failure and HDMI tearing.
104
+
*/
105
+
if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
99
106
timing->h_back_porch += timing->h_front_porch;
100
107
timing->h_front_porch = 0;
101
108
timing->v_back_porch += timing->v_front_porch;
102
109
timing->v_front_porch = 0;
103
110
}
104
-
105
-
timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
106
-
timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
107
111
108
112
/*
109
113
* for DP, divide the horizonal parameters by 2 when
+6
-1
drivers/gpu/drm/msm/dp/dp_display.c
+6
-1
drivers/gpu/drm/msm/dp/dp_display.c
···
128
128
{}
129
129
};
130
130
131
+
static const struct msm_dp_desc msm_dp_desc_sdm845[] = {
132
+
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0 },
133
+
{}
134
+
};
135
+
131
136
static const struct msm_dp_desc msm_dp_desc_sc7180[] = {
132
137
{ .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
133
138
{}
···
185
180
{ .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x },
186
181
{ .compatible = "qcom,sc8280xp-dp", .data = &msm_dp_desc_sc8280xp },
187
182
{ .compatible = "qcom,sc8280xp-edp", .data = &msm_dp_desc_sc8280xp },
188
-
{ .compatible = "qcom,sdm845-dp", .data = &msm_dp_desc_sc7180 },
183
+
{ .compatible = "qcom,sdm845-dp", .data = &msm_dp_desc_sdm845 },
189
184
{ .compatible = "qcom,sm8350-dp", .data = &msm_dp_desc_sc7180 },
190
185
{ .compatible = "qcom,sm8650-dp", .data = &msm_dp_desc_sm8650 },
191
186
{ .compatible = "qcom,x1e80100-dp", .data = &msm_dp_desc_x1e80100 },
+7
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+7
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
···
704
704
/* TODO: Remove this when we have proper display handover support */
705
705
msm_dsi_phy_pll_save_state(phy);
706
706
707
+
/*
708
+
* Store also proper vco_current_rate, because its value will be used in
709
+
* dsi_10nm_pll_restore_state().
710
+
*/
711
+
if (!dsi_pll_10nm_vco_recalc_rate(&pll_10nm->clk_hw, VCO_REF_CLK_RATE))
712
+
pll_10nm->vco_current_rate = pll_10nm->phy->cfg->min_pll_rate;
713
+
707
714
return 0;
708
715
}
709
716
+32
drivers/gpu/drm/msm/msm_debugfs.c
+32
drivers/gpu/drm/msm/msm_debugfs.c
···
208
208
shrink_get, shrink_set,
209
209
"0x%08llx\n");
210
210
211
+
/*
212
+
* Return the number of microseconds to wait until stall-on-fault is
213
+
* re-enabled. If 0 then it is already enabled or will be re-enabled on the
214
+
* next submit (unless there's a leftover devcoredump). This is useful for
215
+
* kernel tests that intentionally produce a fault and check the devcoredump to
216
+
* wait until the cooldown period is over.
217
+
*/
218
+
219
+
static int
220
+
stall_reenable_time_get(void *data, u64 *val)
221
+
{
222
+
struct msm_drm_private *priv = data;
223
+
unsigned long irq_flags;
224
+
225
+
spin_lock_irqsave(&priv->fault_stall_lock, irq_flags);
226
+
227
+
if (priv->stall_enabled)
228
+
*val = 0;
229
+
else
230
+
*val = max(ktime_us_delta(priv->stall_reenable_time, ktime_get()), 0);
231
+
232
+
spin_unlock_irqrestore(&priv->fault_stall_lock, irq_flags);
233
+
234
+
return 0;
235
+
}
236
+
237
+
DEFINE_DEBUGFS_ATTRIBUTE(stall_reenable_time_fops,
238
+
stall_reenable_time_get, NULL,
239
+
"%lld\n");
211
240
212
241
static int msm_gem_show(struct seq_file *m, void *arg)
213
242
{
···
347
318
348
319
debugfs_create_bool("disable_err_irq", 0600, minor->debugfs_root,
349
320
&priv->disable_err_irq);
321
+
322
+
debugfs_create_file("stall_reenable_time_us", 0400, minor->debugfs_root,
323
+
priv, &stall_reenable_time_fops);
350
324
351
325
gpu_devfreq = debugfs_create_dir("devfreq", minor->debugfs_root);
352
326
+7
-3
drivers/gpu/drm/msm/msm_drv.c
+7
-3
drivers/gpu/drm/msm/msm_drv.c
···
245
245
drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
246
246
drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
247
247
248
+
/* Initialize stall-on-fault */
249
+
spin_lock_init(&priv->fault_stall_lock);
250
+
priv->stall_enabled = true;
251
+
248
252
/* Teach lockdep about lock ordering wrt. shrinker: */
249
253
fs_reclaim_acquire(GFP_KERNEL);
250
254
might_lock(&priv->lru.lock);
···
930
926
* is no external component that we need to add since LVDS is within MDP4
931
927
* itself.
932
928
*/
933
-
static int add_components_mdp(struct device *master_dev,
929
+
static int add_mdp_components(struct device *master_dev,
934
930
struct component_match **matchptr)
935
931
{
936
932
struct device_node *np = master_dev->of_node;
···
1034
1030
if (!np)
1035
1031
return 0;
1036
1032
1037
-
if (of_device_is_available(np))
1033
+
if (of_device_is_available(np) && adreno_has_gpu(np))
1038
1034
drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1039
1035
1040
1036
of_node_put(np);
···
1075
1071
1076
1072
/* Add mdp components if we have KMS. */
1077
1073
if (kms_init) {
1078
-
ret = add_components_mdp(master_dev, &match);
1074
+
ret = add_mdp_components(master_dev, &match);
1079
1075
if (ret)
1080
1076
return ret;
1081
1077
}
+23
drivers/gpu/drm/msm/msm_drv.h
+23
drivers/gpu/drm/msm/msm_drv.h
···
222
222
* the sw hangcheck mechanism.
223
223
*/
224
224
bool disable_err_irq;
225
+
226
+
/**
227
+
* @fault_stall_lock:
228
+
*
229
+
* Serialize changes to stall-on-fault state.
230
+
*/
231
+
spinlock_t fault_stall_lock;
232
+
233
+
/**
234
+
* @fault_stall_reenable_time:
235
+
*
236
+
* If stall_enabled is false, when to reenable stall-on-fault.
237
+
* Protected by @fault_stall_lock.
238
+
*/
239
+
ktime_t stall_reenable_time;
240
+
241
+
/**
242
+
* @stall_enabled:
243
+
*
244
+
* Whether stall-on-fault is currently enabled. Protected by
245
+
* @fault_stall_lock.
246
+
*/
247
+
bool stall_enabled;
225
248
};
226
249
227
250
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
+15
-2
drivers/gpu/drm/msm/msm_gem_submit.c
+15
-2
drivers/gpu/drm/msm/msm_gem_submit.c
···
85
85
container_of(kref, struct msm_gem_submit, ref);
86
86
unsigned i;
87
87
88
+
/*
89
+
* In error paths, we could unref the submit without calling
90
+
* drm_sched_entity_push_job(), so msm_job_free() will never
91
+
* get called. Since drm_sched_job_cleanup() will NULL out
92
+
* s_fence, we can use that to detect this case.
93
+
*/
94
+
if (submit->base.s_fence)
95
+
drm_sched_job_cleanup(&submit->base);
96
+
88
97
if (submit->fence_id) {
89
98
spin_lock(&submit->queue->idr_lock);
90
99
idr_remove(&submit->queue->fence_idr, submit->fence_id);
···
658
649
struct msm_ringbuffer *ring;
659
650
struct msm_submit_post_dep *post_deps = NULL;
660
651
struct drm_syncobj **syncobjs_to_reset = NULL;
652
+
struct sync_file *sync_file = NULL;
661
653
int out_fence_fd = -1;
662
654
unsigned i;
663
655
int ret;
···
868
858
}
869
859
870
860
if (ret == 0 && args->flags & MSM_SUBMIT_FENCE_FD_OUT) {
871
-
struct sync_file *sync_file = sync_file_create(submit->user_fence);
861
+
sync_file = sync_file_create(submit->user_fence);
872
862
if (!sync_file) {
873
863
ret = -ENOMEM;
874
864
} else {
···
902
892
out_unlock:
903
893
mutex_unlock(&queue->lock);
904
894
out_post_unlock:
905
-
if (ret && (out_fence_fd >= 0))
895
+
if (ret && (out_fence_fd >= 0)) {
906
896
put_unused_fd(out_fence_fd);
897
+
if (sync_file)
898
+
fput(sync_file->file);
899
+
}
907
900
908
901
if (!IS_ERR_OR_NULL(submit)) {
909
902
msm_gem_submit_put(submit);
+9
-11
drivers/gpu/drm/msm/msm_gpu.c
+9
-11
drivers/gpu/drm/msm/msm_gpu.c
···
257
257
}
258
258
259
259
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
260
-
struct msm_gem_submit *submit, char *comm, char *cmd)
260
+
struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
261
+
char *comm, char *cmd)
261
262
{
262
263
struct msm_gpu_state *state;
263
264
···
277
276
/* Fill in the additional crash state information */
278
277
state->comm = kstrdup(comm, GFP_KERNEL);
279
278
state->cmd = kstrdup(cmd, GFP_KERNEL);
280
-
state->fault_info = gpu->fault_info;
279
+
if (fault_info)
280
+
state->fault_info = *fault_info;
281
281
282
282
if (submit) {
283
283
int i;
···
310
308
}
311
309
#else
312
310
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
313
-
struct msm_gem_submit *submit, char *comm, char *cmd)
311
+
struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
312
+
char *comm, char *cmd)
314
313
{
315
314
}
316
315
#endif
···
408
405
409
406
/* Record the crash state */
410
407
pm_runtime_get_sync(&gpu->pdev->dev);
411
-
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
408
+
msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd);
412
409
413
410
kfree(cmd);
414
411
kfree(comm);
···
462
459
msm_gpu_retire(gpu);
463
460
}
464
461
465
-
static void fault_worker(struct kthread_work *work)
462
+
void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info)
466
463
{
467
-
struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work);
468
464
struct msm_gem_submit *submit;
469
465
struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
470
466
char *comm = NULL, *cmd = NULL;
···
486
484
487
485
/* Record the crash state */
488
486
pm_runtime_get_sync(&gpu->pdev->dev);
489
-
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
487
+
msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd);
490
488
pm_runtime_put_sync(&gpu->pdev->dev);
491
489
492
490
kfree(cmd);
493
491
kfree(comm);
494
492
495
493
resume_smmu:
496
-
memset(&gpu->fault_info, 0, sizeof(gpu->fault_info));
497
-
gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
498
-
499
494
mutex_unlock(&gpu->lock);
500
495
}
501
496
···
881
882
init_waitqueue_head(&gpu->retire_event);
882
883
kthread_init_work(&gpu->retire_work, retire_worker);
883
884
kthread_init_work(&gpu->recover_work, recover_worker);
884
-
kthread_init_work(&gpu->fault_work, fault_worker);
885
885
886
886
priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
887
887
+3
-6
drivers/gpu/drm/msm/msm_gpu.h
+3
-6
drivers/gpu/drm/msm/msm_gpu.h
···
253
253
#define DRM_MSM_HANGCHECK_PROGRESS_RETRIES 3
254
254
struct timer_list hangcheck_timer;
255
255
256
-
/* Fault info for most recent iova fault: */
257
-
struct msm_gpu_fault_info fault_info;
258
-
259
-
/* work for handling GPU ioval faults: */
260
-
struct kthread_work fault_work;
261
-
262
256
/* work for handling GPU recovery: */
263
257
struct kthread_work recover_work;
264
258
···
662
668
void msm_gpu_cleanup(struct msm_gpu *gpu);
663
669
664
670
struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
671
+
bool adreno_has_gpu(struct device_node *node);
665
672
void __init adreno_register(void);
666
673
void __exit adreno_unregister(void);
667
674
···
699
704
700
705
mutex_unlock(&gpu->lock);
701
706
}
707
+
708
+
void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info);
702
709
703
710
/*
704
711
* Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
+4
-8
drivers/gpu/drm/msm/msm_iommu.c
+4
-8
drivers/gpu/drm/msm/msm_iommu.c
···
345
345
unsigned long iova, int flags, void *arg)
346
346
{
347
347
struct msm_iommu *iommu = arg;
348
-
struct msm_mmu *mmu = &iommu->base;
349
348
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
350
349
struct adreno_smmu_fault_info info, *ptr = NULL;
351
350
···
357
358
return iommu->base.handler(iommu->base.arg, iova, flags, ptr);
358
359
359
360
pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
360
-
361
-
if (mmu->funcs->resume_translation)
362
-
mmu->funcs->resume_translation(mmu);
363
361
364
362
return 0;
365
363
}
···
372
376
return -ENOSYS;
373
377
}
374
378
375
-
static void msm_iommu_resume_translation(struct msm_mmu *mmu)
379
+
static void msm_iommu_set_stall(struct msm_mmu *mmu, bool enable)
376
380
{
377
381
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
378
382
379
-
if (adreno_smmu->resume_translation)
380
-
adreno_smmu->resume_translation(adreno_smmu->cookie, true);
383
+
if (adreno_smmu->set_stall)
384
+
adreno_smmu->set_stall(adreno_smmu->cookie, enable);
381
385
}
382
386
383
387
static void msm_iommu_detach(struct msm_mmu *mmu)
···
427
431
.map = msm_iommu_map,
428
432
.unmap = msm_iommu_unmap,
429
433
.destroy = msm_iommu_destroy,
430
-
.resume_translation = msm_iommu_resume_translation,
434
+
.set_stall = msm_iommu_set_stall,
431
435
};
432
436
433
437
struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks)
+1
-1
drivers/gpu/drm/msm/msm_mmu.h
+1
-1
drivers/gpu/drm/msm/msm_mmu.h
+2
-1
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+2
-1
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
···
2255
2255
<reg32 offset="0" name="0">
2256
2256
<bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/>
2257
2257
<bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/>
2258
-
<bitfield name="CLEAR_GLOBAL_LOCAL_TS" pos="2" type="boolean"/>
2258
+
<bitfield name="CLEAR_BV_BR_COUNTER" pos="2" type="boolean"/>
2259
+
<bitfield name="RESET_GLOBAL_LOCAL_TS" pos="3" type="boolean"/>
2259
2260
</reg32>
2260
2261
</domain>
2261
2262
+5
-3
drivers/gpu/drm/msm/registers/gen_header.py
+5
-3
drivers/gpu/drm/msm/registers/gen_header.py
···
11
11
import argparse
12
12
import time
13
13
import datetime
14
+
import re
14
15
15
16
class Error(Exception):
16
17
def __init__(self, message):
···
878
877
""")
879
878
maxlen = 0
880
879
for filepath in p.xml_files:
881
-
maxlen = max(maxlen, len(filepath))
880
+
new_filepath = re.sub("^.+drivers","drivers",filepath)
881
+
maxlen = max(maxlen, len(new_filepath))
882
882
for filepath in p.xml_files:
883
-
pad = " " * (maxlen - len(filepath))
883
+
pad = " " * (maxlen - len(new_filepath))
884
884
filesize = str(os.path.getsize(filepath))
885
885
filesize = " " * (7 - len(filesize)) + filesize
886
886
filetime = time.ctime(os.path.getmtime(filepath))
887
-
print("- " + filepath + pad + " (" + filesize + " bytes, from " + filetime + ")")
887
+
print("- " + new_filepath + pad + " (" + filesize + " bytes, from <stripped>)")
888
888
if p.copyright_year:
889
889
current_year = str(datetime.date.today().year)
890
890
print()
+1
-1
drivers/gpu/drm/nouveau/nouveau_backlight.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_backlight.c
···
42
42
#include "nouveau_acpi.h"
43
43
44
44
static struct ida bl_ida;
45
-
#define BL_NAME_SIZE 15 // 12 for name + 2 for digits + 1 for '\0'
45
+
#define BL_NAME_SIZE 24 // 12 for name + 11 for digits + 1 for '\0'
46
46
47
47
static bool
48
48
nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],
+12
-5
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
+12
-5
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
···
637
637
if (payload_size > max_payload_size) {
638
638
const u32 fn = rpc->function;
639
639
u32 remain_payload_size = payload_size;
640
+
void *next;
640
641
641
-
/* Adjust length, and send initial RPC. */
642
-
rpc->length = sizeof(*rpc) + max_payload_size;
643
-
msg->checksum = rpc->length;
642
+
/* Send initial RPC. */
643
+
next = r535_gsp_rpc_get(gsp, fn, max_payload_size);
644
+
if (IS_ERR(next)) {
645
+
repv = next;
646
+
goto done;
647
+
}
644
648
645
-
repv = r535_gsp_rpc_send(gsp, payload, NVKM_GSP_RPC_REPLY_NOWAIT, 0);
649
+
memcpy(next, payload, max_payload_size);
650
+
651
+
repv = r535_gsp_rpc_send(gsp, next, NVKM_GSP_RPC_REPLY_NOWAIT, 0);
646
652
if (IS_ERR(repv))
647
653
goto done;
648
654
···
659
653
while (remain_payload_size) {
660
654
u32 size = min(remain_payload_size,
661
655
max_payload_size);
662
-
void *next;
663
656
664
657
next = r535_gsp_rpc_get(gsp, NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD, size);
665
658
if (IS_ERR(next)) {
···
679
674
/* Wait for reply. */
680
675
repv = r535_gsp_rpc_handle_reply(gsp, fn, policy, payload_size +
681
676
sizeof(*rpc));
677
+
if (!IS_ERR(repv))
678
+
kvfree(msg);
682
679
} else {
683
680
repv = r535_gsp_rpc_send(gsp, payload, policy, gsp_rpc_len);
684
681
}
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/vmm.c
···
121
121
page_shift -= desc->bits;
122
122
123
123
ctrl->levels[i].physAddress = pd->pt[0]->addr;
124
-
ctrl->levels[i].size = (1 << desc->bits) * desc->size;
124
+
ctrl->levels[i].size = BIT_ULL(desc->bits) * desc->size;
125
125
ctrl->levels[i].aperture = 1;
126
126
ctrl->levels[i].pageShift = page_shift;
127
127
+1
-1
drivers/gpu/drm/solomon/ssd130x.c
+1
-1
drivers/gpu/drm/solomon/ssd130x.c
···
974
974
975
975
static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
976
976
{
977
-
unsigned int columns = DIV_ROUND_UP(ssd130x->height, SSD132X_SEGMENT_WIDTH);
977
+
unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH);
978
978
unsigned int height = ssd130x->height;
979
979
980
980
memset(data_array, 0, columns * height);
+6
-2
drivers/gpu/drm/v3d/v3d_sched.c
+6
-2
drivers/gpu/drm/v3d/v3d_sched.c
···
199
199
struct v3d_dev *v3d = job->v3d;
200
200
struct v3d_file_priv *file = job->file->driver_priv;
201
201
struct v3d_stats *global_stats = &v3d->queue[queue].stats;
202
-
struct v3d_stats *local_stats = &file->stats[queue];
203
202
u64 now = local_clock();
204
203
unsigned long flags;
205
204
···
208
209
else
209
210
preempt_disable();
210
211
211
-
v3d_stats_update(local_stats, now);
212
+
/* Don't update the local stats if the file context has already closed */
213
+
if (file)
214
+
v3d_stats_update(&file->stats[queue], now);
215
+
else
216
+
drm_dbg(&v3d->drm, "The file descriptor was closed before job completion\n");
217
+
212
218
v3d_stats_update(global_stats, now);
213
219
214
220
if (IS_ENABLED(CONFIG_LOCKDEP))
+1
-1
drivers/gpu/drm/xe/xe_gt.c
+1
-1
drivers/gpu/drm/xe/xe_gt.c
+8
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+8
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
···
138
138
int pending_seqno;
139
139
140
140
/*
141
+
* we can get here before the CTs are even initialized if we're wedging
142
+
* very early, in which case there are not going to be any pending
143
+
* fences so we can bail immediately.
144
+
*/
145
+
if (!xe_guc_ct_initialized(>->uc.guc.ct))
146
+
return;
147
+
148
+
/*
141
149
* CT channel is already disabled at this point. No new TLB requests can
142
150
* appear.
143
151
*/
+5
-2
drivers/gpu/drm/xe/xe_guc_ct.c
+5
-2
drivers/gpu/drm/xe/xe_guc_ct.c
···
514
514
*/
515
515
void xe_guc_ct_stop(struct xe_guc_ct *ct)
516
516
{
517
+
if (!xe_guc_ct_initialized(ct))
518
+
return;
519
+
517
520
xe_guc_ct_set_state(ct, XE_GUC_CT_STATE_STOPPED);
518
521
stop_g2h_handler(ct);
519
522
}
···
763
760
u16 seqno;
764
761
int ret;
765
762
766
-
xe_gt_assert(gt, ct->state != XE_GUC_CT_STATE_NOT_INITIALIZED);
763
+
xe_gt_assert(gt, xe_guc_ct_initialized(ct));
767
764
xe_gt_assert(gt, !g2h_len || !g2h_fence);
768
765
xe_gt_assert(gt, !num_g2h || !g2h_fence);
769
766
xe_gt_assert(gt, !g2h_len || num_g2h);
···
1347
1344
u32 action;
1348
1345
u32 *hxg;
1349
1346
1350
-
xe_gt_assert(gt, ct->state != XE_GUC_CT_STATE_NOT_INITIALIZED);
1347
+
xe_gt_assert(gt, xe_guc_ct_initialized(ct));
1351
1348
lockdep_assert_held(&ct->fast_lock);
1352
1349
1353
1350
if (ct->state == XE_GUC_CT_STATE_DISABLED)
+5
drivers/gpu/drm/xe/xe_guc_ct.h
+5
drivers/gpu/drm/xe/xe_guc_ct.h
···
22
22
void xe_guc_ct_snapshot_free(struct xe_guc_ct_snapshot *snapshot);
23
23
void xe_guc_ct_print(struct xe_guc_ct *ct, struct drm_printer *p, bool want_ctb);
24
24
25
+
static inline bool xe_guc_ct_initialized(struct xe_guc_ct *ct)
26
+
{
27
+
return ct->state != XE_GUC_CT_STATE_NOT_INITIALIZED;
28
+
}
29
+
25
30
static inline bool xe_guc_ct_enabled(struct xe_guc_ct *ct)
26
31
{
27
32
return ct->state == XE_GUC_CT_STATE_ENABLED;
+1
-1
drivers/gpu/drm/xe/xe_guc_pc.c
+1
-1
drivers/gpu/drm/xe/xe_guc_pc.c
+3
drivers/gpu/drm/xe/xe_guc_submit.c
+3
drivers/gpu/drm/xe/xe_guc_submit.c