Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"We have GPIO awareness in the pin control core and an interesting
AAEON driver.
Core changes:
- Allow pins to be identified/marked as GPIO mode with a special
callback.
The pin controller core is now "aware" if a pin is in GPIO mode if
the callback is implemented in the driver, and can thus be marked
as "strict", i.e. disallowing simultaneous use of a line as GPIO
and another function such as I2C.
This is enabled in the Qualcomm TLMM driver and also implemeted
from day 1 in the new Broadcom STB driver
- Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL
to better describe what the config is doing, as well as making it
more intuitive what shall be returned when reading this property
New drivers:
- Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver
- Qualcomm Glymur family pin controller driver
- Broadcom STB family pin controller driver
- Tegra186 pin controller driver
- AAEON UP pin controller support.
This is some special pin controller that works as an external
advanced line MUX and amplifier for signals from an Intel SoC. A
cooperative effort with the GPIO maintainer was needed to reach a
solution where we reuse code from the GPIO aggregator/forwarder
driver
- Renesas RZ/T2H and RZ/N2H pin controller support
- Axis ARTPEC-8 subdriver for the Samsung pin controller driver
Improvements:
- Output enable (OEN) support in the Renesas RZG2L driver
- Properly support bias pull up/down in the pinctrl-single driver
- Move over all GPIO portions using generic MMIO GPIO to the new
generic GPIO chip management which has a nice and separate API
- Proper DT bindings for some older Broadcom SoCs
- External GPIO (EGPIO) support in the Qualcomm SM8250
Deleted code:
- Dropped the now unused Samsung S3C24xx drivers"
* tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
pinctrl: use more common syntax for compound literals
pinctrl: Simplify printks with pOF format
pinctrl: qcom: Add SDM660 LPASS LPI TLMM
dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets
pinctrl: qcom: Add glymur pinctrl driver
dt-bindings: pinctrl: qcom: Add Glymur pinctrl
pinctrl: qcom: sm8250: Add egpio support
pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL
pinctrl: keembay: fix double free in keembay_build_functions()
pinctrl: spacemit: fix typo in PRI_TDI pin name
pinctrl: eswin: Fix regulator error check and Kconfig dependency
pinctrl: bcm: Add STB family pin controller driver
dt-bindings: pinctrl: Add support for Broadcom STB pin controller
pinctrl: qcom: make the pinmuxing strict
pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions
pinctrl: qcom: add infrastructure for marking pin functions as GPIOs
pinctrl: allow to mark pin functions as requestable GPIOs
pinctrl: qcom: use generic pin function helpers
pinctrl: make struct pinfunction a pointer in struct function_desc
...
+9120
-767
+137
Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
+137
Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2712c0-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom STB family pin controller
8
+
9
+
maintainers:
10
+
- Ivan T. Ivanov <iivanov@suse.de>
11
+
- A. della Porta <andrea.porta@suse.com>
12
+
13
+
description: >
14
+
Broadcom's STB family of memory-mapped pin controllers.
15
+
16
+
This includes the pin controllers inside the BCM2712 SoC which
17
+
are instances of the STB family and has two silicon variants,
18
+
C0 and D0, which differs slightly in terms of registers layout.
19
+
20
+
The -aon- (Always On) variant is the same IP block but differs
21
+
in the number of pins that are associated and the pinmux functions
22
+
for each of those pins.
23
+
24
+
allOf:
25
+
- $ref: pinctrl.yaml#
26
+
27
+
properties:
28
+
compatible:
29
+
enum:
30
+
- brcm,bcm2712c0-pinctrl
31
+
- brcm,bcm2712c0-aon-pinctrl
32
+
- brcm,bcm2712d0-pinctrl
33
+
- brcm,bcm2712d0-aon-pinctrl
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
patternProperties:
39
+
'-state$':
40
+
oneOf:
41
+
- $ref: '#/$defs/brcmstb-pinctrl-state'
42
+
- patternProperties:
43
+
'-pins$':
44
+
$ref: '#/$defs/brcmstb-pinctrl-state'
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
brcmstb-pinctrl-state:
49
+
allOf:
50
+
- $ref: pincfg-node.yaml#
51
+
- $ref: pinmux-node.yaml#
52
+
53
+
description: >
54
+
Pin controller client devices use pin configuration subnodes (children
55
+
and grandchildren) for desired pin configuration.
56
+
57
+
Client device subnodes use below standard properties.
58
+
59
+
properties:
60
+
pins:
61
+
description:
62
+
List of gpio pins affected by the properties specified in this
63
+
subnode (either this or "groups" must be specified).
64
+
items:
65
+
pattern: '^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$'
66
+
67
+
function:
68
+
description:
69
+
Specify the alternative function to be configured for the specified
70
+
pins.
71
+
enum: [ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8,
72
+
aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm,
73
+
arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2,
74
+
bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii,
75
+
ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c,
76
+
hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out,
77
+
ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0,
78
+
sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e,
79
+
sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0,
80
+
te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0,
81
+
vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1,
82
+
vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3,
83
+
vc_uart4 ]
84
+
85
+
bias-disable: true
86
+
bias-pull-down: true
87
+
bias-pull-up: true
88
+
89
+
required:
90
+
- pins
91
+
92
+
if:
93
+
properties:
94
+
pins:
95
+
not:
96
+
contains:
97
+
pattern: "^emmc_(clk|cmd|dat[0-7]|ds)$"
98
+
then:
99
+
required:
100
+
- function
101
+
else:
102
+
properties:
103
+
function: false
104
+
105
+
additionalProperties: false
106
+
107
+
required:
108
+
- compatible
109
+
- reg
110
+
111
+
unevaluatedProperties: false
112
+
113
+
examples:
114
+
- |
115
+
pinctrl@7d504100 {
116
+
compatible = "brcm,bcm2712c0-pinctrl";
117
+
reg = <0x7d504100 0x30>;
118
+
119
+
bt-shutdown-default-state {
120
+
function = "gpio";
121
+
pins = "gpio29";
122
+
};
123
+
124
+
uarta-default-state {
125
+
rts-tx-pins {
126
+
function = "uart0";
127
+
pins = "gpio24", "gpio26";
128
+
bias-disable;
129
+
};
130
+
131
+
cts-rx-pins {
132
+
function = "uart0";
133
+
pins = "gpio25", "gpio27";
134
+
bias-pull-up;
135
+
};
136
+
};
137
+
};
-99
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
-99
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
···
1
-
Broadcom BCM2835 GPIO (and pinmux) controller
2
-
3
-
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
4
-
controller, and pinmux/control device.
5
-
6
-
Required properties:
7
-
- compatible: "brcm,bcm2835-gpio"
8
-
- compatible: should be one of:
9
-
"brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10
-
"brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11
-
"brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12
-
"brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13
-
- reg: Should contain the physical address of the GPIO module's registers.
14
-
- gpio-controller: Marks the device node as a GPIO controller.
15
-
- #gpio-cells : Should be two. The first cell is the pin number and the
16
-
second cell is used to specify optional parameters:
17
-
- bit 0 specifies polarity (0 for normal, 1 for inverted)
18
-
- interrupts : The interrupt outputs from the controller. One interrupt per
19
-
individual bank followed by the "all banks" interrupt. For BCM7211, an
20
-
additional set of per-bank interrupt line and an "all banks" wake-up
21
-
interrupt may be specified.
22
-
- interrupt-controller: Marks the device node as an interrupt controller.
23
-
- #interrupt-cells : Should be 2.
24
-
The first cell is the GPIO number.
25
-
The second cell is used to specify flags:
26
-
bits[3:0] trigger type and level flags:
27
-
1 = low-to-high edge triggered.
28
-
2 = high-to-low edge triggered.
29
-
4 = active high level-sensitive.
30
-
8 = active low level-sensitive.
31
-
Valid combinations are 1, 2, 3, 4, 8.
32
-
33
-
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
34
-
35
-
Please refer to pinctrl-bindings.txt in this directory for details of the
36
-
common pinctrl bindings used by client devices, including the meaning of the
37
-
phrase "pin configuration node".
38
-
39
-
Each pin configuration node lists the pin(s) to which it applies, and one or
40
-
more of the mux function to select on those pin(s), and pull-up/down
41
-
configuration. Each subnode only affects those parameters that are explicitly
42
-
listed. In other words, a subnode that lists only a mux function implies no
43
-
information about any pull configuration. Similarly, a subnode that lists only
44
-
a pul parameter implies no information about the mux function.
45
-
46
-
The BCM2835 pin configuration and multiplexing supports the generic bindings.
47
-
For details on each properties, you can refer to ./pinctrl-bindings.txt.
48
-
49
-
Required sub-node properties:
50
-
- pins
51
-
- function
52
-
53
-
Optional sub-node properties:
54
-
- bias-disable
55
-
- bias-pull-up
56
-
- bias-pull-down
57
-
- output-high
58
-
- output-low
59
-
60
-
Legacy pin configuration and multiplexing binding:
61
-
*** (Its use is deprecated, use generic multiplexing and configuration
62
-
bindings instead)
63
-
64
-
Required subnode-properties:
65
-
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
66
-
are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
67
-
68
-
Optional subnode-properties:
69
-
- brcm,function: Integer, containing the function to mux to the pin(s):
70
-
0: GPIO in
71
-
1: GPIO out
72
-
2: alt5
73
-
3: alt4
74
-
4: alt0
75
-
5: alt1
76
-
6: alt2
77
-
7: alt3
78
-
- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
79
-
0: none
80
-
1: down
81
-
2: up
82
-
83
-
Each of brcm,function and brcm,pull may contain either a single value which
84
-
will be applied to all pins in brcm,pins, or 1 value for each entry in
85
-
brcm,pins.
86
-
87
-
Example:
88
-
89
-
gpio: gpio {
90
-
compatible = "brcm,bcm2835-gpio";
91
-
reg = <0x2200000 0xb4>;
92
-
interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
93
-
94
-
gpio-controller;
95
-
#gpio-cells = <2>;
96
-
97
-
interrupt-controller;
98
-
#interrupt-cells = <2>;
99
-
};
+120
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml
+120
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2835-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom BCM2835 GPIO (and pinmux) controller
8
+
9
+
maintainers:
10
+
- Florian Fainelli <f.fainelli@gmail.com>
11
+
12
+
description: >
13
+
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
14
+
controller, and pinmux/control device.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- brcm,bcm2835-gpio
20
+
- brcm,bcm2711-gpio
21
+
- brcm,bcm7211-gpio
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
'#gpio-cells':
27
+
const: 2
28
+
29
+
gpio-controller: true
30
+
gpio-ranges: true
31
+
gpio-line-names: true
32
+
33
+
interrupts:
34
+
description: >
35
+
Interrupt outputs: one per bank, then the combined “all banks” line.
36
+
BCM7211 may specify up to four per-bank wake-up lines and one combined
37
+
wake-up interrupt.
38
+
minItems: 4
39
+
maxItems: 10
40
+
41
+
'#interrupt-cells':
42
+
const: 2
43
+
44
+
interrupt-controller: true
45
+
46
+
additionalProperties:
47
+
oneOf:
48
+
- type: object
49
+
additionalProperties: false
50
+
51
+
patternProperties:
52
+
'^pins?-':
53
+
type: object
54
+
allOf:
55
+
- $ref: /schemas/pinctrl/pincfg-node.yaml#
56
+
- $ref: /schemas/pinctrl/pinmux-node.yaml#
57
+
additionalProperties: false
58
+
59
+
properties:
60
+
pins: true
61
+
function: true
62
+
bias-disable: true
63
+
bias-pull-up: true
64
+
bias-pull-down: true
65
+
output-high: true
66
+
output-low: true
67
+
68
+
required:
69
+
- pins
70
+
- function
71
+
72
+
- type: object
73
+
additionalProperties: false
74
+
deprecated: true
75
+
76
+
properties:
77
+
brcm,pins:
78
+
description:
79
+
GPIO pin numbers for legacy configuration.
80
+
$ref: /schemas/types.yaml#/definitions/uint32-array
81
+
82
+
brcm,function:
83
+
description:
84
+
Legacy mux function for the pins (0=input, 1=output, 2–7=alt functions).
85
+
$ref: /schemas/types.yaml#/definitions/uint32-array
86
+
maximum: 7
87
+
88
+
brcm,pull:
89
+
description: >
90
+
Legacy pull setting for the pins (0=none, 1=pull-down, 2=pull-up).
91
+
$ref: /schemas/types.yaml#/definitions/uint32-array
92
+
maximum: 2
93
+
94
+
required:
95
+
- brcm,pins
96
+
97
+
allOf:
98
+
- if:
99
+
properties:
100
+
compatible:
101
+
contains:
102
+
enum:
103
+
- brcm,bcm2835-gpio
104
+
- brcm,bcm2711-gpio
105
+
then:
106
+
properties:
107
+
interrupts:
108
+
maxItems: 5
109
+
110
+
examples:
111
+
- |
112
+
gpio@2200000 {
113
+
compatible = "brcm,bcm2835-gpio";
114
+
reg = <0x2200000 0xb4>;
115
+
interrupts = <2 17>, <2 19>, <2 18>, <2 20>, <2 21>;
116
+
#gpio-cells = <2>;
117
+
gpio-controller;
118
+
#interrupt-cells = <2>;
119
+
interrupt-controller;
120
+
};
-123
Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
-123
Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt
···
1
-
Broadcom iProc GPIO/PINCONF Controller
2
-
3
-
Required properties:
4
-
5
-
- compatible:
6
-
"brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7
-
supports full-featured pinctrl and GPIO functions used in various iProc
8
-
based SoCs
9
-
10
-
May contain an SoC-specific compatibility string to accommodate any
11
-
SoC-specific features
12
-
13
-
"brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14
-
"brcm,cygnus-crmu-gpio" for Cygnus SoCs
15
-
16
-
"brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
17
-
disabled
18
-
19
-
"brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
20
-
pinctrl support completely disabled in this IP block. In Stingray, a
21
-
different IP block is used to handle pinctrl related functions
22
-
23
-
- reg:
24
-
Define the base and range of the I/O address space that contains SoC
25
-
GPIO/PINCONF controller registers
26
-
27
-
- ngpios:
28
-
Total number of in-use slots in GPIO controller
29
-
30
-
- #gpio-cells:
31
-
Must be two. The first cell is the GPIO pin number (within the
32
-
controller's pin space) and the second cell is used for the following:
33
-
bit[0]: polarity (0 for active high and 1 for active low)
34
-
35
-
- gpio-controller:
36
-
Specifies that the node is a GPIO controller
37
-
38
-
Optional properties:
39
-
40
-
- interrupts:
41
-
Interrupt ID
42
-
43
-
- interrupt-controller:
44
-
Specifies that the node is an interrupt controller
45
-
46
-
- gpio-ranges:
47
-
Specifies the mapping between gpio controller and pin-controllers pins.
48
-
This requires 4 fields in cells defined as -
49
-
1. Phandle of pin-controller.
50
-
2. GPIO base pin offset.
51
-
3 Pin-control base pin offset.
52
-
4. number of gpio pins which are linearly mapped from pin base.
53
-
54
-
Supported generic PINCONF properties in child nodes:
55
-
56
-
- pins:
57
-
The list of pins (within the controller's own pin space) that properties
58
-
in the node apply to. Pin names are "gpio-<pin>"
59
-
60
-
- bias-disable:
61
-
Disable pin bias
62
-
63
-
- bias-pull-up:
64
-
Enable internal pull up resistor
65
-
66
-
- bias-pull-down:
67
-
Enable internal pull down resistor
68
-
69
-
- drive-strength:
70
-
Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
71
-
72
-
Example:
73
-
gpio_ccm: gpio@1800a000 {
74
-
compatible = "brcm,cygnus-ccm-gpio";
75
-
reg = <0x1800a000 0x50>,
76
-
<0x0301d164 0x20>;
77
-
ngpios = <24>;
78
-
#gpio-cells = <2>;
79
-
gpio-controller;
80
-
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
81
-
interrupt-controller;
82
-
83
-
touch_pins: touch_pins {
84
-
pwr: pwr {
85
-
pins = "gpio-0";
86
-
drive-strength = <16>;
87
-
};
88
-
89
-
event: event {
90
-
pins = "gpio-1";
91
-
bias-pull-up;
92
-
};
93
-
};
94
-
};
95
-
96
-
gpio_asiu: gpio@180a5000 {
97
-
compatible = "brcm,cygnus-asiu-gpio";
98
-
reg = <0x180a5000 0x668>;
99
-
ngpios = <146>;
100
-
#gpio-cells = <2>;
101
-
gpio-controller;
102
-
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
103
-
interrupt-controller;
104
-
gpio-ranges = <&pinctrl 0 42 1>,
105
-
<&pinctrl 1 44 3>;
106
-
};
107
-
108
-
/*
109
-
* Touchscreen that uses the CCM GPIO 0 and 1
110
-
*/
111
-
tsc {
112
-
...
113
-
...
114
-
gpio-pwr = <&gpio_ccm 0 0>;
115
-
gpio-event = <&gpio_ccm 1 0>;
116
-
};
117
-
118
-
/* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */
119
-
bluetooth {
120
-
...
121
-
...
122
-
bcm,rfkill-bank-sel = <&gpio_asiu 5 1>
123
-
}
+111
Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml
+111
Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/brcm,iproc-gpio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom iProc GPIO/PINCONF Controller
8
+
9
+
maintainers:
10
+
- Ray Jui <rjui@broadcom.com>
11
+
- Scott Branden <sbranden@broadcom.com>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- brcm,cygnus-asiu-gpio
18
+
- brcm,cygnus-ccm-gpio
19
+
- brcm,cygnus-crmu-gpio
20
+
- brcm,iproc-gpio
21
+
- brcm,iproc-stingray-gpio
22
+
- items:
23
+
- enum:
24
+
- brcm,iproc-hr2-gpio
25
+
- brcm,iproc-nsp-gpio
26
+
- const: brcm,iproc-gpio
27
+
28
+
reg:
29
+
minItems: 1
30
+
items:
31
+
- description: GPIO Bank registers
32
+
- description: IO Ctrl registers
33
+
34
+
"#gpio-cells":
35
+
const: 2
36
+
37
+
gpio-controller: true
38
+
39
+
gpio-ranges: true
40
+
41
+
ngpios: true
42
+
43
+
"#interrupt-cells":
44
+
const: 2
45
+
46
+
interrupts:
47
+
maxItems: 1
48
+
49
+
interrupt-controller: true
50
+
51
+
required:
52
+
- compatible
53
+
- reg
54
+
- "#gpio-cells"
55
+
- gpio-controller
56
+
- ngpios
57
+
58
+
patternProperties:
59
+
'-pins$':
60
+
type: object
61
+
additionalProperties:
62
+
description: Pin configuration child nodes.
63
+
allOf:
64
+
- $ref: pincfg-node.yaml#
65
+
- $ref: pinmux-node.yaml#
66
+
additionalProperties: false
67
+
68
+
properties:
69
+
pins:
70
+
items:
71
+
pattern: '^gpio-'
72
+
73
+
bias-disable: true
74
+
bias-pull-up: true
75
+
bias-pull-down: true
76
+
77
+
drive-strength:
78
+
enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]
79
+
80
+
required:
81
+
- pins
82
+
83
+
additionalProperties: false
84
+
85
+
examples:
86
+
- |
87
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
88
+
89
+
gpio@1800a000 {
90
+
compatible = "brcm,cygnus-ccm-gpio";
91
+
reg = <0x1800a000 0x50>,
92
+
<0x0301d164 0x20>;
93
+
ngpios = <24>;
94
+
#gpio-cells = <2>;
95
+
gpio-controller;
96
+
#interrupt-cells = <2>;
97
+
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
98
+
interrupt-controller;
99
+
100
+
touch-pins {
101
+
pwr {
102
+
pins = "gpio-0";
103
+
drive-strength = <16>;
104
+
};
105
+
106
+
event {
107
+
pins = "gpio-1";
108
+
bias-pull-up;
109
+
};
110
+
};
111
+
};
+2
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
+2
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
+285
Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml
+285
Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra186-pinmux.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra186 Pinmux Controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- nvidia,tegra186-pinmux
17
+
- nvidia,tegra186-pinmux-aon
18
+
19
+
reg:
20
+
items:
21
+
- description: pinmux registers
22
+
23
+
patternProperties:
24
+
"^pinmux(-[a-z0-9-]+)?$":
25
+
type: object
26
+
27
+
# pin groups
28
+
additionalProperties:
29
+
$ref: nvidia,tegra-pinmux-common.yaml
30
+
unevaluatedProperties: false
31
+
properties:
32
+
nvidia,function:
33
+
enum: [ aud, can0, can1, ccla, dca, dcb, dcc, directdc, directdc1,
34
+
displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
35
+
dspk0, dspk1, dtv, eqos, extperiph1, extperiph2, extperiph3,
36
+
extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c7,
37
+
i2c8, i2c9, i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, iqc0, iqc1,
38
+
nv, pe, pe0, pe1, pe2, qspi, rsvd0, rsvd1, rsvd2, rsvd3,
39
+
sata, sce, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1,
40
+
spi2, spi3, spi4, touch, uarta, uartb, uartc, uartd, uarte,
41
+
uartf, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
42
+
wdt ]
43
+
44
+
nvidia,pull: true
45
+
nvidia,tristate: true
46
+
nvidia,schmitt: true
47
+
nvidia,enable-input: true
48
+
nvidia,open-drain: true
49
+
nvidia,lock: true
50
+
nvidia,drive-type: true
51
+
nvidia,io-hv: true
52
+
53
+
required:
54
+
- nvidia,pins
55
+
56
+
additionalProperties: false
57
+
58
+
allOf:
59
+
- if:
60
+
properties:
61
+
compatible:
62
+
const: nvidia,tegra186-pinmux
63
+
then:
64
+
patternProperties:
65
+
"^pinmux(-[a-z0-9-]+)?$":
66
+
type: object
67
+
additionalProperties:
68
+
properties:
69
+
nvidia,pins:
70
+
description: An array of strings. Each string contains the name
71
+
of a pin or group. Valid values for these names are listed
72
+
below.
73
+
items:
74
+
enum: [ pex_l0_rst_n_pa0, pex_l0_clkreq_n_pa1,
75
+
pex_wake_n_pa2, pex_l1_rst_n_pa3,
76
+
pex_l1_clkreq_n_pa4, pex_l2_rst_n_pa5,
77
+
pex_l2_clkreq_n_pa6, uart4_tx_pb0, uart4_rx_pb1,
78
+
uart4_rts_pb2, uart4_cts_pb3, gpio_wan1_pb4,
79
+
gpio_wan2_pb5, gpio_wan3_pb6, gpio_wan4_pc0,
80
+
dap2_sclk_pc1, dap2_dout_pc2, dap2_din_pc3,
81
+
dap2_fs_pc4, gen1_i2c_scl_pc5, gen1_i2c_sda_pc6,
82
+
sdmmc1_clk_pd0, sdmmc1_cmd_pd1, sdmmc1_dat0_pd2,
83
+
sdmmc1_dat1_pd3, sdmmc1_dat2_pd4, sdmmc1_dat3_pd5,
84
+
eqos_txc_pe0, eqos_td0_pe1, eqos_td1_pe2,
85
+
eqos_td2_pe3, eqos_td3_pe4, eqos_tx_ctl_pe5,
86
+
eqos_rd0_pe6, eqos_rd1_pe7, eqos_rd2_pf0,
87
+
eqos_rd3_pf1, eqos_rx_ctl_pf2, eqos_rxc_pf3,
88
+
eqos_mdio_pf4, eqos_mdc_pf5, sdmmc3_clk_pg0,
89
+
sdmmc3_cmd_pg1, sdmmc3_dat0_pg2, sdmmc3_dat1_pg3,
90
+
sdmmc3_dat2_pg4, sdmmc3_dat3_pg5, gpio_wan5_ph0,
91
+
gpio_wan6_ph1, gpio_wan7_ph2, gpio_wan8_ph3,
92
+
bcpu_pwr_req_ph4, mcpu_pwr_req_ph5, gpu_pwr_req_ph6,
93
+
gpio_pq0_pi0, gpio_pq1_pi1, gpio_pq2_pi2,
94
+
gpio_pq3_pi3, gpio_pq4_pi4, gpio_pq5_pi5,
95
+
gpio_pq6_pi6, gpio_pq7_pi7, dap1_sclk_pj0,
96
+
dap1_dout_pj1, dap1_din_pj2, dap1_fs_pj3,
97
+
aud_mclk_pj4, gpio_aud0_pj5, gpio_aud1_pj6,
98
+
gpio_aud2_pj7, gpio_aud3_pk0, gen7_i2c_scl_pl0,
99
+
gen7_i2c_sda_pl1, gen9_i2c_scl_pl2, gen9_i2c_sda_pl3,
100
+
usb_vbus_en0_pl4, usb_vbus_en1_pl5, gp_pwm6_pl6,
101
+
gp_pwm7_pl7, dmic1_dat_pm0, dmic1_clk_pm1,
102
+
dmic2_dat_pm2, dmic2_clk_pm3, dmic4_dat_pm4,
103
+
dmic4_clk_pm5, gpio_cam1_pn0, gpio_cam2_pn1,
104
+
gpio_cam3_pn2, gpio_cam4_pn3, gpio_cam6_pn5,
105
+
gpio_cam7_pn6, extperiph1_clk_po0,
106
+
extperiph2_clk_po1, cam_i2c_scl_po2, cam_i2c_sda_po3,
107
+
dp_aux_ch0_hpd_pp0, dp_aux_ch1_hpd_pp1, hdmi_cec_pp2,
108
+
gpio_edp0_pp3, gpio_edp1_pp4, gpio_edp2_pp5,
109
+
gpio_edp3_pp6, directdc1_clk_pq0, directdc1_in_pq1,
110
+
directdc1_out0_pq2, directdc1_out1_pq3,
111
+
directdc1_out2_pq4, directdc1_out3_pq5,
112
+
qspi_sck_pr0, qspi_io0_pr1, qspi_io1_pr2,
113
+
qspi_io2_pr3, qspi_io3_pr4, qspi_cs_n_pr5,
114
+
uart1_tx_pt0, uart1_rx_pt1, uart1_rts_pt2,
115
+
uart1_cts_pt3, uart2_tx_px0, uart2_rx_px1,
116
+
uart2_rts_px2, uart2_cts_px3, uart5_tx_px4,
117
+
uart5_rx_px5, uart5_rts_px6, uart5_cts_px7,
118
+
gpio_mdm1_py0, gpio_mdm2_py1, gpio_mdm3_py2,
119
+
gpio_mdm4_py3, gpio_mdm5_py4, gpio_mdm6_py5,
120
+
gpio_mdm7_py6, ufs0_ref_clk_pbb0, ufs0_rst_pbb1,
121
+
dap4_sclk_pcc0, dap4_dout_pcc1, dap4_din_pcc2,
122
+
dap4_fs_pcc3, directdc_comp, sdmmc1_comp, eqos_comp,
123
+
sdmmc3_comp, qspi_comp,
124
+
# drive groups
125
+
drive_gpio_aud3_pk0, drive_gpio_aud2_pj7,
126
+
drive_gpio_aud1_pj6, drive_gpio_aud0_pj5,
127
+
drive_aud_mclk_pj4, drive_dap1_fs_pj3,
128
+
drive_dap1_din_pj2, drive_dap1_dout_pj1,
129
+
drive_dap1_sclk_pj0, drive_dmic1_clk_pm1,
130
+
drive_dmic1_dat_pm0, drive_dmic2_dat_pm2,
131
+
drive_dmic2_clk_pm3, drive_dmic4_dat_pm4,
132
+
drive_dmic4_clk_pm5, drive_dap4_fs_pcc3,
133
+
drive_dap4_din_pcc2, drive_dap4_dout_pcc1,
134
+
drive_dap4_sclk_pcc0, drive_extperiph2_clk_po1,
135
+
drive_extperiph1_clk_po0, drive_cam_i2c_sda_po3,
136
+
drive_cam_i2c_scl_po2, drive_gpio_cam1_pn0,
137
+
drive_gpio_cam2_pn1, drive_gpio_cam3_pn2,
138
+
drive_gpio_cam4_pn3, drive_gpio_cam5_pn4,
139
+
drive_gpio_cam6_pn5, drive_gpio_cam7_pn6,
140
+
drive_dap2_din_pc3, drive_dap2_dout_pc2,
141
+
drive_dap2_fs_pc4, drive_dap2_sclk_pc1,
142
+
drive_uart4_cts_pb3, drive_uart4_rts_pb2,
143
+
drive_uart4_rx_pb1, drive_uart4_tx_pb0,
144
+
drive_gpio_wan4_pc0, drive_gpio_wan3_pb6,
145
+
drive_gpio_wan2_pb5, drive_gpio_wan1_pb4,
146
+
drive_gen1_i2c_scl_pc5, drive_gen1_i2c_sda_pc6,
147
+
drive_uart1_cts_pt3, drive_uart1_rts_pt2,
148
+
drive_uart1_rx_pt1, drive_uart1_tx_pt0,
149
+
drive_directdc1_out3_pq5, drive_directdc1_out2_pq4,
150
+
drive_directdc1_out1_pq3, drive_directdc1_out0_pq2,
151
+
drive_directdc1_in_pq1, drive_directdc1_clk_pq0,
152
+
drive_gpio_pq0_pi0, drive_gpio_pq1_pi1,
153
+
drive_gpio_pq2_pi2, drive_gpio_pq3_pi3,
154
+
drive_gpio_pq4_pi4, drive_gpio_pq5_pi5,
155
+
drive_gpio_pq6_pi6, drive_gpio_pq7_pi7,
156
+
drive_gpio_edp2_pp5, drive_gpio_edp3_pp6,
157
+
drive_gpio_edp0_pp3, drive_gpio_edp1_pp4,
158
+
drive_dp_aux_ch0_hpd_pp0, drive_dp_aux_ch1_hpd_pp1,
159
+
drive_hdmi_cec_pp2, drive_pex_l2_clkreq_n_pa6,
160
+
drive_pex_wake_n_pa2, drive_pex_l1_clkreq_n_pa4,
161
+
drive_pex_l1_rst_n_pa3, drive_pex_l0_clkreq_n_pa1,
162
+
drive_pex_l0_rst_n_pa0, drive_pex_l2_rst_n_pa5,
163
+
drive_sdmmc1_clk_pd0, drive_sdmmc1_cmd_pd1,
164
+
drive_sdmmc1_dat3_pd5, drive_sdmmc1_dat2_pd4,
165
+
drive_sdmmc1_dat1_pd3, drive_sdmmc1_dat0_pd2,
166
+
drive_eqos_td3_pe4, drive_eqos_td2_pe3,
167
+
drive_eqos_td1_pe2, drive_eqos_td0_pe1,
168
+
drive_eqos_rd3_pf1, drive_eqos_rd2_pf0,
169
+
drive_eqos_rd1_pe7, drive_eqos_mdio_pf4,
170
+
drive_eqos_rd0_pe6, drive_eqos_mdc_pf5,
171
+
drive_eqos_txc_pe0, drive_eqos_rxc_pf3,
172
+
drive_eqos_tx_ctl_pe5, drive_eqos_rx_ctl_pf2,
173
+
drive_sdmmc3_dat3_pg5, drive_sdmmc3_dat2_pg4,
174
+
drive_sdmmc3_dat1_pg3, drive_sdmmc3_dat0_pg2,
175
+
drive_sdmmc3_cmd_pg1, drive_sdmmc3_clk_pg0,
176
+
drive_qspi_io3_pr4, drive_qspi_io2_pr3,
177
+
drive_qspi_io1_pr2, drive_qspi_io0_pr1,
178
+
drive_qspi_sck_pr0, drive_qspi_cs_n_pr5,
179
+
drive_gpio_wan8_ph3, drive_gpio_wan7_ph2,
180
+
drive_gpio_wan6_ph1, drive_gpio_wan5_ph0,
181
+
drive_uart2_tx_px0, drive_uart2_rx_px1,
182
+
drive_uart2_rts_px2, drive_uart2_cts_px3,
183
+
drive_uart5_rx_px5, drive_uart5_tx_px4,
184
+
drive_uart5_rts_px6, drive_uart5_cts_px7,
185
+
drive_gpio_mdm1_py0, drive_gpio_mdm2_py1,
186
+
drive_gpio_mdm3_py2, drive_gpio_mdm4_py3,
187
+
drive_gpio_mdm5_py4, drive_gpio_mdm6_py5,
188
+
drive_gpio_mdm7_py6, drive_bcpu_pwr_req_ph4,
189
+
drive_mcpu_pwr_req_ph5, drive_gpu_pwr_req_ph6,
190
+
drive_gen7_i2c_scl_pl0, drive_gen7_i2c_sda_pl1,
191
+
drive_gen9_i2c_sda_pl3, drive_gen9_i2c_scl_pl2,
192
+
drive_usb_vbus_en0_pl4, drive_usb_vbus_en1_pl5,
193
+
drive_gp_pwm7_pl7, drive_gp_pwm6_pl6,
194
+
drive_ufs0_rst_pbb1, drive_ufs0_ref_clk_pbb0,
195
+
drive_directdc_comp, drive_sdmmc1_comp,
196
+
drive_eqos_comp, drive_sdmmc3_comp, drive_sdmmc4_clk,
197
+
drive_sdmmc4_cmd, drive_sdmmc4_dqs,
198
+
drive_sdmmc4_dat7, drive_sdmmc4_dat6,
199
+
drive_sdmmc4_dat5, drive_sdmmc4_dat4,
200
+
drive_sdmmc4_dat3, drive_sdmmc4_dat2,
201
+
drive_sdmmc4_dat1, drive_sdmmc4_dat0,
202
+
drive_qspi_comp ]
203
+
204
+
- if:
205
+
properties:
206
+
compatible:
207
+
const: nvidia,tegra186-pinmux-aon
208
+
then:
209
+
patternProperties:
210
+
"^pinmux(-[a-z0-9-]+)?$":
211
+
type: object
212
+
additionalProperties:
213
+
properties:
214
+
nvidia,pins:
215
+
items:
216
+
enum: [ pwr_i2c_scl_ps0, pwr_i2c_sda_ps1, batt_oc_ps2,
217
+
safe_state_ps3, vcomp_alert_ps4, gpio_dis0_pu0,
218
+
gpio_dis1_pu1, gpio_dis2_pu2, gpio_dis3_pu3,
219
+
gpio_dis4_pu4, gpio_dis5_pu5, gpio_sen0_pv0,
220
+
gpio_sen1_pv1, gpio_sen2_pv2, gpio_sen3_pv3,
221
+
gpio_sen4_pv4, gpio_sen5_pv5, gpio_sen6_pv6,
222
+
gpio_sen7_pv7, gen8_i2c_scl_pw0, gen8_i2c_sda_pw1,
223
+
uart3_tx_pw2, uart3_rx_pw3, uart3_rts_pw4,
224
+
uart3_cts_pw5, uart7_tx_pw6, uart7_rx_pw7,
225
+
can1_dout_pz0, can1_din_pz1, can0_dout_pz2,
226
+
can0_din_pz3, can_gpio0_paa0, can_gpio1_paa1,
227
+
can_gpio2_paa2, can_gpio3_paa3, can_gpio4_paa4,
228
+
can_gpio5_paa5, can_gpio6_paa6, can_gpio7_paa7,
229
+
gpio_sen8_pee0, gpio_sen9_pee1, touch_clk_pee2,
230
+
power_on_pff0, gpio_sw1_pff1, gpio_sw2_pff2,
231
+
gpio_sw3_pff3, gpio_sw4_pff4, shutdown, pmu_int,
232
+
soc_pwr_req, clk_32k_in,
233
+
# drive groups
234
+
drive_touch_clk_pee2, drive_uart3_cts_pw5,
235
+
drive_uart3_rts_pw4, drive_uart3_rx_pw3,
236
+
drive_uart3_tx_pw2, drive_gen8_i2c_sda_pw1,
237
+
drive_gen8_i2c_scl_pw0, drive_uart7_rx_pw7,
238
+
drive_uart7_tx_pw6, drive_gpio_sen0_pv0,
239
+
drive_gpio_sen1_pv1, drive_gpio_sen2_pv2,
240
+
drive_gpio_sen3_pv3, drive_gpio_sen4_pv4,
241
+
drive_gpio_sen5_pv5, drive_gpio_sen6_pv6,
242
+
drive_gpio_sen7_pv7, drive_gpio_sen8_pee0,
243
+
drive_gpio_sen9_pee1, drive_can_gpio7_paa7,
244
+
drive_can1_dout_pz0, drive_can1_din_pz1,
245
+
drive_can0_dout_pz2, drive_can0_din_pz3,
246
+
drive_can_gpio0_paa0, drive_can_gpio1_paa1,
247
+
drive_can_gpio2_paa2, drive_can_gpio3_paa3,
248
+
drive_can_gpio4_paa4, drive_can_gpio5_paa5,
249
+
drive_can_gpio6_paa6, drive_gpio_sw1_pff1,
250
+
drive_gpio_sw2_pff2, drive_gpio_sw3_pff3,
251
+
drive_gpio_sw4_pff4, drive_shutdown, drive_pmu_int,
252
+
drive_safe_state_ps3, drive_vcomp_alert_ps4,
253
+
drive_soc_pwr_req, drive_batt_oc_ps2,
254
+
drive_clk_32k_in, drive_power_on_pff0,
255
+
drive_pwr_i2c_scl_ps0, drive_pwr_i2c_sda_ps1,
256
+
drive_gpio_dis0_pu0, drive_gpio_dis1_pu1,
257
+
drive_gpio_dis2_pu2, drive_gpio_dis3_pu3,
258
+
drive_gpio_dis4_pu4, drive_gpio_dis5_pu5 ]
259
+
260
+
required:
261
+
- compatible
262
+
- reg
263
+
264
+
examples:
265
+
- |
266
+
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
267
+
268
+
pinmux@2430000 {
269
+
compatible = "nvidia,tegra186-pinmux";
270
+
reg = <0x2430000 0x15000>;
271
+
272
+
pinctrl-names = "jetson_io";
273
+
pinctrl-0 = <&jetson_io_pinmux>;
274
+
275
+
jetson_io_pinmux: pinmux {
276
+
hdr40-pin7 {
277
+
nvidia,pins = "aud_mclk_pj4";
278
+
nvidia,function = "aud";
279
+
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
280
+
nvidia,tristate = <TEGRA_PIN_DISABLE>;
281
+
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
282
+
};
283
+
};
284
+
};
285
+
...
+133
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
+133
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. Glymur TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,glymur-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges:
29
+
minItems: 1
30
+
maxItems: 125
31
+
32
+
gpio-line-names:
33
+
maxItems: 250
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-glymur-tlmm-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-glymur-tlmm-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-glymur-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
oneOf:
60
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$"
61
+
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb,
70
+
audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4,
71
+
cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
72
+
cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete,
73
+
ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi,
74
+
edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en,
75
+
eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1,
76
+
gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda,
77
+
i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws,
78
+
ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p,
79
+
mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk,
80
+
pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag,
81
+
pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc,
82
+
qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2,
83
+
qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7,
84
+
qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
85
+
qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3,
86
+
qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1,
87
+
sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n,
88
+
sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng,
89
+
tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx,
90
+
usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx,
91
+
usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx,
92
+
usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
93
+
94
+
required:
95
+
- pins
96
+
97
+
required:
98
+
- compatible
99
+
- reg
100
+
101
+
unevaluatedProperties: false
102
+
103
+
examples:
104
+
- |
105
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
106
+
tlmm: pinctrl@f100000 {
107
+
compatible = "qcom,glymur-tlmm";
108
+
reg = <0x0f100000 0xf00000>;
109
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
110
+
gpio-controller;
111
+
#gpio-cells = <2>;
112
+
interrupt-controller;
113
+
#interrupt-cells = <2>;
114
+
gpio-ranges = <&tlmm 0 0 249>;
115
+
wakeup-parent = <&pdc>;
116
+
gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>;
117
+
qup_uart21_default: qup-uart21-default-state {
118
+
tx-pins {
119
+
pins = "gpio86";
120
+
function = "qup2_se5";
121
+
drive-strength = <2>;
122
+
bias-disable;
123
+
};
124
+
125
+
rx-pins {
126
+
pins = "gpio87";
127
+
function = "qup2_se5";
128
+
drive-strength = <2>;
129
+
bias-disable;
130
+
};
131
+
};
132
+
};
133
+
...
+16
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+16
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
···
20
20
reg:
21
21
maxItems: 2
22
22
23
+
clocks:
24
+
items:
25
+
- description: LPASS Core voting clock
26
+
- description: LPASS Audio voting clock
27
+
28
+
clock-names:
29
+
items:
30
+
- const: core
31
+
- const: audio
32
+
23
33
patternProperties:
24
34
"-state$":
25
35
oneOf:
···
80
70
81
71
examples:
82
72
- |
73
+
#include <dt-bindings/sound/qcom,q6afe.h>
83
74
lpass_tlmm: pinctrl@33c0000 {
84
75
compatible = "qcom,sc7280-lpass-lpi-pinctrl";
85
76
reg = <0x33c0000 0x20000>,
86
77
<0x3550000 0x10000>;
78
+
79
+
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
80
+
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
81
+
clock-names = "core", "audio";
82
+
87
83
gpio-controller;
88
84
#gpio-cells = <2>;
89
85
gpio-ranges = <&lpass_tlmm 0 0 15>;
+109
Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml
+109
Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDM660 SoC LPASS LPI TLMM
8
+
9
+
maintainers:
10
+
- Nickolay Goppen <setotau@mainlining.org>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,sdm660-lpass-lpi-pinctrl
19
+
20
+
reg:
21
+
items:
22
+
- description: LPASS LPI TLMM Control and Status registers
23
+
24
+
patternProperties:
25
+
"-state$":
26
+
oneOf:
27
+
- $ref: "#/$defs/qcom-sdm660-lpass-state"
28
+
- patternProperties:
29
+
"-pins$":
30
+
$ref: "#/$defs/qcom-sdm660-lpass-state"
31
+
additionalProperties: false
32
+
33
+
$defs:
34
+
qcom-sdm660-lpass-state:
35
+
type: object
36
+
description:
37
+
Pinctrl node's client devices use subnodes for desired pin configuration.
38
+
Client device subnodes use below standard properties.
39
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
40
+
unevaluatedProperties: false
41
+
42
+
properties:
43
+
pins:
44
+
description:
45
+
List of gpio pins affected by the properties specified in this
46
+
subnode.
47
+
items:
48
+
pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$"
49
+
50
+
function:
51
+
enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,
52
+
mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync ]
53
+
description:
54
+
Specify the alternative function to be configured for the specified
55
+
pins.
56
+
57
+
allOf:
58
+
- $ref: qcom,lpass-lpi-common.yaml#
59
+
60
+
required:
61
+
- compatible
62
+
- reg
63
+
64
+
unevaluatedProperties: false
65
+
66
+
examples:
67
+
- |
68
+
lpi_tlmm: pinctrl@15070000 {
69
+
compatible = "qcom,sdm660-lpass-lpi-pinctrl";
70
+
reg = <0x15070000 0x20000>;
71
+
gpio-controller;
72
+
#gpio-cells = <2>;
73
+
gpio-ranges = <&lpi_tlmm 0 0 32>;
74
+
75
+
cdc_pdm_default: cdc-pdm-default-state {
76
+
clk-pins {
77
+
pins = "gpio18";
78
+
function = "pdm_clk";
79
+
drive-strength = <8>;
80
+
output-high;
81
+
};
82
+
83
+
sync-pins{
84
+
pins = "gpio19";
85
+
function = "pdm_sync";
86
+
drive-strength = <4>;
87
+
output-high;
88
+
};
89
+
90
+
tx-pins {
91
+
pins = "gpio20";
92
+
function = "pdm_tx";
93
+
drive-strength = <8>;
94
+
};
95
+
96
+
rx-pins {
97
+
pins = "gpio21", "gpio23", "gpio25";
98
+
function = "pdm_rx";
99
+
drive-strength = <4>;
100
+
output-high;
101
+
};
102
+
};
103
+
104
+
cdc_comp_default: cdc-comp-default-state {
105
+
pins = "gpio22", "gpio24";
106
+
function = "comp_rx";
107
+
drive-strength = <8>;
108
+
};
109
+
};
+34
-1
Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml
+34
-1
Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml
···
72
72
pins:
73
73
description:
74
74
List of gpio pins affected by the properties specified in this
75
-
subnode.
75
+
subnode (either this or "groups" must be specified).
76
76
items:
77
77
pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$'
78
+
79
+
groups:
80
+
description:
81
+
List of groups affected by the properties specified in this
82
+
subnode (either this or "pins" must be specified).
83
+
items:
84
+
anyOf:
85
+
- pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$'
86
+
- enum: [ uart0, uart0_ctrl, uart1, uart1_ctrl, uart2, uart2_ctrl,
87
+
uart3, uart3_ctrl, uart4, uart4_ctrl, uart5_0,
88
+
uart5_0_ctrl, uart5_1, uart5_1_ctrl, uart5_2,
89
+
uart5_2_ctrl, uart5_3,
90
+
sd0, sd1,
91
+
i2s0, i2s0_dual, i2s0_quad, i2s1, i2s1_dual, i2s1_quad,
92
+
i2s2_0, i2s2_0_dual, i2s2_1, i2s2_1_dual,
93
+
i2c4_0, i2c4_1, i2c4_2, i2c4_3, i2c6_0, i2c6_1, i2c5_0,
94
+
i2c5_1, i2c5_2, i2c5_3, i2c0_0, i2c0_1, i2c1_0, i2c1_1,
95
+
i2c2_0, i2c2_1, i2c3_0, i2c3_1, i2c3_2,
96
+
dpi_16bit, dpi_16bit_cpadhi, dpi_16bit_pad666,
97
+
dpi_18bit, dpi_18bit_cpadhi, dpi_24bit,
98
+
spi0, spi0_quad, spi1, spi2, spi3, spi4, spi5, spi6_0,
99
+
spi6_1, spi7_0, spi7_1, spi8_0, spi8_1,
100
+
aaud_0, aaud_1, aaud_2, aaud_3, aaud_4,
101
+
vbus0_0, vbus0_1, vbus1, vbus2, vbus3,
102
+
mic_0, mic_1, mic_2, mic_3,
103
+
ir ]
78
104
79
105
function:
80
106
enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none,
···
128
102
enum: [ 0, 1 ]
129
103
drive-strength:
130
104
enum: [ 2, 4, 8, 12 ]
105
+
106
+
required:
107
+
- function
108
+
109
+
oneOf:
110
+
- required: [ groups ]
111
+
- required: [ pins ]
131
112
132
113
additionalProperties: false
133
114
+172
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
+172
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
8
+
9
+
maintainers:
10
+
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
+
12
+
description:
13
+
The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
14
+
Pin multiplexing and GPIO configuration are performed on a per-pin basis.
15
+
Each port supports up to 8 pins, each configurable for either GPIO (port mode)
16
+
or alternate function mode. Each pin supports function mode values ranging from
17
+
0x0 to 0x2A, allowing selection from up to 43 different functions.
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- renesas,r9a09g077-pinctrl # RZ/T2H
23
+
- renesas,r9a09g087-pinctrl # RZ/N2H
24
+
25
+
reg:
26
+
minItems: 1
27
+
items:
28
+
- description: Non-safety I/O Port base
29
+
- description: Safety I/O Port safety region base
30
+
- description: Safety I/O Port Non-safety region base
31
+
32
+
reg-names:
33
+
minItems: 1
34
+
items:
35
+
- const: nsr
36
+
- const: srs
37
+
- const: srn
38
+
39
+
gpio-controller: true
40
+
41
+
'#gpio-cells':
42
+
const: 2
43
+
description:
44
+
The first cell contains the global GPIO port index, constructed using the
45
+
RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
46
+
(e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
47
+
flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
48
+
49
+
gpio-ranges:
50
+
maxItems: 1
51
+
52
+
clocks:
53
+
maxItems: 1
54
+
55
+
power-domains:
56
+
maxItems: 1
57
+
58
+
definitions:
59
+
renesas-rzt2h-n2h-pins-node:
60
+
type: object
61
+
allOf:
62
+
- $ref: pincfg-node.yaml#
63
+
- $ref: pinmux-node.yaml#
64
+
properties:
65
+
pinmux:
66
+
description:
67
+
Values are constructed from I/O port number, pin number, and
68
+
alternate function configuration number using the RZT2H_PORT_PINMUX()
69
+
helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
70
+
pins: true
71
+
phandle: true
72
+
input: true
73
+
input-enable: true
74
+
output-enable: true
75
+
oneOf:
76
+
- required: [pinmux]
77
+
- required: [pins]
78
+
additionalProperties: false
79
+
80
+
patternProperties:
81
+
# Grouping nodes: allow multiple "-pins" subnodes within a "-group"
82
+
'.*-group$':
83
+
type: object
84
+
description:
85
+
Pin controller client devices can organize pin configuration entries into
86
+
grouping nodes ending in "-group". These group nodes may contain multiple
87
+
child nodes each ending in "-pins" to configure distinct sets of pins.
88
+
additionalProperties: false
89
+
patternProperties:
90
+
'-pins$':
91
+
$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
92
+
93
+
# Standalone "-pins" nodes under client devices or groups
94
+
'-pins$':
95
+
$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
96
+
97
+
'-hog$':
98
+
type: object
99
+
description: GPIO hog node
100
+
properties:
101
+
gpio-hog: true
102
+
gpios: true
103
+
input: true
104
+
output-high: true
105
+
output-low: true
106
+
line-name: true
107
+
required:
108
+
- gpio-hog
109
+
- gpios
110
+
additionalProperties: false
111
+
112
+
allOf:
113
+
- $ref: pinctrl.yaml#
114
+
115
+
required:
116
+
- compatible
117
+
- reg
118
+
- reg-names
119
+
- gpio-controller
120
+
- '#gpio-cells'
121
+
- gpio-ranges
122
+
- clocks
123
+
- power-domains
124
+
125
+
unevaluatedProperties: false
126
+
127
+
examples:
128
+
- |
129
+
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
130
+
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
131
+
132
+
pinctrl@802c0000 {
133
+
compatible = "renesas,r9a09g077-pinctrl";
134
+
reg = <0x802c0000 0x2000>,
135
+
<0x812c0000 0x2000>,
136
+
<0x802b0000 0x2000>;
137
+
reg-names = "nsr", "srs", "srn";
138
+
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
139
+
gpio-controller;
140
+
#gpio-cells = <2>;
141
+
gpio-ranges = <&pinctrl 0 0 288>;
142
+
power-domains = <&cpg>;
143
+
144
+
serial0-pins {
145
+
pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
146
+
<RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
147
+
};
148
+
149
+
sd1-pwr-en-hog {
150
+
gpio-hog;
151
+
gpios = <RZT2H_GPIO(39, 2) 0>;
152
+
output-high;
153
+
line-name = "sd1_pwr_en";
154
+
};
155
+
156
+
i2c0-pins {
157
+
pins = "RIIC0_SDA", "RIIC0_SCL";
158
+
input-enable;
159
+
};
160
+
161
+
sd0-sd-group {
162
+
ctrl-pins {
163
+
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
164
+
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
165
+
};
166
+
167
+
data-pins {
168
+
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
169
+
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
170
+
};
171
+
};
172
+
};
+1
-18
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+1
-18
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
···
30
30
compatible:
31
31
oneOf:
32
32
- enum:
33
-
- samsung,s3c2410-wakeup-eint
34
-
- samsung,s3c2412-wakeup-eint
35
33
- samsung,s3c64xx-wakeup-eint
36
34
- samsung,s5pv210-wakeup-eint
37
35
- samsung,exynos4210-wakeup-eint
···
57
59
description:
58
60
Interrupt used by multiplexed external wake-up interrupts.
59
61
minItems: 1
60
-
maxItems: 6
62
+
maxItems: 4
61
63
62
64
required:
63
65
- compatible
64
66
65
67
allOf:
66
-
- if:
67
-
properties:
68
-
compatible:
69
-
contains:
70
-
enum:
71
-
- samsung,s3c2410-wakeup-eint
72
-
- samsung,s3c2412-wakeup-eint
73
-
then:
74
-
properties:
75
-
interrupts:
76
-
minItems: 6
77
-
maxItems: 6
78
-
required:
79
-
- interrupts
80
-
81
68
- if:
82
69
properties:
83
70
compatible:
+1
-4
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+1
-4
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
···
35
35
36
36
compatible:
37
37
enum:
38
+
- axis,artpec8-pinctrl
38
39
- google,gs101-pinctrl
39
-
- samsung,s3c2412-pinctrl
40
-
- samsung,s3c2416-pinctrl
41
-
- samsung,s3c2440-pinctrl
42
-
- samsung,s3c2450-pinctrl
43
40
- samsung,s3c64xx-pinctrl
44
41
- samsung,s5pv210-pinctrl
45
42
- samsung,exynos2200-pinctrl
+2
-2
Documentation/driver-api/pin-control.rst
+2
-2
Documentation/driver-api/pin-control.rst
···
863
863
a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
864
864
and you find this in the documentation:
865
865
866
-
PIN_CONFIG_OUTPUT:
866
+
PIN_CONFIG_LEVEL:
867
867
this will configure the pin in output, use argument
868
868
1 to indicate high level, argument 0 to indicate low level.
869
869
···
897
897
};
898
898
899
899
static unsigned long uart_sleep_mode[] = {
900
-
PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
900
+
PIN_CONF_PACKED(PIN_CONFIG_LEVEL, 0),
901
901
};
902
902
903
903
static struct pinctrl_map pinmap[] __initdata = {
+21
drivers/base/devres.c
+21
drivers/base/devres.c
···
1117
1117
}
1118
1118
EXPORT_SYMBOL_GPL(devm_kmemdup);
1119
1119
1120
+
/**
1121
+
* devm_kmemdup_const - conditionally duplicate and manage a region of memory
1122
+
*
1123
+
* @dev: Device this memory belongs to
1124
+
* @src: memory region to duplicate
1125
+
* @len: memory region length,
1126
+
* @gfp: GFP mask to use
1127
+
*
1128
+
* Return: source address if it is in .rodata or the return value of kmemdup()
1129
+
* to which the function falls back otherwise.
1130
+
*/
1131
+
const void *
1132
+
devm_kmemdup_const(struct device *dev, const void *src, size_t len, gfp_t gfp)
1133
+
{
1134
+
if (is_kernel_rodata((unsigned long)src))
1135
+
return src;
1136
+
1137
+
return devm_kmemdup(dev, src, len, gfp);
1138
+
}
1139
+
EXPORT_SYMBOL_GPL(devm_kmemdup_const);
1140
+
1120
1141
struct pages_devres {
1121
1142
unsigned long addr;
1122
1143
unsigned int order;
+1
-1
drivers/gpio/gpio-rockchip.c
+1
-1
drivers/gpio/gpio-rockchip.c
···
769
769
list_del(&cfg->head);
770
770
771
771
switch (cfg->param) {
772
-
case PIN_CONFIG_OUTPUT:
772
+
case PIN_CONFIG_LEVEL:
773
773
ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
774
774
if (ret)
775
775
dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
+22
-1
drivers/pinctrl/Kconfig
+22
-1
drivers/pinctrl/Kconfig
···
211
211
depends on ARCH_ESWIN || COMPILE_TEST
212
212
select PINMUX
213
213
select GENERIC_PINCONF
214
+
select REGULATOR
215
+
select REGULATOR_FIXED_VOLTAGE
214
216
help
215
217
This driver support for the pin controller in ESWIN's EIC7700 SoC,
216
218
which supports pin multiplexing, pin configuration,and rgmii voltage
···
564
562
interrupt-controller.
565
563
566
564
config PINCTRL_SX150X
567
-
bool "Semtech SX150x I2C GPIO expander pinctrl driver"
565
+
tristate "Semtech SX150x I2C GPIO expander pinctrl driver"
568
566
depends on I2C=y
569
567
select PINMUX
570
568
select PINCONF
···
613
611
614
612
This driver is needed for RISC-V development boards like
615
613
the BeagleV Ahead and the LicheePi 4A.
614
+
615
+
config PINCTRL_UPBOARD
616
+
tristate "AAeon UP board FPGA pin controller"
617
+
depends on MFD_UPBOARD_FPGA
618
+
select PINMUX
619
+
select GENERIC_PINCTRL_GROUPS
620
+
select GENERIC_PINMUX_FUNCTIONS
621
+
select GPIOLIB
622
+
select GPIO_AGGREGATOR
623
+
help
624
+
Pin controller for the FPGA GPIO lines on UP boards. Due to the
625
+
hardware layout, the driver controls the FPGA pins in tandem with
626
+
their corresponding Intel SoC GPIOs.
627
+
628
+
Currently supported:
629
+
- UP Squared
630
+
631
+
To compile this driver as a module, choose M here: the module
632
+
will be called pinctrl-upboard.
616
633
617
634
config PINCTRL_ZYNQ
618
635
bool "Pinctrl driver for Xilinx Zynq"
+1
drivers/pinctrl/Makefile
+1
drivers/pinctrl/Makefile
···
60
60
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
61
61
obj-$(CONFIG_PINCTRL_TPS6594) += pinctrl-tps6594.o
62
62
obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o
63
+
obj-$(CONFIG_PINCTRL_UPBOARD) += pinctrl-upboard.o
63
64
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
64
65
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
65
66
+12
drivers/pinctrl/bcm/Kconfig
+12
drivers/pinctrl/bcm/Kconfig
···
106
106
help
107
107
Say Y here to enable the Broadcom BCM63268 GPIO driver.
108
108
109
+
config PINCTRL_BRCMSTB
110
+
tristate "Broadcom STB product line pin controller driver"
111
+
depends on OF && (ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST)
112
+
select PINMUX
113
+
select PINCONF
114
+
select GENERIC_PINCONF
115
+
help
116
+
Enable pin muxing and configuration functionality
117
+
for Broadcom STB product line chipsets.
118
+
119
+
source "drivers/pinctrl/bcm/Kconfig.stb"
120
+
109
121
config PINCTRL_IPROC_GPIO
110
122
bool "Broadcom iProc GPIO (with PINCONF) driver"
111
123
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
+10
drivers/pinctrl/bcm/Kconfig.stb
+10
drivers/pinctrl/bcm/Kconfig.stb
+2
drivers/pinctrl/bcm/Makefile
+2
drivers/pinctrl/bcm/Makefile
···
11
11
obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
12
12
obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
13
13
obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o
14
+
obj-$(CONFIG_PINCTRL_BRCMSTB) += pinctrl-brcmstb.o
15
+
obj-$(CONFIG_PINCTRL_BCM2712) += pinctrl-brcmstb-bcm2712.o
14
16
obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
15
17
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
16
18
obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
+3
-3
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+3
-3
drivers/pinctrl/bcm/pinctrl-bcm2835.c
···
1023
1023
/* No way to read back bias config in HW */
1024
1024
1025
1025
switch (param) {
1026
-
case PIN_CONFIG_OUTPUT:
1026
+
case PIN_CONFIG_LEVEL:
1027
1027
if (fsel != BCM2835_FSEL_GPIO_OUT)
1028
1028
return -EINVAL;
1029
1029
···
1091
1091
break;
1092
1092
1093
1093
/* Set output-high or output-low */
1094
-
case PIN_CONFIG_OUTPUT:
1094
+
case PIN_CONFIG_LEVEL:
1095
1095
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1096
1096
break;
1097
1097
···
1202
1202
break;
1203
1203
1204
1204
/* Set output-high or output-low */
1205
-
case PIN_CONFIG_OUTPUT:
1205
+
case PIN_CONFIG_LEVEL:
1206
1206
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1207
1207
break;
1208
1208
+1
-3
drivers/pinctrl/bcm/pinctrl-bcm6358.c
+1
-3
drivers/pinctrl/bcm/pinctrl-bcm6358.c
···
343
343
pc = platform_get_drvdata(pdev);
344
344
345
345
priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);
346
-
if (IS_ERR(priv->overlays))
347
-
return PTR_ERR(priv->overlays);
348
346
349
-
return 0;
347
+
return PTR_ERR_OR_ZERO(priv->overlays);
350
348
}
351
349
352
350
static const struct of_device_id bcm6358_pinctrl_match[] = {
+747
drivers/pinctrl/bcm/pinctrl-brcmstb-bcm2712.c
+747
drivers/pinctrl/bcm/pinctrl-brcmstb-bcm2712.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Driver for Broadcom brcmstb GPIO units (pinctrl only)
4
+
*
5
+
* Copyright (C) 2024-2025 Ivan T. Ivanov, Andrea della Porta
6
+
* Copyright (C) 2021-3 Raspberry Pi Ltd.
7
+
* Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
8
+
*
9
+
* Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
10
+
* pinctrl-nomadik.c, please see original file for copyright information
11
+
* pinctrl-tegra.c, please see original file for copyright information
12
+
*/
13
+
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/of.h>
16
+
#include "pinctrl-brcmstb.h"
17
+
18
+
#define BRCMSTB_FSEL_COUNT 8
19
+
#define BRCMSTB_FSEL_MASK 0xf
20
+
21
+
#define BRCMSTB_PIN(i, f1, f2, f3, f4, f5, f6, f7, f8) \
22
+
[i] = { \
23
+
.funcs = (u8[]) { \
24
+
func_##f1, \
25
+
func_##f2, \
26
+
func_##f3, \
27
+
func_##f4, \
28
+
func_##f5, \
29
+
func_##f6, \
30
+
func_##f7, \
31
+
func_##f8, \
32
+
}, \
33
+
.n_funcs = BRCMSTB_FSEL_COUNT, \
34
+
.func_mask = BRCMSTB_FSEL_MASK, \
35
+
}
36
+
37
+
enum bcm2712_funcs {
38
+
func_gpio,
39
+
func_alt1,
40
+
func_alt2,
41
+
func_alt3,
42
+
func_alt4,
43
+
func_alt5,
44
+
func_alt6,
45
+
func_alt7,
46
+
func_alt8,
47
+
func_aon_cpu_standbyb,
48
+
func_aon_fp_4sec_resetb,
49
+
func_aon_gpclk,
50
+
func_aon_pwm,
51
+
func_arm_jtag,
52
+
func_aud_fs_clk0,
53
+
func_avs_pmu_bsc,
54
+
func_bsc_m0,
55
+
func_bsc_m1,
56
+
func_bsc_m2,
57
+
func_bsc_m3,
58
+
func_clk_observe,
59
+
func_ctl_hdmi_5v,
60
+
func_enet0,
61
+
func_enet0_mii,
62
+
func_enet0_rgmii,
63
+
func_ext_sc_clk,
64
+
func_fl0,
65
+
func_fl1,
66
+
func_gpclk0,
67
+
func_gpclk1,
68
+
func_gpclk2,
69
+
func_hdmi_tx0_auto_i2c,
70
+
func_hdmi_tx0_bsc,
71
+
func_hdmi_tx1_auto_i2c,
72
+
func_hdmi_tx1_bsc,
73
+
func_i2s_in,
74
+
func_i2s_out,
75
+
func_ir_in,
76
+
func_mtsif,
77
+
func_mtsif_alt,
78
+
func_mtsif_alt1,
79
+
func_pdm,
80
+
func_pkt,
81
+
func_pm_led_out,
82
+
func_sc0,
83
+
func_sd0,
84
+
func_sd2,
85
+
func_sd_card_a,
86
+
func_sd_card_b,
87
+
func_sd_card_c,
88
+
func_sd_card_d,
89
+
func_sd_card_e,
90
+
func_sd_card_f,
91
+
func_sd_card_g,
92
+
func_spdif_out,
93
+
func_spi_m,
94
+
func_spi_s,
95
+
func_sr_edm_sense,
96
+
func_te0,
97
+
func_te1,
98
+
func_tsio,
99
+
func_uart0,
100
+
func_uart1,
101
+
func_uart2,
102
+
func_usb_pwr,
103
+
func_usb_vbus,
104
+
func_uui,
105
+
func_vc_i2c0,
106
+
func_vc_i2c3,
107
+
func_vc_i2c4,
108
+
func_vc_i2c5,
109
+
func_vc_i2csl,
110
+
func_vc_pcm,
111
+
func_vc_pwm0,
112
+
func_vc_pwm1,
113
+
func_vc_spi0,
114
+
func_vc_spi3,
115
+
func_vc_spi4,
116
+
func_vc_spi5,
117
+
func_vc_uart0,
118
+
func_vc_uart2,
119
+
func_vc_uart3,
120
+
func_vc_uart4,
121
+
func__,
122
+
func_count = func__
123
+
};
124
+
125
+
static const struct pin_regs bcm2712_c0_gpio_pin_regs[] = {
126
+
GPIO_REGS(0, 0, 0, 7, 7),
127
+
GPIO_REGS(1, 0, 1, 7, 8),
128
+
GPIO_REGS(2, 0, 2, 7, 9),
129
+
GPIO_REGS(3, 0, 3, 7, 10),
130
+
GPIO_REGS(4, 0, 4, 7, 11),
131
+
GPIO_REGS(5, 0, 5, 7, 12),
132
+
GPIO_REGS(6, 0, 6, 7, 13),
133
+
GPIO_REGS(7, 0, 7, 7, 14),
134
+
GPIO_REGS(8, 1, 0, 8, 0),
135
+
GPIO_REGS(9, 1, 1, 8, 1),
136
+
GPIO_REGS(10, 1, 2, 8, 2),
137
+
GPIO_REGS(11, 1, 3, 8, 3),
138
+
GPIO_REGS(12, 1, 4, 8, 4),
139
+
GPIO_REGS(13, 1, 5, 8, 5),
140
+
GPIO_REGS(14, 1, 6, 8, 6),
141
+
GPIO_REGS(15, 1, 7, 8, 7),
142
+
GPIO_REGS(16, 2, 0, 8, 8),
143
+
GPIO_REGS(17, 2, 1, 8, 9),
144
+
GPIO_REGS(18, 2, 2, 8, 10),
145
+
GPIO_REGS(19, 2, 3, 8, 11),
146
+
GPIO_REGS(20, 2, 4, 8, 12),
147
+
GPIO_REGS(21, 2, 5, 8, 13),
148
+
GPIO_REGS(22, 2, 6, 8, 14),
149
+
GPIO_REGS(23, 2, 7, 9, 0),
150
+
GPIO_REGS(24, 3, 0, 9, 1),
151
+
GPIO_REGS(25, 3, 1, 9, 2),
152
+
GPIO_REGS(26, 3, 2, 9, 3),
153
+
GPIO_REGS(27, 3, 3, 9, 4),
154
+
GPIO_REGS(28, 3, 4, 9, 5),
155
+
GPIO_REGS(29, 3, 5, 9, 6),
156
+
GPIO_REGS(30, 3, 6, 9, 7),
157
+
GPIO_REGS(31, 3, 7, 9, 8),
158
+
GPIO_REGS(32, 4, 0, 9, 9),
159
+
GPIO_REGS(33, 4, 1, 9, 10),
160
+
GPIO_REGS(34, 4, 2, 9, 11),
161
+
GPIO_REGS(35, 4, 3, 9, 12),
162
+
GPIO_REGS(36, 4, 4, 9, 13),
163
+
GPIO_REGS(37, 4, 5, 9, 14),
164
+
GPIO_REGS(38, 4, 6, 10, 0),
165
+
GPIO_REGS(39, 4, 7, 10, 1),
166
+
GPIO_REGS(40, 5, 0, 10, 2),
167
+
GPIO_REGS(41, 5, 1, 10, 3),
168
+
GPIO_REGS(42, 5, 2, 10, 4),
169
+
GPIO_REGS(43, 5, 3, 10, 5),
170
+
GPIO_REGS(44, 5, 4, 10, 6),
171
+
GPIO_REGS(45, 5, 5, 10, 7),
172
+
GPIO_REGS(46, 5, 6, 10, 8),
173
+
GPIO_REGS(47, 5, 7, 10, 9),
174
+
GPIO_REGS(48, 6, 0, 10, 10),
175
+
GPIO_REGS(49, 6, 1, 10, 11),
176
+
GPIO_REGS(50, 6, 2, 10, 12),
177
+
GPIO_REGS(51, 6, 3, 10, 13),
178
+
GPIO_REGS(52, 6, 4, 10, 14),
179
+
GPIO_REGS(53, 6, 5, 11, 0),
180
+
EMMC_REGS(54, 11, 1), /* EMMC_CMD */
181
+
EMMC_REGS(55, 11, 2), /* EMMC_DS */
182
+
EMMC_REGS(56, 11, 3), /* EMMC_CLK */
183
+
EMMC_REGS(57, 11, 4), /* EMMC_DAT0 */
184
+
EMMC_REGS(58, 11, 5), /* EMMC_DAT1 */
185
+
EMMC_REGS(59, 11, 6), /* EMMC_DAT2 */
186
+
EMMC_REGS(60, 11, 7), /* EMMC_DAT3 */
187
+
EMMC_REGS(61, 11, 8), /* EMMC_DAT4 */
188
+
EMMC_REGS(62, 11, 9), /* EMMC_DAT5 */
189
+
EMMC_REGS(63, 11, 10), /* EMMC_DAT6 */
190
+
EMMC_REGS(64, 11, 11), /* EMMC_DAT7 */
191
+
};
192
+
193
+
static struct pin_regs bcm2712_c0_aon_gpio_pin_regs[] = {
194
+
AON_GPIO_REGS(0, 3, 0, 6, 10),
195
+
AON_GPIO_REGS(1, 3, 1, 6, 11),
196
+
AON_GPIO_REGS(2, 3, 2, 6, 12),
197
+
AON_GPIO_REGS(3, 3, 3, 6, 13),
198
+
AON_GPIO_REGS(4, 3, 4, 6, 14),
199
+
AON_GPIO_REGS(5, 3, 5, 7, 0),
200
+
AON_GPIO_REGS(6, 3, 6, 7, 1),
201
+
AON_GPIO_REGS(7, 3, 7, 7, 2),
202
+
AON_GPIO_REGS(8, 4, 0, 7, 3),
203
+
AON_GPIO_REGS(9, 4, 1, 7, 4),
204
+
AON_GPIO_REGS(10, 4, 2, 7, 5),
205
+
AON_GPIO_REGS(11, 4, 3, 7, 6),
206
+
AON_GPIO_REGS(12, 4, 4, 7, 7),
207
+
AON_GPIO_REGS(13, 4, 5, 7, 8),
208
+
AON_GPIO_REGS(14, 4, 6, 7, 9),
209
+
AON_GPIO_REGS(15, 4, 7, 7, 10),
210
+
AON_GPIO_REGS(16, 5, 0, 7, 11),
211
+
AON_SGPIO_REGS(0, 0, 0),
212
+
AON_SGPIO_REGS(1, 0, 1),
213
+
AON_SGPIO_REGS(2, 0, 2),
214
+
AON_SGPIO_REGS(3, 0, 3),
215
+
AON_SGPIO_REGS(4, 1, 0),
216
+
AON_SGPIO_REGS(5, 2, 0),
217
+
};
218
+
219
+
static const struct pinctrl_pin_desc bcm2712_c0_gpio_pins[] = {
220
+
GPIO_PIN(0),
221
+
GPIO_PIN(1),
222
+
GPIO_PIN(2),
223
+
GPIO_PIN(3),
224
+
GPIO_PIN(4),
225
+
GPIO_PIN(5),
226
+
GPIO_PIN(6),
227
+
GPIO_PIN(7),
228
+
GPIO_PIN(8),
229
+
GPIO_PIN(9),
230
+
GPIO_PIN(10),
231
+
GPIO_PIN(11),
232
+
GPIO_PIN(12),
233
+
GPIO_PIN(13),
234
+
GPIO_PIN(14),
235
+
GPIO_PIN(15),
236
+
GPIO_PIN(16),
237
+
GPIO_PIN(17),
238
+
GPIO_PIN(18),
239
+
GPIO_PIN(19),
240
+
GPIO_PIN(20),
241
+
GPIO_PIN(21),
242
+
GPIO_PIN(22),
243
+
GPIO_PIN(23),
244
+
GPIO_PIN(24),
245
+
GPIO_PIN(25),
246
+
GPIO_PIN(26),
247
+
GPIO_PIN(27),
248
+
GPIO_PIN(28),
249
+
GPIO_PIN(29),
250
+
GPIO_PIN(30),
251
+
GPIO_PIN(31),
252
+
GPIO_PIN(32),
253
+
GPIO_PIN(33),
254
+
GPIO_PIN(34),
255
+
GPIO_PIN(35),
256
+
GPIO_PIN(36),
257
+
GPIO_PIN(37),
258
+
GPIO_PIN(38),
259
+
GPIO_PIN(39),
260
+
GPIO_PIN(40),
261
+
GPIO_PIN(41),
262
+
GPIO_PIN(42),
263
+
GPIO_PIN(43),
264
+
GPIO_PIN(44),
265
+
GPIO_PIN(45),
266
+
GPIO_PIN(46),
267
+
GPIO_PIN(47),
268
+
GPIO_PIN(48),
269
+
GPIO_PIN(49),
270
+
GPIO_PIN(50),
271
+
GPIO_PIN(51),
272
+
GPIO_PIN(52),
273
+
GPIO_PIN(53),
274
+
PINCTRL_PIN(54, "emmc_cmd"),
275
+
PINCTRL_PIN(55, "emmc_ds"),
276
+
PINCTRL_PIN(56, "emmc_clk"),
277
+
PINCTRL_PIN(57, "emmc_dat0"),
278
+
PINCTRL_PIN(58, "emmc_dat1"),
279
+
PINCTRL_PIN(59, "emmc_dat2"),
280
+
PINCTRL_PIN(60, "emmc_dat3"),
281
+
PINCTRL_PIN(61, "emmc_dat4"),
282
+
PINCTRL_PIN(62, "emmc_dat5"),
283
+
PINCTRL_PIN(63, "emmc_dat6"),
284
+
PINCTRL_PIN(64, "emmc_dat7"),
285
+
};
286
+
287
+
static struct pinctrl_pin_desc bcm2712_c0_aon_gpio_pins[] = {
288
+
AON_GPIO_PIN(0), AON_GPIO_PIN(1), AON_GPIO_PIN(2), AON_GPIO_PIN(3),
289
+
AON_GPIO_PIN(4), AON_GPIO_PIN(5), AON_GPIO_PIN(6), AON_GPIO_PIN(7),
290
+
AON_GPIO_PIN(8), AON_GPIO_PIN(9), AON_GPIO_PIN(10), AON_GPIO_PIN(11),
291
+
AON_GPIO_PIN(12), AON_GPIO_PIN(13), AON_GPIO_PIN(14), AON_GPIO_PIN(15),
292
+
AON_GPIO_PIN(16), AON_SGPIO_PIN(0), AON_SGPIO_PIN(1), AON_SGPIO_PIN(2),
293
+
AON_SGPIO_PIN(3), AON_SGPIO_PIN(4), AON_SGPIO_PIN(5),
294
+
};
295
+
296
+
static const struct pin_regs bcm2712_d0_gpio_pin_regs[] = {
297
+
GPIO_REGS(1, 0, 0, 4, 5),
298
+
GPIO_REGS(2, 0, 1, 4, 6),
299
+
GPIO_REGS(3, 0, 2, 4, 7),
300
+
GPIO_REGS(4, 0, 3, 4, 8),
301
+
GPIO_REGS(10, 0, 4, 4, 9),
302
+
GPIO_REGS(11, 0, 5, 4, 10),
303
+
GPIO_REGS(12, 0, 6, 4, 11),
304
+
GPIO_REGS(13, 0, 7, 4, 12),
305
+
GPIO_REGS(14, 1, 0, 4, 13),
306
+
GPIO_REGS(15, 1, 1, 4, 14),
307
+
GPIO_REGS(18, 1, 2, 5, 0),
308
+
GPIO_REGS(19, 1, 3, 5, 1),
309
+
GPIO_REGS(20, 1, 4, 5, 2),
310
+
GPIO_REGS(21, 1, 5, 5, 3),
311
+
GPIO_REGS(22, 1, 6, 5, 4),
312
+
GPIO_REGS(23, 1, 7, 5, 5),
313
+
GPIO_REGS(24, 2, 0, 5, 6),
314
+
GPIO_REGS(25, 2, 1, 5, 7),
315
+
GPIO_REGS(26, 2, 2, 5, 8),
316
+
GPIO_REGS(27, 2, 3, 5, 9),
317
+
GPIO_REGS(28, 2, 4, 5, 10),
318
+
GPIO_REGS(29, 2, 5, 5, 11),
319
+
GPIO_REGS(30, 2, 6, 5, 12),
320
+
GPIO_REGS(31, 2, 7, 5, 13),
321
+
GPIO_REGS(32, 3, 0, 5, 14),
322
+
GPIO_REGS(33, 3, 1, 6, 0),
323
+
GPIO_REGS(34, 3, 2, 6, 1),
324
+
GPIO_REGS(35, 3, 3, 6, 2),
325
+
EMMC_REGS(36, 6, 3), /* EMMC_CMD */
326
+
EMMC_REGS(37, 6, 4), /* EMMC_DS */
327
+
EMMC_REGS(38, 6, 5), /* EMMC_CLK */
328
+
EMMC_REGS(39, 6, 6), /* EMMC_DAT0 */
329
+
EMMC_REGS(40, 6, 7), /* EMMC_DAT1 */
330
+
EMMC_REGS(41, 6, 8), /* EMMC_DAT2 */
331
+
EMMC_REGS(42, 6, 9), /* EMMC_DAT3 */
332
+
EMMC_REGS(43, 6, 10), /* EMMC_DAT4 */
333
+
EMMC_REGS(44, 6, 11), /* EMMC_DAT5 */
334
+
EMMC_REGS(45, 6, 12), /* EMMC_DAT6 */
335
+
EMMC_REGS(46, 6, 13), /* EMMC_DAT7 */
336
+
};
337
+
338
+
static struct pin_regs bcm2712_d0_aon_gpio_pin_regs[] = {
339
+
AON_GPIO_REGS(0, 3, 0, 5, 9),
340
+
AON_GPIO_REGS(1, 3, 1, 5, 10),
341
+
AON_GPIO_REGS(2, 3, 2, 5, 11),
342
+
AON_GPIO_REGS(3, 3, 3, 5, 12),
343
+
AON_GPIO_REGS(4, 3, 4, 5, 13),
344
+
AON_GPIO_REGS(5, 3, 5, 5, 14),
345
+
AON_GPIO_REGS(6, 3, 6, 6, 0),
346
+
AON_GPIO_REGS(8, 3, 7, 6, 1),
347
+
AON_GPIO_REGS(9, 4, 0, 6, 2),
348
+
AON_GPIO_REGS(12, 4, 1, 6, 3),
349
+
AON_GPIO_REGS(13, 4, 2, 6, 4),
350
+
AON_GPIO_REGS(14, 4, 3, 6, 5),
351
+
AON_SGPIO_REGS(0, 0, 0),
352
+
AON_SGPIO_REGS(1, 0, 1),
353
+
AON_SGPIO_REGS(2, 0, 2),
354
+
AON_SGPIO_REGS(3, 0, 3),
355
+
AON_SGPIO_REGS(4, 1, 0),
356
+
AON_SGPIO_REGS(5, 2, 0),
357
+
};
358
+
359
+
static const struct pinctrl_pin_desc bcm2712_d0_gpio_pins[] = {
360
+
GPIO_PIN(1),
361
+
GPIO_PIN(2),
362
+
GPIO_PIN(3),
363
+
GPIO_PIN(4),
364
+
GPIO_PIN(10),
365
+
GPIO_PIN(11),
366
+
GPIO_PIN(12),
367
+
GPIO_PIN(13),
368
+
GPIO_PIN(14),
369
+
GPIO_PIN(15),
370
+
GPIO_PIN(18),
371
+
GPIO_PIN(19),
372
+
GPIO_PIN(20),
373
+
GPIO_PIN(21),
374
+
GPIO_PIN(22),
375
+
GPIO_PIN(23),
376
+
GPIO_PIN(24),
377
+
GPIO_PIN(25),
378
+
GPIO_PIN(26),
379
+
GPIO_PIN(27),
380
+
GPIO_PIN(28),
381
+
GPIO_PIN(29),
382
+
GPIO_PIN(30),
383
+
GPIO_PIN(31),
384
+
GPIO_PIN(32),
385
+
GPIO_PIN(33),
386
+
GPIO_PIN(34),
387
+
GPIO_PIN(35),
388
+
PINCTRL_PIN(36, "emmc_cmd"),
389
+
PINCTRL_PIN(37, "emmc_ds"),
390
+
PINCTRL_PIN(38, "emmc_clk"),
391
+
PINCTRL_PIN(39, "emmc_dat0"),
392
+
PINCTRL_PIN(40, "emmc_dat1"),
393
+
PINCTRL_PIN(41, "emmc_dat2"),
394
+
PINCTRL_PIN(42, "emmc_dat3"),
395
+
PINCTRL_PIN(43, "emmc_dat4"),
396
+
PINCTRL_PIN(44, "emmc_dat5"),
397
+
PINCTRL_PIN(45, "emmc_dat6"),
398
+
PINCTRL_PIN(46, "emmc_dat7"),
399
+
};
400
+
401
+
static struct pinctrl_pin_desc bcm2712_d0_aon_gpio_pins[] = {
402
+
AON_GPIO_PIN(0), AON_GPIO_PIN(1), AON_GPIO_PIN(2), AON_GPIO_PIN(3),
403
+
AON_GPIO_PIN(4), AON_GPIO_PIN(5), AON_GPIO_PIN(6), AON_GPIO_PIN(8),
404
+
AON_GPIO_PIN(9), AON_GPIO_PIN(12), AON_GPIO_PIN(13), AON_GPIO_PIN(14),
405
+
AON_SGPIO_PIN(0), AON_SGPIO_PIN(1), AON_SGPIO_PIN(2),
406
+
AON_SGPIO_PIN(3), AON_SGPIO_PIN(4), AON_SGPIO_PIN(5),
407
+
};
408
+
409
+
static const char * const bcm2712_func_names[] = {
410
+
BRCMSTB_FUNC(gpio),
411
+
BRCMSTB_FUNC(alt1),
412
+
BRCMSTB_FUNC(alt2),
413
+
BRCMSTB_FUNC(alt3),
414
+
BRCMSTB_FUNC(alt4),
415
+
BRCMSTB_FUNC(alt5),
416
+
BRCMSTB_FUNC(alt6),
417
+
BRCMSTB_FUNC(alt7),
418
+
BRCMSTB_FUNC(alt8),
419
+
BRCMSTB_FUNC(aon_cpu_standbyb),
420
+
BRCMSTB_FUNC(aon_fp_4sec_resetb),
421
+
BRCMSTB_FUNC(aon_gpclk),
422
+
BRCMSTB_FUNC(aon_pwm),
423
+
BRCMSTB_FUNC(arm_jtag),
424
+
BRCMSTB_FUNC(aud_fs_clk0),
425
+
BRCMSTB_FUNC(avs_pmu_bsc),
426
+
BRCMSTB_FUNC(bsc_m0),
427
+
BRCMSTB_FUNC(bsc_m1),
428
+
BRCMSTB_FUNC(bsc_m2),
429
+
BRCMSTB_FUNC(bsc_m3),
430
+
BRCMSTB_FUNC(clk_observe),
431
+
BRCMSTB_FUNC(ctl_hdmi_5v),
432
+
BRCMSTB_FUNC(enet0),
433
+
BRCMSTB_FUNC(enet0_mii),
434
+
BRCMSTB_FUNC(enet0_rgmii),
435
+
BRCMSTB_FUNC(ext_sc_clk),
436
+
BRCMSTB_FUNC(fl0),
437
+
BRCMSTB_FUNC(fl1),
438
+
BRCMSTB_FUNC(gpclk0),
439
+
BRCMSTB_FUNC(gpclk1),
440
+
BRCMSTB_FUNC(gpclk2),
441
+
BRCMSTB_FUNC(hdmi_tx0_auto_i2c),
442
+
BRCMSTB_FUNC(hdmi_tx0_bsc),
443
+
BRCMSTB_FUNC(hdmi_tx1_auto_i2c),
444
+
BRCMSTB_FUNC(hdmi_tx1_bsc),
445
+
BRCMSTB_FUNC(i2s_in),
446
+
BRCMSTB_FUNC(i2s_out),
447
+
BRCMSTB_FUNC(ir_in),
448
+
BRCMSTB_FUNC(mtsif),
449
+
BRCMSTB_FUNC(mtsif_alt),
450
+
BRCMSTB_FUNC(mtsif_alt1),
451
+
BRCMSTB_FUNC(pdm),
452
+
BRCMSTB_FUNC(pkt),
453
+
BRCMSTB_FUNC(pm_led_out),
454
+
BRCMSTB_FUNC(sc0),
455
+
BRCMSTB_FUNC(sd0),
456
+
BRCMSTB_FUNC(sd2),
457
+
BRCMSTB_FUNC(sd_card_a),
458
+
BRCMSTB_FUNC(sd_card_b),
459
+
BRCMSTB_FUNC(sd_card_c),
460
+
BRCMSTB_FUNC(sd_card_d),
461
+
BRCMSTB_FUNC(sd_card_e),
462
+
BRCMSTB_FUNC(sd_card_f),
463
+
BRCMSTB_FUNC(sd_card_g),
464
+
BRCMSTB_FUNC(spdif_out),
465
+
BRCMSTB_FUNC(spi_m),
466
+
BRCMSTB_FUNC(spi_s),
467
+
BRCMSTB_FUNC(sr_edm_sense),
468
+
BRCMSTB_FUNC(te0),
469
+
BRCMSTB_FUNC(te1),
470
+
BRCMSTB_FUNC(tsio),
471
+
BRCMSTB_FUNC(uart0),
472
+
BRCMSTB_FUNC(uart1),
473
+
BRCMSTB_FUNC(uart2),
474
+
BRCMSTB_FUNC(usb_pwr),
475
+
BRCMSTB_FUNC(usb_vbus),
476
+
BRCMSTB_FUNC(uui),
477
+
BRCMSTB_FUNC(vc_i2c0),
478
+
BRCMSTB_FUNC(vc_i2c3),
479
+
BRCMSTB_FUNC(vc_i2c4),
480
+
BRCMSTB_FUNC(vc_i2c5),
481
+
BRCMSTB_FUNC(vc_i2csl),
482
+
BRCMSTB_FUNC(vc_pcm),
483
+
BRCMSTB_FUNC(vc_pwm0),
484
+
BRCMSTB_FUNC(vc_pwm1),
485
+
BRCMSTB_FUNC(vc_spi0),
486
+
BRCMSTB_FUNC(vc_spi3),
487
+
BRCMSTB_FUNC(vc_spi4),
488
+
BRCMSTB_FUNC(vc_spi5),
489
+
BRCMSTB_FUNC(vc_uart0),
490
+
BRCMSTB_FUNC(vc_uart2),
491
+
BRCMSTB_FUNC(vc_uart3),
492
+
BRCMSTB_FUNC(vc_uart4),
493
+
};
494
+
495
+
static const struct brcmstb_pin_funcs bcm2712_c0_aon_gpio_pin_funcs[] = {
496
+
BRCMSTB_PIN(0, ir_in, vc_spi0, vc_uart3, vc_i2c3, te0, vc_i2c0, _, _),
497
+
BRCMSTB_PIN(1, vc_pwm0, vc_spi0, vc_uart3, vc_i2c3, te1, aon_pwm, vc_i2c0, vc_pwm1),
498
+
BRCMSTB_PIN(2, vc_pwm0, vc_spi0, vc_uart3, ctl_hdmi_5v, fl0, aon_pwm, ir_in, vc_pwm1),
499
+
BRCMSTB_PIN(3, ir_in, vc_spi0, vc_uart3, aon_fp_4sec_resetb, fl1, sd_card_g, aon_gpclk, _),
500
+
BRCMSTB_PIN(4, gpclk0, vc_spi0, vc_i2csl, aon_gpclk, pm_led_out, aon_pwm, sd_card_g, vc_pwm0),
501
+
BRCMSTB_PIN(5, gpclk1, ir_in, vc_i2csl, clk_observe, aon_pwm, sd_card_g, vc_pwm0, _),
502
+
BRCMSTB_PIN(6, uart1, vc_uart4, gpclk2, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
503
+
BRCMSTB_PIN(7, uart1, vc_uart4, gpclk0, aon_pwm, vc_uart0, vc_spi3, _, _),
504
+
BRCMSTB_PIN(8, uart1, vc_uart4, vc_i2csl, ctl_hdmi_5v, vc_uart0, vc_spi3, _, _),
505
+
BRCMSTB_PIN(9, uart1, vc_uart4, vc_i2csl, aon_pwm, vc_uart0, vc_spi3, _, _),
506
+
BRCMSTB_PIN(10, tsio, ctl_hdmi_5v, sc0, spdif_out, vc_spi5, usb_pwr, aon_gpclk, sd_card_f),
507
+
BRCMSTB_PIN(11, tsio, uart0, sc0, aud_fs_clk0, vc_spi5, usb_vbus, vc_uart2, sd_card_f),
508
+
BRCMSTB_PIN(12, tsio, uart0, vc_uart0, tsio, vc_spi5, usb_pwr, vc_uart2, sd_card_f),
509
+
BRCMSTB_PIN(13, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
510
+
BRCMSTB_PIN(14, bsc_m1, uart0, vc_uart0, uui, vc_spi5, arm_jtag, vc_uart2, vc_i2c3),
511
+
BRCMSTB_PIN(15, ir_in, aon_fp_4sec_resetb, vc_uart0, pm_led_out, ctl_hdmi_5v, aon_pwm, aon_gpclk, _),
512
+
BRCMSTB_PIN(16, aon_cpu_standbyb, gpclk0, pm_led_out, ctl_hdmi_5v, vc_pwm0, usb_pwr, aud_fs_clk0, _),
513
+
};
514
+
515
+
static const struct brcmstb_pin_funcs bcm2712_c0_gpio_pin_funcs[] = {
516
+
BRCMSTB_PIN(0, bsc_m3, vc_i2c0, gpclk0, enet0, vc_pwm1, vc_spi0, ir_in, _),
517
+
BRCMSTB_PIN(1, bsc_m3, vc_i2c0, gpclk1, enet0, vc_pwm1, sr_edm_sense, vc_spi0, vc_uart3),
518
+
BRCMSTB_PIN(2, pdm, i2s_in, gpclk2, vc_spi4, pkt, vc_spi0, vc_uart3, _),
519
+
BRCMSTB_PIN(3, pdm, i2s_in, vc_spi4, pkt, vc_spi0, vc_uart3, _, _),
520
+
BRCMSTB_PIN(4, pdm, i2s_in, arm_jtag, vc_spi4, pkt, vc_spi0, vc_uart3, _),
521
+
BRCMSTB_PIN(5, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
522
+
BRCMSTB_PIN(6, pdm, vc_i2c3, arm_jtag, sd_card_e, vc_spi4, pkt, vc_pcm, vc_i2c5),
523
+
BRCMSTB_PIN(7, i2s_out, spdif_out, arm_jtag, sd_card_e, vc_i2c3, enet0_rgmii, vc_pcm, vc_spi4),
524
+
BRCMSTB_PIN(8, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, vc_i2c3, enet0_mii, vc_pcm, vc_spi4),
525
+
BRCMSTB_PIN(9, i2s_out, aud_fs_clk0, arm_jtag, sd_card_e, enet0_mii, sd_card_c, vc_spi4, _),
526
+
BRCMSTB_PIN(10, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
527
+
BRCMSTB_PIN(11, bsc_m3, mtsif_alt1, i2s_in, i2s_out, vc_spi5, enet0_mii, sd_card_c, vc_spi4),
528
+
BRCMSTB_PIN(12, spi_s, mtsif_alt1, i2s_in, i2s_out, vc_spi5, vc_i2csl, sd0, sd_card_d),
529
+
BRCMSTB_PIN(13, spi_s, mtsif_alt1, i2s_out, usb_vbus, vc_spi5, vc_i2csl, sd0, sd_card_d),
530
+
BRCMSTB_PIN(14, spi_s, vc_i2csl, enet0_rgmii, arm_jtag, vc_spi5, vc_pwm0, vc_i2c4, sd_card_d),
531
+
BRCMSTB_PIN(15, spi_s, vc_i2csl, vc_spi3, arm_jtag, vc_pwm0, vc_i2c4, gpclk0, _),
532
+
BRCMSTB_PIN(16, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, gpclk1, _),
533
+
BRCMSTB_PIN(17, sd_card_b, i2s_out, vc_spi3, i2s_in, ext_sc_clk, sd0, enet0_rgmii, gpclk2),
534
+
BRCMSTB_PIN(18, sd_card_b, i2s_out, vc_spi3, i2s_in, sd0, enet0_rgmii, vc_pwm1, _),
535
+
BRCMSTB_PIN(19, sd_card_b, usb_pwr, vc_spi3, pkt, spdif_out, sd0, ir_in, vc_pwm1),
536
+
BRCMSTB_PIN(20, sd_card_b, uui, vc_uart0, arm_jtag, uart2, usb_pwr, vc_pcm, vc_uart4),
537
+
BRCMSTB_PIN(21, usb_pwr, uui, vc_uart0, arm_jtag, uart2, sd_card_b, vc_pcm, vc_uart4),
538
+
BRCMSTB_PIN(22, usb_pwr, enet0, vc_uart0, mtsif, uart2, usb_vbus, vc_pcm, vc_i2c5),
539
+
BRCMSTB_PIN(23, usb_vbus, enet0, vc_uart0, mtsif, uart2, i2s_out, vc_pcm, vc_i2c5),
540
+
BRCMSTB_PIN(24, mtsif, pkt, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3, _),
541
+
BRCMSTB_PIN(25, mtsif, pkt, sc0, uart0, enet0_rgmii, enet0_rgmii, vc_i2c4, vc_uart3),
542
+
BRCMSTB_PIN(26, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
543
+
BRCMSTB_PIN(27, mtsif, pkt, sc0, uart0, enet0_rgmii, vc_uart4, vc_spi5, _),
544
+
BRCMSTB_PIN(28, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
545
+
BRCMSTB_PIN(29, mtsif, pkt, sc0, enet0_rgmii, vc_uart4, vc_spi5, _, _),
546
+
BRCMSTB_PIN(30, mtsif, pkt, sc0, sd2, enet0_rgmii, gpclk0, vc_pwm0, _),
547
+
BRCMSTB_PIN(31, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_pwm0, _),
548
+
BRCMSTB_PIN(32, mtsif, pkt, sc0, sd2, enet0_rgmii, vc_spi3, vc_uart3, _),
549
+
BRCMSTB_PIN(33, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_uart3, _, _),
550
+
BRCMSTB_PIN(34, mtsif, pkt, ext_sc_clk, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _),
551
+
BRCMSTB_PIN(35, mtsif, pkt, sd2, enet0_rgmii, vc_spi3, vc_i2c5, _, _),
552
+
BRCMSTB_PIN(36, sd0, mtsif, sc0, i2s_in, vc_uart3, vc_uart2, _, _),
553
+
BRCMSTB_PIN(37, sd0, mtsif, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
554
+
BRCMSTB_PIN(38, sd0, mtsif_alt, sc0, vc_spi0, i2s_in, vc_uart3, vc_uart2, _),
555
+
BRCMSTB_PIN(39, sd0, mtsif_alt, sc0, vc_spi0, vc_uart3, vc_uart2, _, _),
556
+
BRCMSTB_PIN(40, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
557
+
BRCMSTB_PIN(41, sd0, mtsif_alt, sc0, vc_spi0, bsc_m3, _, _, _),
558
+
BRCMSTB_PIN(42, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
559
+
BRCMSTB_PIN(43, vc_spi0, mtsif_alt, vc_i2c0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
560
+
BRCMSTB_PIN(44, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
561
+
BRCMSTB_PIN(45, vc_spi0, mtsif_alt, enet0, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m),
562
+
BRCMSTB_PIN(46, vc_spi0, mtsif_alt, sd_card_a, mtsif_alt1, arm_jtag, pdm, spi_m, _),
563
+
BRCMSTB_PIN(47, enet0, mtsif_alt, i2s_out, mtsif_alt1, arm_jtag, _, _, _),
564
+
BRCMSTB_PIN(48, sc0, usb_pwr, spdif_out, mtsif, _, _, _, _),
565
+
BRCMSTB_PIN(49, sc0, usb_pwr, aud_fs_clk0, mtsif, _, _, _, _),
566
+
BRCMSTB_PIN(50, sc0, usb_vbus, sc0, _, _, _, _, _),
567
+
BRCMSTB_PIN(51, sc0, enet0, sc0, sr_edm_sense, _, _, _, _),
568
+
BRCMSTB_PIN(52, sc0, enet0, vc_pwm1, _, _, _, _, _),
569
+
BRCMSTB_PIN(53, sc0, enet0_rgmii, ext_sc_clk, _, _, _, _, _),
570
+
};
571
+
572
+
static const struct brcmstb_pin_funcs bcm2712_d0_aon_gpio_pin_funcs[] = {
573
+
BRCMSTB_PIN(0, ir_in, vc_spi0, vc_uart0, vc_i2c3, uart0, vc_i2c0, _, _),
574
+
BRCMSTB_PIN(1, vc_pwm0, vc_spi0, vc_uart0, vc_i2c3, uart0, aon_pwm, vc_i2c0, vc_pwm1),
575
+
BRCMSTB_PIN(2, vc_pwm0, vc_spi0, vc_uart0, ctl_hdmi_5v, uart0, aon_pwm, ir_in, vc_pwm1),
576
+
BRCMSTB_PIN(3, ir_in, vc_spi0, vc_uart0, uart0, sd_card_g, aon_gpclk, _, _),
577
+
BRCMSTB_PIN(4, gpclk0, vc_spi0, pm_led_out, aon_pwm, sd_card_g, vc_pwm0, _, _),
578
+
BRCMSTB_PIN(5, gpclk1, ir_in, aon_pwm, sd_card_g, vc_pwm0, _, _, _),
579
+
BRCMSTB_PIN(6, uart1, vc_uart2, ctl_hdmi_5v, gpclk2, vc_spi3, _, _, _),
580
+
BRCMSTB_PIN(7, _, _, _, _, _, _, _, _), /* non-existent on D0 silicon */
581
+
BRCMSTB_PIN(8, uart1, vc_uart2, ctl_hdmi_5v, vc_spi0, vc_spi3, _, _, _),
582
+
BRCMSTB_PIN(9, uart1, vc_uart2, vc_uart0, aon_pwm, vc_spi0, vc_uart2, vc_spi3, _),
583
+
BRCMSTB_PIN(10, _, _, _, _, _, _, _, _), /* non-existent on D0 silicon */
584
+
BRCMSTB_PIN(11, _, _, _, _, _, _, _, _), /* non-existent on D0 silicon */
585
+
BRCMSTB_PIN(12, uart1, vc_uart2, vc_uart0, vc_spi0, usb_pwr, vc_uart2, vc_spi3, _),
586
+
BRCMSTB_PIN(13, bsc_m1, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3, _),
587
+
BRCMSTB_PIN(14, bsc_m1, aon_gpclk, vc_uart0, uui, vc_spi0, arm_jtag, vc_uart2, vc_i2c3),
588
+
};
589
+
590
+
static const struct brcmstb_pin_funcs bcm2712_d0_gpio_pin_funcs[] = {
591
+
BRCMSTB_PIN(1, vc_i2c0, usb_pwr, gpclk0, sd_card_e, vc_spi3, sr_edm_sense, vc_spi0, vc_uart0),
592
+
BRCMSTB_PIN(2, vc_i2c0, usb_pwr, gpclk1, sd_card_e, vc_spi3, clk_observe, vc_spi0, vc_uart0),
593
+
BRCMSTB_PIN(3, vc_i2c3, usb_vbus, gpclk2, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
594
+
BRCMSTB_PIN(4, vc_i2c3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, vc_spi0, vc_uart0, _),
595
+
BRCMSTB_PIN(10, bsc_m3, vc_pwm1, vc_spi3, sd_card_e, vc_spi3, gpclk0, _, _),
596
+
BRCMSTB_PIN(11, bsc_m3, vc_spi3, clk_observe, sd_card_c, gpclk1, _, _, _),
597
+
BRCMSTB_PIN(12, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
598
+
BRCMSTB_PIN(13, spi_s, vc_spi3, sd_card_c, sd_card_d, _, _, _, _),
599
+
BRCMSTB_PIN(14, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, sd_card_d, _, _),
600
+
BRCMSTB_PIN(15, spi_s, uui, arm_jtag, vc_pwm0, vc_i2c0, gpclk0, _, _),
601
+
BRCMSTB_PIN(18, sd_card_f, vc_pwm1, _, _, _, _, _, _),
602
+
BRCMSTB_PIN(19, sd_card_f, usb_pwr, vc_pwm1, _, _, _, _, _),
603
+
BRCMSTB_PIN(20, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
604
+
BRCMSTB_PIN(21, vc_i2c3, uui, vc_uart0, arm_jtag, vc_uart2, _, _, _),
605
+
BRCMSTB_PIN(22, sd_card_f, vc_uart0, vc_i2c3, _, _, _, _, _),
606
+
BRCMSTB_PIN(23, vc_uart0, vc_i2c3, _, _, _, _, _, _),
607
+
BRCMSTB_PIN(24, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
608
+
BRCMSTB_PIN(25, sd_card_b, vc_spi0, arm_jtag, uart0, usb_pwr, vc_uart2, vc_uart0, _),
609
+
BRCMSTB_PIN(26, sd_card_b, vc_spi0, arm_jtag, uart0, usb_vbus, vc_uart2, vc_spi0, _),
610
+
BRCMSTB_PIN(27, sd_card_b, vc_spi0, arm_jtag, uart0, vc_uart2, vc_spi0, _, _),
611
+
BRCMSTB_PIN(28, sd_card_b, vc_spi0, arm_jtag, vc_i2c0, vc_spi0, _, _, _),
612
+
BRCMSTB_PIN(29, arm_jtag, vc_i2c0, vc_spi0, _, _, _, _, _),
613
+
BRCMSTB_PIN(30, sd2, gpclk0, vc_pwm0, _, _, _, _, _),
614
+
BRCMSTB_PIN(31, sd2, vc_spi3, vc_pwm0, _, _, _, _, _),
615
+
BRCMSTB_PIN(32, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
616
+
BRCMSTB_PIN(33, sd2, vc_spi3, vc_uart3, _, _, _, _, _),
617
+
BRCMSTB_PIN(34, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
618
+
BRCMSTB_PIN(35, sd2, vc_spi3, vc_i2c5, _, _, _, _, _),
619
+
};
620
+
621
+
static const struct pinctrl_desc bcm2712_c0_pinctrl_desc = {
622
+
.name = "pinctrl-bcm2712",
623
+
.pins = bcm2712_c0_gpio_pins,
624
+
.npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
625
+
};
626
+
627
+
static const struct pinctrl_desc bcm2712_c0_aon_pinctrl_desc = {
628
+
.name = "aon-pinctrl-bcm2712",
629
+
.pins = bcm2712_c0_aon_gpio_pins,
630
+
.npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
631
+
};
632
+
633
+
static const struct pinctrl_desc bcm2712_d0_pinctrl_desc = {
634
+
.name = "pinctrl-bcm2712",
635
+
.pins = bcm2712_d0_gpio_pins,
636
+
.npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
637
+
};
638
+
639
+
static const struct pinctrl_desc bcm2712_d0_aon_pinctrl_desc = {
640
+
.name = "aon-pinctrl-bcm2712",
641
+
.pins = bcm2712_d0_aon_gpio_pins,
642
+
.npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
643
+
};
644
+
645
+
static const struct pinctrl_gpio_range bcm2712_c0_pinctrl_gpio_range = {
646
+
.name = "pinctrl-bcm2712",
647
+
.npins = ARRAY_SIZE(bcm2712_c0_gpio_pins),
648
+
};
649
+
650
+
static const struct pinctrl_gpio_range bcm2712_c0_aon_pinctrl_gpio_range = {
651
+
.name = "aon-pinctrl-bcm2712",
652
+
.npins = ARRAY_SIZE(bcm2712_c0_aon_gpio_pins),
653
+
};
654
+
655
+
static const struct pinctrl_gpio_range bcm2712_d0_pinctrl_gpio_range = {
656
+
.name = "pinctrl-bcm2712",
657
+
.npins = ARRAY_SIZE(bcm2712_d0_gpio_pins),
658
+
};
659
+
660
+
static const struct pinctrl_gpio_range bcm2712_d0_aon_pinctrl_gpio_range = {
661
+
.name = "aon-pinctrl-bcm2712",
662
+
.npins = ARRAY_SIZE(bcm2712_d0_aon_gpio_pins),
663
+
};
664
+
665
+
static const struct brcmstb_pdata bcm2712_c0_pdata = {
666
+
.pctl_desc = &bcm2712_c0_pinctrl_desc,
667
+
.gpio_range = &bcm2712_c0_pinctrl_gpio_range,
668
+
.pin_regs = bcm2712_c0_gpio_pin_regs,
669
+
.pin_funcs = bcm2712_c0_gpio_pin_funcs,
670
+
.func_count = func_count,
671
+
.func_gpio = func_gpio,
672
+
.func_names = bcm2712_func_names,
673
+
};
674
+
675
+
static const struct brcmstb_pdata bcm2712_c0_aon_pdata = {
676
+
.pctl_desc = &bcm2712_c0_aon_pinctrl_desc,
677
+
.gpio_range = &bcm2712_c0_aon_pinctrl_gpio_range,
678
+
.pin_regs = bcm2712_c0_aon_gpio_pin_regs,
679
+
.pin_funcs = bcm2712_c0_aon_gpio_pin_funcs,
680
+
.func_count = func_count,
681
+
.func_gpio = func_gpio,
682
+
.func_names = bcm2712_func_names,
683
+
};
684
+
685
+
static const struct brcmstb_pdata bcm2712_d0_pdata = {
686
+
.pctl_desc = &bcm2712_d0_pinctrl_desc,
687
+
.gpio_range = &bcm2712_d0_pinctrl_gpio_range,
688
+
.pin_regs = bcm2712_d0_gpio_pin_regs,
689
+
.pin_funcs = bcm2712_d0_gpio_pin_funcs,
690
+
.func_count = func_count,
691
+
.func_gpio = func_gpio,
692
+
.func_names = bcm2712_func_names,
693
+
};
694
+
695
+
static const struct brcmstb_pdata bcm2712_d0_aon_pdata = {
696
+
.pctl_desc = &bcm2712_d0_aon_pinctrl_desc,
697
+
.gpio_range = &bcm2712_d0_aon_pinctrl_gpio_range,
698
+
.pin_regs = bcm2712_d0_aon_gpio_pin_regs,
699
+
.pin_funcs = bcm2712_d0_aon_gpio_pin_funcs,
700
+
.func_count = func_count,
701
+
.func_gpio = func_gpio,
702
+
.func_names = bcm2712_func_names,
703
+
};
704
+
705
+
static int bcm2712_pinctrl_probe(struct platform_device *pdev)
706
+
{
707
+
return brcmstb_pinctrl_probe(pdev);
708
+
}
709
+
710
+
static const struct of_device_id bcm2712_pinctrl_match[] = {
711
+
{
712
+
.compatible = "brcm,bcm2712c0-pinctrl",
713
+
.data = &bcm2712_c0_pdata
714
+
},
715
+
{
716
+
.compatible = "brcm,bcm2712c0-aon-pinctrl",
717
+
.data = &bcm2712_c0_aon_pdata
718
+
},
719
+
720
+
{
721
+
.compatible = "brcm,bcm2712d0-pinctrl",
722
+
.data = &bcm2712_d0_pdata
723
+
},
724
+
{
725
+
.compatible = "brcm,bcm2712d0-aon-pinctrl",
726
+
.data = &bcm2712_d0_aon_pdata
727
+
},
728
+
{ /* sentinel */ }
729
+
};
730
+
MODULE_DEVICE_TABLE(of, bcm2712_pinctrl_match);
731
+
732
+
static struct platform_driver bcm2712_pinctrl_driver = {
733
+
.probe = bcm2712_pinctrl_probe,
734
+
.driver = {
735
+
.name = "pinctrl-bcm2712",
736
+
.of_match_table = bcm2712_pinctrl_match,
737
+
.suppress_bind_attrs = true,
738
+
},
739
+
};
740
+
module_platform_driver(bcm2712_pinctrl_driver);
741
+
742
+
MODULE_AUTHOR("Phil Elwell");
743
+
MODULE_AUTHOR("Jonathan Bell");
744
+
MODULE_AUTHOR("Ivan T. Ivanov");
745
+
MODULE_AUTHOR("Andrea della Porta");
746
+
MODULE_DESCRIPTION("Broadcom BCM2712 pinctrl driver");
747
+
MODULE_LICENSE("GPL");
+442
drivers/pinctrl/bcm/pinctrl-brcmstb.c
+442
drivers/pinctrl/bcm/pinctrl-brcmstb.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Driver for Broadcom brcmstb GPIO units (pinctrl only)
4
+
*
5
+
* Copyright (C) 2024-2025 Ivan T. Ivanov, Andrea della Porta
6
+
* Copyright (C) 2021-3 Raspberry Pi Ltd.
7
+
* Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
8
+
*
9
+
* Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
10
+
* pinctrl-nomadik.c, please see original file for copyright information
11
+
* pinctrl-tegra.c, please see original file for copyright information
12
+
*/
13
+
14
+
#include <linux/device.h>
15
+
#include <linux/err.h>
16
+
#include <linux/init.h>
17
+
#include <linux/io.h>
18
+
#include <linux/of.h>
19
+
#include <linux/pinctrl/pinconf.h>
20
+
#include <linux/pinctrl/pinctrl.h>
21
+
#include <linux/pinctrl/pinmux.h>
22
+
#include <linux/pinctrl/pinconf-generic.h>
23
+
#include <linux/seq_file.h>
24
+
#include <linux/slab.h>
25
+
#include <linux/spinlock.h>
26
+
#include <linux/cleanup.h>
27
+
28
+
#include "pinctrl-brcmstb.h"
29
+
30
+
#define BRCMSTB_PULL_NONE 0
31
+
#define BRCMSTB_PULL_DOWN 1
32
+
#define BRCMSTB_PULL_UP 2
33
+
#define BRCMSTB_PULL_MASK 0x3
34
+
35
+
#define BIT_TO_REG(b) (((b) >> 5) << 2)
36
+
#define BIT_TO_SHIFT(b) ((b) & 0x1f)
37
+
38
+
struct brcmstb_pinctrl {
39
+
struct device *dev;
40
+
void __iomem *base;
41
+
struct pinctrl_dev *pctl_dev;
42
+
struct pinctrl_desc pctl_desc;
43
+
const struct pin_regs *pin_regs;
44
+
const struct brcmstb_pin_funcs *pin_funcs;
45
+
const char * const *func_names;
46
+
unsigned int func_count;
47
+
unsigned int func_gpio;
48
+
const char *const *gpio_groups;
49
+
struct pinctrl_gpio_range gpio_range;
50
+
/* Protect FSEL registers */
51
+
spinlock_t fsel_lock;
52
+
};
53
+
54
+
static unsigned int brcmstb_pinctrl_fsel_get(struct brcmstb_pinctrl *pc,
55
+
unsigned int pin)
56
+
{
57
+
u32 bit = pc->pin_regs[pin].mux_bit;
58
+
unsigned int func;
59
+
int fsel;
60
+
u32 val;
61
+
62
+
if (!bit)
63
+
return pc->func_gpio;
64
+
65
+
bit &= ~MUX_BIT_VALID;
66
+
67
+
val = readl(pc->base + BIT_TO_REG(bit));
68
+
fsel = (val >> BIT_TO_SHIFT(bit)) & pc->pin_funcs[pin].func_mask;
69
+
func = pc->pin_funcs[pin].funcs[fsel];
70
+
71
+
if (func >= pc->func_count)
72
+
func = fsel;
73
+
74
+
dev_dbg(pc->dev, "get %04x: %08x (%u => %s)\n",
75
+
BIT_TO_REG(bit), val, pin,
76
+
pc->func_names[func]);
77
+
78
+
return func;
79
+
}
80
+
81
+
static int brcmstb_pinctrl_fsel_set(struct brcmstb_pinctrl *pc,
82
+
unsigned int pin, unsigned int func)
83
+
{
84
+
u32 bit = pc->pin_regs[pin].mux_bit, val, fsel_mask;
85
+
const u8 *pin_funcs;
86
+
int fsel;
87
+
int cur;
88
+
int i;
89
+
90
+
if (!bit || func >= pc->func_count)
91
+
return -EINVAL;
92
+
93
+
bit &= ~MUX_BIT_VALID;
94
+
95
+
fsel = pc->pin_funcs[pin].n_funcs + 1;
96
+
fsel_mask = pc->pin_funcs[pin].func_mask;
97
+
98
+
if (func >= fsel) {
99
+
/* Convert to an fsel number */
100
+
pin_funcs = pc->pin_funcs[pin].funcs;
101
+
for (i = 1; i < fsel; i++) {
102
+
if (pin_funcs[i - 1] == func) {
103
+
fsel = i;
104
+
break;
105
+
}
106
+
}
107
+
} else {
108
+
fsel = func;
109
+
}
110
+
111
+
if (fsel >= pc->pin_funcs[pin].n_funcs + 1)
112
+
return -EINVAL;
113
+
114
+
guard(spinlock_irqsave)(&pc->fsel_lock);
115
+
116
+
val = readl(pc->base + BIT_TO_REG(bit));
117
+
cur = (val >> BIT_TO_SHIFT(bit)) & fsel_mask;
118
+
119
+
dev_dbg(pc->dev, "read %04x: %08x (%u => %s)\n",
120
+
BIT_TO_REG(bit), val, pin,
121
+
pc->func_names[cur]);
122
+
123
+
if (cur != fsel) {
124
+
val &= ~(fsel_mask << BIT_TO_SHIFT(bit));
125
+
val |= fsel << BIT_TO_SHIFT(bit);
126
+
127
+
dev_dbg(pc->dev, "write %04x: %08x (%u <= %s)\n",
128
+
BIT_TO_REG(bit), val, pin,
129
+
pc->func_names[fsel]);
130
+
writel(val, pc->base + BIT_TO_REG(bit));
131
+
}
132
+
133
+
return 0;
134
+
}
135
+
136
+
static int brcmstb_pctl_get_groups_count(struct pinctrl_dev *pctldev)
137
+
{
138
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
139
+
140
+
return pc->pctl_desc.npins;
141
+
}
142
+
143
+
static const char *brcmstb_pctl_get_group_name(struct pinctrl_dev *pctldev,
144
+
unsigned int selector)
145
+
{
146
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
147
+
148
+
return pc->gpio_groups[selector];
149
+
}
150
+
151
+
static int brcmstb_pctl_get_group_pins(struct pinctrl_dev *pctldev,
152
+
unsigned int selector,
153
+
const unsigned int **pins,
154
+
unsigned int *num_pins)
155
+
{
156
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
157
+
158
+
*pins = &pc->pctl_desc.pins[selector].number;
159
+
*num_pins = 1;
160
+
161
+
return 0;
162
+
}
163
+
164
+
static void brcmstb_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
165
+
struct seq_file *s, unsigned int offset)
166
+
{
167
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
168
+
unsigned int fsel = brcmstb_pinctrl_fsel_get(pc, offset);
169
+
const char *fname = pc->func_names[fsel];
170
+
171
+
seq_printf(s, "function %s", fname);
172
+
}
173
+
174
+
static void brcmstb_pctl_dt_free_map(struct pinctrl_dev *pctldev,
175
+
struct pinctrl_map *maps,
176
+
unsigned int num_maps)
177
+
{
178
+
int i;
179
+
180
+
for (i = 0; i < num_maps; i++)
181
+
if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
182
+
kfree(maps[i].data.configs.configs);
183
+
184
+
kfree(maps);
185
+
}
186
+
187
+
static const struct pinctrl_ops brcmstb_pctl_ops = {
188
+
.get_groups_count = brcmstb_pctl_get_groups_count,
189
+
.get_group_name = brcmstb_pctl_get_group_name,
190
+
.get_group_pins = brcmstb_pctl_get_group_pins,
191
+
.pin_dbg_show = brcmstb_pctl_pin_dbg_show,
192
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
193
+
.dt_free_map = brcmstb_pctl_dt_free_map,
194
+
};
195
+
196
+
static int brcmstb_pmx_free(struct pinctrl_dev *pctldev, unsigned int offset)
197
+
{
198
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
199
+
200
+
/* disable by setting to GPIO */
201
+
return brcmstb_pinctrl_fsel_set(pc, offset, pc->func_gpio);
202
+
}
203
+
204
+
static int brcmstb_pmx_get_functions_count(struct pinctrl_dev *pctldev)
205
+
{
206
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
207
+
208
+
return pc->func_count;
209
+
}
210
+
211
+
static const char *brcmstb_pmx_get_function_name(struct pinctrl_dev *pctldev,
212
+
unsigned int selector)
213
+
{
214
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
215
+
216
+
return (selector < pc->func_count) ? pc->func_names[selector] : NULL;
217
+
}
218
+
219
+
static int brcmstb_pmx_get_function_groups(struct pinctrl_dev *pctldev,
220
+
unsigned int selector,
221
+
const char *const **groups,
222
+
unsigned *const num_groups)
223
+
{
224
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
225
+
226
+
*groups = pc->gpio_groups;
227
+
*num_groups = pc->pctl_desc.npins;
228
+
229
+
return 0;
230
+
}
231
+
232
+
static int brcmstb_pmx_set(struct pinctrl_dev *pctldev,
233
+
unsigned int func_selector,
234
+
unsigned int group_selector)
235
+
{
236
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
237
+
const struct pinctrl_desc *pctldesc = &pc->pctl_desc;
238
+
const struct pinctrl_pin_desc *pindesc;
239
+
240
+
if (group_selector >= pctldesc->npins)
241
+
return -EINVAL;
242
+
243
+
pindesc = &pctldesc->pins[group_selector];
244
+
return brcmstb_pinctrl_fsel_set(pc, pindesc->number, func_selector);
245
+
}
246
+
247
+
static int brcmstb_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
248
+
struct pinctrl_gpio_range *range,
249
+
unsigned int pin)
250
+
{
251
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
252
+
253
+
return brcmstb_pinctrl_fsel_set(pc, pin, pc->func_gpio);
254
+
}
255
+
256
+
static void brcmstb_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
257
+
struct pinctrl_gpio_range *range,
258
+
unsigned int offset)
259
+
{
260
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
261
+
262
+
/* disable by setting to GPIO */
263
+
(void)brcmstb_pinctrl_fsel_set(pc, offset, pc->func_gpio);
264
+
}
265
+
266
+
static bool brcmstb_pmx_function_is_gpio(struct pinctrl_dev *pctldev,
267
+
unsigned int selector)
268
+
{
269
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
270
+
271
+
return pc->func_gpio == selector;
272
+
}
273
+
274
+
static const struct pinmux_ops brcmstb_pmx_ops = {
275
+
.free = brcmstb_pmx_free,
276
+
.get_functions_count = brcmstb_pmx_get_functions_count,
277
+
.get_function_name = brcmstb_pmx_get_function_name,
278
+
.get_function_groups = brcmstb_pmx_get_function_groups,
279
+
.set_mux = brcmstb_pmx_set,
280
+
.gpio_request_enable = brcmstb_pmx_gpio_request_enable,
281
+
.gpio_disable_free = brcmstb_pmx_gpio_disable_free,
282
+
.function_is_gpio = brcmstb_pmx_function_is_gpio,
283
+
.strict = true,
284
+
};
285
+
286
+
static unsigned int brcmstb_pull_config_get(struct brcmstb_pinctrl *pc,
287
+
unsigned int pin)
288
+
{
289
+
u32 bit = pc->pin_regs[pin].pad_bit, val;
290
+
291
+
if (bit == PAD_BIT_INVALID)
292
+
return BRCMSTB_PULL_NONE;
293
+
294
+
val = readl(pc->base + BIT_TO_REG(bit));
295
+
return (val >> BIT_TO_SHIFT(bit)) & BRCMSTB_PULL_MASK;
296
+
}
297
+
298
+
static int brcmstb_pull_config_set(struct brcmstb_pinctrl *pc,
299
+
unsigned int pin, unsigned int arg)
300
+
{
301
+
u32 bit = pc->pin_regs[pin].pad_bit, val;
302
+
303
+
if (bit == PAD_BIT_INVALID) {
304
+
dev_warn(pc->dev, "Can't set pulls for %s\n",
305
+
pc->gpio_groups[pin]);
306
+
return -EINVAL;
307
+
}
308
+
309
+
guard(spinlock_irqsave)(&pc->fsel_lock);
310
+
311
+
val = readl(pc->base + BIT_TO_REG(bit));
312
+
val &= ~(BRCMSTB_PULL_MASK << BIT_TO_SHIFT(bit));
313
+
val |= (arg << BIT_TO_SHIFT(bit));
314
+
writel(val, pc->base + BIT_TO_REG(bit));
315
+
316
+
return 0;
317
+
}
318
+
319
+
static int brcmstb_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
320
+
unsigned long *config)
321
+
{
322
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
323
+
enum pin_config_param param = pinconf_to_config_param(*config);
324
+
u32 arg;
325
+
326
+
switch (param) {
327
+
case PIN_CONFIG_BIAS_DISABLE:
328
+
arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_NONE);
329
+
break;
330
+
case PIN_CONFIG_BIAS_PULL_DOWN:
331
+
arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_DOWN);
332
+
break;
333
+
case PIN_CONFIG_BIAS_PULL_UP:
334
+
arg = (brcmstb_pull_config_get(pc, pin) == BRCMSTB_PULL_UP);
335
+
break;
336
+
default:
337
+
return -ENOTSUPP;
338
+
}
339
+
340
+
*config = pinconf_to_config_packed(param, arg);
341
+
342
+
return 0;
343
+
}
344
+
345
+
static int brcmstb_pinconf_set(struct pinctrl_dev *pctldev,
346
+
unsigned int pin, unsigned long *configs,
347
+
unsigned int num_configs)
348
+
{
349
+
struct brcmstb_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
350
+
int ret = 0;
351
+
u32 param;
352
+
int i;
353
+
354
+
for (i = 0; i < num_configs; i++) {
355
+
param = pinconf_to_config_param(configs[i]);
356
+
357
+
switch (param) {
358
+
case PIN_CONFIG_BIAS_DISABLE:
359
+
ret = brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_NONE);
360
+
break;
361
+
case PIN_CONFIG_BIAS_PULL_DOWN:
362
+
ret = brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_DOWN);
363
+
break;
364
+
case PIN_CONFIG_BIAS_PULL_UP:
365
+
ret = brcmstb_pull_config_set(pc, pin, BRCMSTB_PULL_UP);
366
+
break;
367
+
default:
368
+
return -ENOTSUPP;
369
+
}
370
+
}
371
+
372
+
return ret;
373
+
}
374
+
375
+
static const struct pinconf_ops brcmstb_pinconf_ops = {
376
+
.is_generic = true,
377
+
.pin_config_get = brcmstb_pinconf_get,
378
+
.pin_config_set = brcmstb_pinconf_set,
379
+
};
380
+
381
+
int brcmstb_pinctrl_probe(struct platform_device *pdev)
382
+
{
383
+
struct device *dev = &pdev->dev;
384
+
struct device_node *np = dev->of_node;
385
+
const struct brcmstb_pdata *pdata;
386
+
struct brcmstb_pinctrl *pc;
387
+
const char **names;
388
+
int num_pins, i;
389
+
390
+
pdata = of_device_get_match_data(dev);
391
+
392
+
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
393
+
if (!pc)
394
+
return -ENOMEM;
395
+
396
+
platform_set_drvdata(pdev, pc);
397
+
pc->dev = dev;
398
+
spin_lock_init(&pc->fsel_lock);
399
+
400
+
pc->base = devm_of_iomap(dev, np, 0, NULL);
401
+
if (IS_ERR(pc->base))
402
+
return dev_err_probe(&pdev->dev, PTR_ERR(pc->base),
403
+
"Could not get IO memory\n");
404
+
405
+
pc->pctl_desc = *pdata->pctl_desc;
406
+
pc->pctl_desc.pctlops = &brcmstb_pctl_ops;
407
+
pc->pctl_desc.pmxops = &brcmstb_pmx_ops;
408
+
pc->pctl_desc.confops = &brcmstb_pinconf_ops;
409
+
pc->pctl_desc.owner = THIS_MODULE;
410
+
num_pins = pc->pctl_desc.npins;
411
+
names = devm_kmalloc_array(dev, num_pins, sizeof(const char *),
412
+
GFP_KERNEL);
413
+
if (!names)
414
+
return -ENOMEM;
415
+
416
+
for (i = 0; i < num_pins; i++)
417
+
names[i] = pc->pctl_desc.pins[i].name;
418
+
419
+
pc->gpio_groups = names;
420
+
pc->pin_regs = pdata->pin_regs;
421
+
pc->pin_funcs = pdata->pin_funcs;
422
+
pc->func_count = pdata->func_count;
423
+
pc->func_names = pdata->func_names;
424
+
425
+
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
426
+
if (IS_ERR(pc->pctl_dev))
427
+
return dev_err_probe(&pdev->dev, PTR_ERR(pc->pctl_dev),
428
+
"Failed to register pinctrl device\n");
429
+
430
+
pc->gpio_range = *pdata->gpio_range;
431
+
pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
432
+
433
+
return 0;
434
+
}
435
+
EXPORT_SYMBOL(brcmstb_pinctrl_probe);
436
+
437
+
MODULE_AUTHOR("Phil Elwell");
438
+
MODULE_AUTHOR("Jonathan Bell");
439
+
MODULE_AUTHOR("Ivan T. Ivanov");
440
+
MODULE_AUTHOR("Andrea della Porta");
441
+
MODULE_DESCRIPTION("Broadcom brcmstb pinctrl driver");
442
+
MODULE_LICENSE("GPL");
+93
drivers/pinctrl/bcm/pinctrl-brcmstb.h
+93
drivers/pinctrl/bcm/pinctrl-brcmstb.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Header for Broadcom brcmstb GPIO based drivers
4
+
*
5
+
* Copyright (C) 2024-2025 Ivan T. Ivanov, Andrea della Porta
6
+
* Copyright (C) 2021-3 Raspberry Pi Ltd.
7
+
* Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
8
+
*
9
+
* Based heavily on the BCM2835 GPIO & pinctrl driver, which was inspired by:
10
+
* pinctrl-nomadik.c, please see original file for copyright information
11
+
* pinctrl-tegra.c, please see original file for copyright information
12
+
*/
13
+
14
+
#ifndef __PINCTRL_BRCMSTB_H__
15
+
#define __PINCTRL_BRCMSTB_H__
16
+
17
+
#include <linux/types.h>
18
+
#include <linux/platform_device.h>
19
+
20
+
#define BRCMSTB_FUNC(f) \
21
+
[func_##f] = #f
22
+
23
+
#define MUX_BIT_VALID 0x8000
24
+
#define PAD_BIT_INVALID 0xffff
25
+
26
+
#define MUX_BIT(muxreg, muxshift) \
27
+
(MUX_BIT_VALID + ((muxreg) << 5) + ((muxshift) << 2))
28
+
#define PAD_BIT(padreg, padshift) \
29
+
(((padreg) << 5) + ((padshift) << 1))
30
+
31
+
#define GPIO_REGS(n, muxreg, muxshift, padreg, padshift) \
32
+
[n] = { MUX_BIT(muxreg, muxshift), PAD_BIT(padreg, padshift) }
33
+
34
+
#define EMMC_REGS(n, padreg, padshift) \
35
+
[n] = { 0, PAD_BIT(padreg, padshift) }
36
+
37
+
#define AON_GPIO_REGS(n, muxreg, muxshift, padreg, padshift) \
38
+
GPIO_REGS(n, muxreg, muxshift, padreg, padshift)
39
+
40
+
#define AON_SGPIO_REGS(n, muxreg, muxshift) \
41
+
[(n) + 32] = { MUX_BIT(muxreg, muxshift), PAD_BIT_INVALID }
42
+
43
+
#define GPIO_PIN(n) PINCTRL_PIN(n, "gpio" #n)
44
+
/**
45
+
* AON pins are in the Always-On power domain. SGPIOs are also 'Safe'
46
+
* being 5V tolerant (necessary for the HDMI I2C pins), and can be driven
47
+
* while the power is off.
48
+
*/
49
+
#define AON_GPIO_PIN(n) PINCTRL_PIN(n, "aon_gpio" #n)
50
+
#define AON_SGPIO_PIN(n) PINCTRL_PIN((n) + 32, "aon_sgpio" #n)
51
+
52
+
struct pin_regs {
53
+
u16 mux_bit;
54
+
u16 pad_bit;
55
+
};
56
+
57
+
/**
58
+
* struct brcmstb_pin_funcs - pins provide their primary/alternate
59
+
* functions in this struct
60
+
* @func_mask: mask representing valid bits of the function selector
61
+
* in the registers
62
+
* @funcs: array of function identifiers
63
+
* @n_funcs: number of identifiers of the @funcs array above
64
+
*/
65
+
struct brcmstb_pin_funcs {
66
+
const u32 func_mask;
67
+
const u8 *funcs;
68
+
const unsigned int n_funcs;
69
+
};
70
+
71
+
/**
72
+
* struct brcmstb_pdata - specific data for a pinctrl chip implementation
73
+
* @pctl_desc: pin controller descriptor for this implementation
74
+
* @gpio_range: range of GPIOs served by this controller
75
+
* @pin_regs: array of register descriptors for each pin
76
+
* @pin_funcs: array of all possible assignable function for each pin
77
+
* @func_count: total number of functions
78
+
* @func_gpio: which function number is GPIO (usually 0)
79
+
* @func_names: an array listing all function names
80
+
*/
81
+
struct brcmstb_pdata {
82
+
const struct pinctrl_desc *pctl_desc;
83
+
const struct pinctrl_gpio_range *gpio_range;
84
+
const struct pin_regs *pin_regs;
85
+
const struct brcmstb_pin_funcs *pin_funcs;
86
+
const unsigned int func_count;
87
+
const unsigned int func_gpio;
88
+
const char * const *func_names;
89
+
};
90
+
91
+
int brcmstb_pinctrl_probe(struct platform_device *pdev);
92
+
93
+
#endif
+2
-2
drivers/pinctrl/cirrus/pinctrl-madera-core.c
+2
-2
drivers/pinctrl/cirrus/pinctrl-madera-core.c
···
804
804
if (conf[0] & MADERA_GP1_IP_CFG_MASK)
805
805
result = 1;
806
806
break;
807
-
case PIN_CONFIG_OUTPUT:
807
+
case PIN_CONFIG_LEVEL:
808
808
if ((conf[1] & MADERA_GP1_DIR_MASK) &&
809
809
(conf[0] & MADERA_GP1_LVL_MASK))
810
810
result = 1;
···
902
902
mask[1] |= MADERA_GP1_DIR_MASK;
903
903
conf[1] |= MADERA_GP1_DIR;
904
904
break;
905
-
case PIN_CONFIG_OUTPUT:
905
+
case PIN_CONFIG_LEVEL:
906
906
val = pinconf_to_config_argument(*configs);
907
907
mask[0] |= MADERA_GP1_LVL_MASK;
908
908
if (val)
+20
-25
drivers/pinctrl/freescale/pinctrl-imx.c
+20
-25
drivers/pinctrl/freescale/pinctrl-imx.c
···
245
245
{
246
246
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
247
247
const struct imx_pinctrl_soc_info *info = ipctl->info;
248
-
struct function_desc *func;
248
+
const struct function_desc *func;
249
249
struct group_desc *grp;
250
250
struct imx_pin *pin;
251
251
unsigned int npins;
···
266
266
npins = grp->grp.npins;
267
267
268
268
dev_dbg(ipctl->dev, "enable function %s group %s\n",
269
-
func->func.name, grp->grp.name);
269
+
func->func->name, grp->grp.name);
270
270
271
271
for (i = 0; i < npins; i++) {
272
272
/*
···
580
580
u32 index)
581
581
{
582
582
struct pinctrl_dev *pctl = ipctl->pctl;
583
-
struct function_desc *func;
583
+
struct pinfunction *func;
584
584
struct group_desc *grp;
585
585
const char **group_names;
586
+
int ret;
586
587
u32 i;
587
588
588
589
dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
589
590
590
-
func = pinmux_generic_get_function(pctl, index);
591
+
func = devm_kzalloc(ipctl->dev, sizeof(*func), GFP_KERNEL);
591
592
if (!func)
592
-
return -EINVAL;
593
+
return -ENOMEM;
593
594
594
595
/* Initialise function */
595
-
func->func.name = np->name;
596
-
func->func.ngroups = of_get_child_count(np);
597
-
if (func->func.ngroups == 0) {
596
+
func->name = np->name;
597
+
func->ngroups = of_get_child_count(np);
598
+
if (func->ngroups == 0) {
598
599
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
599
600
return -EINVAL;
600
601
}
601
602
602
-
group_names = devm_kcalloc(ipctl->dev, func->func.ngroups,
603
-
sizeof(*func->func.groups), GFP_KERNEL);
603
+
group_names = devm_kcalloc(ipctl->dev, func->ngroups,
604
+
sizeof(*func->groups), GFP_KERNEL);
604
605
if (!group_names)
605
606
return -ENOMEM;
606
607
i = 0;
607
608
for_each_child_of_node_scoped(np, child)
608
609
group_names[i++] = child->name;
609
-
func->func.groups = group_names;
610
+
func->groups = group_names;
611
+
612
+
ret = pinmux_generic_add_pinfunction(pctl, func, NULL);
613
+
if (ret < 0)
614
+
return ret;
610
615
611
616
i = 0;
612
617
for_each_child_of_node_scoped(np, child) {
···
620
615
return -ENOMEM;
621
616
622
617
mutex_lock(&ipctl->mutex);
618
+
/*
619
+
* FIXME: This should use pinctrl_generic_add_group() and not
620
+
* access the private radix tree directly.
621
+
*/
623
622
radix_tree_insert(&pctl->pin_group_tree,
624
623
ipctl->group_index++, grp);
625
624
mutex_unlock(&ipctl->mutex);
···
677
668
return -EINVAL;
678
669
}
679
670
}
680
-
681
-
for (i = 0; i < nfuncs; i++) {
682
-
struct function_desc *function;
683
-
684
-
function = devm_kzalloc(&pdev->dev, sizeof(*function),
685
-
GFP_KERNEL);
686
-
if (!function)
687
-
return -ENOMEM;
688
-
689
-
mutex_lock(&ipctl->mutex);
690
-
radix_tree_insert(&pctl->pin_function_tree, i, function);
691
-
mutex_unlock(&ipctl->mutex);
692
-
}
693
-
pctl->num_functions = nfuncs;
694
671
695
672
ipctl->group_index = 0;
696
673
if (flat_funcs) {
+9
-14
drivers/pinctrl/mediatek/pinctrl-airoha.c
+9
-14
drivers/pinctrl/mediatek/pinctrl-airoha.c
···
35
35
36
36
#define PINCTRL_FUNC_DESC(id) \
37
37
{ \
38
-
.desc = { \
39
-
.func = { \
40
-
.name = #id, \
41
-
.groups = id##_groups, \
42
-
.ngroups = ARRAY_SIZE(id##_groups), \
43
-
} \
44
-
}, \
38
+
.desc = PINCTRL_PINFUNCTION(#id, id##_groups, \
39
+
ARRAY_SIZE(id##_groups)), \
45
40
.groups = id##_func_group, \
46
41
.group_size = ARRAY_SIZE(id##_func_group), \
47
42
}
···
332
337
};
333
338
334
339
struct airoha_pinctrl_func {
335
-
const struct function_desc desc;
340
+
const struct pinfunction desc;
336
341
const struct airoha_pinctrl_func_group *groups;
337
342
u8 group_size;
338
343
};
···
2446
2451
{
2447
2452
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
2448
2453
const struct airoha_pinctrl_func *func;
2449
-
struct function_desc *desc;
2454
+
const struct function_desc *desc;
2450
2455
struct group_desc *grp;
2451
2456
int i;
2452
2457
···
2459
2464
return -EINVAL;
2460
2465
2461
2466
dev_dbg(pctrl_dev->dev, "enable function %s group %s\n",
2462
-
desc->func.name, grp->grp.name);
2467
+
desc->func->name, grp->grp.name);
2463
2468
2464
2469
func = desc->data;
2465
2470
for (i = 0; i < func->group_size; i++) {
···
2768
2773
break;
2769
2774
case PIN_CONFIG_OUTPUT_ENABLE:
2770
2775
case PIN_CONFIG_INPUT_ENABLE:
2771
-
case PIN_CONFIG_OUTPUT: {
2776
+
case PIN_CONFIG_LEVEL: {
2772
2777
bool input = param == PIN_CONFIG_INPUT_ENABLE;
2773
2778
int err;
2774
2779
···
2777
2782
if (err)
2778
2783
return err;
2779
2784
2780
-
if (param == PIN_CONFIG_OUTPUT) {
2785
+
if (param == PIN_CONFIG_LEVEL) {
2781
2786
err = airoha_pinconf_set_pin_value(pctrl_dev,
2782
2787
pin, !!arg);
2783
2788
if (err)
···
2906
2911
2907
2912
func = &airoha_pinctrl_funcs[i];
2908
2913
err = pinmux_generic_add_pinfunction(pinctrl->ctrl,
2909
-
&func->desc.func,
2914
+
&func->desc,
2910
2915
(void *)func);
2911
2916
if (err < 0) {
2912
2917
dev_err(dev, "Failed to register function %s\n",
2913
-
func->desc.func.name);
2918
+
func->desc.name);
2914
2919
return err;
2915
2920
}
2916
2921
}
+5
-7
drivers/pinctrl/mediatek/pinctrl-moore.c
+5
-7
drivers/pinctrl/mediatek/pinctrl-moore.c
···
43
43
unsigned int selector, unsigned int group)
44
44
{
45
45
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
46
-
struct function_desc *func;
46
+
const struct function_desc *func;
47
47
struct group_desc *grp;
48
48
int i, err;
49
49
···
56
56
return -EINVAL;
57
57
58
58
dev_dbg(pctldev->dev, "enable function %s group %s\n",
59
-
func->func.name, grp->grp.name);
59
+
func->func->name, grp->grp.name);
60
60
61
61
for (i = 0; i < grp->grp.npins; i++) {
62
62
const struct mtk_pin_desc *desc;
···
332
332
goto err;
333
333
334
334
break;
335
-
case PIN_CONFIG_OUTPUT:
335
+
case PIN_CONFIG_LEVEL:
336
336
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
337
337
MTK_OUTPUT);
338
338
if (err)
···
622
622
int i, err;
623
623
624
624
for (i = 0; i < hw->soc->nfuncs ; i++) {
625
-
const struct function_desc *function = hw->soc->funcs + i;
626
-
const struct pinfunction *func = &function->func;
625
+
const struct pinfunction *func = hw->soc->funcs + i;
627
626
628
-
err = pinmux_generic_add_pinfunction(hw->pctrl, func,
629
-
function->data);
627
+
err = pinmux_generic_add_pinfunction(hw->pctrl, func, NULL);
630
628
if (err < 0) {
631
629
dev_err(hw->dev, "Failed to register function %s\n",
632
630
func->name);
+2
-5
drivers/pinctrl/mediatek/pinctrl-moore.h
+2
-5
drivers/pinctrl/mediatek/pinctrl-moore.h
···
43
43
.data = id##_funcs, \
44
44
}
45
45
46
-
#define PINCTRL_PIN_FUNCTION(_name_, id) \
47
-
{ \
48
-
.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
49
-
.data = NULL, \
50
-
}
46
+
#define PINCTRL_PIN_FUNCTION(_name_, id) \
47
+
PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups))
51
48
52
49
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
53
50
const struct mtk_pin_soc *soc);
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7622.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7622.c
···
822
822
"uart4_2_rts_cts",};
823
823
static const char *mt7622_wdt_groups[] = { "watchdog", };
824
824
825
-
static const struct function_desc mt7622_functions[] = {
825
+
static const struct pinfunction mt7622_functions[] = {
826
826
PINCTRL_PIN_FUNCTION("antsel", mt7622_antsel),
827
827
PINCTRL_PIN_FUNCTION("emmc", mt7622_emmc),
828
828
PINCTRL_PIN_FUNCTION("eth", mt7622_ethernet),
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7623.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7623.c
···
1340
1340
"uart3_rts_cts", };
1341
1341
static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
1342
1342
1343
-
static const struct function_desc mt7623_functions[] = {
1343
+
static const struct pinfunction mt7623_functions[] = {
1344
1344
PINCTRL_PIN_FUNCTION("audck", mt7623_aud_clk),
1345
1345
PINCTRL_PIN_FUNCTION("disp", mt7623_disp_pwm),
1346
1346
PINCTRL_PIN_FUNCTION("eth", mt7623_ethernet),
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7629.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7629.c
···
384
384
static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
385
385
static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
386
386
387
-
static const struct function_desc mt7629_functions[] = {
387
+
static const struct pinfunction mt7629_functions[] = {
388
388
PINCTRL_PIN_FUNCTION("eth", mt7629_ethernet),
389
389
PINCTRL_PIN_FUNCTION("i2c", mt7629_i2c),
390
390
PINCTRL_PIN_FUNCTION("led", mt7629_led),
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7981.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7981.c
···
977
977
"wf0_mode1", "wf0_mode3", "mt7531_int", };
978
978
static const char *mt7981_ant_groups[] = { "ant_sel", };
979
979
980
-
static const struct function_desc mt7981_functions[] = {
980
+
static const struct pinfunction mt7981_functions[] = {
981
981
PINCTRL_PIN_FUNCTION("wa_aice", mt7981_wa_aice),
982
982
PINCTRL_PIN_FUNCTION("dfd", mt7981_dfd),
983
983
PINCTRL_PIN_FUNCTION("jtag", mt7981_jtag),
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7986.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mt7986.c
···
878
878
static const char *mt7986_wdt_groups[] = { "watchdog", };
879
879
static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
880
880
881
-
static const struct function_desc mt7986_functions[] = {
881
+
static const struct pinfunction mt7986_functions[] = {
882
882
PINCTRL_PIN_FUNCTION("audio", mt7986_audio),
883
883
PINCTRL_PIN_FUNCTION("emmc", mt7986_emmc),
884
884
PINCTRL_PIN_FUNCTION("eth", mt7986_ethernet),
+17
-27
drivers/pinctrl/mediatek/pinctrl-mt7988.c
+17
-27
drivers/pinctrl/mediatek/pinctrl-mt7988.c
···
1464
1464
"drv_vbus_p1",
1465
1465
};
1466
1466
1467
-
static const struct function_desc mt7988_functions[] = {
1468
-
{ { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
1469
-
NULL },
1470
-
{ { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
1471
-
NULL },
1472
-
{ { "int_usxgmii", mt7988_int_usxgmii_groups,
1473
-
ARRAY_SIZE(mt7988_int_usxgmii_groups) },
1474
-
NULL },
1475
-
{ { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, NULL },
1476
-
{ { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, NULL },
1477
-
{ { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, NULL },
1478
-
{ { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
1479
-
NULL },
1480
-
{ { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
1481
-
NULL },
1482
-
{ { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
1483
-
NULL },
1484
-
{ { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
1485
-
NULL },
1486
-
{ { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, NULL },
1487
-
{ { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
1488
-
NULL },
1489
-
{ { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
1490
-
NULL },
1491
-
{ { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, NULL },
1492
-
{ { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, NULL },
1493
-
{ { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, NULL },
1467
+
static const struct pinfunction mt7988_functions[] = {
1468
+
PINCTRL_PIN_FUNCTION("audio", mt7988_audio),
1469
+
PINCTRL_PIN_FUNCTION("jtag", mt7988_jtag),
1470
+
PINCTRL_PIN_FUNCTION("int_usxgmii", mt7988_int_usxgmii),
1471
+
PINCTRL_PIN_FUNCTION("pwm", mt7988_pwm),
1472
+
PINCTRL_PIN_FUNCTION("dfd", mt7988_dfd),
1473
+
PINCTRL_PIN_FUNCTION("i2c", mt7988_i2c),
1474
+
PINCTRL_PIN_FUNCTION("eth", mt7988_ethernet),
1475
+
PINCTRL_PIN_FUNCTION("pcie", mt7988_pcie),
1476
+
PINCTRL_PIN_FUNCTION("pmic", mt7988_pmic),
1477
+
PINCTRL_PIN_FUNCTION("watchdog", mt7988_wdt),
1478
+
PINCTRL_PIN_FUNCTION("spi", mt7988_spi),
1479
+
PINCTRL_PIN_FUNCTION("flash", mt7988_flash),
1480
+
PINCTRL_PIN_FUNCTION("uart", mt7988_uart),
1481
+
PINCTRL_PIN_FUNCTION("udi", mt7988_udi),
1482
+
PINCTRL_PIN_FUNCTION("usb", mt7988_usb),
1483
+
PINCTRL_PIN_FUNCTION("led", mt7988_led),
1494
1484
};
1495
1485
1496
1486
static const struct mtk_eint_hw mt7988_eint_hw = {
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
384
384
mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
385
385
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
386
386
break;
387
-
case PIN_CONFIG_OUTPUT:
387
+
case PIN_CONFIG_LEVEL:
388
388
mtk_gpio_set(pctl->chip, pin, arg);
389
389
ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
390
390
break;
+2
-2
drivers/pinctrl/mediatek/pinctrl-paris.c
+2
-2
drivers/pinctrl/mediatek/pinctrl-paris.c
···
169
169
if (!ret)
170
170
err = -EINVAL;
171
171
break;
172
-
case PIN_CONFIG_OUTPUT:
172
+
case PIN_CONFIG_LEVEL:
173
173
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
174
174
if (err)
175
175
break;
···
292
292
/* regard all non-zero value as enable */
293
293
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
294
294
break;
295
-
case PIN_CONFIG_OUTPUT:
295
+
case PIN_CONFIG_LEVEL:
296
296
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
297
297
arg);
298
298
if (err)
+3
-3
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
+3
-3
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
···
422
422
return -EINVAL;
423
423
arg = 1;
424
424
break;
425
-
case PIN_CONFIG_OUTPUT:
425
+
case PIN_CONFIG_LEVEL:
426
426
ret = aml_pinconf_get_output(info, pin);
427
427
if (ret <= 0)
428
428
return -EINVAL;
···
568
568
switch (param) {
569
569
case PIN_CONFIG_DRIVE_STRENGTH_UA:
570
570
case PIN_CONFIG_OUTPUT_ENABLE:
571
-
case PIN_CONFIG_OUTPUT:
571
+
case PIN_CONFIG_LEVEL:
572
572
arg = pinconf_to_config_argument(configs[i]);
573
573
break;
574
574
···
592
592
case PIN_CONFIG_OUTPUT_ENABLE:
593
593
ret = aml_pinconf_set_output(info, pin, arg);
594
594
break;
595
-
case PIN_CONFIG_OUTPUT:
595
+
case PIN_CONFIG_LEVEL:
596
596
ret = aml_pinconf_set_output_drive(info, pin, arg);
597
597
break;
598
598
default:
+8
drivers/pinctrl/meson/pinctrl-meson-g12a.c
+8
drivers/pinctrl/meson/pinctrl-meson-g12a.c
···
442
442
static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 };
443
443
static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 };
444
444
445
+
static const unsigned int pcie_clkreqn_pins[] = { GPIOC_7 };
446
+
445
447
static const struct meson_pmx_group meson_g12a_periphs_groups[] = {
446
448
GPIO_GROUP(GPIOZ_0),
447
449
GPIO_GROUP(GPIOZ_1),
···
723
721
GROUP(pdm_din2_c, 4),
724
722
GROUP(pdm_din3_c, 4),
725
723
GROUP(pdm_dclk_c, 4),
724
+
GROUP(pcie_clkreqn, 1),
726
725
727
726
/* bank GPIOH */
728
727
GROUP(spi1_mosi, 3),
···
1186
1183
"tdm_c_dout2_z", "tdm_c_dout3_z",
1187
1184
};
1188
1185
1186
+
static const char * const pcie_clkreqn_groups[] = {
1187
+
"pcie_clkreqn"
1188
+
};
1189
+
1189
1190
static const char * const gpio_aobus_groups[] = {
1190
1191
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
1191
1192
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
···
1316
1309
FUNCTION(tdm_a),
1317
1310
FUNCTION(tdm_b),
1318
1311
FUNCTION(tdm_c),
1312
+
FUNCTION(pcie_clkreqn),
1319
1313
};
1320
1314
1321
1315
static const struct meson_pmx_func meson_g12a_aobus_functions[] = {
+10
drivers/pinctrl/meson/pinctrl-meson-gxl.c
+10
drivers/pinctrl/meson/pinctrl-meson-gxl.c
···
187
187
static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 };
188
188
static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 };
189
189
190
+
static const unsigned int i2c_sck_d_pins[] = { GPIOX_11 };
191
+
static const unsigned int i2c_sda_d_pins[] = { GPIOX_10 };
192
+
190
193
static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
191
194
static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
192
195
static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 };
···
414
411
GPIO_GROUP(GPIO_TEST_N),
415
412
416
413
/* Bank X */
414
+
GROUP(i2c_sda_d, 5, 5),
415
+
GROUP(i2c_sck_d, 5, 4),
417
416
GROUP(sdio_d0, 5, 31),
418
417
GROUP(sdio_d1, 5, 30),
419
418
GROUP(sdio_d2, 5, 29),
···
656
651
"i2c_sck_c", "i2c_sda_c", "i2c_sda_c_dv18", "i2c_sck_c_dv19",
657
652
};
658
653
654
+
static const char * const i2c_d_groups[] = {
655
+
"i2c_sck_d", "i2c_sda_d",
656
+
};
657
+
659
658
static const char * const eth_groups[] = {
660
659
"eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
661
660
"eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
···
786
777
FUNCTION(i2c_a),
787
778
FUNCTION(i2c_b),
788
779
FUNCTION(i2c_c),
780
+
FUNCTION(i2c_d),
789
781
FUNCTION(eth),
790
782
FUNCTION(pwm_a),
791
783
FUNCTION(pwm_b),
+3
-3
drivers/pinctrl/meson/pinctrl-meson.c
+3
-3
drivers/pinctrl/meson/pinctrl-meson.c
···
360
360
switch (param) {
361
361
case PIN_CONFIG_DRIVE_STRENGTH_UA:
362
362
case PIN_CONFIG_OUTPUT_ENABLE:
363
-
case PIN_CONFIG_OUTPUT:
363
+
case PIN_CONFIG_LEVEL:
364
364
arg = pinconf_to_config_argument(configs[i]);
365
365
break;
366
366
···
384
384
case PIN_CONFIG_OUTPUT_ENABLE:
385
385
ret = meson_pinconf_set_output(pc, pin, arg);
386
386
break;
387
-
case PIN_CONFIG_OUTPUT:
387
+
case PIN_CONFIG_LEVEL:
388
388
ret = meson_pinconf_set_output_drive(pc, pin, arg);
389
389
break;
390
390
default:
···
502
502
return -EINVAL;
503
503
arg = 1;
504
504
break;
505
-
case PIN_CONFIG_OUTPUT:
505
+
case PIN_CONFIG_LEVEL:
506
506
ret = meson_pinconf_get_output(pc, pin);
507
507
if (ret <= 0)
508
508
return -EINVAL;
+4
-2
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+4
-2
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
···
420
420
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
421
421
unsigned int en_offset = offset;
422
422
unsigned int reg = OUTPUT_VAL;
423
-
unsigned int mask, val, ret;
423
+
unsigned int mask, val;
424
+
int ret;
424
425
425
426
armada_37xx_update_reg(®, &offset);
426
427
mask = BIT(offset);
···
635
634
{
636
635
u32 reg_idx = pin_idx / GPIO_PER_REG;
637
636
u32 bit_num = pin_idx % GPIO_PER_REG;
638
-
u32 p, l, ret;
639
637
unsigned long flags;
638
+
u32 p, l;
639
+
int ret;
640
640
641
641
regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
642
642
+3
-3
drivers/pinctrl/nomadik/pinctrl-abx500.c
+3
-3
drivers/pinctrl/nomadik/pinctrl-abx500.c
···
860
860
861
861
dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
862
862
pin, configs[i],
863
-
(param == PIN_CONFIG_OUTPUT) ? "output " : "input",
864
-
(param == PIN_CONFIG_OUTPUT) ?
863
+
(param == PIN_CONFIG_LEVEL) ? "output " : "input",
864
+
(param == PIN_CONFIG_LEVEL) ?
865
865
str_high_low(argument) :
866
866
(argument ? "pull up" : "pull down"));
867
867
···
907
907
ret = abx500_gpio_direction_input(chip, offset);
908
908
break;
909
909
910
-
case PIN_CONFIG_OUTPUT:
910
+
case PIN_CONFIG_LEVEL:
911
911
ret = abx500_gpio_direction_output(chip, offset,
912
912
argument);
913
913
break;
+2
-1
drivers/pinctrl/nuvoton/pinctrl-ma35.c
+2
-1
drivers/pinctrl/nuvoton/pinctrl-ma35.c
+4
-4
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+4
-4
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
···
1700
1700
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1701
1701
rc = (!pu && pd);
1702
1702
break;
1703
-
case PIN_CONFIG_OUTPUT:
1703
+
case PIN_CONFIG_LEVEL:
1704
1704
case PIN_CONFIG_INPUT_ENABLE:
1705
1705
ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
1706
1706
oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
1707
1707
if (param == PIN_CONFIG_INPUT_ENABLE)
1708
1708
rc = (ie && !oe);
1709
-
else if (param == PIN_CONFIG_OUTPUT)
1709
+
else if (param == PIN_CONFIG_LEVEL)
1710
1710
rc = (!ie && oe);
1711
1711
break;
1712
1712
case PIN_CONFIG_DRIVE_PUSH_PULL:
···
1765
1765
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1766
1766
bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
1767
1767
break;
1768
-
case PIN_CONFIG_OUTPUT:
1768
+
case PIN_CONFIG_LEVEL:
1769
1769
bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
1770
1770
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1771
1771
break;
···
1836
1836
if (!pctrl->gpio_bank[id].base)
1837
1837
return -EINVAL;
1838
1838
1839
-
config = (typeof(config)){
1839
+
config = (struct gpio_generic_chip_config) {
1840
1840
.dev = dev,
1841
1841
.sz = 4,
1842
1842
.dat = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,
+4
-4
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+4
-4
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
···
2187
2187
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
2188
2188
rc = !pu && pd;
2189
2189
break;
2190
-
case PIN_CONFIG_OUTPUT:
2190
+
case PIN_CONFIG_LEVEL:
2191
2191
case PIN_CONFIG_INPUT_ENABLE:
2192
2192
ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
2193
2193
oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
2194
2194
if (param == PIN_CONFIG_INPUT_ENABLE)
2195
2195
rc = (ie && !oe);
2196
-
else if (param == PIN_CONFIG_OUTPUT)
2196
+
else if (param == PIN_CONFIG_LEVEL)
2197
2197
rc = (!ie && oe);
2198
2198
break;
2199
2199
case PIN_CONFIG_DRIVE_PUSH_PULL:
···
2251
2251
iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2252
2252
bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
2253
2253
break;
2254
-
case PIN_CONFIG_OUTPUT:
2254
+
case PIN_CONFIG_LEVEL:
2255
2255
bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
2256
2256
iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2257
2257
break;
···
2329
2329
if (!pctrl->gpio_bank[id].base)
2330
2330
return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id);
2331
2331
2332
-
config = (typeof(config)){
2332
+
config = (struct gpio_generic_chip_config) {
2333
2333
.dev = dev,
2334
2334
.sz = 4,
2335
2335
.dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
+1
-1
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+1
-1
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+3
-3
drivers/pinctrl/pinconf-generic.c
+3
-3
drivers/pinctrl/pinconf-generic.c
···
48
48
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
49
49
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
50
50
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
51
-
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
51
+
PCONFDUMP(PIN_CONFIG_LEVEL, "pin output", "level", true),
52
52
PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true),
53
53
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
54
54
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
···
183
183
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
184
184
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
185
185
{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
186
-
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
186
+
{ "output-high", PIN_CONFIG_LEVEL, 1, },
187
187
{ "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 },
188
-
{ "output-low", PIN_CONFIG_OUTPUT, 0, },
188
+
{ "output-low", PIN_CONFIG_LEVEL, 0, },
189
189
{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
190
190
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
191
191
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
+25
-16
drivers/pinctrl/pinctrl-amd.c
+25
-16
drivers/pinctrl/pinctrl-amd.c
···
383
383
unsigned long flags;
384
384
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
385
385
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
386
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
386
387
387
-
gpiochip_enable_irq(gc, d->hwirq);
388
+
gpiochip_enable_irq(gc, hwirq);
388
389
389
390
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
390
-
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
391
+
pin_reg = readl(gpio_dev->base + hwirq * 4);
391
392
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
392
393
pin_reg |= BIT(INTERRUPT_MASK_OFF);
393
-
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
394
+
writel(pin_reg, gpio_dev->base + hwirq * 4);
394
395
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
395
396
}
396
397
···
401
400
unsigned long flags;
402
401
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403
402
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
403
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
404
404
405
405
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
406
-
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
406
+
pin_reg = readl(gpio_dev->base + hwirq * 4);
407
407
pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
408
408
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
409
-
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
409
+
writel(pin_reg, gpio_dev->base + hwirq * 4);
410
410
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
411
411
412
-
gpiochip_disable_irq(gc, d->hwirq);
412
+
gpiochip_disable_irq(gc, hwirq);
413
413
}
414
414
415
415
static void amd_gpio_irq_mask(struct irq_data *d)
···
419
417
unsigned long flags;
420
418
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
421
419
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
420
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
422
421
423
422
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
424
-
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
423
+
pin_reg = readl(gpio_dev->base + hwirq * 4);
425
424
pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
426
-
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
425
+
writel(pin_reg, gpio_dev->base + hwirq * 4);
427
426
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
428
427
}
429
428
···
434
431
unsigned long flags;
435
432
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
436
433
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
434
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
437
435
438
436
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
439
-
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
437
+
pin_reg = readl(gpio_dev->base + hwirq * 4);
440
438
pin_reg |= BIT(INTERRUPT_MASK_OFF);
441
-
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
439
+
writel(pin_reg, gpio_dev->base + hwirq * 4);
442
440
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
443
441
}
444
442
···
450
446
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
451
447
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
452
448
u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
449
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
453
450
int err;
454
451
452
+
pm_pr_dbg("Setting wake for GPIO %lu to %s\n",
453
+
hwirq, str_enable_disable(on));
454
+
455
455
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
456
-
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
456
+
pin_reg = readl(gpio_dev->base + hwirq * 4);
457
457
458
458
if (on)
459
459
pin_reg |= wake_mask;
460
460
else
461
461
pin_reg &= ~wake_mask;
462
462
463
-
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
463
+
writel(pin_reg, gpio_dev->base + hwirq * 4);
464
464
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
465
465
466
466
if (on)
···
500
492
unsigned long flags;
501
493
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
502
494
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
495
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
503
496
504
497
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
505
-
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
498
+
pin_reg = readl(gpio_dev->base + hwirq * 4);
506
499
507
500
switch (type & IRQ_TYPE_SENSE_MASK) {
508
501
case IRQ_TYPE_EDGE_RISING:
···
569
560
pin_reg_irq_en = pin_reg;
570
561
pin_reg_irq_en |= mask;
571
562
pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
572
-
writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
573
-
while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
563
+
writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
564
+
while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask)
574
565
continue;
575
-
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
566
+
writel(pin_reg, gpio_dev->base + hwirq * 4);
576
567
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
577
568
578
569
return ret;
+1
-1
drivers/pinctrl/pinctrl-at91-pio4.c
+1
-1
drivers/pinctrl/pinctrl-at91-pio4.c
+3
-3
drivers/pinctrl/pinctrl-aw9523.c
+3
-3
drivers/pinctrl/pinctrl-aw9523.c
···
215
215
case PIN_CONFIG_OUTPUT_ENABLE:
216
216
reg = AW9523_REG_CONF_STATE(pin);
217
217
break;
218
-
case PIN_CONFIG_OUTPUT:
218
+
case PIN_CONFIG_LEVEL:
219
219
reg = AW9523_REG_OUT_STATE(pin);
220
220
break;
221
221
default:
···
249
249
switch (param) {
250
250
case PIN_CONFIG_BIAS_PULL_UP:
251
251
case PIN_CONFIG_INPUT_ENABLE:
252
-
case PIN_CONFIG_OUTPUT:
252
+
case PIN_CONFIG_LEVEL:
253
253
val &= BIT(regbit);
254
254
break;
255
255
case PIN_CONFIG_BIAS_PULL_DOWN:
···
301
301
goto end;
302
302
303
303
switch (param) {
304
-
case PIN_CONFIG_OUTPUT:
304
+
case PIN_CONFIG_LEVEL:
305
305
/* First, enable pin output */
306
306
rc = regmap_update_bits(awi->regmap,
307
307
AW9523_REG_CONF_STATE(pin),
+1
-1
drivers/pinctrl/pinctrl-cy8c95x0.c
+1
-1
drivers/pinctrl/pinctrl-cy8c95x0.c
+1
-1
drivers/pinctrl/pinctrl-eic7700.c
+1
-1
drivers/pinctrl/pinctrl-eic7700.c
+3
-3
drivers/pinctrl/pinctrl-equilibrium.c
+3
-3
drivers/pinctrl/pinctrl-equilibrium.c
···
241
241
}
242
242
raw_spin_lock_init(&gctrl->lock);
243
243
244
-
config = (typeof(config)){
244
+
config = (struct gpio_generic_chip_config) {
245
245
.dev = dev,
246
246
.sz = gctrl->bank->nr_pins / 8,
247
247
.dat = gctrl->membase + GPIO_IN,
···
325
325
unsigned int selector, unsigned int group)
326
326
{
327
327
struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
328
-
struct function_desc *func;
328
+
const struct function_desc *func;
329
329
struct group_desc *grp;
330
330
unsigned int *pinmux;
331
331
int i;
···
445
445
}
446
446
raw_spin_unlock_irqrestore(&pctl->lock, flags);
447
447
*config = pinconf_to_config_packed(param, val);
448
-
;
448
+
449
449
return 0;
450
450
}
451
451
+24
-29
drivers/pinctrl/pinctrl-ingenic.c
+24
-29
drivers/pinctrl/pinctrl-ingenic.c
···
96
96
.data = (void *)func, \
97
97
}
98
98
99
-
#define INGENIC_PIN_FUNCTION(_name_, id) \
100
-
{ \
101
-
.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
102
-
.data = NULL, \
103
-
}
99
+
#define INGENIC_PIN_FUNCTION(_name_, id) \
100
+
PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups))
104
101
105
102
enum jz_version {
106
103
ID_JZ4730,
···
125
128
const struct group_desc *groups;
126
129
unsigned int num_groups;
127
130
128
-
const struct function_desc *functions;
131
+
const struct pinfunction *functions;
129
132
unsigned int num_functions;
130
133
131
134
const u32 *pull_ups, *pull_downs;
···
260
263
static const char *jz4730_mii_groups[] = { "mii", };
261
264
static const char *jz4730_i2s_groups[] = { "i2s-data", "i2s-master", "i2s-slave", };
262
265
263
-
static const struct function_desc jz4730_functions[] = {
266
+
static const struct pinfunction jz4730_functions[] = {
264
267
INGENIC_PIN_FUNCTION("mmc", jz4730_mmc),
265
268
INGENIC_PIN_FUNCTION("uart0", jz4730_uart0),
266
269
INGENIC_PIN_FUNCTION("uart1", jz4730_uart1),
···
367
370
static const char *jz4740_pwm6_groups[] = { "pwm6", };
368
371
static const char *jz4740_pwm7_groups[] = { "pwm7", };
369
372
370
-
static const struct function_desc jz4740_functions[] = {
373
+
static const struct pinfunction jz4740_functions[] = {
371
374
INGENIC_PIN_FUNCTION("mmc", jz4740_mmc),
372
375
INGENIC_PIN_FUNCTION("uart0", jz4740_uart0),
373
376
INGENIC_PIN_FUNCTION("uart1", jz4740_uart1),
···
471
474
static const char *jz4725b_pwm4_groups[] = { "pwm4", };
472
475
static const char *jz4725b_pwm5_groups[] = { "pwm5", };
473
476
474
-
static const struct function_desc jz4725b_functions[] = {
477
+
static const struct pinfunction jz4725b_functions[] = {
475
478
INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0),
476
479
INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1),
477
480
INGENIC_PIN_FUNCTION("uart", jz4725b_uart),
···
603
606
static const char *jz4750_pwm4_groups[] = { "pwm4", };
604
607
static const char *jz4750_pwm5_groups[] = { "pwm5", };
605
608
606
-
static const struct function_desc jz4750_functions[] = {
609
+
static const struct pinfunction jz4750_functions[] = {
607
610
INGENIC_PIN_FUNCTION("uart0", jz4750_uart0),
608
611
INGENIC_PIN_FUNCTION("uart1", jz4750_uart1),
609
612
INGENIC_PIN_FUNCTION("uart2", jz4750_uart2),
···
768
771
static const char *jz4755_pwm4_groups[] = { "pwm4", };
769
772
static const char *jz4755_pwm5_groups[] = { "pwm5", };
770
773
771
-
static const struct function_desc jz4755_functions[] = {
774
+
static const struct pinfunction jz4755_functions[] = {
772
775
INGENIC_PIN_FUNCTION("uart0", jz4755_uart0),
773
776
INGENIC_PIN_FUNCTION("uart1", jz4755_uart1),
774
777
INGENIC_PIN_FUNCTION("uart2", jz4755_uart2),
···
1103
1106
static const char *jz4760_pwm7_groups[] = { "pwm7", };
1104
1107
static const char *jz4760_otg_groups[] = { "otg-vbus", };
1105
1108
1106
-
static const struct function_desc jz4760_functions[] = {
1109
+
static const struct pinfunction jz4760_functions[] = {
1107
1110
INGENIC_PIN_FUNCTION("uart0", jz4760_uart0),
1108
1111
INGENIC_PIN_FUNCTION("uart1", jz4760_uart1),
1109
1112
INGENIC_PIN_FUNCTION("uart2", jz4760_uart2),
···
1441
1444
static const char *jz4770_pwm7_groups[] = { "pwm7", };
1442
1445
static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1443
1446
1444
-
static const struct function_desc jz4770_functions[] = {
1447
+
static const struct pinfunction jz4770_functions[] = {
1445
1448
INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1446
1449
INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1447
1450
INGENIC_PIN_FUNCTION("uart2", jz4770_uart2),
···
1720
1723
};
1721
1724
static const char *jz4775_otg_groups[] = { "otg-vbus", };
1722
1725
1723
-
static const struct function_desc jz4775_functions[] = {
1726
+
static const struct pinfunction jz4775_functions[] = {
1724
1727
INGENIC_PIN_FUNCTION("uart0", jz4775_uart0),
1725
1728
INGENIC_PIN_FUNCTION("uart1", jz4775_uart1),
1726
1729
INGENIC_PIN_FUNCTION("uart2", jz4775_uart2),
···
1973
1976
static const char *jz4780_cim_groups[] = { "cim-data", };
1974
1977
static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1975
1978
1976
-
static const struct function_desc jz4780_functions[] = {
1979
+
static const struct pinfunction jz4780_functions[] = {
1977
1980
INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1978
1981
INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1979
1982
INGENIC_PIN_FUNCTION("uart2", jz4780_uart2),
···
2208
2211
static const char *x1000_pwm4_groups[] = { "pwm4", };
2209
2212
static const char *x1000_mac_groups[] = { "mac", };
2210
2213
2211
-
static const struct function_desc x1000_functions[] = {
2214
+
static const struct pinfunction x1000_functions[] = {
2212
2215
INGENIC_PIN_FUNCTION("uart0", x1000_uart0),
2213
2216
INGENIC_PIN_FUNCTION("uart1", x1000_uart1),
2214
2217
INGENIC_PIN_FUNCTION("uart2", x1000_uart2),
···
2338
2341
static const char *x1500_pwm3_groups[] = { "pwm3", };
2339
2342
static const char *x1500_pwm4_groups[] = { "pwm4", };
2340
2343
2341
-
static const struct function_desc x1500_functions[] = {
2344
+
static const struct pinfunction x1500_functions[] = {
2342
2345
INGENIC_PIN_FUNCTION("uart0", x1500_uart0),
2343
2346
INGENIC_PIN_FUNCTION("uart1", x1500_uart1),
2344
2347
INGENIC_PIN_FUNCTION("uart2", x1500_uart2),
···
2559
2562
2560
2563
static const char * const x1600_mac_groups[] = { "mac", };
2561
2564
2562
-
static const struct function_desc x1600_functions[] = {
2565
+
static const struct pinfunction x1600_functions[] = {
2563
2566
INGENIC_PIN_FUNCTION("uart0", x1600_uart0),
2564
2567
INGENIC_PIN_FUNCTION("uart1", x1600_uart1),
2565
2568
INGENIC_PIN_FUNCTION("uart2", x1600_uart2),
···
2776
2779
static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2777
2780
static const char *x1830_mac_groups[] = { "mac", };
2778
2781
2779
-
static const struct function_desc x1830_functions[] = {
2782
+
static const struct pinfunction x1830_functions[] = {
2780
2783
INGENIC_PIN_FUNCTION("uart0", x1830_uart0),
2781
2784
INGENIC_PIN_FUNCTION("uart1", x1830_uart1),
2782
2785
INGENIC_PIN_FUNCTION("sfc", x1830_sfc),
···
3222
3225
static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
3223
3226
static const char *x2000_otg_groups[] = { "otg-vbus", };
3224
3227
3225
-
static const struct function_desc x2000_functions[] = {
3228
+
static const struct pinfunction x2000_functions[] = {
3226
3229
INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
3227
3230
INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
3228
3231
INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
···
3446
3449
3447
3450
static const char *x2100_mac_groups[] = { "mac", };
3448
3451
3449
-
static const struct function_desc x2100_functions[] = {
3452
+
static const struct pinfunction x2100_functions[] = {
3450
3453
INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
3451
3454
INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
3452
3455
INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
···
4000
4003
unsigned int selector, unsigned int group)
4001
4004
{
4002
4005
struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
4003
-
struct function_desc *func;
4006
+
const struct function_desc *func;
4004
4007
struct group_desc *grp;
4005
4008
unsigned int i;
4006
4009
uintptr_t mode;
···
4015
4018
return -EINVAL;
4016
4019
4017
4020
dev_dbg(pctldev->dev, "enable function %s group %s\n",
4018
-
func->func.name, grp->grp.name);
4021
+
func->func->name, grp->grp.name);
4019
4022
4020
4023
mode = (uintptr_t)grp->data;
4021
4024
if (mode <= 3) {
···
4264
4267
case PIN_CONFIG_BIAS_PULL_UP:
4265
4268
case PIN_CONFIG_BIAS_PULL_DOWN:
4266
4269
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4267
-
case PIN_CONFIG_OUTPUT:
4270
+
case PIN_CONFIG_LEVEL:
4268
4271
case PIN_CONFIG_SLEW_RATE:
4269
4272
continue;
4270
4273
default:
···
4305
4308
ingenic_set_schmitt_trigger(jzpc, pin, arg);
4306
4309
break;
4307
4310
4308
-
case PIN_CONFIG_OUTPUT:
4311
+
case PIN_CONFIG_LEVEL:
4309
4312
ret = pinctrl_gpio_direction_output(jzpc->gc,
4310
4313
pin - jzpc->gc->base);
4311
4314
if (ret)
···
4568
4571
}
4569
4572
4570
4573
for (i = 0; i < chip_info->num_functions; i++) {
4571
-
const struct function_desc *function = &chip_info->functions[i];
4572
-
const struct pinfunction *func = &function->func;
4574
+
const struct pinfunction *func = &chip_info->functions[i];
4573
4575
4574
-
err = pinmux_generic_add_pinfunction(jzpc->pctl, func,
4575
-
function->data);
4576
+
err = pinmux_generic_add_pinfunction(jzpc->pctl, func, NULL);
4576
4577
if (err < 0) {
4577
4578
dev_err(dev, "Failed to register function %s\n", func->name);
4578
4579
return err;
+1
-1
drivers/pinctrl/pinctrl-k210.c
+1
-1
drivers/pinctrl/pinctrl-k210.c
+18
-12
drivers/pinctrl/pinctrl-keembay.c
+18
-12
drivers/pinctrl/pinctrl-keembay.c
···
135
135
const struct pinctrl_pin_desc *pins;
136
136
};
137
137
138
+
struct keembay_pinfunction {
139
+
struct pinfunction func;
140
+
u8 mux_mode;
141
+
};
142
+
138
143
static const struct pinctrl_pin_desc keembay_pins[] = {
139
144
KEEMBAY_PIN_DESC(0, "GPIO0",
140
145
KEEMBAY_MUX(0x0, "I2S0_M0"),
···
935
930
unsigned int grp_sel)
936
931
{
937
932
struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
938
-
struct function_desc *func;
933
+
const struct function_desc *func;
939
934
struct group_desc *grp;
940
935
unsigned int val;
941
936
u8 pin_mode;
···
1561
1556
}
1562
1557
1563
1558
static int keembay_add_functions(struct keembay_pinctrl *kpc,
1564
-
struct function_desc *functions)
1559
+
struct keembay_pinfunction *functions)
1565
1560
{
1566
1561
unsigned int i;
1567
1562
1568
1563
/* Assign the groups for each function */
1569
1564
for (i = 0; i < kpc->nfuncs; i++) {
1570
-
struct function_desc *func = &functions[i];
1565
+
struct keembay_pinfunction *func = &functions[i];
1571
1566
const char **group_names;
1572
1567
unsigned int grp_idx = 0;
1573
1568
int j;
···
1593
1588
/* Add all functions */
1594
1589
for (i = 0; i < kpc->nfuncs; i++)
1595
1590
pinmux_generic_add_pinfunction(kpc->pctrl, &functions[i].func,
1596
-
functions[i].data);
1591
+
&functions[i].mux_mode);
1597
1592
1598
1593
return 0;
1599
1594
}
1600
1595
1601
1596
static int keembay_build_functions(struct keembay_pinctrl *kpc)
1602
1597
{
1603
-
struct function_desc *keembay_funcs, *new_funcs;
1598
+
struct keembay_pinfunction *keembay_funcs, *new_funcs;
1604
1599
int i;
1605
1600
1606
1601
/*
···
1608
1603
* being part of 8 (hw maximum) globally unique muxes.
1609
1604
*/
1610
1605
kpc->nfuncs = 0;
1611
-
keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL);
1606
+
keembay_funcs = devm_kcalloc(kpc->dev, kpc->npins * 8,
1607
+
sizeof(*keembay_funcs), GFP_KERNEL);
1612
1608
if (!keembay_funcs)
1613
1609
return -ENOMEM;
1614
1610
···
1619
1613
struct keembay_mux_desc *mux;
1620
1614
1621
1615
for (mux = pdesc->drv_data; mux->name; mux++) {
1622
-
struct function_desc *fdesc;
1616
+
struct keembay_pinfunction *fdesc;
1623
1617
1624
1618
/* Check if we already have function for this mux */
1625
1619
for (fdesc = keembay_funcs; fdesc->func.name; fdesc++) {
···
1633
1627
if (!fdesc->func.name) {
1634
1628
fdesc->func.name = mux->name;
1635
1629
fdesc->func.ngroups = 1;
1636
-
fdesc->data = &mux->mode;
1630
+
fdesc->mux_mode = mux->mode;
1637
1631
kpc->nfuncs++;
1638
1632
}
1639
1633
}
1640
1634
}
1641
1635
1642
1636
/* Reallocate memory based on actual number of functions */
1643
-
new_funcs = krealloc(keembay_funcs, kpc->nfuncs * sizeof(*new_funcs), GFP_KERNEL);
1644
-
if (!new_funcs) {
1645
-
kfree(keembay_funcs);
1637
+
new_funcs = devm_krealloc_array(kpc->dev, keembay_funcs,
1638
+
kpc->nfuncs, sizeof(*new_funcs),
1639
+
GFP_KERNEL);
1640
+
if (!new_funcs)
1646
1641
return -ENOMEM;
1647
-
}
1648
1642
1649
1643
return keembay_add_functions(kpc, new_funcs);
1650
1644
}
+3
-3
drivers/pinctrl/pinctrl-microchip-sgpio.c
+3
-3
drivers/pinctrl/pinctrl-microchip-sgpio.c
···
371
371
val = !bank->is_input;
372
372
break;
373
373
374
-
case PIN_CONFIG_OUTPUT:
374
+
case PIN_CONFIG_LEVEL:
375
375
if (bank->is_input)
376
376
return -EINVAL;
377
377
val = sgpio_output_get(priv, &addr);
···
402
402
arg = pinconf_to_config_argument(configs[cfg]);
403
403
404
404
switch (param) {
405
-
case PIN_CONFIG_OUTPUT:
405
+
case PIN_CONFIG_LEVEL:
406
406
if (bank->is_input)
407
407
return -EINVAL;
408
408
err = sgpio_output_set(priv, &addr, arg);
···
824
824
pctl_desc->confops = &sgpio_confops;
825
825
pctl_desc->owner = THIS_MODULE;
826
826
827
-
pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
827
+
pins = devm_kcalloc(dev, ngpios, sizeof(*pins), GFP_KERNEL);
828
828
if (!pins)
829
829
return -ENOMEM;
830
830
+2
-2
drivers/pinctrl/pinctrl-ocelot.c
+2
-2
drivers/pinctrl/pinctrl-ocelot.c
···
1656
1656
return err;
1657
1657
break;
1658
1658
1659
-
case PIN_CONFIG_OUTPUT:
1659
+
case PIN_CONFIG_LEVEL:
1660
1660
err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
1661
1661
&val);
1662
1662
if (err)
···
1735
1735
1736
1736
case PIN_CONFIG_OUTPUT_ENABLE:
1737
1737
case PIN_CONFIG_INPUT_ENABLE:
1738
-
case PIN_CONFIG_OUTPUT:
1738
+
case PIN_CONFIG_LEVEL:
1739
1739
p = pin % 32;
1740
1740
if (arg)
1741
1741
regmap_write(info->map,
+2
-2
drivers/pinctrl/pinctrl-pic32.c
+2
-2
drivers/pinctrl/pinctrl-pic32.c
···
1905
1905
case PIN_CONFIG_INPUT_ENABLE:
1906
1906
arg = !!(readl(bank->reg_base + TRIS_REG) & mask);
1907
1907
break;
1908
-
case PIN_CONFIG_OUTPUT:
1908
+
case PIN_CONFIG_LEVEL:
1909
1909
arg = !(readl(bank->reg_base + TRIS_REG) & mask);
1910
1910
break;
1911
1911
default:
···
1960
1960
case PIN_CONFIG_INPUT_ENABLE:
1961
1961
pic32_gpio_direction_input(&bank->gpio_chip, offset);
1962
1962
break;
1963
-
case PIN_CONFIG_OUTPUT:
1963
+
case PIN_CONFIG_LEVEL:
1964
1964
pic32_gpio_direction_output(&bank->gpio_chip,
1965
1965
offset, arg);
1966
1966
break;
+2
-2
drivers/pinctrl/pinctrl-rk805.c
+2
-2
drivers/pinctrl/pinctrl-rk805.c
···
541
541
u32 arg = 0;
542
542
543
543
switch (param) {
544
-
case PIN_CONFIG_OUTPUT:
544
+
case PIN_CONFIG_LEVEL:
545
545
case PIN_CONFIG_INPUT_ENABLE:
546
546
arg = rk805_gpio_get(&pci->gpio_chip, pin);
547
547
break;
···
568
568
arg = pinconf_to_config_argument(configs[i]);
569
569
570
570
switch (param) {
571
-
case PIN_CONFIG_OUTPUT:
571
+
case PIN_CONFIG_LEVEL:
572
572
rk805_gpio_set(&pci->gpio_chip, pin, arg);
573
573
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
574
574
break;
+3
-3
drivers/pinctrl/pinctrl-rockchip.c
+3
-3
drivers/pinctrl/pinctrl-rockchip.c
···
3272
3272
param = pinconf_to_config_param(configs[i]);
3273
3273
arg = pinconf_to_config_argument(configs[i]);
3274
3274
3275
-
if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
3275
+
if (param == PIN_CONFIG_LEVEL || param == PIN_CONFIG_INPUT_ENABLE) {
3276
3276
/*
3277
3277
* Check for gpio driver not being probed yet.
3278
3278
* The lock makes sure that either gpio-probe has completed
···
3313
3313
if (rc)
3314
3314
return rc;
3315
3315
break;
3316
-
case PIN_CONFIG_OUTPUT:
3316
+
case PIN_CONFIG_LEVEL:
3317
3317
rc = rockchip_set_mux(bank, pin - bank->pin_base,
3318
3318
RK_FUNC_GPIO);
3319
3319
if (rc != RK_FUNC_GPIO)
···
3392
3392
3393
3393
arg = 1;
3394
3394
break;
3395
-
case PIN_CONFIG_OUTPUT:
3395
+
case PIN_CONFIG_LEVEL:
3396
3396
rc = rockchip_get_mux(bank, pin - bank->pin_base);
3397
3397
if (rc != RK_FUNC_GPIO)
3398
3398
return -EINVAL;
+89
-7
drivers/pinctrl/pinctrl-rp1.c
+89
-7
drivers/pinctrl/pinctrl-rp1.c
···
1440
1440
rp1_output_enable(pin, arg);
1441
1441
break;
1442
1442
1443
-
case PIN_CONFIG_OUTPUT:
1443
+
case PIN_CONFIG_LEVEL:
1444
1444
rp1_set_value(pin, arg);
1445
1445
rp1_set_dir(pin, RP1_DIR_OUTPUT);
1446
1446
rp1_set_fsel(pin, RP1_FSEL_GPIO);
···
1623
1623
1624
1624
static struct rp1_pinctrl rp1_pinctrl_data = {};
1625
1625
1626
-
static const struct regmap_config rp1_pinctrl_regmap_cfg = {
1626
+
static const struct regmap_range rp1_gpio_reg_ranges[] = {
1627
+
/* BANK 0 */
1628
+
regmap_reg_range(0x2004, 0x20dc),
1629
+
regmap_reg_range(0x3004, 0x30dc),
1630
+
regmap_reg_range(0x0004, 0x00dc),
1631
+
regmap_reg_range(0x0124, 0x0124),
1632
+
regmap_reg_range(0x211c, 0x211c),
1633
+
regmap_reg_range(0x311c, 0x311c),
1634
+
/* BANK 1 */
1635
+
regmap_reg_range(0x6004, 0x602c),
1636
+
regmap_reg_range(0x7004, 0x702c),
1637
+
regmap_reg_range(0x4004, 0x402c),
1638
+
regmap_reg_range(0x4124, 0x4124),
1639
+
regmap_reg_range(0x611c, 0x611c),
1640
+
regmap_reg_range(0x711c, 0x711c),
1641
+
/* BANK 2 */
1642
+
regmap_reg_range(0xa004, 0xa09c),
1643
+
regmap_reg_range(0xb004, 0xb09c),
1644
+
regmap_reg_range(0x8004, 0x809c),
1645
+
regmap_reg_range(0x8124, 0x8124),
1646
+
regmap_reg_range(0xa11c, 0xa11c),
1647
+
regmap_reg_range(0xb11c, 0xb11c),
1648
+
};
1649
+
1650
+
static const struct regmap_range rp1_rio_reg_ranges[] = {
1651
+
/* BANK 0 */
1652
+
regmap_reg_range(0x2000, 0x2004),
1653
+
regmap_reg_range(0x3000, 0x3004),
1654
+
regmap_reg_range(0x0004, 0x0008),
1655
+
/* BANK 1 */
1656
+
regmap_reg_range(0x6000, 0x6004),
1657
+
regmap_reg_range(0x7000, 0x7004),
1658
+
regmap_reg_range(0x4004, 0x4008),
1659
+
/* BANK 2 */
1660
+
regmap_reg_range(0xa000, 0xa004),
1661
+
regmap_reg_range(0xb000, 0xb004),
1662
+
regmap_reg_range(0x8004, 0x8008),
1663
+
};
1664
+
1665
+
static const struct regmap_range rp1_pads_reg_ranges[] = {
1666
+
/* BANK 0 */
1667
+
regmap_reg_range(0x0004, 0x0070),
1668
+
/* BANK 1 */
1669
+
regmap_reg_range(0x4004, 0x4018),
1670
+
/* BANK 2 */
1671
+
regmap_reg_range(0x8004, 0x8050),
1672
+
};
1673
+
1674
+
static const struct regmap_access_table rp1_gpio_reg_table = {
1675
+
.yes_ranges = rp1_gpio_reg_ranges,
1676
+
.n_yes_ranges = ARRAY_SIZE(rp1_gpio_reg_ranges),
1677
+
};
1678
+
1679
+
static const struct regmap_access_table rp1_rio_reg_table = {
1680
+
.yes_ranges = rp1_rio_reg_ranges,
1681
+
.n_yes_ranges = ARRAY_SIZE(rp1_rio_reg_ranges),
1682
+
};
1683
+
1684
+
static const struct regmap_access_table rp1_pads_reg_table = {
1685
+
.yes_ranges = rp1_pads_reg_ranges,
1686
+
.n_yes_ranges = ARRAY_SIZE(rp1_pads_reg_ranges),
1687
+
};
1688
+
1689
+
static const struct regmap_config rp1_pinctrl_gpio_regmap_cfg = {
1627
1690
.reg_bits = 32,
1628
1691
.val_bits = 32,
1629
1692
.reg_stride = 4,
1630
-
.fast_io = true,
1631
-
.name = "rp1-pinctrl",
1693
+
.rd_table = &rp1_gpio_reg_table,
1694
+
.name = "rp1-gpio",
1695
+
.max_register = 0xb11c,
1696
+
};
1697
+
1698
+
static const struct regmap_config rp1_pinctrl_rio_regmap_cfg = {
1699
+
.reg_bits = 32,
1700
+
.val_bits = 32,
1701
+
.reg_stride = 4,
1702
+
.rd_table = &rp1_rio_reg_table,
1703
+
.name = "rp1-rio",
1704
+
.max_register = 0xb004,
1705
+
};
1706
+
1707
+
static const struct regmap_config rp1_pinctrl_pads_regmap_cfg = {
1708
+
.reg_bits = 32,
1709
+
.val_bits = 32,
1710
+
.reg_stride = 4,
1711
+
.rd_table = &rp1_pads_reg_table,
1712
+
.name = "rp1-pads",
1713
+
.max_register = 0x8050,
1632
1714
};
1633
1715
1634
1716
static int rp1_gen_regfield(struct device *dev,
···
1767
1685
return dev_err_probe(dev, PTR_ERR(pc->pads_base), "could not get PADS IO memory\n");
1768
1686
1769
1687
gpio_regmap = devm_regmap_init_mmio(dev, pc->gpio_base,
1770
-
&rp1_pinctrl_regmap_cfg);
1688
+
&rp1_pinctrl_gpio_regmap_cfg);
1771
1689
if (IS_ERR(gpio_regmap))
1772
1690
return dev_err_probe(dev, PTR_ERR(gpio_regmap), "could not init GPIO regmap\n");
1773
1691
1774
1692
rio_regmap = devm_regmap_init_mmio(dev, pc->rio_base,
1775
-
&rp1_pinctrl_regmap_cfg);
1693
+
&rp1_pinctrl_rio_regmap_cfg);
1776
1694
if (IS_ERR(rio_regmap))
1777
1695
return dev_err_probe(dev, PTR_ERR(rio_regmap), "could not init RIO regmap\n");
1778
1696
1779
1697
pads_regmap = devm_regmap_init_mmio(dev, pc->pads_base,
1780
-
&rp1_pinctrl_regmap_cfg);
1698
+
&rp1_pinctrl_pads_regmap_cfg);
1781
1699
if (IS_ERR(pads_regmap))
1782
1700
return dev_err_probe(dev, PTR_ERR(pads_regmap), "could not init PADS regmap\n");
1783
1701
+1
-1
drivers/pinctrl/pinctrl-scmi.c
+1
-1
drivers/pinctrl/pinctrl-scmi.c
+5
-3
drivers/pinctrl/pinctrl-single.c
+5
-3
drivers/pinctrl/pinctrl-single.c
···
336
336
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
337
337
struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
338
338
const struct pinctrl_setting_mux *setting;
339
-
struct function_desc *function;
339
+
const struct function_desc *function;
340
340
unsigned fselector;
341
341
342
342
/* If pin is not described in DTS & enabled, mux_setting is NULL. */
···
360
360
unsigned group)
361
361
{
362
362
struct pcs_device *pcs;
363
-
struct function_desc *function;
363
+
const struct function_desc *function;
364
364
struct pcs_function *func;
365
365
int i;
366
366
···
589
589
/* 4 parameters */
590
590
case PIN_CONFIG_BIAS_PULL_DOWN:
591
591
case PIN_CONFIG_BIAS_PULL_UP:
592
-
if (arg)
592
+
if (arg) {
593
593
pcs_pinconf_clear_bias(pctldev, pin);
594
+
data = pcs->read(pcs->base + offset);
595
+
}
594
596
fallthrough;
595
597
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
596
598
data &= ~func->conf[i].mask;
+2
-2
drivers/pinctrl/pinctrl-stmfx.c
+2
-2
drivers/pinctrl/pinctrl-stmfx.c
···
267
267
if ((!dir && !type) || (dir && type))
268
268
arg = 1;
269
269
break;
270
-
case PIN_CONFIG_OUTPUT:
270
+
case PIN_CONFIG_LEVEL:
271
271
if (dir)
272
272
return -EINVAL;
273
273
···
334
334
if (ret)
335
335
return ret;
336
336
break;
337
-
case PIN_CONFIG_OUTPUT:
337
+
case PIN_CONFIG_LEVEL:
338
338
ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
339
339
pin, arg);
340
340
if (ret)
+8
-4
drivers/pinctrl/pinctrl-sx150x.c
+8
-4
drivers/pinctrl/pinctrl-sx150x.c
···
611
611
if (sx150x_pin_is_oscio(pctl, pin)) {
612
612
switch (param) {
613
613
case PIN_CONFIG_DRIVE_PUSH_PULL:
614
-
case PIN_CONFIG_OUTPUT:
614
+
case PIN_CONFIG_LEVEL:
615
615
ret = regmap_read(pctl->regmap,
616
616
pctl->data->pri.x789.reg_clock,
617
617
&data);
···
705
705
}
706
706
break;
707
707
708
-
case PIN_CONFIG_OUTPUT:
708
+
case PIN_CONFIG_LEVEL:
709
709
ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
710
710
if (ret < 0)
711
711
return ret;
···
744
744
arg = pinconf_to_config_argument(configs[i]);
745
745
746
746
if (sx150x_pin_is_oscio(pctl, pin)) {
747
-
if (param == PIN_CONFIG_OUTPUT) {
747
+
if (param == PIN_CONFIG_LEVEL) {
748
748
ret = sx150x_gpio_direction_output(&pctl->gpio,
749
749
pin, arg);
750
750
if (ret < 0)
···
816
816
817
817
break;
818
818
819
-
case PIN_CONFIG_OUTPUT:
819
+
case PIN_CONFIG_LEVEL:
820
820
ret = sx150x_gpio_direction_output(&pctl->gpio,
821
821
pin, arg);
822
822
if (ret < 0)
···
863
863
{ .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
864
864
{},
865
865
};
866
+
MODULE_DEVICE_TABLE(of, sx150x_of_match);
866
867
867
868
static int sx150x_reset(struct sx150x_pinctrl *pctl)
868
869
{
···
1267
1266
return i2c_add_driver(&sx150x_driver);
1268
1267
}
1269
1268
subsys_initcall(sx150x_init);
1269
+
1270
+
MODULE_DESCRIPTION("Semtech SX150x I2C GPIO expander pinctrl driver");
1271
+
MODULE_LICENSE("GPL");
+1070
drivers/pinctrl/pinctrl-upboard.c
+1070
drivers/pinctrl/pinctrl-upboard.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* UP board pin control driver.
4
+
*
5
+
* Copyright (C) 2025 Bootlin
6
+
*
7
+
* Author: Thomas Richard <thomas.richard@bootlin.com>
8
+
*/
9
+
10
+
#include <linux/array_size.h>
11
+
#include <linux/container_of.h>
12
+
#include <linux/device.h>
13
+
#include <linux/dmi.h>
14
+
#include <linux/err.h>
15
+
#include <linux/gpio/forwarder.h>
16
+
#include <linux/mfd/upboard-fpga.h>
17
+
#include <linux/module.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/seq_file.h>
21
+
#include <linux/stddef.h>
22
+
#include <linux/string_choices.h>
23
+
#include <linux/types.h>
24
+
25
+
#include <linux/pinctrl/consumer.h>
26
+
#include <linux/pinctrl/pinctrl.h>
27
+
#include <linux/pinctrl/pinmux.h>
28
+
29
+
#include <linux/gpio/driver.h>
30
+
#include <linux/gpio/consumer.h>
31
+
32
+
#include "core.h"
33
+
#include "pinmux.h"
34
+
35
+
enum upboard_pin_mode {
36
+
UPBOARD_PIN_MODE_FUNCTION,
37
+
UPBOARD_PIN_MODE_GPIO_IN,
38
+
UPBOARD_PIN_MODE_GPIO_OUT,
39
+
UPBOARD_PIN_MODE_DISABLED,
40
+
};
41
+
42
+
struct upboard_pin {
43
+
struct regmap_field *funcbit;
44
+
struct regmap_field *enbit;
45
+
struct regmap_field *dirbit;
46
+
};
47
+
48
+
struct upboard_pingroup {
49
+
struct pingroup grp;
50
+
enum upboard_pin_mode mode;
51
+
const enum upboard_pin_mode *modes;
52
+
};
53
+
54
+
struct upboard_pinctrl_data {
55
+
const struct upboard_pingroup *groups;
56
+
size_t ngroups;
57
+
const struct pinfunction *funcs;
58
+
size_t nfuncs;
59
+
const unsigned int *pin_header;
60
+
size_t ngpio;
61
+
};
62
+
63
+
struct upboard_pinctrl {
64
+
struct device *dev;
65
+
struct pinctrl_dev *pctldev;
66
+
const struct upboard_pinctrl_data *pctrl_data;
67
+
struct gpio_pin_range pin_range;
68
+
struct upboard_pin *pins;
69
+
};
70
+
71
+
struct upboard_pinctrl_map {
72
+
const struct pinctrl_map *maps;
73
+
size_t nmaps;
74
+
};
75
+
76
+
enum upboard_func0_fpgabit {
77
+
UPBOARD_FUNC_I2C0_EN = 8,
78
+
UPBOARD_FUNC_I2C1_EN = 9,
79
+
UPBOARD_FUNC_CEC0_EN = 12,
80
+
UPBOARD_FUNC_ADC0_EN = 14,
81
+
};
82
+
83
+
static const struct reg_field upboard_i2c0_reg =
84
+
REG_FIELD(UPBOARD_REG_FUNC_EN0, UPBOARD_FUNC_I2C0_EN, UPBOARD_FUNC_I2C0_EN);
85
+
86
+
static const struct reg_field upboard_i2c1_reg =
87
+
REG_FIELD(UPBOARD_REG_FUNC_EN0, UPBOARD_FUNC_I2C1_EN, UPBOARD_FUNC_I2C1_EN);
88
+
89
+
static const struct reg_field upboard_adc0_reg =
90
+
REG_FIELD(UPBOARD_REG_FUNC_EN0, UPBOARD_FUNC_ADC0_EN, UPBOARD_FUNC_ADC0_EN);
91
+
92
+
#define UPBOARD_UP_BIT_TO_PIN(bit) UPBOARD_UP_BIT_##bit
93
+
94
+
#define UPBOARD_UP_PIN_NAME(id) \
95
+
{ \
96
+
.number = UPBOARD_UP_BIT_##id, \
97
+
.name = #id, \
98
+
}
99
+
100
+
#define UPBOARD_UP_PIN_MUX(bit, data) \
101
+
{ \
102
+
.number = UPBOARD_UP_BIT_##bit, \
103
+
.name = "PINMUX_"#bit, \
104
+
.drv_data = (void *)(data), \
105
+
}
106
+
107
+
#define UPBOARD_UP_PIN_FUNC(id, data) \
108
+
{ \
109
+
.number = UPBOARD_UP_BIT_##id, \
110
+
.name = #id, \
111
+
.drv_data = (void *)(data), \
112
+
}
113
+
114
+
enum upboard_up_fpgabit {
115
+
UPBOARD_UP_BIT_I2C1_SDA,
116
+
UPBOARD_UP_BIT_I2C1_SCL,
117
+
UPBOARD_UP_BIT_ADC0,
118
+
UPBOARD_UP_BIT_UART1_RTS,
119
+
UPBOARD_UP_BIT_GPIO27,
120
+
UPBOARD_UP_BIT_GPIO22,
121
+
UPBOARD_UP_BIT_SPI_MOSI,
122
+
UPBOARD_UP_BIT_SPI_MISO,
123
+
UPBOARD_UP_BIT_SPI_CLK,
124
+
UPBOARD_UP_BIT_I2C0_SDA,
125
+
UPBOARD_UP_BIT_GPIO5,
126
+
UPBOARD_UP_BIT_GPIO6,
127
+
UPBOARD_UP_BIT_PWM1,
128
+
UPBOARD_UP_BIT_I2S_FRM,
129
+
UPBOARD_UP_BIT_GPIO26,
130
+
UPBOARD_UP_BIT_UART1_TX,
131
+
UPBOARD_UP_BIT_UART1_RX,
132
+
UPBOARD_UP_BIT_I2S_CLK,
133
+
UPBOARD_UP_BIT_GPIO23,
134
+
UPBOARD_UP_BIT_GPIO24,
135
+
UPBOARD_UP_BIT_GPIO25,
136
+
UPBOARD_UP_BIT_SPI_CS0,
137
+
UPBOARD_UP_BIT_SPI_CS1,
138
+
UPBOARD_UP_BIT_I2C0_SCL,
139
+
UPBOARD_UP_BIT_PWM0,
140
+
UPBOARD_UP_BIT_UART1_CTS,
141
+
UPBOARD_UP_BIT_I2S_DIN,
142
+
UPBOARD_UP_BIT_I2S_DOUT,
143
+
};
144
+
145
+
static const struct pinctrl_pin_desc upboard_up_pins[] = {
146
+
UPBOARD_UP_PIN_FUNC(I2C1_SDA, &upboard_i2c1_reg),
147
+
UPBOARD_UP_PIN_FUNC(I2C1_SCL, &upboard_i2c1_reg),
148
+
UPBOARD_UP_PIN_FUNC(ADC0, &upboard_adc0_reg),
149
+
UPBOARD_UP_PIN_NAME(UART1_RTS),
150
+
UPBOARD_UP_PIN_NAME(GPIO27),
151
+
UPBOARD_UP_PIN_NAME(GPIO22),
152
+
UPBOARD_UP_PIN_NAME(SPI_MOSI),
153
+
UPBOARD_UP_PIN_NAME(SPI_MISO),
154
+
UPBOARD_UP_PIN_NAME(SPI_CLK),
155
+
UPBOARD_UP_PIN_FUNC(I2C0_SDA, &upboard_i2c0_reg),
156
+
UPBOARD_UP_PIN_NAME(GPIO5),
157
+
UPBOARD_UP_PIN_NAME(GPIO6),
158
+
UPBOARD_UP_PIN_NAME(PWM1),
159
+
UPBOARD_UP_PIN_NAME(I2S_FRM),
160
+
UPBOARD_UP_PIN_NAME(GPIO26),
161
+
UPBOARD_UP_PIN_NAME(UART1_TX),
162
+
UPBOARD_UP_PIN_NAME(UART1_RX),
163
+
UPBOARD_UP_PIN_NAME(I2S_CLK),
164
+
UPBOARD_UP_PIN_NAME(GPIO23),
165
+
UPBOARD_UP_PIN_NAME(GPIO24),
166
+
UPBOARD_UP_PIN_NAME(GPIO25),
167
+
UPBOARD_UP_PIN_NAME(SPI_CS0),
168
+
UPBOARD_UP_PIN_NAME(SPI_CS1),
169
+
UPBOARD_UP_PIN_FUNC(I2C0_SCL, &upboard_i2c0_reg),
170
+
UPBOARD_UP_PIN_NAME(PWM0),
171
+
UPBOARD_UP_PIN_NAME(UART1_CTS),
172
+
UPBOARD_UP_PIN_NAME(I2S_DIN),
173
+
UPBOARD_UP_PIN_NAME(I2S_DOUT),
174
+
};
175
+
176
+
static const unsigned int upboard_up_pin_header[] = {
177
+
UPBOARD_UP_BIT_TO_PIN(I2C0_SDA),
178
+
UPBOARD_UP_BIT_TO_PIN(I2C0_SCL),
179
+
UPBOARD_UP_BIT_TO_PIN(I2C1_SDA),
180
+
UPBOARD_UP_BIT_TO_PIN(I2C1_SCL),
181
+
UPBOARD_UP_BIT_TO_PIN(ADC0),
182
+
UPBOARD_UP_BIT_TO_PIN(GPIO5),
183
+
UPBOARD_UP_BIT_TO_PIN(GPIO6),
184
+
UPBOARD_UP_BIT_TO_PIN(SPI_CS1),
185
+
UPBOARD_UP_BIT_TO_PIN(SPI_CS0),
186
+
UPBOARD_UP_BIT_TO_PIN(SPI_MISO),
187
+
UPBOARD_UP_BIT_TO_PIN(SPI_MOSI),
188
+
UPBOARD_UP_BIT_TO_PIN(SPI_CLK),
189
+
UPBOARD_UP_BIT_TO_PIN(PWM0),
190
+
UPBOARD_UP_BIT_TO_PIN(PWM1),
191
+
UPBOARD_UP_BIT_TO_PIN(UART1_TX),
192
+
UPBOARD_UP_BIT_TO_PIN(UART1_RX),
193
+
UPBOARD_UP_BIT_TO_PIN(UART1_CTS),
194
+
UPBOARD_UP_BIT_TO_PIN(UART1_RTS),
195
+
UPBOARD_UP_BIT_TO_PIN(I2S_CLK),
196
+
UPBOARD_UP_BIT_TO_PIN(I2S_FRM),
197
+
UPBOARD_UP_BIT_TO_PIN(I2S_DIN),
198
+
UPBOARD_UP_BIT_TO_PIN(I2S_DOUT),
199
+
UPBOARD_UP_BIT_TO_PIN(GPIO22),
200
+
UPBOARD_UP_BIT_TO_PIN(GPIO23),
201
+
UPBOARD_UP_BIT_TO_PIN(GPIO24),
202
+
UPBOARD_UP_BIT_TO_PIN(GPIO25),
203
+
UPBOARD_UP_BIT_TO_PIN(GPIO26),
204
+
UPBOARD_UP_BIT_TO_PIN(GPIO27),
205
+
};
206
+
207
+
static const unsigned int upboard_up_uart1_pins[] = {
208
+
UPBOARD_UP_BIT_TO_PIN(UART1_TX),
209
+
UPBOARD_UP_BIT_TO_PIN(UART1_RX),
210
+
UPBOARD_UP_BIT_TO_PIN(UART1_RTS),
211
+
UPBOARD_UP_BIT_TO_PIN(UART1_CTS),
212
+
};
213
+
214
+
static const enum upboard_pin_mode upboard_up_uart1_modes[] = {
215
+
UPBOARD_PIN_MODE_GPIO_OUT,
216
+
UPBOARD_PIN_MODE_GPIO_IN,
217
+
UPBOARD_PIN_MODE_GPIO_OUT,
218
+
UPBOARD_PIN_MODE_GPIO_IN,
219
+
};
220
+
221
+
static_assert(ARRAY_SIZE(upboard_up_uart1_modes) == ARRAY_SIZE(upboard_up_uart1_pins));
222
+
223
+
static const unsigned int upboard_up_i2c0_pins[] = {
224
+
UPBOARD_UP_BIT_TO_PIN(I2C0_SCL),
225
+
UPBOARD_UP_BIT_TO_PIN(I2C0_SDA),
226
+
};
227
+
228
+
static const unsigned int upboard_up_i2c1_pins[] = {
229
+
UPBOARD_UP_BIT_TO_PIN(I2C1_SCL),
230
+
UPBOARD_UP_BIT_TO_PIN(I2C1_SDA),
231
+
};
232
+
233
+
static const unsigned int upboard_up_spi2_pins[] = {
234
+
UPBOARD_UP_BIT_TO_PIN(SPI_MOSI),
235
+
UPBOARD_UP_BIT_TO_PIN(SPI_MISO),
236
+
UPBOARD_UP_BIT_TO_PIN(SPI_CLK),
237
+
UPBOARD_UP_BIT_TO_PIN(SPI_CS0),
238
+
UPBOARD_UP_BIT_TO_PIN(SPI_CS1),
239
+
};
240
+
241
+
static const enum upboard_pin_mode upboard_up_spi2_modes[] = {
242
+
UPBOARD_PIN_MODE_GPIO_OUT,
243
+
UPBOARD_PIN_MODE_GPIO_IN,
244
+
UPBOARD_PIN_MODE_GPIO_OUT,
245
+
UPBOARD_PIN_MODE_GPIO_OUT,
246
+
UPBOARD_PIN_MODE_GPIO_OUT,
247
+
};
248
+
249
+
static_assert(ARRAY_SIZE(upboard_up_spi2_modes) == ARRAY_SIZE(upboard_up_spi2_pins));
250
+
251
+
static const unsigned int upboard_up_i2s0_pins[] = {
252
+
UPBOARD_UP_BIT_TO_PIN(I2S_FRM),
253
+
UPBOARD_UP_BIT_TO_PIN(I2S_CLK),
254
+
UPBOARD_UP_BIT_TO_PIN(I2S_DIN),
255
+
UPBOARD_UP_BIT_TO_PIN(I2S_DOUT),
256
+
};
257
+
258
+
static const enum upboard_pin_mode upboard_up_i2s0_modes[] = {
259
+
UPBOARD_PIN_MODE_GPIO_OUT,
260
+
UPBOARD_PIN_MODE_GPIO_OUT,
261
+
UPBOARD_PIN_MODE_GPIO_IN,
262
+
UPBOARD_PIN_MODE_GPIO_OUT,
263
+
};
264
+
265
+
static_assert(ARRAY_SIZE(upboard_up_i2s0_pins) == ARRAY_SIZE(upboard_up_i2s0_modes));
266
+
267
+
static const unsigned int upboard_up_pwm0_pins[] = {
268
+
UPBOARD_UP_BIT_TO_PIN(PWM0),
269
+
};
270
+
271
+
static const unsigned int upboard_up_pwm1_pins[] = {
272
+
UPBOARD_UP_BIT_TO_PIN(PWM1),
273
+
};
274
+
275
+
static const unsigned int upboard_up_adc0_pins[] = {
276
+
UPBOARD_UP_BIT_TO_PIN(ADC0),
277
+
};
278
+
279
+
#define UPBOARD_PINGROUP(n, p, m) \
280
+
{ \
281
+
.grp = PINCTRL_PINGROUP(n, p, ARRAY_SIZE(p)), \
282
+
.mode = __builtin_choose_expr( \
283
+
__builtin_types_compatible_p(typeof(m), const enum upboard_pin_mode *), \
284
+
0, m), \
285
+
.modes = __builtin_choose_expr( \
286
+
__builtin_types_compatible_p(typeof(m), const enum upboard_pin_mode *), \
287
+
m, NULL), \
288
+
}
289
+
290
+
static const struct upboard_pingroup upboard_up_pin_groups[] = {
291
+
UPBOARD_PINGROUP("uart1_grp", upboard_up_uart1_pins, &upboard_up_uart1_modes[0]),
292
+
UPBOARD_PINGROUP("i2c0_grp", upboard_up_i2c0_pins, UPBOARD_PIN_MODE_GPIO_OUT),
293
+
UPBOARD_PINGROUP("i2c1_grp", upboard_up_i2c1_pins, UPBOARD_PIN_MODE_GPIO_OUT),
294
+
UPBOARD_PINGROUP("spi2_grp", upboard_up_spi2_pins, &upboard_up_spi2_modes[0]),
295
+
UPBOARD_PINGROUP("i2s0_grp", upboard_up_i2s0_pins, &upboard_up_i2s0_modes[0]),
296
+
UPBOARD_PINGROUP("pwm0_grp", upboard_up_pwm0_pins, UPBOARD_PIN_MODE_GPIO_OUT),
297
+
UPBOARD_PINGROUP("pwm1_grp", upboard_up_pwm1_pins, UPBOARD_PIN_MODE_GPIO_OUT),
298
+
UPBOARD_PINGROUP("adc0_grp", upboard_up_adc0_pins, UPBOARD_PIN_MODE_GPIO_IN),
299
+
};
300
+
301
+
static const char * const upboard_up_uart1_groups[] = { "uart1_grp" };
302
+
static const char * const upboard_up_i2c0_groups[] = { "i2c0_grp" };
303
+
static const char * const upboard_up_i2c1_groups[] = { "i2c1_grp" };
304
+
static const char * const upboard_up_spi2_groups[] = { "spi2_grp" };
305
+
static const char * const upboard_up_i2s0_groups[] = { "i2s0_grp" };
306
+
static const char * const upboard_up_pwm0_groups[] = { "pwm0_grp" };
307
+
static const char * const upboard_up_pwm1_groups[] = { "pwm1_grp" };
308
+
static const char * const upboard_up_adc0_groups[] = { "adc0_grp" };
309
+
310
+
#define UPBOARD_FUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, ARRAY_SIZE(groups))
311
+
312
+
static const struct pinfunction upboard_up_pin_functions[] = {
313
+
UPBOARD_FUNCTION("uart1", upboard_up_uart1_groups),
314
+
UPBOARD_FUNCTION("i2c0", upboard_up_i2c0_groups),
315
+
UPBOARD_FUNCTION("i2c1", upboard_up_i2c1_groups),
316
+
UPBOARD_FUNCTION("spi2", upboard_up_spi2_groups),
317
+
UPBOARD_FUNCTION("i2s0", upboard_up_i2s0_groups),
318
+
UPBOARD_FUNCTION("pwm0", upboard_up_pwm0_groups),
319
+
UPBOARD_FUNCTION("pwm1", upboard_up_pwm1_groups),
320
+
UPBOARD_FUNCTION("adc0", upboard_up_adc0_groups),
321
+
};
322
+
323
+
static const struct upboard_pinctrl_data upboard_up_pinctrl_data = {
324
+
.groups = &upboard_up_pin_groups[0],
325
+
.ngroups = ARRAY_SIZE(upboard_up_pin_groups),
326
+
.funcs = &upboard_up_pin_functions[0],
327
+
.nfuncs = ARRAY_SIZE(upboard_up_pin_functions),
328
+
.pin_header = &upboard_up_pin_header[0],
329
+
.ngpio = ARRAY_SIZE(upboard_up_pin_header),
330
+
};
331
+
332
+
#define UPBOARD_UP2_BIT_TO_PIN(bit) UPBOARD_UP2_BIT_##bit
333
+
334
+
#define UPBOARD_UP2_PIN_NAME(id) \
335
+
{ \
336
+
.number = UPBOARD_UP2_BIT_##id, \
337
+
.name = #id, \
338
+
}
339
+
340
+
#define UPBOARD_UP2_PIN_MUX(bit, data) \
341
+
{ \
342
+
.number = UPBOARD_UP2_BIT_##bit, \
343
+
.name = "PINMUX_"#bit, \
344
+
.drv_data = (void *)(data), \
345
+
}
346
+
347
+
#define UPBOARD_UP2_PIN_FUNC(id, data) \
348
+
{ \
349
+
.number = UPBOARD_UP2_BIT_##id, \
350
+
.name = #id, \
351
+
.drv_data = (void *)(data), \
352
+
}
353
+
354
+
enum upboard_up2_fpgabit {
355
+
UPBOARD_UP2_BIT_UART1_TXD,
356
+
UPBOARD_UP2_BIT_UART1_RXD,
357
+
UPBOARD_UP2_BIT_UART1_RTS,
358
+
UPBOARD_UP2_BIT_UART1_CTS,
359
+
UPBOARD_UP2_BIT_GPIO3_ADC0,
360
+
UPBOARD_UP2_BIT_GPIO5_ADC2,
361
+
UPBOARD_UP2_BIT_GPIO6_ADC3,
362
+
UPBOARD_UP2_BIT_GPIO11,
363
+
UPBOARD_UP2_BIT_EXHAT_LVDS1n,
364
+
UPBOARD_UP2_BIT_EXHAT_LVDS1p,
365
+
UPBOARD_UP2_BIT_SPI2_TXD,
366
+
UPBOARD_UP2_BIT_SPI2_RXD,
367
+
UPBOARD_UP2_BIT_SPI2_FS1,
368
+
UPBOARD_UP2_BIT_SPI2_FS0,
369
+
UPBOARD_UP2_BIT_SPI2_CLK,
370
+
UPBOARD_UP2_BIT_SPI1_TXD,
371
+
UPBOARD_UP2_BIT_SPI1_RXD,
372
+
UPBOARD_UP2_BIT_SPI1_FS1,
373
+
UPBOARD_UP2_BIT_SPI1_FS0,
374
+
UPBOARD_UP2_BIT_SPI1_CLK,
375
+
UPBOARD_UP2_BIT_I2C0_SCL,
376
+
UPBOARD_UP2_BIT_I2C0_SDA,
377
+
UPBOARD_UP2_BIT_I2C1_SCL,
378
+
UPBOARD_UP2_BIT_I2C1_SDA,
379
+
UPBOARD_UP2_BIT_PWM1,
380
+
UPBOARD_UP2_BIT_PWM0,
381
+
UPBOARD_UP2_BIT_EXHAT_LVDS0n,
382
+
UPBOARD_UP2_BIT_EXHAT_LVDS0p,
383
+
UPBOARD_UP2_BIT_GPIO24,
384
+
UPBOARD_UP2_BIT_GPIO10,
385
+
UPBOARD_UP2_BIT_GPIO2,
386
+
UPBOARD_UP2_BIT_GPIO1,
387
+
UPBOARD_UP2_BIT_EXHAT_LVDS3n,
388
+
UPBOARD_UP2_BIT_EXHAT_LVDS3p,
389
+
UPBOARD_UP2_BIT_EXHAT_LVDS4n,
390
+
UPBOARD_UP2_BIT_EXHAT_LVDS4p,
391
+
UPBOARD_UP2_BIT_EXHAT_LVDS5n,
392
+
UPBOARD_UP2_BIT_EXHAT_LVDS5p,
393
+
UPBOARD_UP2_BIT_I2S_SDO,
394
+
UPBOARD_UP2_BIT_I2S_SDI,
395
+
UPBOARD_UP2_BIT_I2S_WS_SYNC,
396
+
UPBOARD_UP2_BIT_I2S_BCLK,
397
+
UPBOARD_UP2_BIT_EXHAT_LVDS6n,
398
+
UPBOARD_UP2_BIT_EXHAT_LVDS6p,
399
+
UPBOARD_UP2_BIT_EXHAT_LVDS7n,
400
+
UPBOARD_UP2_BIT_EXHAT_LVDS7p,
401
+
UPBOARD_UP2_BIT_EXHAT_LVDS2n,
402
+
UPBOARD_UP2_BIT_EXHAT_LVDS2p,
403
+
};
404
+
405
+
static const struct pinctrl_pin_desc upboard_up2_pins[] = {
406
+
UPBOARD_UP2_PIN_NAME(UART1_TXD),
407
+
UPBOARD_UP2_PIN_NAME(UART1_RXD),
408
+
UPBOARD_UP2_PIN_NAME(UART1_RTS),
409
+
UPBOARD_UP2_PIN_NAME(UART1_CTS),
410
+
UPBOARD_UP2_PIN_NAME(GPIO3_ADC0),
411
+
UPBOARD_UP2_PIN_NAME(GPIO5_ADC2),
412
+
UPBOARD_UP2_PIN_NAME(GPIO6_ADC3),
413
+
UPBOARD_UP2_PIN_NAME(GPIO11),
414
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS1n),
415
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS1p),
416
+
UPBOARD_UP2_PIN_NAME(SPI2_TXD),
417
+
UPBOARD_UP2_PIN_NAME(SPI2_RXD),
418
+
UPBOARD_UP2_PIN_NAME(SPI2_FS1),
419
+
UPBOARD_UP2_PIN_NAME(SPI2_FS0),
420
+
UPBOARD_UP2_PIN_NAME(SPI2_CLK),
421
+
UPBOARD_UP2_PIN_NAME(SPI1_TXD),
422
+
UPBOARD_UP2_PIN_NAME(SPI1_RXD),
423
+
UPBOARD_UP2_PIN_NAME(SPI1_FS1),
424
+
UPBOARD_UP2_PIN_NAME(SPI1_FS0),
425
+
UPBOARD_UP2_PIN_NAME(SPI1_CLK),
426
+
UPBOARD_UP2_PIN_MUX(I2C0_SCL, &upboard_i2c0_reg),
427
+
UPBOARD_UP2_PIN_MUX(I2C0_SDA, &upboard_i2c0_reg),
428
+
UPBOARD_UP2_PIN_MUX(I2C1_SCL, &upboard_i2c1_reg),
429
+
UPBOARD_UP2_PIN_MUX(I2C1_SDA, &upboard_i2c1_reg),
430
+
UPBOARD_UP2_PIN_NAME(PWM1),
431
+
UPBOARD_UP2_PIN_NAME(PWM0),
432
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS0n),
433
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS0p),
434
+
UPBOARD_UP2_PIN_MUX(GPIO24, &upboard_i2c0_reg),
435
+
UPBOARD_UP2_PIN_MUX(GPIO10, &upboard_i2c0_reg),
436
+
UPBOARD_UP2_PIN_MUX(GPIO2, &upboard_i2c1_reg),
437
+
UPBOARD_UP2_PIN_MUX(GPIO1, &upboard_i2c1_reg),
438
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS3n),
439
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS3p),
440
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS4n),
441
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS4p),
442
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS5n),
443
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS5p),
444
+
UPBOARD_UP2_PIN_NAME(I2S_SDO),
445
+
UPBOARD_UP2_PIN_NAME(I2S_SDI),
446
+
UPBOARD_UP2_PIN_NAME(I2S_WS_SYNC),
447
+
UPBOARD_UP2_PIN_NAME(I2S_BCLK),
448
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS6n),
449
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS6p),
450
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS7n),
451
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS7p),
452
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS2n),
453
+
UPBOARD_UP2_PIN_NAME(EXHAT_LVDS2p),
454
+
};
455
+
456
+
static const unsigned int upboard_up2_pin_header[] = {
457
+
UPBOARD_UP2_BIT_TO_PIN(GPIO10),
458
+
UPBOARD_UP2_BIT_TO_PIN(GPIO24),
459
+
UPBOARD_UP2_BIT_TO_PIN(GPIO1),
460
+
UPBOARD_UP2_BIT_TO_PIN(GPIO2),
461
+
UPBOARD_UP2_BIT_TO_PIN(GPIO3_ADC0),
462
+
UPBOARD_UP2_BIT_TO_PIN(GPIO11),
463
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_CLK),
464
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_FS1),
465
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_FS0),
466
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_RXD),
467
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_TXD),
468
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_CLK),
469
+
UPBOARD_UP2_BIT_TO_PIN(PWM0),
470
+
UPBOARD_UP2_BIT_TO_PIN(PWM1),
471
+
UPBOARD_UP2_BIT_TO_PIN(UART1_TXD),
472
+
UPBOARD_UP2_BIT_TO_PIN(UART1_RXD),
473
+
UPBOARD_UP2_BIT_TO_PIN(UART1_CTS),
474
+
UPBOARD_UP2_BIT_TO_PIN(UART1_RTS),
475
+
UPBOARD_UP2_BIT_TO_PIN(I2S_BCLK),
476
+
UPBOARD_UP2_BIT_TO_PIN(I2S_WS_SYNC),
477
+
UPBOARD_UP2_BIT_TO_PIN(I2S_SDI),
478
+
UPBOARD_UP2_BIT_TO_PIN(I2S_SDO),
479
+
UPBOARD_UP2_BIT_TO_PIN(GPIO6_ADC3),
480
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_FS1),
481
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_RXD),
482
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_TXD),
483
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_FS0),
484
+
UPBOARD_UP2_BIT_TO_PIN(GPIO5_ADC2),
485
+
};
486
+
487
+
static const unsigned int upboard_up2_uart1_pins[] = {
488
+
UPBOARD_UP2_BIT_TO_PIN(UART1_TXD),
489
+
UPBOARD_UP2_BIT_TO_PIN(UART1_RXD),
490
+
UPBOARD_UP2_BIT_TO_PIN(UART1_RTS),
491
+
UPBOARD_UP2_BIT_TO_PIN(UART1_CTS),
492
+
};
493
+
494
+
static const enum upboard_pin_mode upboard_up2_uart1_modes[] = {
495
+
UPBOARD_PIN_MODE_GPIO_OUT,
496
+
UPBOARD_PIN_MODE_GPIO_IN,
497
+
UPBOARD_PIN_MODE_GPIO_OUT,
498
+
UPBOARD_PIN_MODE_GPIO_IN,
499
+
};
500
+
501
+
static_assert(ARRAY_SIZE(upboard_up2_uart1_modes) == ARRAY_SIZE(upboard_up2_uart1_pins));
502
+
503
+
static const unsigned int upboard_up2_i2c0_pins[] = {
504
+
UPBOARD_UP2_BIT_TO_PIN(I2C0_SCL),
505
+
UPBOARD_UP2_BIT_TO_PIN(I2C0_SDA),
506
+
UPBOARD_UP2_BIT_TO_PIN(GPIO24),
507
+
UPBOARD_UP2_BIT_TO_PIN(GPIO10),
508
+
};
509
+
510
+
static const unsigned int upboard_up2_i2c1_pins[] = {
511
+
UPBOARD_UP2_BIT_TO_PIN(I2C1_SCL),
512
+
UPBOARD_UP2_BIT_TO_PIN(I2C1_SDA),
513
+
UPBOARD_UP2_BIT_TO_PIN(GPIO2),
514
+
UPBOARD_UP2_BIT_TO_PIN(GPIO1),
515
+
};
516
+
517
+
static const unsigned int upboard_up2_spi1_pins[] = {
518
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_TXD),
519
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_RXD),
520
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_FS1),
521
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_FS0),
522
+
UPBOARD_UP2_BIT_TO_PIN(SPI1_CLK),
523
+
};
524
+
525
+
static const unsigned int upboard_up2_spi2_pins[] = {
526
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_TXD),
527
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_RXD),
528
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_FS1),
529
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_FS0),
530
+
UPBOARD_UP2_BIT_TO_PIN(SPI2_CLK),
531
+
};
532
+
533
+
static const enum upboard_pin_mode upboard_up2_spi_modes[] = {
534
+
UPBOARD_PIN_MODE_GPIO_OUT,
535
+
UPBOARD_PIN_MODE_GPIO_IN,
536
+
UPBOARD_PIN_MODE_GPIO_OUT,
537
+
UPBOARD_PIN_MODE_GPIO_OUT,
538
+
UPBOARD_PIN_MODE_GPIO_OUT,
539
+
};
540
+
541
+
static_assert(ARRAY_SIZE(upboard_up2_spi_modes) == ARRAY_SIZE(upboard_up2_spi1_pins));
542
+
543
+
static_assert(ARRAY_SIZE(upboard_up2_spi_modes) == ARRAY_SIZE(upboard_up2_spi2_pins));
544
+
545
+
static const unsigned int upboard_up2_i2s0_pins[] = {
546
+
UPBOARD_UP2_BIT_TO_PIN(I2S_BCLK),
547
+
UPBOARD_UP2_BIT_TO_PIN(I2S_WS_SYNC),
548
+
UPBOARD_UP2_BIT_TO_PIN(I2S_SDI),
549
+
UPBOARD_UP2_BIT_TO_PIN(I2S_SDO),
550
+
};
551
+
552
+
static const enum upboard_pin_mode upboard_up2_i2s0_modes[] = {
553
+
UPBOARD_PIN_MODE_GPIO_OUT,
554
+
UPBOARD_PIN_MODE_GPIO_OUT,
555
+
UPBOARD_PIN_MODE_GPIO_IN,
556
+
UPBOARD_PIN_MODE_GPIO_OUT,
557
+
};
558
+
559
+
static_assert(ARRAY_SIZE(upboard_up2_i2s0_modes) == ARRAY_SIZE(upboard_up2_i2s0_pins));
560
+
561
+
static const unsigned int upboard_up2_pwm0_pins[] = {
562
+
UPBOARD_UP2_BIT_TO_PIN(PWM0),
563
+
};
564
+
565
+
static const unsigned int upboard_up2_pwm1_pins[] = {
566
+
UPBOARD_UP2_BIT_TO_PIN(PWM1),
567
+
};
568
+
569
+
static const unsigned int upboard_up2_adc0_pins[] = {
570
+
UPBOARD_UP2_BIT_TO_PIN(GPIO3_ADC0),
571
+
};
572
+
573
+
static const unsigned int upboard_up2_adc2_pins[] = {
574
+
UPBOARD_UP2_BIT_TO_PIN(GPIO5_ADC2),
575
+
};
576
+
577
+
static const unsigned int upboard_up2_adc3_pins[] = {
578
+
UPBOARD_UP2_BIT_TO_PIN(GPIO6_ADC3),
579
+
};
580
+
581
+
static const struct upboard_pingroup upboard_up2_pin_groups[] = {
582
+
UPBOARD_PINGROUP("uart1_grp", upboard_up2_uart1_pins, &upboard_up2_uart1_modes[0]),
583
+
UPBOARD_PINGROUP("i2c0_grp", upboard_up2_i2c0_pins, UPBOARD_PIN_MODE_FUNCTION),
584
+
UPBOARD_PINGROUP("i2c1_grp", upboard_up2_i2c1_pins, UPBOARD_PIN_MODE_FUNCTION),
585
+
UPBOARD_PINGROUP("spi1_grp", upboard_up2_spi1_pins, &upboard_up2_spi_modes[0]),
586
+
UPBOARD_PINGROUP("spi2_grp", upboard_up2_spi2_pins, &upboard_up2_spi_modes[0]),
587
+
UPBOARD_PINGROUP("i2s0_grp", upboard_up2_i2s0_pins, &upboard_up2_i2s0_modes[0]),
588
+
UPBOARD_PINGROUP("pwm0_grp", upboard_up2_pwm0_pins, UPBOARD_PIN_MODE_GPIO_OUT),
589
+
UPBOARD_PINGROUP("pwm1_grp", upboard_up2_pwm1_pins, UPBOARD_PIN_MODE_GPIO_OUT),
590
+
UPBOARD_PINGROUP("adc0_grp", upboard_up2_adc0_pins, UPBOARD_PIN_MODE_GPIO_IN),
591
+
UPBOARD_PINGROUP("adc2_grp", upboard_up2_adc2_pins, UPBOARD_PIN_MODE_GPIO_IN),
592
+
UPBOARD_PINGROUP("adc3_grp", upboard_up2_adc3_pins, UPBOARD_PIN_MODE_GPIO_IN),
593
+
};
594
+
595
+
static const char * const upboard_up2_uart1_groups[] = { "uart1_grp" };
596
+
static const char * const upboard_up2_i2c0_groups[] = { "i2c0_grp" };
597
+
static const char * const upboard_up2_i2c1_groups[] = { "i2c1_grp" };
598
+
static const char * const upboard_up2_spi1_groups[] = { "spi1_grp" };
599
+
static const char * const upboard_up2_spi2_groups[] = { "spi2_grp" };
600
+
static const char * const upboard_up2_i2s0_groups[] = { "i2s0_grp" };
601
+
static const char * const upboard_up2_pwm0_groups[] = { "pwm0_grp" };
602
+
static const char * const upboard_up2_pwm1_groups[] = { "pwm1_grp" };
603
+
static const char * const upboard_up2_adc0_groups[] = { "adc0_grp" };
604
+
static const char * const upboard_up2_adc2_groups[] = { "adc2_grp" };
605
+
static const char * const upboard_up2_adc3_groups[] = { "adc3_grp" };
606
+
607
+
static const struct pinfunction upboard_up2_pin_functions[] = {
608
+
UPBOARD_FUNCTION("uart1", upboard_up2_uart1_groups),
609
+
UPBOARD_FUNCTION("i2c0", upboard_up2_i2c0_groups),
610
+
UPBOARD_FUNCTION("i2c1", upboard_up2_i2c1_groups),
611
+
UPBOARD_FUNCTION("spi1", upboard_up2_spi1_groups),
612
+
UPBOARD_FUNCTION("spi2", upboard_up2_spi2_groups),
613
+
UPBOARD_FUNCTION("i2s0", upboard_up2_i2s0_groups),
614
+
UPBOARD_FUNCTION("pwm0", upboard_up2_pwm0_groups),
615
+
UPBOARD_FUNCTION("pwm1", upboard_up2_pwm1_groups),
616
+
UPBOARD_FUNCTION("adc0", upboard_up2_adc0_groups),
617
+
UPBOARD_FUNCTION("adc2", upboard_up2_adc2_groups),
618
+
UPBOARD_FUNCTION("adc3", upboard_up2_adc3_groups),
619
+
};
620
+
621
+
static const struct upboard_pinctrl_data upboard_up2_pinctrl_data = {
622
+
.groups = &upboard_up2_pin_groups[0],
623
+
.ngroups = ARRAY_SIZE(upboard_up2_pin_groups),
624
+
.funcs = &upboard_up2_pin_functions[0],
625
+
.nfuncs = ARRAY_SIZE(upboard_up2_pin_functions),
626
+
.pin_header = &upboard_up2_pin_header[0],
627
+
.ngpio = ARRAY_SIZE(upboard_up2_pin_header),
628
+
};
629
+
630
+
static int upboard_pinctrl_set_function(struct pinctrl_dev *pctldev, unsigned int offset)
631
+
{
632
+
struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
633
+
struct upboard_pin *p = &pctrl->pins[offset];
634
+
int ret;
635
+
636
+
if (!p->funcbit)
637
+
return -EPERM;
638
+
639
+
ret = regmap_field_write(p->enbit, 0);
640
+
if (ret)
641
+
return ret;
642
+
643
+
return regmap_field_write(p->funcbit, 1);
644
+
}
645
+
646
+
static int upboard_pinctrl_gpio_commit_enable(struct pinctrl_dev *pctldev, unsigned int offset)
647
+
{
648
+
struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
649
+
struct upboard_pin *p = &pctrl->pins[offset];
650
+
int ret;
651
+
652
+
if (p->funcbit) {
653
+
ret = regmap_field_write(p->funcbit, 0);
654
+
if (ret)
655
+
return ret;
656
+
}
657
+
658
+
return regmap_field_write(p->enbit, 1);
659
+
}
660
+
661
+
static int upboard_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
662
+
struct pinctrl_gpio_range *range,
663
+
unsigned int offset)
664
+
{
665
+
return upboard_pinctrl_gpio_commit_enable(pctldev, offset);
666
+
}
667
+
668
+
static void upboard_pinctrl_gpio_commit_disable(struct pinctrl_dev *pctldev, unsigned int offset)
669
+
{
670
+
struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
671
+
struct upboard_pin *p = &pctrl->pins[offset];
672
+
673
+
regmap_field_write(p->enbit, 0);
674
+
};
675
+
676
+
static void upboard_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
677
+
struct pinctrl_gpio_range *range, unsigned int offset)
678
+
{
679
+
return upboard_pinctrl_gpio_commit_disable(pctldev, offset);
680
+
}
681
+
682
+
static int upboard_pinctrl_gpio_commit_direction(struct pinctrl_dev *pctldev, unsigned int offset,
683
+
bool input)
684
+
{
685
+
struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
686
+
struct upboard_pin *p = &pctrl->pins[offset];
687
+
688
+
return regmap_field_write(p->dirbit, input);
689
+
}
690
+
691
+
static int upboard_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
692
+
struct pinctrl_gpio_range *range,
693
+
unsigned int offset, bool input)
694
+
{
695
+
return upboard_pinctrl_gpio_commit_direction(pctldev, offset, input);
696
+
}
697
+
698
+
static int upboard_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
699
+
unsigned int group_selector)
700
+
{
701
+
struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
702
+
const struct upboard_pinctrl_data *pctrl_data = pctrl->pctrl_data;
703
+
const struct upboard_pingroup *upgroups = pctrl_data->groups;
704
+
struct group_desc *grp;
705
+
unsigned int mode, i;
706
+
int ret;
707
+
708
+
grp = pinctrl_generic_get_group(pctldev, group_selector);
709
+
if (!grp)
710
+
return -EINVAL;
711
+
712
+
for (i = 0; i < grp->grp.npins; i++) {
713
+
mode = upgroups[group_selector].mode ?: upgroups[group_selector].modes[i];
714
+
if (mode == UPBOARD_PIN_MODE_FUNCTION) {
715
+
ret = upboard_pinctrl_set_function(pctldev, grp->grp.pins[i]);
716
+
if (ret)
717
+
return ret;
718
+
719
+
continue;
720
+
}
721
+
722
+
ret = upboard_pinctrl_gpio_commit_enable(pctldev, grp->grp.pins[i]);
723
+
if (ret)
724
+
return ret;
725
+
726
+
ret = upboard_pinctrl_gpio_commit_direction(pctldev, grp->grp.pins[i],
727
+
mode == UPBOARD_PIN_MODE_GPIO_IN);
728
+
if (ret)
729
+
return ret;
730
+
}
731
+
732
+
return 0;
733
+
}
734
+
735
+
static const struct pinmux_ops upboard_pinmux_ops = {
736
+
.get_functions_count = pinmux_generic_get_function_count,
737
+
.get_function_name = pinmux_generic_get_function_name,
738
+
.get_function_groups = pinmux_generic_get_function_groups,
739
+
.set_mux = upboard_pinctrl_set_mux,
740
+
.gpio_request_enable = upboard_pinctrl_gpio_request_enable,
741
+
.gpio_disable_free = upboard_pinctrl_gpio_disable_free,
742
+
.gpio_set_direction = upboard_pinctrl_gpio_set_direction,
743
+
};
744
+
745
+
static int upboard_pinctrl_pin_get_mode(struct pinctrl_dev *pctldev, unsigned int pin)
746
+
{
747
+
struct upboard_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
748
+
struct upboard_pin *p = &pctrl->pins[pin];
749
+
unsigned int val;
750
+
int ret;
751
+
752
+
if (p->funcbit) {
753
+
ret = regmap_field_read(p->funcbit, &val);
754
+
if (ret)
755
+
return ret;
756
+
if (val)
757
+
return UPBOARD_PIN_MODE_FUNCTION;
758
+
}
759
+
760
+
ret = regmap_field_read(p->enbit, &val);
761
+
if (ret)
762
+
return ret;
763
+
if (!val)
764
+
return UPBOARD_PIN_MODE_DISABLED;
765
+
766
+
ret = regmap_field_read(p->dirbit, &val);
767
+
if (ret)
768
+
return ret;
769
+
770
+
return val ? UPBOARD_PIN_MODE_GPIO_IN : UPBOARD_PIN_MODE_GPIO_OUT;
771
+
}
772
+
773
+
static void upboard_pinctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
774
+
unsigned int offset)
775
+
{
776
+
int ret;
777
+
778
+
ret = upboard_pinctrl_pin_get_mode(pctldev, offset);
779
+
if (ret == UPBOARD_PIN_MODE_FUNCTION)
780
+
seq_puts(s, "mode function ");
781
+
else if (ret == UPBOARD_PIN_MODE_DISABLED)
782
+
seq_puts(s, "HIGH-Z ");
783
+
else if (ret < 0)
784
+
seq_puts(s, "N/A ");
785
+
else
786
+
seq_printf(s, "GPIO (%s) ", str_input_output(ret == UPBOARD_PIN_MODE_GPIO_IN));
787
+
}
788
+
789
+
static const struct pinctrl_ops upboard_pinctrl_ops = {
790
+
.get_groups_count = pinctrl_generic_get_group_count,
791
+
.get_group_name = pinctrl_generic_get_group_name,
792
+
.get_group_pins = pinctrl_generic_get_group_pins,
793
+
.pin_dbg_show = upboard_pinctrl_dbg_show,
794
+
};
795
+
796
+
static int upboard_gpio_request(struct gpio_chip *gc, unsigned int offset)
797
+
{
798
+
struct gpiochip_fwd *fwd = gpiochip_get_data(gc);
799
+
struct upboard_pinctrl *pctrl = gpiochip_fwd_get_data(fwd);
800
+
unsigned int pin = pctrl->pctrl_data->pin_header[offset];
801
+
struct gpio_desc *desc;
802
+
int ret;
803
+
804
+
ret = pinctrl_gpio_request(gc, offset);
805
+
if (ret)
806
+
return ret;
807
+
808
+
desc = gpiod_get_index(pctrl->dev, "external", pin, 0);
809
+
if (IS_ERR(desc)) {
810
+
pinctrl_gpio_free(gc, offset);
811
+
return PTR_ERR(desc);
812
+
}
813
+
814
+
return gpiochip_fwd_desc_add(fwd, desc, offset);
815
+
}
816
+
817
+
static void upboard_gpio_free(struct gpio_chip *gc, unsigned int offset)
818
+
{
819
+
struct gpiochip_fwd *fwd = gpiochip_get_data(gc);
820
+
821
+
gpiochip_fwd_desc_free(fwd, offset);
822
+
pinctrl_gpio_free(gc, offset);
823
+
}
824
+
825
+
static int upboard_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
826
+
{
827
+
struct gpiochip_fwd *fwd = gpiochip_get_data(gc);
828
+
struct upboard_pinctrl *pctrl = gpiochip_fwd_get_data(fwd);
829
+
unsigned int pin = pctrl->pctrl_data->pin_header[offset];
830
+
int mode;
831
+
832
+
/* If the pin is in function mode or high-z, input direction is returned */
833
+
mode = upboard_pinctrl_pin_get_mode(pctrl->pctldev, pin);
834
+
if (mode < 0)
835
+
return mode;
836
+
837
+
if (mode == UPBOARD_PIN_MODE_GPIO_OUT)
838
+
return GPIO_LINE_DIRECTION_OUT;
839
+
840
+
return GPIO_LINE_DIRECTION_IN;
841
+
}
842
+
843
+
static int upboard_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
844
+
{
845
+
struct gpiochip_fwd *fwd = gpiochip_get_data(gc);
846
+
int ret;
847
+
848
+
ret = pinctrl_gpio_direction_input(gc, offset);
849
+
if (ret)
850
+
return ret;
851
+
852
+
return gpiochip_fwd_gpio_direction_input(fwd, offset);
853
+
}
854
+
855
+
static int upboard_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
856
+
{
857
+
struct gpiochip_fwd *fwd = gpiochip_get_data(gc);
858
+
int ret;
859
+
860
+
ret = pinctrl_gpio_direction_output(gc, offset);
861
+
if (ret)
862
+
return ret;
863
+
864
+
return gpiochip_fwd_gpio_direction_output(fwd, offset, value);
865
+
}
866
+
867
+
static int upboard_pinctrl_register_groups(struct upboard_pinctrl *pctrl)
868
+
{
869
+
const struct upboard_pingroup *groups = pctrl->pctrl_data->groups;
870
+
size_t ngroups = pctrl->pctrl_data->ngroups;
871
+
unsigned int i;
872
+
int ret;
873
+
874
+
for (i = 0; i < ngroups; i++) {
875
+
ret = pinctrl_generic_add_group(pctrl->pctldev, groups[i].grp.name,
876
+
groups[i].grp.pins, groups[i].grp.npins, pctrl);
877
+
if (ret < 0)
878
+
return ret;
879
+
}
880
+
881
+
return 0;
882
+
}
883
+
884
+
static int upboard_pinctrl_register_functions(struct upboard_pinctrl *pctrl)
885
+
{
886
+
const struct pinfunction *funcs = pctrl->pctrl_data->funcs;
887
+
size_t nfuncs = pctrl->pctrl_data->nfuncs;
888
+
unsigned int i;
889
+
int ret;
890
+
891
+
for (i = 0; i < nfuncs ; i++) {
892
+
ret = pinmux_generic_add_function(pctrl->pctldev, funcs[i].name,
893
+
funcs[i].groups, funcs[i].ngroups, NULL);
894
+
if (ret < 0)
895
+
return ret;
896
+
}
897
+
898
+
return 0;
899
+
}
900
+
901
+
static const struct pinctrl_map pinctrl_map_apl01[] = {
902
+
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INT3452:00", "pwm0_grp", "pwm0"),
903
+
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INT3452:00", "pwm1_grp", "pwm1"),
904
+
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INT3452:00", "uart1_grp", "uart1"),
905
+
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INT3452:02", "i2c0_grp", "i2c0"),
906
+
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INT3452:02", "i2c1_grp", "i2c1"),
907
+
PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INT3452:01", "ssp0_grp", "ssp0"),
908
+
};
909
+
910
+
static const struct upboard_pinctrl_map upboard_pinctrl_map_apl01 = {
911
+
.maps = &pinctrl_map_apl01[0],
912
+
.nmaps = ARRAY_SIZE(pinctrl_map_apl01),
913
+
};
914
+
915
+
static const struct dmi_system_id dmi_platform_info[] = {
916
+
{
917
+
/* UP Squared */
918
+
.matches = {
919
+
DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
920
+
DMI_EXACT_MATCH(DMI_BOARD_NAME, "UP-APL01"),
921
+
},
922
+
.driver_data = (void *)&upboard_pinctrl_map_apl01,
923
+
},
924
+
{ }
925
+
};
926
+
927
+
static int upboard_pinctrl_probe(struct platform_device *pdev)
928
+
{
929
+
struct device *dev = &pdev->dev;
930
+
struct upboard_fpga *fpga = dev_get_drvdata(dev->parent);
931
+
const struct upboard_pinctrl_map *board_map;
932
+
const struct dmi_system_id *dmi_id;
933
+
struct pinctrl_desc *pctldesc;
934
+
struct upboard_pinctrl *pctrl;
935
+
struct upboard_pin *pins;
936
+
struct gpiochip_fwd *fwd;
937
+
struct pinctrl *pinctrl;
938
+
struct gpio_chip *chip;
939
+
unsigned int i;
940
+
int ret;
941
+
942
+
pctldesc = devm_kzalloc(dev, sizeof(*pctldesc), GFP_KERNEL);
943
+
if (!pctldesc)
944
+
return -ENOMEM;
945
+
946
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
947
+
if (!pctrl)
948
+
return -ENOMEM;
949
+
950
+
switch (fpga->fpga_data->type) {
951
+
case UPBOARD_UP_FPGA:
952
+
pctldesc->pins = upboard_up_pins;
953
+
pctldesc->npins = ARRAY_SIZE(upboard_up_pins);
954
+
pctrl->pctrl_data = &upboard_up_pinctrl_data;
955
+
break;
956
+
case UPBOARD_UP2_FPGA:
957
+
pctldesc->pins = upboard_up2_pins;
958
+
pctldesc->npins = ARRAY_SIZE(upboard_up2_pins);
959
+
pctrl->pctrl_data = &upboard_up2_pinctrl_data;
960
+
break;
961
+
default:
962
+
return dev_err_probe(dev, -ENODEV, "Unsupported device type %d\n",
963
+
fpga->fpga_data->type);
964
+
}
965
+
966
+
dmi_id = dmi_first_match(dmi_platform_info);
967
+
if (!dmi_id)
968
+
return dev_err_probe(dev, -ENODEV, "Unsupported board\n");
969
+
970
+
board_map = (const struct upboard_pinctrl_map *)dmi_id->driver_data;
971
+
972
+
pctldesc->name = dev_name(dev);
973
+
pctldesc->owner = THIS_MODULE;
974
+
pctldesc->pctlops = &upboard_pinctrl_ops;
975
+
pctldesc->pmxops = &upboard_pinmux_ops;
976
+
977
+
pctrl->dev = dev;
978
+
979
+
pins = devm_kcalloc(dev, pctldesc->npins, sizeof(*pins), GFP_KERNEL);
980
+
if (!pins)
981
+
return -ENOMEM;
982
+
983
+
/* Initialize pins */
984
+
for (i = 0; i < pctldesc->npins; i++) {
985
+
const struct pinctrl_pin_desc *pin_desc = &pctldesc->pins[i];
986
+
unsigned int regoff = pin_desc->number / UPBOARD_REGISTER_SIZE;
987
+
unsigned int lsb = pin_desc->number % UPBOARD_REGISTER_SIZE;
988
+
struct reg_field * const fld_func = pin_desc->drv_data;
989
+
struct upboard_pin *pin = &pins[i];
990
+
struct reg_field fldconf = {};
991
+
992
+
if (fld_func) {
993
+
pin->funcbit = devm_regmap_field_alloc(dev, fpga->regmap, *fld_func);
994
+
if (IS_ERR(pin->funcbit))
995
+
return PTR_ERR(pin->funcbit);
996
+
}
997
+
998
+
fldconf.reg = UPBOARD_REG_GPIO_EN0 + regoff;
999
+
fldconf.lsb = lsb;
1000
+
fldconf.msb = lsb;
1001
+
pin->enbit = devm_regmap_field_alloc(dev, fpga->regmap, fldconf);
1002
+
if (IS_ERR(pin->enbit))
1003
+
return PTR_ERR(pin->enbit);
1004
+
1005
+
fldconf.reg = UPBOARD_REG_GPIO_DIR0 + regoff;
1006
+
fldconf.lsb = lsb;
1007
+
fldconf.msb = lsb;
1008
+
pin->dirbit = devm_regmap_field_alloc(dev, fpga->regmap, fldconf);
1009
+
if (IS_ERR(pin->dirbit))
1010
+
return PTR_ERR(pin->dirbit);
1011
+
}
1012
+
1013
+
pctrl->pins = pins;
1014
+
1015
+
ret = devm_pinctrl_register_and_init(dev, pctldesc, pctrl, &pctrl->pctldev);
1016
+
if (ret)
1017
+
return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
1018
+
1019
+
ret = upboard_pinctrl_register_groups(pctrl);
1020
+
if (ret)
1021
+
return dev_err_probe(dev, ret, "Failed to register groups\n");
1022
+
1023
+
ret = upboard_pinctrl_register_functions(pctrl);
1024
+
if (ret)
1025
+
return dev_err_probe(dev, ret, "Failed to register functions\n");
1026
+
1027
+
ret = devm_pinctrl_register_mappings(dev, board_map->maps, board_map->nmaps);
1028
+
if (ret)
1029
+
return ret;
1030
+
1031
+
pinctrl = devm_pinctrl_get_select_default(dev);
1032
+
if (IS_ERR(pinctrl))
1033
+
return dev_err_probe(dev, PTR_ERR(pinctrl), "Failed to select pinctrl\n");
1034
+
1035
+
ret = pinctrl_enable(pctrl->pctldev);
1036
+
if (ret)
1037
+
return ret;
1038
+
1039
+
fwd = devm_gpiochip_fwd_alloc(dev, pctrl->pctrl_data->ngpio);
1040
+
if (IS_ERR(fwd))
1041
+
return dev_err_probe(dev, PTR_ERR(fwd), "Failed to allocate the gpiochip forwarder\n");
1042
+
1043
+
chip = gpiochip_fwd_get_gpiochip(fwd);
1044
+
chip->request = upboard_gpio_request;
1045
+
chip->free = upboard_gpio_free;
1046
+
chip->get_direction = upboard_gpio_get_direction;
1047
+
chip->direction_output = upboard_gpio_direction_output;
1048
+
chip->direction_input = upboard_gpio_direction_input;
1049
+
1050
+
ret = gpiochip_fwd_register(fwd, pctrl);
1051
+
if (ret)
1052
+
return dev_err_probe(dev, ret, "Failed to register the gpiochip forwarder\n");
1053
+
1054
+
return gpiochip_add_sparse_pin_range(chip, dev_name(dev), 0, pctrl->pctrl_data->pin_header,
1055
+
pctrl->pctrl_data->ngpio);
1056
+
}
1057
+
1058
+
static struct platform_driver upboard_pinctrl_driver = {
1059
+
.driver = {
1060
+
.name = "upboard-pinctrl",
1061
+
},
1062
+
.probe = upboard_pinctrl_probe,
1063
+
};
1064
+
module_platform_driver(upboard_pinctrl_driver);
1065
+
1066
+
MODULE_AUTHOR("Thomas Richard <thomas.richard@bootlin.com");
1067
+
MODULE_DESCRIPTION("UP Board HAT pin controller driver");
1068
+
MODULE_LICENSE("GPL");
1069
+
MODULE_ALIAS("platform:upboard-pinctrl");
1070
+
MODULE_IMPORT_NS("GPIO_FORWARDER");
+1
-1
drivers/pinctrl/pinctrl-zynqmp.c
+1
-1
drivers/pinctrl/pinctrl-zynqmp.c
+60
-10
drivers/pinctrl/pinmux.c
+60
-10
drivers/pinctrl/pinmux.c
···
89
89
{
90
90
struct pin_desc *desc = pin_desc_get(pctldev, pin);
91
91
const struct pinmux_ops *ops = pctldev->desc->pmxops;
92
+
const struct pinctrl_setting_mux *mux_setting;
93
+
bool func_is_gpio = false;
92
94
93
95
/* Can't inspect pin, assume it can be used */
94
96
if (!desc || !ops)
95
97
return true;
96
98
99
+
mux_setting = desc->mux_setting;
100
+
97
101
guard(mutex)(&desc->mux_lock);
98
-
if (ops->strict && desc->mux_usecount)
102
+
if (mux_setting && ops->function_is_gpio)
103
+
func_is_gpio = ops->function_is_gpio(pctldev, mux_setting->func);
104
+
105
+
if (ops->strict && desc->mux_usecount && !func_is_gpio)
99
106
return false;
100
107
101
108
return !(ops->strict && !!desc->gpio_owner);
···
123
116
{
124
117
struct pin_desc *desc;
125
118
const struct pinmux_ops *ops = pctldev->desc->pmxops;
119
+
const struct pinctrl_setting_mux *mux_setting;
126
120
int status = -EINVAL;
121
+
bool gpio_ok = false;
127
122
128
123
desc = pin_desc_get(pctldev, pin);
129
124
if (desc == NULL) {
···
135
126
goto out;
136
127
}
137
128
129
+
mux_setting = desc->mux_setting;
130
+
138
131
dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
139
132
pin, desc->name, owner);
140
133
141
134
scoped_guard(mutex, &desc->mux_lock) {
142
-
if ((!gpio_range || ops->strict) &&
135
+
if (mux_setting) {
136
+
if (ops->function_is_gpio)
137
+
gpio_ok = ops->function_is_gpio(pctldev,
138
+
mux_setting->func);
139
+
} else {
140
+
gpio_ok = true;
141
+
}
142
+
143
+
if ((!gpio_range || ops->strict) && !gpio_ok &&
143
144
desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
144
145
dev_err(pctldev->dev,
145
146
"pin %s already requested by %s; cannot claim for %s\n",
···
157
138
goto out;
158
139
}
159
140
160
-
if ((gpio_range || ops->strict) && desc->gpio_owner) {
141
+
if ((gpio_range || ops->strict) && !gpio_ok && desc->gpio_owner) {
161
142
dev_err(pctldev->dev,
162
143
"pin %s already requested by %s; cannot claim for %s\n",
163
144
desc->name, desc->gpio_owner, owner);
···
356
337
while (selector < nfuncs) {
357
338
const char *fname = ops->get_function_name(pctldev, selector);
358
339
359
-
if (!strcmp(function, fname))
340
+
if (fname && !strcmp(function, fname))
360
341
return selector;
361
342
362
343
selector++;
···
829
810
if (!function)
830
811
return NULL;
831
812
832
-
return function->func.name;
813
+
return function->func->name;
833
814
}
834
815
EXPORT_SYMBOL_GPL(pinmux_generic_get_function_name);
835
816
···
854
835
__func__, selector);
855
836
return -EINVAL;
856
837
}
857
-
*groups = function->func.groups;
858
-
*ngroups = function->func.ngroups;
838
+
*groups = function->func->groups;
839
+
*ngroups = function->func->ngroups;
859
840
860
841
return 0;
861
842
}
···
866
847
* @pctldev: pin controller device
867
848
* @selector: function number
868
849
*/
869
-
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
870
-
unsigned int selector)
850
+
const struct function_desc *
851
+
pinmux_generic_get_function(struct pinctrl_dev *pctldev, unsigned int selector)
871
852
{
872
853
struct function_desc *function;
873
854
···
879
860
return function;
880
861
}
881
862
EXPORT_SYMBOL_GPL(pinmux_generic_get_function);
863
+
864
+
/**
865
+
* pinmux_generic_function_is_gpio() - returns true if given function is a GPIO
866
+
* @pctldev: pin controller device
867
+
* @selector: function number
868
+
*
869
+
* Returns:
870
+
* True if given function is a GPIO, false otherwise.
871
+
*/
872
+
bool pinmux_generic_function_is_gpio(struct pinctrl_dev *pctldev,
873
+
unsigned int selector)
874
+
{
875
+
struct function_desc *function;
876
+
877
+
function = radix_tree_lookup(&pctldev->pin_function_tree, selector);
878
+
if (!function)
879
+
return false;
880
+
881
+
return function->func->flags & PINFUNCTION_FLAG_GPIO;
882
+
}
883
+
EXPORT_SYMBOL_GPL(pinmux_generic_function_is_gpio);
882
884
883
885
/**
884
886
* pinmux_generic_add_function() - adds a function group
···
943
903
if (!function)
944
904
return -ENOMEM;
945
905
946
-
function->func = *func;
906
+
/*
907
+
* FIXME: It's generally a bad idea to use devres in subsystem core
908
+
* code - managed interfaces are aimed at drivers - but pinctrl already
909
+
* uses it all over the place so it's a larger piece of technical debt
910
+
* to fix.
911
+
*/
912
+
function->func = devm_kmemdup_const(pctldev->dev, func,
913
+
sizeof(*func), GFP_KERNEL);
914
+
if (!function->func)
915
+
return -ENOMEM;
916
+
947
917
function->data = data;
948
918
949
919
error = radix_tree_insert(&pctldev->pin_function_tree, selector, function);
+6
-3
drivers/pinctrl/pinmux.h
+6
-3
drivers/pinctrl/pinmux.h
···
137
137
* @data: pin controller driver specific data
138
138
*/
139
139
struct function_desc {
140
-
struct pinfunction func;
140
+
const struct pinfunction *func;
141
141
void *data;
142
142
};
143
143
···
152
152
const char * const **groups,
153
153
unsigned int * const ngroups);
154
154
155
-
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
156
-
unsigned int selector);
155
+
const struct function_desc *
156
+
pinmux_generic_get_function(struct pinctrl_dev *pctldev, unsigned int selector);
157
157
158
158
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
159
159
const char *name,
···
168
168
unsigned int selector);
169
169
170
170
void pinmux_generic_free_functions(struct pinctrl_dev *pctldev);
171
+
172
+
bool pinmux_generic_function_is_gpio(struct pinctrl_dev *pctldev,
173
+
unsigned int selector);
171
174
172
175
#else
173
176
+11
drivers/pinctrl/qcom/Kconfig
+11
drivers/pinctrl/qcom/Kconfig
···
8
8
depends on OF
9
9
select QCOM_SCM
10
10
select PINMUX
11
+
select GENERIC_PINMUX_FUNCTIONS
11
12
select PINCONF
12
13
select GENERIC_PINCONF
13
14
select GPIOLIB_IRQCHIP
···
68
67
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
69
68
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
70
69
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
70
+
71
+
config PINCTRL_SDM660_LPASS_LPI
72
+
tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver"
73
+
depends on GPIOLIB
74
+
depends on ARM64 || COMPILE_TEST
75
+
depends on PINCTRL_LPASS_LPI
76
+
help
77
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
78
+
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
79
+
(Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform.
71
80
72
81
config PINCTRL_SM4250_LPASS_LPI
73
82
tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
+10
drivers/pinctrl/qcom/Kconfig.msm
+10
drivers/pinctrl/qcom/Kconfig.msm
···
15
15
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16
16
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
17
17
18
+
config PINCTRL_GLYMUR
19
+
tristate "Qualcomm Technologies Inc Glymur pin controller driver"
20
+
depends on ARM64 || COMPILE_TEST
21
+
help
22
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
23
+
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
24
+
block found on the Qualcomm Technologies Inc Glymur platform.
25
+
Say Y here to compile statically, or M here to compile it as a module.
26
+
If unsure, say N.
27
+
18
28
config PINCTRL_IPQ4019
19
29
tristate "Qualcomm IPQ4019 pin controller driver"
20
30
depends on ARM || COMPILE_TEST
+2
drivers/pinctrl/qcom/Makefile
+2
drivers/pinctrl/qcom/Makefile
···
3
3
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
4
4
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
5
5
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
6
+
obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
6
7
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
7
8
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
8
9
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
···
45
44
obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
46
45
obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
47
46
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
47
+
obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o
48
48
obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
49
49
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
50
50
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
+1777
drivers/pinctrl/qcom/pinctrl-glymur.c
+1777
drivers/pinctrl/qcom/pinctrl-glymur.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/pinctrl/pinctrl.h>
11
+
12
+
#include "pinctrl-msm.h"
13
+
14
+
#define REG_SIZE 0x1000
15
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
16
+
{ \
17
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
18
+
gpio##id##_pins, \
19
+
ARRAY_SIZE(gpio##id##_pins)), \
20
+
.ctl_reg = REG_SIZE * id, \
21
+
.io_reg = 0x4 + REG_SIZE * id, \
22
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
23
+
.intr_status_reg = 0xc + REG_SIZE * id, \
24
+
.intr_target_reg = 0x8 + REG_SIZE * id, \
25
+
.mux_bit = 2, \
26
+
.pull_bit = 0, \
27
+
.drv_bit = 6, \
28
+
.egpio_enable = 12, \
29
+
.egpio_present = 11, \
30
+
.oe_bit = 9, \
31
+
.in_bit = 0, \
32
+
.out_bit = 1, \
33
+
.intr_enable_bit = 0, \
34
+
.intr_status_bit = 0, \
35
+
.intr_target_bit = 5, \
36
+
.intr_target_kpss_val = 3, \
37
+
.intr_raw_status_bit = 4, \
38
+
.intr_polarity_bit = 1, \
39
+
.intr_detection_bit = 2, \
40
+
.intr_detection_width = 2, \
41
+
.funcs = (int[]){ \
42
+
msm_mux_gpio, /* gpio mode */ \
43
+
msm_mux_##f1, \
44
+
msm_mux_##f2, \
45
+
msm_mux_##f3, \
46
+
msm_mux_##f4, \
47
+
msm_mux_##f5, \
48
+
msm_mux_##f6, \
49
+
msm_mux_##f7, \
50
+
msm_mux_##f8, \
51
+
msm_mux_##f9, \
52
+
msm_mux_##f10, \
53
+
msm_mux_##f11 /* egpio mode */ \
54
+
}, \
55
+
.nfuncs = 12, \
56
+
}
57
+
58
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
59
+
{ \
60
+
.grp = PINCTRL_PINGROUP(#pg_name, \
61
+
pg_name##_pins, \
62
+
ARRAY_SIZE(pg_name##_pins)), \
63
+
.ctl_reg = ctl, \
64
+
.io_reg = 0, \
65
+
.intr_cfg_reg = 0, \
66
+
.intr_status_reg = 0, \
67
+
.intr_target_reg = 0, \
68
+
.mux_bit = -1, \
69
+
.pull_bit = pull, \
70
+
.drv_bit = drv, \
71
+
.oe_bit = -1, \
72
+
.in_bit = -1, \
73
+
.out_bit = -1, \
74
+
.intr_enable_bit = -1, \
75
+
.intr_status_bit = -1, \
76
+
.intr_target_bit = -1, \
77
+
.intr_raw_status_bit = -1, \
78
+
.intr_polarity_bit = -1, \
79
+
.intr_detection_bit = -1, \
80
+
.intr_detection_width = -1, \
81
+
}
82
+
83
+
#define UFS_RESET(pg_name, ctl, io) \
84
+
{ \
85
+
.grp = PINCTRL_PINGROUP(#pg_name, \
86
+
pg_name##_pins, \
87
+
ARRAY_SIZE(pg_name##_pins)), \
88
+
.ctl_reg = ctl, \
89
+
.io_reg = io, \
90
+
.intr_cfg_reg = 0, \
91
+
.intr_status_reg = 0, \
92
+
.intr_target_reg = 0, \
93
+
.mux_bit = -1, \
94
+
.pull_bit = 3, \
95
+
.drv_bit = 0, \
96
+
.oe_bit = -1, \
97
+
.in_bit = -1, \
98
+
.out_bit = 0, \
99
+
.intr_enable_bit = -1, \
100
+
.intr_status_bit = -1, \
101
+
.intr_target_bit = -1, \
102
+
.intr_raw_status_bit = -1, \
103
+
.intr_polarity_bit = -1, \
104
+
.intr_detection_bit = -1, \
105
+
.intr_detection_width = -1, \
106
+
}
107
+
108
+
static const struct pinctrl_pin_desc glymur_pins[] = {
109
+
PINCTRL_PIN(0, "GPIO_0"),
110
+
PINCTRL_PIN(1, "GPIO_1"),
111
+
PINCTRL_PIN(2, "GPIO_2"),
112
+
PINCTRL_PIN(3, "GPIO_3"),
113
+
PINCTRL_PIN(4, "GPIO_4"),
114
+
PINCTRL_PIN(5, "GPIO_5"),
115
+
PINCTRL_PIN(6, "GPIO_6"),
116
+
PINCTRL_PIN(7, "GPIO_7"),
117
+
PINCTRL_PIN(8, "GPIO_8"),
118
+
PINCTRL_PIN(9, "GPIO_9"),
119
+
PINCTRL_PIN(10, "GPIO_10"),
120
+
PINCTRL_PIN(11, "GPIO_11"),
121
+
PINCTRL_PIN(12, "GPIO_12"),
122
+
PINCTRL_PIN(13, "GPIO_13"),
123
+
PINCTRL_PIN(14, "GPIO_14"),
124
+
PINCTRL_PIN(15, "GPIO_15"),
125
+
PINCTRL_PIN(16, "GPIO_16"),
126
+
PINCTRL_PIN(17, "GPIO_17"),
127
+
PINCTRL_PIN(18, "GPIO_18"),
128
+
PINCTRL_PIN(19, "GPIO_19"),
129
+
PINCTRL_PIN(20, "GPIO_20"),
130
+
PINCTRL_PIN(21, "GPIO_21"),
131
+
PINCTRL_PIN(22, "GPIO_22"),
132
+
PINCTRL_PIN(23, "GPIO_23"),
133
+
PINCTRL_PIN(24, "GPIO_24"),
134
+
PINCTRL_PIN(25, "GPIO_25"),
135
+
PINCTRL_PIN(26, "GPIO_26"),
136
+
PINCTRL_PIN(27, "GPIO_27"),
137
+
PINCTRL_PIN(28, "GPIO_28"),
138
+
PINCTRL_PIN(29, "GPIO_29"),
139
+
PINCTRL_PIN(30, "GPIO_30"),
140
+
PINCTRL_PIN(31, "GPIO_31"),
141
+
PINCTRL_PIN(32, "GPIO_32"),
142
+
PINCTRL_PIN(33, "GPIO_33"),
143
+
PINCTRL_PIN(34, "GPIO_34"),
144
+
PINCTRL_PIN(35, "GPIO_35"),
145
+
PINCTRL_PIN(36, "GPIO_36"),
146
+
PINCTRL_PIN(37, "GPIO_37"),
147
+
PINCTRL_PIN(38, "GPIO_38"),
148
+
PINCTRL_PIN(39, "GPIO_39"),
149
+
PINCTRL_PIN(40, "GPIO_40"),
150
+
PINCTRL_PIN(41, "GPIO_41"),
151
+
PINCTRL_PIN(42, "GPIO_42"),
152
+
PINCTRL_PIN(43, "GPIO_43"),
153
+
PINCTRL_PIN(44, "GPIO_44"),
154
+
PINCTRL_PIN(45, "GPIO_45"),
155
+
PINCTRL_PIN(46, "GPIO_46"),
156
+
PINCTRL_PIN(47, "GPIO_47"),
157
+
PINCTRL_PIN(48, "GPIO_48"),
158
+
PINCTRL_PIN(49, "GPIO_49"),
159
+
PINCTRL_PIN(50, "GPIO_50"),
160
+
PINCTRL_PIN(51, "GPIO_51"),
161
+
PINCTRL_PIN(52, "GPIO_52"),
162
+
PINCTRL_PIN(53, "GPIO_53"),
163
+
PINCTRL_PIN(54, "GPIO_54"),
164
+
PINCTRL_PIN(55, "GPIO_55"),
165
+
PINCTRL_PIN(56, "GPIO_56"),
166
+
PINCTRL_PIN(57, "GPIO_57"),
167
+
PINCTRL_PIN(58, "GPIO_58"),
168
+
PINCTRL_PIN(59, "GPIO_59"),
169
+
PINCTRL_PIN(60, "GPIO_60"),
170
+
PINCTRL_PIN(61, "GPIO_61"),
171
+
PINCTRL_PIN(62, "GPIO_62"),
172
+
PINCTRL_PIN(63, "GPIO_63"),
173
+
PINCTRL_PIN(64, "GPIO_64"),
174
+
PINCTRL_PIN(65, "GPIO_65"),
175
+
PINCTRL_PIN(66, "GPIO_66"),
176
+
PINCTRL_PIN(67, "GPIO_67"),
177
+
PINCTRL_PIN(68, "GPIO_68"),
178
+
PINCTRL_PIN(69, "GPIO_69"),
179
+
PINCTRL_PIN(70, "GPIO_70"),
180
+
PINCTRL_PIN(71, "GPIO_71"),
181
+
PINCTRL_PIN(72, "GPIO_72"),
182
+
PINCTRL_PIN(73, "GPIO_73"),
183
+
PINCTRL_PIN(74, "GPIO_74"),
184
+
PINCTRL_PIN(75, "GPIO_75"),
185
+
PINCTRL_PIN(76, "GPIO_76"),
186
+
PINCTRL_PIN(77, "GPIO_77"),
187
+
PINCTRL_PIN(78, "GPIO_78"),
188
+
PINCTRL_PIN(79, "GPIO_79"),
189
+
PINCTRL_PIN(80, "GPIO_80"),
190
+
PINCTRL_PIN(81, "GPIO_81"),
191
+
PINCTRL_PIN(82, "GPIO_82"),
192
+
PINCTRL_PIN(83, "GPIO_83"),
193
+
PINCTRL_PIN(84, "GPIO_84"),
194
+
PINCTRL_PIN(85, "GPIO_85"),
195
+
PINCTRL_PIN(86, "GPIO_86"),
196
+
PINCTRL_PIN(87, "GPIO_87"),
197
+
PINCTRL_PIN(88, "GPIO_88"),
198
+
PINCTRL_PIN(89, "GPIO_89"),
199
+
PINCTRL_PIN(90, "GPIO_90"),
200
+
PINCTRL_PIN(91, "GPIO_91"),
201
+
PINCTRL_PIN(92, "GPIO_92"),
202
+
PINCTRL_PIN(93, "GPIO_93"),
203
+
PINCTRL_PIN(94, "GPIO_94"),
204
+
PINCTRL_PIN(95, "GPIO_95"),
205
+
PINCTRL_PIN(96, "GPIO_96"),
206
+
PINCTRL_PIN(97, "GPIO_97"),
207
+
PINCTRL_PIN(98, "GPIO_98"),
208
+
PINCTRL_PIN(99, "GPIO_99"),
209
+
PINCTRL_PIN(100, "GPIO_100"),
210
+
PINCTRL_PIN(101, "GPIO_101"),
211
+
PINCTRL_PIN(102, "GPIO_102"),
212
+
PINCTRL_PIN(103, "GPIO_103"),
213
+
PINCTRL_PIN(104, "GPIO_104"),
214
+
PINCTRL_PIN(105, "GPIO_105"),
215
+
PINCTRL_PIN(106, "GPIO_106"),
216
+
PINCTRL_PIN(107, "GPIO_107"),
217
+
PINCTRL_PIN(108, "GPIO_108"),
218
+
PINCTRL_PIN(109, "GPIO_109"),
219
+
PINCTRL_PIN(110, "GPIO_110"),
220
+
PINCTRL_PIN(111, "GPIO_111"),
221
+
PINCTRL_PIN(112, "GPIO_112"),
222
+
PINCTRL_PIN(113, "GPIO_113"),
223
+
PINCTRL_PIN(114, "GPIO_114"),
224
+
PINCTRL_PIN(115, "GPIO_115"),
225
+
PINCTRL_PIN(116, "GPIO_116"),
226
+
PINCTRL_PIN(117, "GPIO_117"),
227
+
PINCTRL_PIN(118, "GPIO_118"),
228
+
PINCTRL_PIN(119, "GPIO_119"),
229
+
PINCTRL_PIN(120, "GPIO_120"),
230
+
PINCTRL_PIN(121, "GPIO_121"),
231
+
PINCTRL_PIN(122, "GPIO_122"),
232
+
PINCTRL_PIN(123, "GPIO_123"),
233
+
PINCTRL_PIN(124, "GPIO_124"),
234
+
PINCTRL_PIN(125, "GPIO_125"),
235
+
PINCTRL_PIN(126, "GPIO_126"),
236
+
PINCTRL_PIN(127, "GPIO_127"),
237
+
PINCTRL_PIN(128, "GPIO_128"),
238
+
PINCTRL_PIN(129, "GPIO_129"),
239
+
PINCTRL_PIN(130, "GPIO_130"),
240
+
PINCTRL_PIN(131, "GPIO_131"),
241
+
PINCTRL_PIN(132, "GPIO_132"),
242
+
PINCTRL_PIN(133, "GPIO_133"),
243
+
PINCTRL_PIN(134, "GPIO_134"),
244
+
PINCTRL_PIN(135, "GPIO_135"),
245
+
PINCTRL_PIN(136, "GPIO_136"),
246
+
PINCTRL_PIN(137, "GPIO_137"),
247
+
PINCTRL_PIN(138, "GPIO_138"),
248
+
PINCTRL_PIN(139, "GPIO_139"),
249
+
PINCTRL_PIN(140, "GPIO_140"),
250
+
PINCTRL_PIN(141, "GPIO_141"),
251
+
PINCTRL_PIN(142, "GPIO_142"),
252
+
PINCTRL_PIN(143, "GPIO_143"),
253
+
PINCTRL_PIN(144, "GPIO_144"),
254
+
PINCTRL_PIN(145, "GPIO_145"),
255
+
PINCTRL_PIN(146, "GPIO_146"),
256
+
PINCTRL_PIN(147, "GPIO_147"),
257
+
PINCTRL_PIN(148, "GPIO_148"),
258
+
PINCTRL_PIN(149, "GPIO_149"),
259
+
PINCTRL_PIN(150, "GPIO_150"),
260
+
PINCTRL_PIN(151, "GPIO_151"),
261
+
PINCTRL_PIN(152, "GPIO_152"),
262
+
PINCTRL_PIN(153, "GPIO_153"),
263
+
PINCTRL_PIN(154, "GPIO_154"),
264
+
PINCTRL_PIN(155, "GPIO_155"),
265
+
PINCTRL_PIN(156, "GPIO_156"),
266
+
PINCTRL_PIN(157, "GPIO_157"),
267
+
PINCTRL_PIN(158, "GPIO_158"),
268
+
PINCTRL_PIN(159, "GPIO_159"),
269
+
PINCTRL_PIN(160, "GPIO_160"),
270
+
PINCTRL_PIN(161, "GPIO_161"),
271
+
PINCTRL_PIN(162, "GPIO_162"),
272
+
PINCTRL_PIN(163, "GPIO_163"),
273
+
PINCTRL_PIN(164, "GPIO_164"),
274
+
PINCTRL_PIN(165, "GPIO_165"),
275
+
PINCTRL_PIN(166, "GPIO_166"),
276
+
PINCTRL_PIN(167, "GPIO_167"),
277
+
PINCTRL_PIN(168, "GPIO_168"),
278
+
PINCTRL_PIN(169, "GPIO_169"),
279
+
PINCTRL_PIN(170, "GPIO_170"),
280
+
PINCTRL_PIN(171, "GPIO_171"),
281
+
PINCTRL_PIN(172, "GPIO_172"),
282
+
PINCTRL_PIN(173, "GPIO_173"),
283
+
PINCTRL_PIN(174, "GPIO_174"),
284
+
PINCTRL_PIN(175, "GPIO_175"),
285
+
PINCTRL_PIN(176, "GPIO_176"),
286
+
PINCTRL_PIN(177, "GPIO_177"),
287
+
PINCTRL_PIN(178, "GPIO_178"),
288
+
PINCTRL_PIN(179, "GPIO_179"),
289
+
PINCTRL_PIN(180, "GPIO_180"),
290
+
PINCTRL_PIN(181, "GPIO_181"),
291
+
PINCTRL_PIN(182, "GPIO_182"),
292
+
PINCTRL_PIN(183, "GPIO_183"),
293
+
PINCTRL_PIN(184, "GPIO_184"),
294
+
PINCTRL_PIN(185, "GPIO_185"),
295
+
PINCTRL_PIN(186, "GPIO_186"),
296
+
PINCTRL_PIN(187, "GPIO_187"),
297
+
PINCTRL_PIN(188, "GPIO_188"),
298
+
PINCTRL_PIN(189, "GPIO_189"),
299
+
PINCTRL_PIN(190, "GPIO_190"),
300
+
PINCTRL_PIN(191, "GPIO_191"),
301
+
PINCTRL_PIN(192, "GPIO_192"),
302
+
PINCTRL_PIN(193, "GPIO_193"),
303
+
PINCTRL_PIN(194, "GPIO_194"),
304
+
PINCTRL_PIN(195, "GPIO_195"),
305
+
PINCTRL_PIN(196, "GPIO_196"),
306
+
PINCTRL_PIN(197, "GPIO_197"),
307
+
PINCTRL_PIN(198, "GPIO_198"),
308
+
PINCTRL_PIN(199, "GPIO_199"),
309
+
PINCTRL_PIN(200, "GPIO_200"),
310
+
PINCTRL_PIN(201, "GPIO_201"),
311
+
PINCTRL_PIN(202, "GPIO_202"),
312
+
PINCTRL_PIN(203, "GPIO_203"),
313
+
PINCTRL_PIN(204, "GPIO_204"),
314
+
PINCTRL_PIN(205, "GPIO_205"),
315
+
PINCTRL_PIN(206, "GPIO_206"),
316
+
PINCTRL_PIN(207, "GPIO_207"),
317
+
PINCTRL_PIN(208, "GPIO_208"),
318
+
PINCTRL_PIN(209, "GPIO_209"),
319
+
PINCTRL_PIN(210, "GPIO_210"),
320
+
PINCTRL_PIN(211, "GPIO_211"),
321
+
PINCTRL_PIN(212, "GPIO_212"),
322
+
PINCTRL_PIN(213, "GPIO_213"),
323
+
PINCTRL_PIN(214, "GPIO_214"),
324
+
PINCTRL_PIN(215, "GPIO_215"),
325
+
PINCTRL_PIN(216, "GPIO_216"),
326
+
PINCTRL_PIN(217, "GPIO_217"),
327
+
PINCTRL_PIN(218, "GPIO_218"),
328
+
PINCTRL_PIN(219, "GPIO_219"),
329
+
PINCTRL_PIN(220, "GPIO_220"),
330
+
PINCTRL_PIN(221, "GPIO_221"),
331
+
PINCTRL_PIN(222, "GPIO_222"),
332
+
PINCTRL_PIN(223, "GPIO_223"),
333
+
PINCTRL_PIN(224, "GPIO_224"),
334
+
PINCTRL_PIN(225, "GPIO_225"),
335
+
PINCTRL_PIN(226, "GPIO_226"),
336
+
PINCTRL_PIN(227, "GPIO_227"),
337
+
PINCTRL_PIN(228, "GPIO_228"),
338
+
PINCTRL_PIN(229, "GPIO_229"),
339
+
PINCTRL_PIN(230, "GPIO_230"),
340
+
PINCTRL_PIN(231, "GPIO_231"),
341
+
PINCTRL_PIN(232, "GPIO_232"),
342
+
PINCTRL_PIN(233, "GPIO_233"),
343
+
PINCTRL_PIN(234, "GPIO_234"),
344
+
PINCTRL_PIN(235, "GPIO_235"),
345
+
PINCTRL_PIN(236, "GPIO_236"),
346
+
PINCTRL_PIN(237, "GPIO_237"),
347
+
PINCTRL_PIN(238, "GPIO_238"),
348
+
PINCTRL_PIN(239, "GPIO_239"),
349
+
PINCTRL_PIN(240, "GPIO_240"),
350
+
PINCTRL_PIN(241, "GPIO_241"),
351
+
PINCTRL_PIN(242, "GPIO_242"),
352
+
PINCTRL_PIN(243, "GPIO_243"),
353
+
PINCTRL_PIN(244, "GPIO_244"),
354
+
PINCTRL_PIN(245, "GPIO_245"),
355
+
PINCTRL_PIN(246, "GPIO_246"),
356
+
PINCTRL_PIN(247, "GPIO_247"),
357
+
PINCTRL_PIN(248, "GPIO_248"),
358
+
PINCTRL_PIN(249, "GPIO_249"),
359
+
};
360
+
361
+
#define DECLARE_MSM_GPIO_PINS(pin) \
362
+
static const unsigned int gpio##pin##_pins[] = { pin }
363
+
DECLARE_MSM_GPIO_PINS(0);
364
+
DECLARE_MSM_GPIO_PINS(1);
365
+
DECLARE_MSM_GPIO_PINS(2);
366
+
DECLARE_MSM_GPIO_PINS(3);
367
+
DECLARE_MSM_GPIO_PINS(4);
368
+
DECLARE_MSM_GPIO_PINS(5);
369
+
DECLARE_MSM_GPIO_PINS(6);
370
+
DECLARE_MSM_GPIO_PINS(7);
371
+
DECLARE_MSM_GPIO_PINS(8);
372
+
DECLARE_MSM_GPIO_PINS(9);
373
+
DECLARE_MSM_GPIO_PINS(10);
374
+
DECLARE_MSM_GPIO_PINS(11);
375
+
DECLARE_MSM_GPIO_PINS(12);
376
+
DECLARE_MSM_GPIO_PINS(13);
377
+
DECLARE_MSM_GPIO_PINS(14);
378
+
DECLARE_MSM_GPIO_PINS(15);
379
+
DECLARE_MSM_GPIO_PINS(16);
380
+
DECLARE_MSM_GPIO_PINS(17);
381
+
DECLARE_MSM_GPIO_PINS(18);
382
+
DECLARE_MSM_GPIO_PINS(19);
383
+
DECLARE_MSM_GPIO_PINS(20);
384
+
DECLARE_MSM_GPIO_PINS(21);
385
+
DECLARE_MSM_GPIO_PINS(22);
386
+
DECLARE_MSM_GPIO_PINS(23);
387
+
DECLARE_MSM_GPIO_PINS(24);
388
+
DECLARE_MSM_GPIO_PINS(25);
389
+
DECLARE_MSM_GPIO_PINS(26);
390
+
DECLARE_MSM_GPIO_PINS(27);
391
+
DECLARE_MSM_GPIO_PINS(28);
392
+
DECLARE_MSM_GPIO_PINS(29);
393
+
DECLARE_MSM_GPIO_PINS(30);
394
+
DECLARE_MSM_GPIO_PINS(31);
395
+
DECLARE_MSM_GPIO_PINS(32);
396
+
DECLARE_MSM_GPIO_PINS(33);
397
+
DECLARE_MSM_GPIO_PINS(34);
398
+
DECLARE_MSM_GPIO_PINS(35);
399
+
DECLARE_MSM_GPIO_PINS(36);
400
+
DECLARE_MSM_GPIO_PINS(37);
401
+
DECLARE_MSM_GPIO_PINS(38);
402
+
DECLARE_MSM_GPIO_PINS(39);
403
+
DECLARE_MSM_GPIO_PINS(40);
404
+
DECLARE_MSM_GPIO_PINS(41);
405
+
DECLARE_MSM_GPIO_PINS(42);
406
+
DECLARE_MSM_GPIO_PINS(43);
407
+
DECLARE_MSM_GPIO_PINS(44);
408
+
DECLARE_MSM_GPIO_PINS(45);
409
+
DECLARE_MSM_GPIO_PINS(46);
410
+
DECLARE_MSM_GPIO_PINS(47);
411
+
DECLARE_MSM_GPIO_PINS(48);
412
+
DECLARE_MSM_GPIO_PINS(49);
413
+
DECLARE_MSM_GPIO_PINS(50);
414
+
DECLARE_MSM_GPIO_PINS(51);
415
+
DECLARE_MSM_GPIO_PINS(52);
416
+
DECLARE_MSM_GPIO_PINS(53);
417
+
DECLARE_MSM_GPIO_PINS(54);
418
+
DECLARE_MSM_GPIO_PINS(55);
419
+
DECLARE_MSM_GPIO_PINS(56);
420
+
DECLARE_MSM_GPIO_PINS(57);
421
+
DECLARE_MSM_GPIO_PINS(58);
422
+
DECLARE_MSM_GPIO_PINS(59);
423
+
DECLARE_MSM_GPIO_PINS(60);
424
+
DECLARE_MSM_GPIO_PINS(61);
425
+
DECLARE_MSM_GPIO_PINS(62);
426
+
DECLARE_MSM_GPIO_PINS(63);
427
+
DECLARE_MSM_GPIO_PINS(64);
428
+
DECLARE_MSM_GPIO_PINS(65);
429
+
DECLARE_MSM_GPIO_PINS(66);
430
+
DECLARE_MSM_GPIO_PINS(67);
431
+
DECLARE_MSM_GPIO_PINS(68);
432
+
DECLARE_MSM_GPIO_PINS(69);
433
+
DECLARE_MSM_GPIO_PINS(70);
434
+
DECLARE_MSM_GPIO_PINS(71);
435
+
DECLARE_MSM_GPIO_PINS(72);
436
+
DECLARE_MSM_GPIO_PINS(73);
437
+
DECLARE_MSM_GPIO_PINS(74);
438
+
DECLARE_MSM_GPIO_PINS(75);
439
+
DECLARE_MSM_GPIO_PINS(76);
440
+
DECLARE_MSM_GPIO_PINS(77);
441
+
DECLARE_MSM_GPIO_PINS(78);
442
+
DECLARE_MSM_GPIO_PINS(79);
443
+
DECLARE_MSM_GPIO_PINS(80);
444
+
DECLARE_MSM_GPIO_PINS(81);
445
+
DECLARE_MSM_GPIO_PINS(82);
446
+
DECLARE_MSM_GPIO_PINS(83);
447
+
DECLARE_MSM_GPIO_PINS(84);
448
+
DECLARE_MSM_GPIO_PINS(85);
449
+
DECLARE_MSM_GPIO_PINS(86);
450
+
DECLARE_MSM_GPIO_PINS(87);
451
+
DECLARE_MSM_GPIO_PINS(88);
452
+
DECLARE_MSM_GPIO_PINS(89);
453
+
DECLARE_MSM_GPIO_PINS(90);
454
+
DECLARE_MSM_GPIO_PINS(91);
455
+
DECLARE_MSM_GPIO_PINS(92);
456
+
DECLARE_MSM_GPIO_PINS(93);
457
+
DECLARE_MSM_GPIO_PINS(94);
458
+
DECLARE_MSM_GPIO_PINS(95);
459
+
DECLARE_MSM_GPIO_PINS(96);
460
+
DECLARE_MSM_GPIO_PINS(97);
461
+
DECLARE_MSM_GPIO_PINS(98);
462
+
DECLARE_MSM_GPIO_PINS(99);
463
+
DECLARE_MSM_GPIO_PINS(100);
464
+
DECLARE_MSM_GPIO_PINS(101);
465
+
DECLARE_MSM_GPIO_PINS(102);
466
+
DECLARE_MSM_GPIO_PINS(103);
467
+
DECLARE_MSM_GPIO_PINS(104);
468
+
DECLARE_MSM_GPIO_PINS(105);
469
+
DECLARE_MSM_GPIO_PINS(106);
470
+
DECLARE_MSM_GPIO_PINS(107);
471
+
DECLARE_MSM_GPIO_PINS(108);
472
+
DECLARE_MSM_GPIO_PINS(109);
473
+
DECLARE_MSM_GPIO_PINS(110);
474
+
DECLARE_MSM_GPIO_PINS(111);
475
+
DECLARE_MSM_GPIO_PINS(112);
476
+
DECLARE_MSM_GPIO_PINS(113);
477
+
DECLARE_MSM_GPIO_PINS(114);
478
+
DECLARE_MSM_GPIO_PINS(115);
479
+
DECLARE_MSM_GPIO_PINS(116);
480
+
DECLARE_MSM_GPIO_PINS(117);
481
+
DECLARE_MSM_GPIO_PINS(118);
482
+
DECLARE_MSM_GPIO_PINS(119);
483
+
DECLARE_MSM_GPIO_PINS(120);
484
+
DECLARE_MSM_GPIO_PINS(121);
485
+
DECLARE_MSM_GPIO_PINS(122);
486
+
DECLARE_MSM_GPIO_PINS(123);
487
+
DECLARE_MSM_GPIO_PINS(124);
488
+
DECLARE_MSM_GPIO_PINS(125);
489
+
DECLARE_MSM_GPIO_PINS(126);
490
+
DECLARE_MSM_GPIO_PINS(127);
491
+
DECLARE_MSM_GPIO_PINS(128);
492
+
DECLARE_MSM_GPIO_PINS(129);
493
+
DECLARE_MSM_GPIO_PINS(130);
494
+
DECLARE_MSM_GPIO_PINS(131);
495
+
DECLARE_MSM_GPIO_PINS(132);
496
+
DECLARE_MSM_GPIO_PINS(133);
497
+
DECLARE_MSM_GPIO_PINS(134);
498
+
DECLARE_MSM_GPIO_PINS(135);
499
+
DECLARE_MSM_GPIO_PINS(136);
500
+
DECLARE_MSM_GPIO_PINS(137);
501
+
DECLARE_MSM_GPIO_PINS(138);
502
+
DECLARE_MSM_GPIO_PINS(139);
503
+
DECLARE_MSM_GPIO_PINS(140);
504
+
DECLARE_MSM_GPIO_PINS(141);
505
+
DECLARE_MSM_GPIO_PINS(142);
506
+
DECLARE_MSM_GPIO_PINS(143);
507
+
DECLARE_MSM_GPIO_PINS(144);
508
+
DECLARE_MSM_GPIO_PINS(145);
509
+
DECLARE_MSM_GPIO_PINS(146);
510
+
DECLARE_MSM_GPIO_PINS(147);
511
+
DECLARE_MSM_GPIO_PINS(148);
512
+
DECLARE_MSM_GPIO_PINS(149);
513
+
DECLARE_MSM_GPIO_PINS(150);
514
+
DECLARE_MSM_GPIO_PINS(151);
515
+
DECLARE_MSM_GPIO_PINS(152);
516
+
DECLARE_MSM_GPIO_PINS(153);
517
+
DECLARE_MSM_GPIO_PINS(154);
518
+
DECLARE_MSM_GPIO_PINS(155);
519
+
DECLARE_MSM_GPIO_PINS(156);
520
+
DECLARE_MSM_GPIO_PINS(157);
521
+
DECLARE_MSM_GPIO_PINS(158);
522
+
DECLARE_MSM_GPIO_PINS(159);
523
+
DECLARE_MSM_GPIO_PINS(160);
524
+
DECLARE_MSM_GPIO_PINS(161);
525
+
DECLARE_MSM_GPIO_PINS(162);
526
+
DECLARE_MSM_GPIO_PINS(163);
527
+
DECLARE_MSM_GPIO_PINS(164);
528
+
DECLARE_MSM_GPIO_PINS(165);
529
+
DECLARE_MSM_GPIO_PINS(166);
530
+
DECLARE_MSM_GPIO_PINS(167);
531
+
DECLARE_MSM_GPIO_PINS(168);
532
+
DECLARE_MSM_GPIO_PINS(169);
533
+
DECLARE_MSM_GPIO_PINS(170);
534
+
DECLARE_MSM_GPIO_PINS(171);
535
+
DECLARE_MSM_GPIO_PINS(172);
536
+
DECLARE_MSM_GPIO_PINS(173);
537
+
DECLARE_MSM_GPIO_PINS(174);
538
+
DECLARE_MSM_GPIO_PINS(175);
539
+
DECLARE_MSM_GPIO_PINS(176);
540
+
DECLARE_MSM_GPIO_PINS(177);
541
+
DECLARE_MSM_GPIO_PINS(178);
542
+
DECLARE_MSM_GPIO_PINS(179);
543
+
DECLARE_MSM_GPIO_PINS(180);
544
+
DECLARE_MSM_GPIO_PINS(181);
545
+
DECLARE_MSM_GPIO_PINS(182);
546
+
DECLARE_MSM_GPIO_PINS(183);
547
+
DECLARE_MSM_GPIO_PINS(184);
548
+
DECLARE_MSM_GPIO_PINS(185);
549
+
DECLARE_MSM_GPIO_PINS(186);
550
+
DECLARE_MSM_GPIO_PINS(187);
551
+
DECLARE_MSM_GPIO_PINS(188);
552
+
DECLARE_MSM_GPIO_PINS(189);
553
+
DECLARE_MSM_GPIO_PINS(190);
554
+
DECLARE_MSM_GPIO_PINS(191);
555
+
DECLARE_MSM_GPIO_PINS(192);
556
+
DECLARE_MSM_GPIO_PINS(193);
557
+
DECLARE_MSM_GPIO_PINS(194);
558
+
DECLARE_MSM_GPIO_PINS(195);
559
+
DECLARE_MSM_GPIO_PINS(196);
560
+
DECLARE_MSM_GPIO_PINS(197);
561
+
DECLARE_MSM_GPIO_PINS(198);
562
+
DECLARE_MSM_GPIO_PINS(199);
563
+
DECLARE_MSM_GPIO_PINS(200);
564
+
DECLARE_MSM_GPIO_PINS(201);
565
+
DECLARE_MSM_GPIO_PINS(202);
566
+
DECLARE_MSM_GPIO_PINS(203);
567
+
DECLARE_MSM_GPIO_PINS(204);
568
+
DECLARE_MSM_GPIO_PINS(205);
569
+
DECLARE_MSM_GPIO_PINS(206);
570
+
DECLARE_MSM_GPIO_PINS(207);
571
+
DECLARE_MSM_GPIO_PINS(208);
572
+
DECLARE_MSM_GPIO_PINS(209);
573
+
DECLARE_MSM_GPIO_PINS(210);
574
+
DECLARE_MSM_GPIO_PINS(211);
575
+
DECLARE_MSM_GPIO_PINS(212);
576
+
DECLARE_MSM_GPIO_PINS(213);
577
+
DECLARE_MSM_GPIO_PINS(214);
578
+
DECLARE_MSM_GPIO_PINS(215);
579
+
DECLARE_MSM_GPIO_PINS(216);
580
+
DECLARE_MSM_GPIO_PINS(217);
581
+
DECLARE_MSM_GPIO_PINS(218);
582
+
DECLARE_MSM_GPIO_PINS(219);
583
+
DECLARE_MSM_GPIO_PINS(220);
584
+
DECLARE_MSM_GPIO_PINS(221);
585
+
DECLARE_MSM_GPIO_PINS(222);
586
+
DECLARE_MSM_GPIO_PINS(223);
587
+
DECLARE_MSM_GPIO_PINS(224);
588
+
DECLARE_MSM_GPIO_PINS(225);
589
+
DECLARE_MSM_GPIO_PINS(226);
590
+
DECLARE_MSM_GPIO_PINS(227);
591
+
DECLARE_MSM_GPIO_PINS(228);
592
+
DECLARE_MSM_GPIO_PINS(229);
593
+
DECLARE_MSM_GPIO_PINS(230);
594
+
DECLARE_MSM_GPIO_PINS(231);
595
+
DECLARE_MSM_GPIO_PINS(232);
596
+
DECLARE_MSM_GPIO_PINS(233);
597
+
DECLARE_MSM_GPIO_PINS(234);
598
+
DECLARE_MSM_GPIO_PINS(235);
599
+
DECLARE_MSM_GPIO_PINS(236);
600
+
DECLARE_MSM_GPIO_PINS(237);
601
+
DECLARE_MSM_GPIO_PINS(238);
602
+
DECLARE_MSM_GPIO_PINS(239);
603
+
DECLARE_MSM_GPIO_PINS(240);
604
+
DECLARE_MSM_GPIO_PINS(241);
605
+
DECLARE_MSM_GPIO_PINS(242);
606
+
DECLARE_MSM_GPIO_PINS(243);
607
+
DECLARE_MSM_GPIO_PINS(244);
608
+
DECLARE_MSM_GPIO_PINS(245);
609
+
DECLARE_MSM_GPIO_PINS(246);
610
+
DECLARE_MSM_GPIO_PINS(247);
611
+
DECLARE_MSM_GPIO_PINS(248);
612
+
DECLARE_MSM_GPIO_PINS(249);
613
+
614
+
static const unsigned int ufs_reset_pins[] = { 250 };
615
+
static const unsigned int sdc2_clk_pins[] = { 251 };
616
+
static const unsigned int sdc2_cmd_pins[] = { 252 };
617
+
static const unsigned int sdc2_data_pins[] = { 253 };
618
+
619
+
enum glymur_functions {
620
+
msm_mux_gpio,
621
+
msm_mux_resout_gpio_n,
622
+
msm_mux_aoss_cti,
623
+
msm_mux_asc_cci,
624
+
msm_mux_atest_char,
625
+
msm_mux_atest_usb,
626
+
msm_mux_audio_ext_mclk0,
627
+
msm_mux_audio_ext_mclk1,
628
+
msm_mux_audio_ref_clk,
629
+
msm_mux_cam_asc_mclk4,
630
+
msm_mux_cam_mclk,
631
+
msm_mux_cci_async_in,
632
+
msm_mux_cci_i2c_scl,
633
+
msm_mux_cci_i2c_sda,
634
+
msm_mux_cci_timer,
635
+
msm_mux_cmu_rng,
636
+
msm_mux_cri_trng,
637
+
msm_mux_dbg_out_clk,
638
+
msm_mux_ddr_bist_complete,
639
+
msm_mux_ddr_bist_fail,
640
+
msm_mux_ddr_bist_start,
641
+
msm_mux_ddr_bist_stop,
642
+
msm_mux_ddr_pxi,
643
+
msm_mux_edp0_hot,
644
+
msm_mux_edp0_lcd,
645
+
msm_mux_edp1_lcd,
646
+
msm_mux_egpio,
647
+
msm_mux_eusb_ac_en,
648
+
msm_mux_gcc_gp1,
649
+
msm_mux_gcc_gp2,
650
+
msm_mux_gcc_gp3,
651
+
msm_mux_host2wlan_sol,
652
+
msm_mux_i2c0_s_scl,
653
+
msm_mux_i2c0_s_sda,
654
+
msm_mux_i2s0_data,
655
+
msm_mux_i2s0_sck,
656
+
msm_mux_i2s0_ws,
657
+
msm_mux_i2s1_data,
658
+
msm_mux_i2s1_sck,
659
+
msm_mux_i2s1_ws,
660
+
msm_mux_ibi_i3c,
661
+
msm_mux_jitter_bist,
662
+
msm_mux_mdp_vsync_out,
663
+
msm_mux_mdp_vsync_e,
664
+
msm_mux_mdp_vsync_p,
665
+
msm_mux_mdp_vsync_s,
666
+
msm_mux_pcie3a_clk,
667
+
msm_mux_pcie3a_rst_n,
668
+
msm_mux_pcie3b_clk,
669
+
msm_mux_pcie4_clk_req_n,
670
+
msm_mux_pcie5_clk_req_n,
671
+
msm_mux_pcie6_clk_req_n,
672
+
msm_mux_phase_flag,
673
+
msm_mux_pll_bist_sync,
674
+
msm_mux_pll_clk_aux,
675
+
msm_mux_pmc_oca_n,
676
+
msm_mux_pmc_uva_n,
677
+
msm_mux_prng_rosc,
678
+
msm_mux_qdss_cti,
679
+
msm_mux_qdss_gpio,
680
+
msm_mux_qspi0,
681
+
msm_mux_qup0_se0,
682
+
msm_mux_qup0_se1,
683
+
msm_mux_qup0_se2,
684
+
msm_mux_qup0_se3,
685
+
msm_mux_qup0_se4,
686
+
msm_mux_qup0_se5,
687
+
msm_mux_qup0_se6,
688
+
msm_mux_qup0_se7,
689
+
msm_mux_qup1_se0,
690
+
msm_mux_qup1_se1,
691
+
msm_mux_qup1_se2,
692
+
msm_mux_qup1_se3,
693
+
msm_mux_qup1_se4,
694
+
msm_mux_qup1_se5,
695
+
msm_mux_qup1_se6,
696
+
msm_mux_qup1_se7,
697
+
msm_mux_qup2_se0,
698
+
msm_mux_qup2_se1,
699
+
msm_mux_qup2_se2,
700
+
msm_mux_qup2_se3,
701
+
msm_mux_qup2_se4,
702
+
msm_mux_qup2_se5,
703
+
msm_mux_qup2_se6,
704
+
msm_mux_qup2_se7,
705
+
msm_mux_qup3_se0,
706
+
msm_mux_qup3_se1,
707
+
msm_mux_sd_write_protect,
708
+
msm_mux_sdc4_clk,
709
+
msm_mux_sdc4_cmd,
710
+
msm_mux_sdc4_data,
711
+
msm_mux_smb_acok_n,
712
+
msm_mux_sys_throttle,
713
+
msm_mux_tb_trig_sdc2,
714
+
msm_mux_tb_trig_sdc4,
715
+
msm_mux_tmess_prng,
716
+
msm_mux_tsense_pwm,
717
+
msm_mux_tsense_therm,
718
+
msm_mux_usb0_dp,
719
+
msm_mux_usb0_phy_ps,
720
+
msm_mux_usb0_sbrx,
721
+
msm_mux_usb0_sbtx,
722
+
msm_mux_usb0_tmu,
723
+
msm_mux_usb1_dbg,
724
+
msm_mux_usb1_dp,
725
+
msm_mux_usb1_phy_ps,
726
+
msm_mux_usb1_sbrx,
727
+
msm_mux_usb1_sbtx,
728
+
msm_mux_usb1_tmu,
729
+
msm_mux_usb2_dp,
730
+
msm_mux_usb2_phy_ps,
731
+
msm_mux_usb2_sbrx,
732
+
msm_mux_usb2_sbtx,
733
+
msm_mux_usb2_tmu,
734
+
msm_mux_vsense_trigger_mirnat,
735
+
msm_mux_wcn_sw,
736
+
msm_mux_wcn_sw_ctrl,
737
+
msm_mux__,
738
+
};
739
+
740
+
static const char *const gpio_groups[] = {
741
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
742
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
743
+
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
744
+
"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
745
+
"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
746
+
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
747
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
748
+
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
749
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
750
+
"gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
751
+
"gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
752
+
"gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
753
+
"gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
754
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
755
+
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
756
+
"gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
757
+
"gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
758
+
"gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
759
+
"gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
760
+
"gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
761
+
"gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
762
+
"gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
763
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
764
+
"gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
765
+
"gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
766
+
"gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
767
+
"gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
768
+
"gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
769
+
"gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173",
770
+
"gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179",
771
+
"gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185",
772
+
"gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191",
773
+
"gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197",
774
+
"gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203",
775
+
"gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
776
+
"gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215",
777
+
"gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221",
778
+
"gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227",
779
+
"gpio228", "gpio229", "gpio230", "gpio231", "gpio232", "gpio233",
780
+
"gpio234", "gpio235", "gpio236", "gpio237", "gpio238", "gpio239",
781
+
"gpio240", "gpio241", "gpio242", "gpio243", "gpio244", "gpio245",
782
+
"gpio246", "gpio247", "gpio248", "gpio249",
783
+
};
784
+
785
+
static const char *const resout_gpio_n_groups[] = {
786
+
"gpio160",
787
+
};
788
+
789
+
static const char *const aoss_cti_groups[] = {
790
+
"gpio60",
791
+
"gpio61",
792
+
"gpio62",
793
+
"gpio63",
794
+
};
795
+
796
+
static const char *const asc_cci_groups[] = {
797
+
"gpio235",
798
+
"gpio236",
799
+
};
800
+
801
+
static const char *const atest_char_groups[] = {
802
+
"gpio172", "gpio184", "gpio188", "gpio164",
803
+
"gpio163",
804
+
};
805
+
806
+
static const char *const atest_usb_groups[] = {
807
+
"gpio39", "gpio40", "gpio41", "gpio38",
808
+
"gpio44", "gpio45", "gpio42", "gpio43",
809
+
"gpio49", "gpio50", "gpio51", "gpio48",
810
+
"gpio54", "gpio55", "gpio52", "gpio53",
811
+
"gpio65", "gpio66", "gpio46", "gpio47",
812
+
"gpio72", "gpio73", "gpio80", "gpio81",
813
+
};
814
+
815
+
static const char *const audio_ext_mclk0_groups[] = {
816
+
"gpio134",
817
+
};
818
+
819
+
static const char *const audio_ext_mclk1_groups[] = {
820
+
"gpio142",
821
+
};
822
+
823
+
static const char *const audio_ref_clk_groups[] = {
824
+
"gpio142",
825
+
};
826
+
827
+
static const char *const cam_asc_mclk4_groups[] = {
828
+
"gpio100",
829
+
};
830
+
831
+
static const char *const cam_mclk_groups[] = {
832
+
"gpio96",
833
+
"gpio97",
834
+
"gpio98",
835
+
"gpio99",
836
+
};
837
+
838
+
static const char *const cci_async_in_groups[] = {
839
+
"gpio113", "gpio112", "gpio111",
840
+
};
841
+
842
+
static const char *const cci_i2c_scl_groups[] = {
843
+
"gpio102", "gpio104", "gpio106",
844
+
};
845
+
846
+
static const char *const cci_i2c_sda_groups[] = {
847
+
"gpio101", "gpio103", "gpio105",
848
+
};
849
+
850
+
static const char *const cci_timer_groups[] = {
851
+
"gpio109", "gpio110", "gpio111", "gpio112",
852
+
"gpio113",
853
+
};
854
+
855
+
static const char *const cmu_rng_groups[] = {
856
+
"gpio48", "gpio47", "gpio46", "gpio45",
857
+
};
858
+
859
+
static const char *const cri_trng_groups[] = {
860
+
"gpio173",
861
+
};
862
+
863
+
static const char *const dbg_out_clk_groups[] = {
864
+
"gpio51",
865
+
};
866
+
867
+
static const char *const ddr_bist_complete_groups[] = {
868
+
"gpio57",
869
+
};
870
+
871
+
static const char *const ddr_bist_fail_groups[] = {
872
+
"gpio56",
873
+
};
874
+
875
+
static const char *const ddr_bist_start_groups[] = {
876
+
"gpio54",
877
+
};
878
+
879
+
static const char *const ddr_bist_stop_groups[] = {
880
+
"gpio55",
881
+
};
882
+
883
+
static const char *const ddr_pxi_groups[] = {
884
+
"gpio38", "gpio39", "gpio40", "gpio41",
885
+
"gpio72", "gpio73", "gpio80", "gpio81",
886
+
"gpio42", "gpio43", "gpio44", "gpio45",
887
+
"gpio46", "gpio47", "gpio48", "gpio49",
888
+
"gpio50", "gpio51", "gpio52", "gpio53",
889
+
"gpio54", "gpio55", "gpio65", "gpio66",
890
+
};
891
+
892
+
static const char *const edp0_hot_groups[] = {
893
+
"gpio119",
894
+
};
895
+
896
+
static const char *const edp0_lcd_groups[] = {
897
+
"gpio120",
898
+
};
899
+
900
+
static const char *const edp1_lcd_groups[] = {
901
+
"gpio115",
902
+
"gpio119",
903
+
};
904
+
905
+
static const char *const egpio_groups[] = {
906
+
"gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197",
907
+
"gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203",
908
+
"gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
909
+
"gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215",
910
+
"gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221",
911
+
"gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227",
912
+
"gpio228", "gpio229", "gpio230", "gpio231", "gpio232", "gpio233",
913
+
"gpio234", "gpio235", "gpio236", "gpio237", "gpio238", "gpio239",
914
+
"gpio240", "gpio241", "gpio242", "gpio243", "gpio244",
915
+
};
916
+
917
+
static const char *const eusb_ac_en_groups[] = {
918
+
"gpio168", "gpio177", "gpio186", "gpio69",
919
+
"gpio187", "gpio178",
920
+
};
921
+
922
+
static const char *const gcc_gp1_groups[] = {
923
+
"gpio71",
924
+
"gpio72",
925
+
};
926
+
927
+
static const char *const gcc_gp2_groups[] = {
928
+
"gpio64",
929
+
"gpio73",
930
+
};
931
+
932
+
static const char *const gcc_gp3_groups[] = {
933
+
"gpio74",
934
+
"gpio82",
935
+
};
936
+
937
+
static const char *const host2wlan_sol_groups[] = {
938
+
"gpio118",
939
+
};
940
+
941
+
static const char *const i2c0_s_scl_groups[] = {
942
+
"gpio7",
943
+
};
944
+
945
+
static const char *const i2c0_s_sda_groups[] = {
946
+
"gpio6",
947
+
};
948
+
949
+
static const char *const i2s0_data_groups[] = {
950
+
"gpio136", "gpio137",
951
+
};
952
+
953
+
static const char *const i2s0_sck_groups[] = {
954
+
"gpio135",
955
+
};
956
+
957
+
static const char *const i2s0_ws_groups[] = {
958
+
"gpio138",
959
+
};
960
+
961
+
static const char *const i2s1_data_groups[] = {
962
+
"gpio140", "gpio142",
963
+
};
964
+
965
+
static const char *const i2s1_sck_groups[] = {
966
+
"gpio139",
967
+
};
968
+
969
+
static const char *const i2s1_ws_groups[] = {
970
+
"gpio141",
971
+
};
972
+
973
+
static const char *const ibi_i3c_groups[] = {
974
+
"gpio0", "gpio1", "gpio4", "gpio5", "gpio32", "gpio33",
975
+
"gpio36", "gpio37", "gpio64", "gpio65", "gpio68", "gpio69",
976
+
};
977
+
978
+
static const char *const jitter_bist_groups[] = {
979
+
"gpio52",
980
+
};
981
+
982
+
static const char *const mdp_vsync_out_groups[] = {
983
+
"gpio114", "gpio114", "gpio115", "gpio115",
984
+
"gpio109", "gpio110", "gpio111", "gpio112",
985
+
"gpio113",
986
+
};
987
+
988
+
static const char *const mdp_vsync_e_groups[] = {
989
+
"gpio106",
990
+
};
991
+
992
+
static const char *const mdp_vsync_p_groups[] = {
993
+
"gpio98",
994
+
};
995
+
996
+
static const char *const mdp_vsync_s_groups[] = {
997
+
"gpio105",
998
+
};
999
+
1000
+
static const char *const pcie3a_clk_groups[] = {
1001
+
"gpio144",
1002
+
};
1003
+
1004
+
static const char *const pcie3a_rst_n_groups[] = {
1005
+
"gpio143",
1006
+
};
1007
+
1008
+
static const char *const pcie3b_clk_groups[] = {
1009
+
"gpio156",
1010
+
};
1011
+
1012
+
static const char *const pcie4_clk_req_n_groups[] = {
1013
+
"gpio147",
1014
+
};
1015
+
1016
+
static const char *const pcie5_clk_req_n_groups[] = {
1017
+
"gpio153",
1018
+
};
1019
+
1020
+
static const char *const pcie6_clk_req_n_groups[] = {
1021
+
"gpio150",
1022
+
};
1023
+
1024
+
static const char *const phase_flag_groups[] = {
1025
+
"gpio6", "gpio7", "gpio16", "gpio17",
1026
+
"gpio18", "gpio19", "gpio20", "gpio21",
1027
+
"gpio22", "gpio23", "gpio24", "gpio25",
1028
+
"gpio8", "gpio26", "gpio27", "gpio163",
1029
+
"gpio164", "gpio188", "gpio184", "gpio172",
1030
+
"gpio186", "gpio173", "gpio76", "gpio9",
1031
+
"gpio77", "gpio78", "gpio10", "gpio11",
1032
+
"gpio12", "gpio13", "gpio14", "gpio15",
1033
+
};
1034
+
1035
+
static const char *const pll_bist_sync_groups[] = {
1036
+
"gpio28",
1037
+
};
1038
+
1039
+
static const char *const pll_clk_aux_groups[] = {
1040
+
"gpio35",
1041
+
};
1042
+
1043
+
static const char *const pmc_oca_n_groups[] = {
1044
+
"gpio249",
1045
+
};
1046
+
1047
+
static const char *const pmc_uva_n_groups[] = {
1048
+
"gpio248",
1049
+
};
1050
+
1051
+
static const char *const prng_rosc_groups[] = {
1052
+
"gpio186", "gpio188", "gpio164", "gpio163",
1053
+
};
1054
+
1055
+
static const char *const qdss_cti_groups[] = {
1056
+
"gpio18", "gpio19", "gpio23", "gpio27",
1057
+
"gpio161", "gpio162", "gpio215", "gpio217",
1058
+
};
1059
+
1060
+
static const char *const qdss_gpio_groups[] = {
1061
+
"gpio104", "gpio151", "gpio227", "gpio228",
1062
+
"gpio96", "gpio219", "gpio97", "gpio220",
1063
+
"gpio108", "gpio231", "gpio109", "gpio232",
1064
+
"gpio110", "gpio233", "gpio111", "gpio234",
1065
+
"gpio112", "gpio235", "gpio113", "gpio236",
1066
+
"gpio149", "gpio221", "gpio99", "gpio222",
1067
+
"gpio100", "gpio223", "gpio101", "gpio224",
1068
+
"gpio102", "gpio225", "gpio103", "gpio226",
1069
+
"gpio152", "gpio237", "gpio107", "gpio238",
1070
+
};
1071
+
1072
+
static const char *const qspi0_groups[] = {
1073
+
"gpio127", "gpio132", "gpio133", "gpio128",
1074
+
"gpio129", "gpio130", "gpio131",
1075
+
};
1076
+
1077
+
static const char *const qup0_se0_groups[] = {
1078
+
"gpio0", "gpio1", "gpio2", "gpio3",
1079
+
};
1080
+
1081
+
static const char *const qup0_se1_groups[] = {
1082
+
"gpio4", "gpio5", "gpio6", "gpio7",
1083
+
};
1084
+
1085
+
static const char *const qup0_se2_groups[] = {
1086
+
"gpio8", "gpio9", "gpio10", "gpio11",
1087
+
"gpio17", "gpio18", "gpio19",
1088
+
};
1089
+
1090
+
static const char *const qup0_se3_groups[] = {
1091
+
"gpio12", "gpio13", "gpio14", "gpio15",
1092
+
"gpio21", "gpio22", "gpio23",
1093
+
};
1094
+
1095
+
static const char *const qup0_se4_groups[] = {
1096
+
"gpio16", "gpio17", "gpio18", "gpio19",
1097
+
};
1098
+
1099
+
static const char *const qup0_se5_groups[] = {
1100
+
"gpio20", "gpio21", "gpio22", "gpio23",
1101
+
};
1102
+
1103
+
static const char *const qup0_se6_groups[] = {
1104
+
"gpio6", "gpio7", "gpio4", "gpio5",
1105
+
};
1106
+
1107
+
static const char *const qup0_se7_groups[] = {
1108
+
"gpio14", "gpio15", "gpio12", "gpio13",
1109
+
};
1110
+
1111
+
static const char *const qup1_se0_groups[] = {
1112
+
"gpio32", "gpio33", "gpio34", "gpio35",
1113
+
};
1114
+
1115
+
static const char *const qup1_se1_groups[] = {
1116
+
"gpio36", "gpio37", "gpio38", "gpio39",
1117
+
};
1118
+
1119
+
static const char *const qup1_se2_groups[] = {
1120
+
"gpio40", "gpio41", "gpio42", "gpio43",
1121
+
"gpio49", "gpio50", "gpio51",
1122
+
};
1123
+
1124
+
static const char *const qup1_se3_groups[] = {
1125
+
"gpio44", "gpio45", "gpio46", "gpio47",
1126
+
"gpio33", "gpio34", "gpio35",
1127
+
};
1128
+
1129
+
static const char *const qup1_se4_groups[] = {
1130
+
"gpio48", "gpio49", "gpio50", "gpio51",
1131
+
};
1132
+
1133
+
static const char *const qup1_se5_groups[] = {
1134
+
"gpio52", "gpio53", "gpio54", "gpio55",
1135
+
};
1136
+
1137
+
static const char *const qup1_se6_groups[] = {
1138
+
"gpio56", "gpio57", "gpio58", "gpio59",
1139
+
};
1140
+
1141
+
static const char *const qup1_se7_groups[] = {
1142
+
"gpio54", "gpio55", "gpio52", "gpio53",
1143
+
};
1144
+
1145
+
static const char *const qup2_se0_groups[] = {
1146
+
"gpio64", "gpio65", "gpio66", "gpio67",
1147
+
};
1148
+
1149
+
static const char *const qup2_se1_groups[] = {
1150
+
"gpio68", "gpio69", "gpio70", "gpio71",
1151
+
};
1152
+
1153
+
static const char *const qup2_se2_groups[] = {
1154
+
"gpio72", "gpio73", "gpio74", "gpio75",
1155
+
"gpio81", "gpio82", "gpio83",
1156
+
};
1157
+
1158
+
static const char *const qup2_se3_groups[] = {
1159
+
"gpio76", "gpio77", "gpio78", "gpio79",
1160
+
"gpio65", "gpio66", "gpio67",
1161
+
};
1162
+
1163
+
static const char *const qup2_se4_groups[] = {
1164
+
"gpio80", "gpio81", "gpio82", "gpio83",
1165
+
};
1166
+
1167
+
static const char *const qup2_se5_groups[] = {
1168
+
"gpio84", "gpio85", "gpio86", "gpio87",
1169
+
};
1170
+
1171
+
static const char *const qup2_se6_groups[] = {
1172
+
"gpio88", "gpio89", "gpio90", "gpio91",
1173
+
};
1174
+
1175
+
static const char *const qup2_se7_groups[] = {
1176
+
"gpio80", "gpio81", "gpio82", "gpio83",
1177
+
};
1178
+
1179
+
static const char *const qup3_se0_groups[] = {
1180
+
"gpio128", "gpio129", "gpio127", "gpio132",
1181
+
"gpio130", "gpio131", "gpio133", "gpio247",
1182
+
};
1183
+
1184
+
static const char *const qup3_se1_groups[] = {
1185
+
"gpio40", "gpio41", "gpio42", "gpio43",
1186
+
"gpio49", "gpio50", "gpio51", "gpio48",
1187
+
};
1188
+
1189
+
static const char *const sd_write_protect_groups[] = {
1190
+
"gpio162",
1191
+
};
1192
+
1193
+
static const char *const sdc4_clk_groups[] = {
1194
+
"gpio127",
1195
+
};
1196
+
1197
+
static const char *const sdc4_cmd_groups[] = {
1198
+
"gpio132",
1199
+
};
1200
+
1201
+
static const char *const sdc4_data_groups[] = {
1202
+
"gpio128",
1203
+
"gpio129",
1204
+
"gpio130",
1205
+
"gpio131",
1206
+
};
1207
+
1208
+
static const char *const smb_acok_n_groups[] = {
1209
+
"gpio245",
1210
+
};
1211
+
1212
+
static const char *const sys_throttle_groups[] = {
1213
+
"gpio39",
1214
+
"gpio94",
1215
+
};
1216
+
1217
+
static const char *const tb_trig_sdc2_groups[] = {
1218
+
"gpio137",
1219
+
};
1220
+
1221
+
static const char *const tb_trig_sdc4_groups[] = {
1222
+
"gpio133",
1223
+
};
1224
+
1225
+
static const char *const tmess_prng_groups[] = {
1226
+
"gpio92", "gpio93", "gpio94", "gpio95",
1227
+
};
1228
+
1229
+
static const char *const tsense_pwm_groups[] = {
1230
+
"gpio28", "gpio29", "gpio30", "gpio31",
1231
+
"gpio34", "gpio138", "gpio139", "gpio140",
1232
+
};
1233
+
1234
+
static const char *const tsense_therm_groups[] = {
1235
+
"gpio141",
1236
+
};
1237
+
1238
+
static const char *const usb0_dp_groups[] = {
1239
+
"gpio122",
1240
+
};
1241
+
1242
+
static const char *const usb0_phy_ps_groups[] = {
1243
+
"gpio121",
1244
+
};
1245
+
1246
+
static const char *const usb0_sbrx_groups[] = {
1247
+
"gpio163",
1248
+
};
1249
+
1250
+
static const char *const usb0_sbtx_groups[] = {
1251
+
"gpio164",
1252
+
"gpio165",
1253
+
};
1254
+
1255
+
static const char *const usb0_tmu_groups[] = {
1256
+
"gpio98",
1257
+
};
1258
+
1259
+
static const char *const usb1_dbg_groups[] = {
1260
+
"gpio105",
1261
+
"gpio106",
1262
+
};
1263
+
1264
+
static const char *const usb1_dp_groups[] = {
1265
+
"gpio124",
1266
+
};
1267
+
1268
+
static const char *const usb1_phy_ps_groups[] = {
1269
+
"gpio123",
1270
+
};
1271
+
1272
+
static const char *const usb1_sbrx_groups[] = {
1273
+
"gpio172",
1274
+
};
1275
+
1276
+
static const char *const usb1_sbtx_groups[] = {
1277
+
"gpio173",
1278
+
"gpio174",
1279
+
};
1280
+
1281
+
static const char *const usb1_tmu_groups[] = {
1282
+
"gpio98",
1283
+
};
1284
+
1285
+
static const char *const usb2_dp_groups[] = {
1286
+
"gpio126",
1287
+
};
1288
+
1289
+
static const char *const usb2_phy_ps_groups[] = {
1290
+
"gpio125",
1291
+
};
1292
+
1293
+
static const char *const usb2_sbrx_groups[] = {
1294
+
"gpio181",
1295
+
};
1296
+
1297
+
static const char *const usb2_sbtx_groups[] = {
1298
+
"gpio182",
1299
+
"gpio183",
1300
+
};
1301
+
1302
+
static const char *const usb2_tmu_groups[] = {
1303
+
"gpio98",
1304
+
};
1305
+
1306
+
static const char *const vsense_trigger_mirnat_groups[] = {
1307
+
"gpio38",
1308
+
};
1309
+
1310
+
static const char *const wcn_sw_groups[] = {
1311
+
"gpio221",
1312
+
};
1313
+
1314
+
static const char *const wcn_sw_ctrl_groups[] = {
1315
+
"gpio214",
1316
+
};
1317
+
1318
+
static const struct pinfunction glymur_functions[] = {
1319
+
MSM_PIN_FUNCTION(gpio),
1320
+
MSM_PIN_FUNCTION(resout_gpio_n),
1321
+
MSM_PIN_FUNCTION(aoss_cti),
1322
+
MSM_PIN_FUNCTION(asc_cci),
1323
+
MSM_PIN_FUNCTION(atest_char),
1324
+
MSM_PIN_FUNCTION(atest_usb),
1325
+
MSM_PIN_FUNCTION(audio_ext_mclk0),
1326
+
MSM_PIN_FUNCTION(audio_ext_mclk1),
1327
+
MSM_PIN_FUNCTION(audio_ref_clk),
1328
+
MSM_PIN_FUNCTION(cam_asc_mclk4),
1329
+
MSM_PIN_FUNCTION(cam_mclk),
1330
+
MSM_PIN_FUNCTION(cci_async_in),
1331
+
MSM_PIN_FUNCTION(cci_i2c_scl),
1332
+
MSM_PIN_FUNCTION(cci_i2c_sda),
1333
+
MSM_PIN_FUNCTION(cci_timer),
1334
+
MSM_PIN_FUNCTION(cmu_rng),
1335
+
MSM_PIN_FUNCTION(cri_trng),
1336
+
MSM_PIN_FUNCTION(dbg_out_clk),
1337
+
MSM_PIN_FUNCTION(ddr_bist_complete),
1338
+
MSM_PIN_FUNCTION(ddr_bist_fail),
1339
+
MSM_PIN_FUNCTION(ddr_bist_start),
1340
+
MSM_PIN_FUNCTION(ddr_bist_stop),
1341
+
MSM_PIN_FUNCTION(ddr_pxi),
1342
+
MSM_PIN_FUNCTION(edp0_hot),
1343
+
MSM_PIN_FUNCTION(edp0_lcd),
1344
+
MSM_PIN_FUNCTION(edp1_lcd),
1345
+
MSM_PIN_FUNCTION(egpio),
1346
+
MSM_PIN_FUNCTION(eusb_ac_en),
1347
+
MSM_PIN_FUNCTION(gcc_gp1),
1348
+
MSM_PIN_FUNCTION(gcc_gp2),
1349
+
MSM_PIN_FUNCTION(gcc_gp3),
1350
+
MSM_PIN_FUNCTION(host2wlan_sol),
1351
+
MSM_PIN_FUNCTION(i2c0_s_scl),
1352
+
MSM_PIN_FUNCTION(i2c0_s_sda),
1353
+
MSM_PIN_FUNCTION(i2s0_data),
1354
+
MSM_PIN_FUNCTION(i2s0_sck),
1355
+
MSM_PIN_FUNCTION(i2s0_ws),
1356
+
MSM_PIN_FUNCTION(i2s1_data),
1357
+
MSM_PIN_FUNCTION(i2s1_sck),
1358
+
MSM_PIN_FUNCTION(i2s1_ws),
1359
+
MSM_PIN_FUNCTION(ibi_i3c),
1360
+
MSM_PIN_FUNCTION(jitter_bist),
1361
+
MSM_PIN_FUNCTION(mdp_vsync_out),
1362
+
MSM_PIN_FUNCTION(mdp_vsync_e),
1363
+
MSM_PIN_FUNCTION(mdp_vsync_p),
1364
+
MSM_PIN_FUNCTION(mdp_vsync_s),
1365
+
MSM_PIN_FUNCTION(pcie3a_clk),
1366
+
MSM_PIN_FUNCTION(pcie3a_rst_n),
1367
+
MSM_PIN_FUNCTION(pcie3b_clk),
1368
+
MSM_PIN_FUNCTION(pcie4_clk_req_n),
1369
+
MSM_PIN_FUNCTION(pcie5_clk_req_n),
1370
+
MSM_PIN_FUNCTION(pcie6_clk_req_n),
1371
+
MSM_PIN_FUNCTION(phase_flag),
1372
+
MSM_PIN_FUNCTION(pll_bist_sync),
1373
+
MSM_PIN_FUNCTION(pll_clk_aux),
1374
+
MSM_PIN_FUNCTION(pmc_oca_n),
1375
+
MSM_PIN_FUNCTION(pmc_uva_n),
1376
+
MSM_PIN_FUNCTION(prng_rosc),
1377
+
MSM_PIN_FUNCTION(qdss_cti),
1378
+
MSM_PIN_FUNCTION(qdss_gpio),
1379
+
MSM_PIN_FUNCTION(qspi0),
1380
+
MSM_PIN_FUNCTION(qup0_se0),
1381
+
MSM_PIN_FUNCTION(qup0_se1),
1382
+
MSM_PIN_FUNCTION(qup0_se2),
1383
+
MSM_PIN_FUNCTION(qup0_se3),
1384
+
MSM_PIN_FUNCTION(qup0_se4),
1385
+
MSM_PIN_FUNCTION(qup0_se5),
1386
+
MSM_PIN_FUNCTION(qup0_se6),
1387
+
MSM_PIN_FUNCTION(qup0_se7),
1388
+
MSM_PIN_FUNCTION(qup1_se0),
1389
+
MSM_PIN_FUNCTION(qup1_se1),
1390
+
MSM_PIN_FUNCTION(qup1_se2),
1391
+
MSM_PIN_FUNCTION(qup1_se3),
1392
+
MSM_PIN_FUNCTION(qup1_se4),
1393
+
MSM_PIN_FUNCTION(qup1_se5),
1394
+
MSM_PIN_FUNCTION(qup1_se6),
1395
+
MSM_PIN_FUNCTION(qup1_se7),
1396
+
MSM_PIN_FUNCTION(qup2_se0),
1397
+
MSM_PIN_FUNCTION(qup2_se1),
1398
+
MSM_PIN_FUNCTION(qup2_se2),
1399
+
MSM_PIN_FUNCTION(qup2_se3),
1400
+
MSM_PIN_FUNCTION(qup2_se4),
1401
+
MSM_PIN_FUNCTION(qup2_se5),
1402
+
MSM_PIN_FUNCTION(qup2_se6),
1403
+
MSM_PIN_FUNCTION(qup2_se7),
1404
+
MSM_PIN_FUNCTION(qup3_se0),
1405
+
MSM_PIN_FUNCTION(qup3_se1),
1406
+
MSM_PIN_FUNCTION(sd_write_protect),
1407
+
MSM_PIN_FUNCTION(sdc4_clk),
1408
+
MSM_PIN_FUNCTION(sdc4_cmd),
1409
+
MSM_PIN_FUNCTION(sdc4_data),
1410
+
MSM_PIN_FUNCTION(smb_acok_n),
1411
+
MSM_PIN_FUNCTION(sys_throttle),
1412
+
MSM_PIN_FUNCTION(tb_trig_sdc2),
1413
+
MSM_PIN_FUNCTION(tb_trig_sdc4),
1414
+
MSM_PIN_FUNCTION(tmess_prng),
1415
+
MSM_PIN_FUNCTION(tsense_pwm),
1416
+
MSM_PIN_FUNCTION(tsense_therm),
1417
+
MSM_PIN_FUNCTION(usb0_dp),
1418
+
MSM_PIN_FUNCTION(usb0_phy_ps),
1419
+
MSM_PIN_FUNCTION(usb0_sbrx),
1420
+
MSM_PIN_FUNCTION(usb0_sbtx),
1421
+
MSM_PIN_FUNCTION(usb0_tmu),
1422
+
MSM_PIN_FUNCTION(usb1_dbg),
1423
+
MSM_PIN_FUNCTION(usb1_dp),
1424
+
MSM_PIN_FUNCTION(usb1_phy_ps),
1425
+
MSM_PIN_FUNCTION(usb1_sbrx),
1426
+
MSM_PIN_FUNCTION(usb1_sbtx),
1427
+
MSM_PIN_FUNCTION(usb1_tmu),
1428
+
MSM_PIN_FUNCTION(usb2_dp),
1429
+
MSM_PIN_FUNCTION(usb2_phy_ps),
1430
+
MSM_PIN_FUNCTION(usb2_sbrx),
1431
+
MSM_PIN_FUNCTION(usb2_sbtx),
1432
+
MSM_PIN_FUNCTION(usb2_tmu),
1433
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1434
+
MSM_PIN_FUNCTION(wcn_sw),
1435
+
MSM_PIN_FUNCTION(wcn_sw_ctrl),
1436
+
};
1437
+
1438
+
static const struct msm_pingroup glymur_groups[] = {
1439
+
[0] = PINGROUP(0, qup0_se0, ibi_i3c, _, _, _, _, _, _, _, _, _),
1440
+
[1] = PINGROUP(1, qup0_se0, ibi_i3c, _, _, _, _, _, _, _, _, _),
1441
+
[2] = PINGROUP(2, qup0_se0, _, _, _, _, _, _, _, _, _, _),
1442
+
[3] = PINGROUP(3, qup0_se0, _, _, _, _, _, _, _, _, _, _),
1443
+
[4] = PINGROUP(4, qup0_se1, qup0_se6, ibi_i3c, _, _, _, _, _, _, _, _),
1444
+
[5] = PINGROUP(5, qup0_se1, qup0_se6, ibi_i3c, _, _, _, _, _, _, _, _),
1445
+
[6] = PINGROUP(6, qup0_se1, qup0_se6, i2c0_s_sda, phase_flag, _, _, _, _, _, _, _),
1446
+
[7] = PINGROUP(7, qup0_se1, qup0_se6, i2c0_s_scl, phase_flag, _, _, _, _, _, _, _),
1447
+
[8] = PINGROUP(8, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _),
1448
+
[9] = PINGROUP(9, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _),
1449
+
[10] = PINGROUP(10, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _),
1450
+
[11] = PINGROUP(11, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _),
1451
+
[12] = PINGROUP(12, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _),
1452
+
[13] = PINGROUP(13, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _),
1453
+
[14] = PINGROUP(14, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _),
1454
+
[15] = PINGROUP(15, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _),
1455
+
[16] = PINGROUP(16, qup0_se4, phase_flag, _, _, _, _, _, _, _, _, _),
1456
+
[17] = PINGROUP(17, qup0_se4, qup0_se2, phase_flag, _, _, _, _, _, _, _, _),
1457
+
[18] = PINGROUP(18, qup0_se4, qup0_se2, phase_flag, _, qdss_cti, _, _, _, _, _, _),
1458
+
[19] = PINGROUP(19, qup0_se4, qup0_se2, phase_flag, _, qdss_cti, _, _, _, _, _, _),
1459
+
[20] = PINGROUP(20, qup0_se5, _, phase_flag, _, _, _, _, _, _, _, _),
1460
+
[21] = PINGROUP(21, qup0_se5, qup0_se3, _, phase_flag, _, _, _, _, _, _, _),
1461
+
[22] = PINGROUP(22, qup0_se5, qup0_se3, _, phase_flag, _, _, _, _, _, _, _),
1462
+
[23] = PINGROUP(23, qup0_se5, qup0_se3, phase_flag, _, qdss_cti, _, _, _, _, _, _),
1463
+
[24] = PINGROUP(24, phase_flag, _, _, _, _, _, _, _, _, _, _),
1464
+
[25] = PINGROUP(25, phase_flag, _, _, _, _, _, _, _, _, _, _),
1465
+
[26] = PINGROUP(26, phase_flag, _, _, _, _, _, _, _, _, _, _),
1466
+
[27] = PINGROUP(27, phase_flag, _, qdss_cti, _, _, _, _, _, _, _, _),
1467
+
[28] = PINGROUP(28, pll_bist_sync, tsense_pwm, _, _, _, _, _, _, _, _, _),
1468
+
[29] = PINGROUP(29, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1469
+
[30] = PINGROUP(30, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1470
+
[31] = PINGROUP(31, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1471
+
[32] = PINGROUP(32, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, _),
1472
+
[33] = PINGROUP(33, qup1_se0, ibi_i3c, qup1_se3, _, _, _, _, _, _, _, _),
1473
+
[34] = PINGROUP(34, qup1_se0, qup1_se3, tsense_pwm, _, _, _, _, _, _, _, _),
1474
+
[35] = PINGROUP(35, qup1_se0, qup1_se3, pll_clk_aux, _, _, _, _, _, _, _, _),
1475
+
[36] = PINGROUP(36, qup1_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1476
+
[37] = PINGROUP(37, qup1_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1477
+
[38] = PINGROUP(38, qup1_se1, atest_usb, ddr_pxi, vsense_trigger_mirnat, _, _, _, _,
1478
+
_, _, _),
1479
+
[39] = PINGROUP(39, qup1_se1, sys_throttle, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1480
+
[40] = PINGROUP(40, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1481
+
[41] = PINGROUP(41, qup1_se2, qup3_se1, qup3_se0, atest_usb, ddr_pxi, _, _, _, _,
1482
+
_, _),
1483
+
[42] = PINGROUP(42, qup1_se2, qup3_se1, qup0_se1, atest_usb, ddr_pxi, _, _, _, _,
1484
+
_, _),
1485
+
[43] = PINGROUP(43, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1486
+
[44] = PINGROUP(44, qup1_se3, _, atest_usb, ddr_pxi, _, _, _, _, _, _, _),
1487
+
[45] = PINGROUP(45, qup1_se3, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1488
+
[46] = PINGROUP(46, qup1_se3, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1489
+
[47] = PINGROUP(47, qup1_se3, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1490
+
[48] = PINGROUP(48, qup1_se4, qup3_se1, cmu_rng, _, atest_usb, ddr_pxi, _, _, _,
1491
+
_, _),
1492
+
[49] = PINGROUP(49, qup1_se4, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _,
1493
+
_, _, _),
1494
+
[50] = PINGROUP(50, qup1_se4, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _,
1495
+
_, _, _),
1496
+
[51] = PINGROUP(51, qup1_se4, qup1_se2, qup3_se1, dbg_out_clk, atest_usb,
1497
+
ddr_pxi, _, _, _, _, _),
1498
+
[52] = PINGROUP(52, qup1_se5, qup1_se7, jitter_bist, atest_usb, ddr_pxi, _, _, _,
1499
+
_, _, _),
1500
+
[53] = PINGROUP(53, qup1_se5, qup1_se7, _, atest_usb, ddr_pxi, _, _, _, _, _, _),
1501
+
[54] = PINGROUP(54, qup1_se5, qup1_se7, ddr_bist_start, atest_usb, ddr_pxi, _, _,
1502
+
_, _, _, _),
1503
+
[55] = PINGROUP(55, qup1_se5, qup1_se7, ddr_bist_stop, atest_usb, ddr_pxi, _, _,
1504
+
_, _, _, _),
1505
+
[56] = PINGROUP(56, qup1_se6, ddr_bist_fail, _, _, _, _, _, _, _, _, _),
1506
+
[57] = PINGROUP(57, qup1_se6, ddr_bist_complete, _, _, _, _, _, _, _, _, _),
1507
+
[58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _),
1508
+
[59] = PINGROUP(59, qup1_se6, _, _, _, _, _, _, _, _, _, _),
1509
+
[60] = PINGROUP(60, aoss_cti, _, _, _, _, _, _, _, _, _, _),
1510
+
[61] = PINGROUP(61, aoss_cti, _, _, _, _, _, _, _, _, _, _),
1511
+
[62] = PINGROUP(62, aoss_cti, _, _, _, _, _, _, _, _, _, _),
1512
+
[63] = PINGROUP(63, aoss_cti, _, _, _, _, _, _, _, _, _, _),
1513
+
[64] = PINGROUP(64, qup2_se0, ibi_i3c, gcc_gp2, _, _, _, _, _, _, _, _),
1514
+
[65] = PINGROUP(65, qup2_se0, qup2_se3, ibi_i3c, atest_usb, ddr_pxi, _, _, _, _,
1515
+
_, _),
1516
+
[66] = PINGROUP(66, qup2_se0, qup2_se3, atest_usb, ddr_pxi, _, _, _, _, _, _, _),
1517
+
[67] = PINGROUP(67, qup2_se0, qup2_se3, _, _, _, _, _, _, _, _, _),
1518
+
[68] = PINGROUP(68, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1519
+
[69] = PINGROUP(69, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1520
+
[70] = PINGROUP(70, qup2_se1, _, _, _, _, _, _, _, _, _, _),
1521
+
[71] = PINGROUP(71, qup2_se1, gcc_gp1, _, _, _, _, _, _, _, _, _),
1522
+
[72] = PINGROUP(72, qup2_se2, gcc_gp1, atest_usb, ddr_pxi, _, _, _, _, _, _, _),
1523
+
[73] = PINGROUP(73, qup2_se2, gcc_gp2, atest_usb, ddr_pxi, _, _, _, _, _, _, _),
1524
+
[74] = PINGROUP(74, qup2_se2, gcc_gp3, _, _, _, _, _, _, _, _, _),
1525
+
[75] = PINGROUP(75, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1526
+
[76] = PINGROUP(76, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _),
1527
+
[77] = PINGROUP(77, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _),
1528
+
[78] = PINGROUP(78, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _),
1529
+
[79] = PINGROUP(79, qup2_se3, _, _, _, _, _, _, _, _, _, _),
1530
+
[80] = PINGROUP(80, qup2_se4, qup2_se7, atest_usb, ddr_pxi, _, _, _, _, _, _, _),
1531
+
[81] = PINGROUP(81, qup2_se4, qup2_se2, qup2_se7, atest_usb, ddr_pxi, _, _, _,
1532
+
_, _, _),
1533
+
[82] = PINGROUP(82, qup2_se4, qup2_se2, qup2_se7, gcc_gp3, _, _, _, _, _, _, _),
1534
+
[83] = PINGROUP(83, qup2_se4, qup2_se2, qup2_se7, _, _, _, _, _, _, _, _),
1535
+
[84] = PINGROUP(84, qup2_se5, _, _, _, _, _, _, _, _, _, _),
1536
+
[85] = PINGROUP(85, qup2_se5, _, _, _, _, _, _, _, _, _, _),
1537
+
[86] = PINGROUP(86, qup2_se5, _, _, _, _, _, _, _, _, _, _),
1538
+
[87] = PINGROUP(87, qup2_se5, _, _, _, _, _, _, _, _, _, _),
1539
+
[88] = PINGROUP(88, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1540
+
[89] = PINGROUP(89, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1541
+
[90] = PINGROUP(90, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1542
+
[91] = PINGROUP(91, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1543
+
[92] = PINGROUP(92, tmess_prng, _, _, _, _, _, _, _, _, _, _),
1544
+
[93] = PINGROUP(93, tmess_prng, _, _, _, _, _, _, _, _, _, _),
1545
+
[94] = PINGROUP(94, sys_throttle, tmess_prng, _, _, _, _, _, _, _, _, _),
1546
+
[95] = PINGROUP(95, tmess_prng, _, _, _, _, _, _, _, _, _, _),
1547
+
[96] = PINGROUP(96, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _, _),
1548
+
[97] = PINGROUP(97, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _, _),
1549
+
[98] = PINGROUP(98, cam_mclk, mdp_vsync_p, usb0_tmu, usb1_tmu, usb2_tmu, _, _, _, _, _, _),
1550
+
[99] = PINGROUP(99, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _, _),
1551
+
[100] = PINGROUP(100, cam_asc_mclk4, qdss_gpio, _, _, _, _, _, _, _, _, _),
1552
+
[101] = PINGROUP(101, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _),
1553
+
[102] = PINGROUP(102, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _),
1554
+
[103] = PINGROUP(103, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _),
1555
+
[104] = PINGROUP(104, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _),
1556
+
[105] = PINGROUP(105, cci_i2c_sda, mdp_vsync_s, usb1_dbg, _, _, _, _, _, _, _, _),
1557
+
[106] = PINGROUP(106, cci_i2c_scl, mdp_vsync_e, usb1_dbg, _, _, _, _, _, _, _, _),
1558
+
[107] = PINGROUP(107, qdss_gpio, _, _, _, _, _, _, _, _, _, _),
1559
+
[108] = PINGROUP(108, qdss_gpio, _, _, _, _, _, _, _, _, _, _),
1560
+
[109] = PINGROUP(109, cci_timer, mdp_vsync_out, qdss_gpio, _, _, _, _, _, _, _, _),
1561
+
[110] = PINGROUP(110, cci_timer, mdp_vsync_out, qdss_gpio, _, _, _, _, _, _, _, _),
1562
+
[111] = PINGROUP(111, cci_timer, cci_async_in, mdp_vsync_out, qdss_gpio, _, _, _, _,
1563
+
_, _, _),
1564
+
[112] = PINGROUP(112, cci_timer, cci_async_in, mdp_vsync_out, qdss_gpio, _, _, _, _,
1565
+
_, _, _),
1566
+
[113] = PINGROUP(113, cci_timer, cci_async_in, mdp_vsync_out, qdss_gpio, _, _, _, _,
1567
+
_, _, _),
1568
+
[114] = PINGROUP(114, mdp_vsync_out, mdp_vsync_out, _, _, _, _, _, _, _, _, _),
1569
+
[115] = PINGROUP(115, mdp_vsync_out, mdp_vsync_out, edp1_lcd, _, _, _, _, _, _, _, _),
1570
+
[116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _),
1571
+
[117] = PINGROUP(117, _, _, _, _, _, _, _, _, _, _, _),
1572
+
[118] = PINGROUP(118, host2wlan_sol, _, _, _, _, _, _, _, _, _, _),
1573
+
[119] = PINGROUP(119, edp0_hot, edp1_lcd, _, _, _, _, _, _, _, _, _),
1574
+
[120] = PINGROUP(120, edp0_lcd, _, _, _, _, _, _, _, _, _, _),
1575
+
[121] = PINGROUP(121, usb0_phy_ps, _, _, _, _, _, _, _, _, _, _),
1576
+
[122] = PINGROUP(122, usb0_dp, _, _, _, _, _, _, _, _, _, _),
1577
+
[123] = PINGROUP(123, usb1_phy_ps, _, _, _, _, _, _, _, _, _, _),
1578
+
[124] = PINGROUP(124, usb1_dp, _, _, _, _, _, _, _, _, _, _),
1579
+
[125] = PINGROUP(125, usb2_phy_ps, _, _, _, _, _, _, _, _, _, _),
1580
+
[126] = PINGROUP(126, usb2_dp, _, _, _, _, _, _, _, _, _, _),
1581
+
[127] = PINGROUP(127, qspi0, sdc4_clk, qup3_se0, _, _, _, _, _, _, _, _),
1582
+
[128] = PINGROUP(128, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _),
1583
+
[129] = PINGROUP(129, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _),
1584
+
[130] = PINGROUP(130, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _),
1585
+
[131] = PINGROUP(131, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _),
1586
+
[132] = PINGROUP(132, qspi0, sdc4_cmd, qup3_se0, _, _, _, _, _, _, _, _),
1587
+
[133] = PINGROUP(133, qspi0, tb_trig_sdc4, qup3_se0, _, _, _, _, _, _, _, _),
1588
+
[134] = PINGROUP(134, audio_ext_mclk0, _, _, _, _, _, _, _, _, _, _),
1589
+
[135] = PINGROUP(135, i2s0_sck, _, _, _, _, _, _, _, _, _, _),
1590
+
[136] = PINGROUP(136, i2s0_data, _, _, _, _, _, _, _, _, _, _),
1591
+
[137] = PINGROUP(137, i2s0_data, tb_trig_sdc2, _, _, _, _, _, _, _, _, _),
1592
+
[138] = PINGROUP(138, i2s0_ws, tsense_pwm, _, _, _, _, _, _, _, _, _),
1593
+
[139] = PINGROUP(139, i2s1_sck, tsense_pwm, _, _, _, _, _, _, _, _, _),
1594
+
[140] = PINGROUP(140, i2s1_data, tsense_pwm, _, _, _, _, _, _, _, _, _),
1595
+
[141] = PINGROUP(141, i2s1_ws, tsense_therm, _, _, _, _, _, _, _, _, _),
1596
+
[142] = PINGROUP(142, i2s1_data, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _, _, _),
1597
+
[143] = PINGROUP(143, pcie3a_rst_n, _, _, _, _, _, _, _, _, _, _),
1598
+
[144] = PINGROUP(144, pcie3a_clk, _, _, _, _, _, _, _, _, _, _),
1599
+
[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _, _, _),
1600
+
[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _, _, _),
1601
+
[147] = PINGROUP(147, pcie4_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1602
+
[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, _),
1603
+
[149] = PINGROUP(149, qdss_gpio, _, _, _, _, _, _, _, _, _, _),
1604
+
[150] = PINGROUP(150, pcie6_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1605
+
[151] = PINGROUP(151, qdss_gpio, _, _, _, _, _, _, _, _, _, _),
1606
+
[152] = PINGROUP(152, qdss_gpio, _, _, _, _, _, _, _, _, _, _),
1607
+
[153] = PINGROUP(153, pcie5_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1608
+
[154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _),
1609
+
[155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _),
1610
+
[156] = PINGROUP(156, pcie3b_clk, _, _, _, _, _, _, _, _, _, _),
1611
+
[157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
1612
+
[158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _),
1613
+
[159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _),
1614
+
[160] = PINGROUP(160, resout_gpio_n, _, _, _, _, _, _, _, _, _, _),
1615
+
[161] = PINGROUP(161, qdss_cti, _, _, _, _, _, _, _, _, _, _),
1616
+
[162] = PINGROUP(162, sd_write_protect, qdss_cti, _, _, _, _, _, _, _, _, _),
1617
+
[163] = PINGROUP(163, usb0_sbrx, prng_rosc, phase_flag, _, atest_char, _, _, _,
1618
+
_, _, _),
1619
+
[164] = PINGROUP(164, usb0_sbtx, prng_rosc, phase_flag, _, atest_char, _, _, _, _, _,
1620
+
_),
1621
+
[165] = PINGROUP(165, usb0_sbtx, _, _, _, _, _, _, _, _, _, _),
1622
+
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _),
1623
+
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, _),
1624
+
[168] = PINGROUP(168, eusb_ac_en, _, _, _, _, _, _, _, _, _, _),
1625
+
[169] = PINGROUP(169, eusb_ac_en, _, _, _, _, _, _, _, _, _, _),
1626
+
[170] = PINGROUP(170, _, _, _, _, _, _, _, _, _, _, _),
1627
+
[171] = PINGROUP(171, _, _, _, _, _, _, _, _, _, _, _),
1628
+
[172] = PINGROUP(172, usb1_sbrx, phase_flag, _, atest_char, _, _, _, _, _, _, _),
1629
+
[173] = PINGROUP(173, usb1_sbtx, cri_trng, phase_flag, _, _, _, _, _, _, _, _),
1630
+
[174] = PINGROUP(174, usb1_sbtx, _, _, _, _, _, _, _, _, _, _),
1631
+
[175] = PINGROUP(175, _, _, _, _, _, _, _, _, _, _, _),
1632
+
[176] = PINGROUP(176, _, _, _, _, _, _, _, _, _, _, _),
1633
+
[177] = PINGROUP(177, eusb_ac_en, _, _, _, _, _, _, _, _, _, _),
1634
+
[178] = PINGROUP(178, eusb_ac_en, _, _, _, _, _, _, _, _, _, _),
1635
+
[179] = PINGROUP(179, _, _, _, _, _, _, _, _, _, _, _),
1636
+
[180] = PINGROUP(180, _, _, _, _, _, _, _, _, _, _, _),
1637
+
[181] = PINGROUP(181, usb2_sbrx, _, _, _, _, _, _, _, _, _, _),
1638
+
[182] = PINGROUP(182, usb2_sbtx, _, _, _, _, _, _, _, _, _, _),
1639
+
[183] = PINGROUP(183, usb2_sbtx, _, _, _, _, _, _, _, _, _, _),
1640
+
[184] = PINGROUP(184, phase_flag, _, atest_char, _, _, _, _, _, _, _, _),
1641
+
[185] = PINGROUP(185, _, _, _, _, _, _, _, _, _, _, _),
1642
+
[186] = PINGROUP(186, eusb_ac_en, prng_rosc, phase_flag, _, _, _, _, _, _, _, _),
1643
+
[187] = PINGROUP(187, eusb_ac_en, _, _, _, _, _, _, _, _, _, _),
1644
+
[188] = PINGROUP(188, prng_rosc, phase_flag, _, atest_char, _, _, _, _, _, _, _),
1645
+
[189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, _),
1646
+
[190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, _),
1647
+
[191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, _),
1648
+
[192] = PINGROUP(192, _, _, _, _, _, _, _, _, _, _, egpio),
1649
+
[193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio),
1650
+
[194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio),
1651
+
[195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio),
1652
+
[196] = PINGROUP(196, _, _, _, _, _, _, _, _, _, _, egpio),
1653
+
[197] = PINGROUP(197, _, _, _, _, _, _, _, _, _, _, egpio),
1654
+
[198] = PINGROUP(198, _, _, _, _, _, _, _, _, _, _, egpio),
1655
+
[199] = PINGROUP(199, _, _, _, _, _, _, _, _, _, _, egpio),
1656
+
[200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio),
1657
+
[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio),
1658
+
[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio),
1659
+
[203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio),
1660
+
[204] = PINGROUP(204, _, _, _, _, _, _, _, _, _, _, egpio),
1661
+
[205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio),
1662
+
[206] = PINGROUP(206, _, _, _, _, _, _, _, _, _, _, egpio),
1663
+
[207] = PINGROUP(207, _, _, _, _, _, _, _, _, _, _, egpio),
1664
+
[208] = PINGROUP(208, _, _, _, _, _, _, _, _, _, _, egpio),
1665
+
[209] = PINGROUP(209, _, _, _, _, _, _, _, _, _, _, egpio),
1666
+
[210] = PINGROUP(210, _, _, _, _, _, _, _, _, _, _, egpio),
1667
+
[211] = PINGROUP(211, _, _, _, _, _, _, _, _, _, _, egpio),
1668
+
[212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio),
1669
+
[213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio),
1670
+
[214] = PINGROUP(214, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, egpio),
1671
+
[215] = PINGROUP(215, _, qdss_cti, _, _, _, _, _, _, _, _, egpio),
1672
+
[216] = PINGROUP(216, _, _, _, _, _, _, _, _, _, _, egpio),
1673
+
[217] = PINGROUP(217, _, qdss_cti, _, _, _, _, _, _, _, _, egpio),
1674
+
[218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio),
1675
+
[219] = PINGROUP(219, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1676
+
[220] = PINGROUP(220, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1677
+
[221] = PINGROUP(221, wcn_sw, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
1678
+
[222] = PINGROUP(222, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1679
+
[223] = PINGROUP(223, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1680
+
[224] = PINGROUP(224, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1681
+
[225] = PINGROUP(225, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1682
+
[226] = PINGROUP(226, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1683
+
[227] = PINGROUP(227, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1684
+
[228] = PINGROUP(228, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1685
+
[229] = PINGROUP(229, _, _, _, _, _, _, _, _, _, _, egpio),
1686
+
[230] = PINGROUP(230, _, _, _, _, _, _, _, _, _, _, egpio),
1687
+
[231] = PINGROUP(231, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1688
+
[232] = PINGROUP(232, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1689
+
[233] = PINGROUP(233, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1690
+
[234] = PINGROUP(234, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1691
+
[235] = PINGROUP(235, asc_cci, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1692
+
[236] = PINGROUP(236, asc_cci, qdss_gpio, _, _, _, _, _, _, _, _, egpio),
1693
+
[237] = PINGROUP(237, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1694
+
[238] = PINGROUP(238, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio),
1695
+
[239] = PINGROUP(239, _, _, _, _, _, _, _, _, _, _, egpio),
1696
+
[240] = PINGROUP(240, _, _, _, _, _, _, _, _, _, _, egpio),
1697
+
[241] = PINGROUP(241, _, _, _, _, _, _, _, _, _, _, egpio),
1698
+
[242] = PINGROUP(242, _, _, _, _, _, _, _, _, _, _, egpio),
1699
+
[243] = PINGROUP(243, _, _, _, _, _, _, _, _, _, _, egpio),
1700
+
[244] = PINGROUP(244, _, _, _, _, _, _, _, _, _, _, egpio),
1701
+
[245] = PINGROUP(245, smb_acok_n, _, _, _, _, _, _, _, _, _, _),
1702
+
[246] = PINGROUP(246, _, _, _, _, _, _, _, _, _, _, _),
1703
+
[247] = PINGROUP(247, qup3_se0, _, _, _, _, _, _, _, _, _, _),
1704
+
[248] = PINGROUP(248, pmc_uva_n, _, _, _, _, _, _, _, _, _, _),
1705
+
[249] = PINGROUP(249, pmc_oca_n, _, _, _, _, _, _, _, _, _, _),
1706
+
[250] = UFS_RESET(ufs_reset, 0x104004, 0x105000),
1707
+
[251] = SDC_QDSD_PINGROUP(sdc2_clk, 0xff000, 14, 6),
1708
+
[252] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xff000, 11, 3),
1709
+
[253] = SDC_QDSD_PINGROUP(sdc2_data, 0xff000, 9, 0),
1710
+
};
1711
+
1712
+
static const struct msm_gpio_wakeirq_map glymur_pdc_map[] = {
1713
+
{ 0, 116 }, { 2, 114 }, { 3, 115 }, { 4, 175 }, { 5, 176 },
1714
+
{ 7, 111 }, { 11, 129 }, { 13, 130 }, { 15, 112 }, { 19, 113 },
1715
+
{ 23, 187 }, { 27, 188 }, { 28, 121 }, { 29, 122 }, { 30, 136 },
1716
+
{ 31, 203 }, { 32, 189 }, { 34, 174 }, { 35, 190 }, { 36, 191 },
1717
+
{ 39, 124 }, { 43, 192 }, { 47, 193 }, { 51, 123 }, { 53, 133 },
1718
+
{ 55, 125 }, { 59, 131 }, { 64, 134 }, { 65, 150 }, { 66, 186 },
1719
+
{ 67, 132 }, { 68, 195 }, { 71, 135 }, { 75, 196 }, { 79, 197 },
1720
+
{ 83, 198 }, { 84, 181 }, { 85, 199 }, { 87, 200 }, { 91, 201 },
1721
+
{ 92, 182 }, { 93, 183 }, { 94, 184 }, { 95, 185 }, { 98, 202 },
1722
+
{ 105, 157 }, { 113, 128 }, { 121, 117 }, { 123, 118 }, { 125, 119 },
1723
+
{ 129, 120 }, { 131, 126 }, { 132, 160 }, { 133, 194 }, { 134, 127 },
1724
+
{ 141, 137 }, { 143, 159 }, { 144, 138 }, { 145, 139 }, { 147, 140 },
1725
+
{ 148, 141 }, { 150, 146 }, { 151, 147 }, { 153, 148 }, { 154, 144 },
1726
+
{ 156, 149 }, { 157, 151 }, { 163, 142 }, { 172, 143 }, { 181, 145 },
1727
+
{ 193, 161 }, { 196, 152 }, { 203, 177 }, { 208, 178 }, { 215, 162 },
1728
+
{ 217, 153 }, { 220, 154 }, { 221, 155 }, { 228, 179 }, { 230, 180 },
1729
+
{ 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 },
1730
+
};
1731
+
1732
+
static const struct msm_pinctrl_soc_data glymur_tlmm = {
1733
+
.pins = glymur_pins,
1734
+
.npins = ARRAY_SIZE(glymur_pins),
1735
+
.functions = glymur_functions,
1736
+
.nfunctions = ARRAY_SIZE(glymur_functions),
1737
+
.groups = glymur_groups,
1738
+
.ngroups = ARRAY_SIZE(glymur_groups),
1739
+
.ngpios = 251,
1740
+
.wakeirq_map = glymur_pdc_map,
1741
+
.nwakeirq_map = ARRAY_SIZE(glymur_pdc_map),
1742
+
.egpio_func = 11,
1743
+
};
1744
+
1745
+
static const struct of_device_id glymur_tlmm_of_match[] = {
1746
+
{ .compatible = "qcom,glymur-tlmm", .data = &glymur_tlmm },
1747
+
{ }
1748
+
};
1749
+
1750
+
static int glymur_tlmm_probe(struct platform_device *pdev)
1751
+
{
1752
+
return msm_pinctrl_probe(pdev, &glymur_tlmm);
1753
+
}
1754
+
1755
+
static struct platform_driver glymur_tlmm_driver = {
1756
+
.driver = {
1757
+
.name = "glymur-tlmm",
1758
+
.of_match_table = glymur_tlmm_of_match,
1759
+
},
1760
+
.probe = glymur_tlmm_probe,
1761
+
};
1762
+
1763
+
static int __init glymur_tlmm_init(void)
1764
+
{
1765
+
return platform_driver_register(&glymur_tlmm_driver);
1766
+
}
1767
+
arch_initcall(glymur_tlmm_init);
1768
+
1769
+
static void __exit glymur_tlmm_exit(void)
1770
+
{
1771
+
platform_driver_unregister(&glymur_tlmm_driver);
1772
+
}
1773
+
module_exit(glymur_tlmm_exit);
1774
+
1775
+
MODULE_DESCRIPTION("QTI GLYMUR TLMM driver");
1776
+
MODULE_LICENSE("GPL");
1777
+
MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match);
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq5018.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq5018.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq5332.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq5332.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq5424.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq5424.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq6018.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq6018.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq8074.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq8074.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq9574.c
+1
-1
drivers/pinctrl/qcom/pinctrl-ipq9574.c
+20
-6
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+20
-6
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
···
41
41
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
42
42
unsigned int addr)
43
43
{
44
-
return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
44
+
u32 pin_offset;
45
+
46
+
if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)
47
+
pin_offset = state->data->groups[pin].pin_offset;
48
+
else
49
+
pin_offset = LPI_TLMM_REG_OFFSET * pin;
50
+
51
+
return ioread32(state->tlmm_base + pin_offset + addr);
45
52
}
46
53
47
54
static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
48
55
unsigned int addr, unsigned int val)
49
56
{
50
-
iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
57
+
u32 pin_offset;
58
+
59
+
if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)
60
+
pin_offset = state->data->groups[pin].pin_offset;
61
+
else
62
+
pin_offset = LPI_TLMM_REG_OFFSET * pin;
63
+
64
+
iowrite32(val, state->tlmm_base + pin_offset + addr);
51
65
52
66
return 0;
53
67
}
···
188
174
arg = 1;
189
175
break;
190
176
case PIN_CONFIG_INPUT_ENABLE:
191
-
case PIN_CONFIG_OUTPUT:
177
+
case PIN_CONFIG_LEVEL:
192
178
if (is_out)
193
179
arg = 1;
194
180
break;
···
266
252
case PIN_CONFIG_INPUT_ENABLE:
267
253
output_enabled = false;
268
254
break;
269
-
case PIN_CONFIG_OUTPUT:
255
+
case PIN_CONFIG_LEVEL:
270
256
output_enabled = true;
271
257
value = arg;
272
258
break;
···
328
314
struct lpi_pinctrl *state = gpiochip_get_data(chip);
329
315
unsigned long config;
330
316
331
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
317
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
332
318
333
319
return lpi_config_set(state->ctrl, pin, &config, 1);
334
320
}
···
346
332
struct lpi_pinctrl *state = gpiochip_get_data(chip);
347
333
unsigned long config;
348
334
349
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
335
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
350
336
351
337
return lpi_config_set(state->ctrl, pin, &config, 1);
352
338
}
+18
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+18
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
···
55
55
LPI_MUX_##f4, \
56
56
}, \
57
57
.nfuncs = 5, \
58
+
.pin_offset = 0, \
59
+
}
60
+
61
+
#define LPI_PINGROUP_OFFSET(id, soff, f1, f2, f3, f4, poff) \
62
+
{ \
63
+
.pin = id, \
64
+
.slew_offset = soff, \
65
+
.funcs = (int[]){ \
66
+
LPI_MUX_gpio, \
67
+
LPI_MUX_##f1, \
68
+
LPI_MUX_##f2, \
69
+
LPI_MUX_##f3, \
70
+
LPI_MUX_##f4, \
71
+
}, \
72
+
.nfuncs = 5, \
73
+
.pin_offset = poff, \
58
74
}
59
75
60
76
/*
···
78
62
* pin configuration.
79
63
*/
80
64
#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0)
65
+
#define LPI_FLAG_USE_PREDEFINED_PIN_OFFSET BIT(1)
81
66
82
67
struct lpi_pingroup {
83
68
unsigned int pin;
···
86
69
int slew_offset;
87
70
unsigned int *funcs;
88
71
unsigned int nfuncs;
72
+
unsigned int pin_offset;
89
73
};
90
74
91
75
struct lpi_function {
+1
-1
drivers/pinctrl/qcom/pinctrl-mdm9607.c
+1
-1
drivers/pinctrl/qcom/pinctrl-mdm9607.c
+1
-1
drivers/pinctrl/qcom/pinctrl-mdm9615.c
+1
-1
drivers/pinctrl/qcom/pinctrl-mdm9615.c
+1
-1
drivers/pinctrl/qcom/pinctrl-milos.c
+1
-1
drivers/pinctrl/qcom/pinctrl-milos.c
+18
-33
drivers/pinctrl/qcom/pinctrl-msm.c
+18
-33
drivers/pinctrl/qcom/pinctrl-msm.c
···
31
31
#include "../core.h"
32
32
#include "../pinconf.h"
33
33
#include "../pinctrl-utils.h"
34
+
#include "../pinmux.h"
34
35
35
36
#include "pinctrl-msm.h"
36
37
···
151
150
return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
152
151
}
153
152
154
-
static int msm_get_functions_count(struct pinctrl_dev *pctldev)
155
-
{
156
-
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
157
-
158
-
return pctrl->soc->nfunctions;
159
-
}
160
-
161
-
static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
162
-
unsigned function)
163
-
{
164
-
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
165
-
166
-
return pctrl->soc->functions[function].name;
167
-
}
168
-
169
-
static int msm_get_function_groups(struct pinctrl_dev *pctldev,
170
-
unsigned function,
171
-
const char * const **groups,
172
-
unsigned * const num_groups)
173
-
{
174
-
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
175
-
176
-
*groups = pctrl->soc->functions[function].groups;
177
-
*num_groups = pctrl->soc->functions[function].ngroups;
178
-
return 0;
179
-
}
180
-
181
153
static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
182
154
unsigned function,
183
155
unsigned group)
···
262
288
263
289
static const struct pinmux_ops msm_pinmux_ops = {
264
290
.request = msm_pinmux_request,
265
-
.get_functions_count = msm_get_functions_count,
266
-
.get_function_name = msm_get_function_name,
267
-
.get_function_groups = msm_get_function_groups,
291
+
.get_functions_count = pinmux_generic_get_function_count,
292
+
.get_function_name = pinmux_generic_get_function_name,
293
+
.get_function_groups = pinmux_generic_get_function_groups,
294
+
.function_is_gpio = pinmux_generic_function_is_gpio,
268
295
.gpio_request_enable = msm_pinmux_request_gpio,
269
296
.set_mux = msm_pinmux_set_mux,
297
+
.strict = true,
270
298
};
271
299
272
300
static int msm_config_reg(struct msm_pinctrl *pctrl,
···
295
319
*bit = g->drv_bit;
296
320
*mask = 7;
297
321
break;
298
-
case PIN_CONFIG_OUTPUT:
322
+
case PIN_CONFIG_LEVEL:
299
323
case PIN_CONFIG_INPUT_ENABLE:
300
324
case PIN_CONFIG_OUTPUT_ENABLE:
301
325
*bit = g->oe_bit;
···
385
409
case PIN_CONFIG_DRIVE_STRENGTH:
386
410
arg = msm_regval_to_drive(arg);
387
411
break;
388
-
case PIN_CONFIG_OUTPUT:
412
+
case PIN_CONFIG_LEVEL:
389
413
/* Pin is not output */
390
414
if (!arg)
391
415
return -EINVAL;
···
464
488
else
465
489
arg = (arg / 2) - 1;
466
490
break;
467
-
case PIN_CONFIG_OUTPUT:
491
+
case PIN_CONFIG_LEVEL:
468
492
/* set output value */
469
493
raw_spin_lock_irqsave(&pctrl->lock, flags);
470
494
val = msm_readl_io(pctrl, g);
···
1528
1552
int msm_pinctrl_probe(struct platform_device *pdev,
1529
1553
const struct msm_pinctrl_soc_data *soc_data)
1530
1554
{
1555
+
const struct pinfunction *func;
1531
1556
struct msm_pinctrl *pctrl;
1532
1557
struct resource *res;
1533
1558
int ret;
···
1581
1604
if (IS_ERR(pctrl->pctrl)) {
1582
1605
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1583
1606
return PTR_ERR(pctrl->pctrl);
1607
+
}
1608
+
1609
+
for (i = 0; i < soc_data->nfunctions; i++) {
1610
+
func = &soc_data->functions[i];
1611
+
1612
+
ret = pinmux_generic_add_pinfunction(pctrl->pctrl, func, NULL);
1613
+
if (ret < 0)
1614
+
return ret;
1584
1615
}
1585
1616
1586
1617
ret = msm_gpio_init(pctrl);
+5
drivers/pinctrl/qcom/pinctrl-msm.h
+5
drivers/pinctrl/qcom/pinctrl-msm.h
···
29
29
fname##_groups, \
30
30
ARRAY_SIZE(fname##_groups))
31
31
32
+
#define MSM_GPIO_PIN_FUNCTION(fname) \
33
+
[msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
34
+
fname##_groups, \
35
+
ARRAY_SIZE(fname##_groups))
36
+
32
37
#define QCA_PIN_FUNCTION(fname) \
33
38
[qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
34
39
fname##_groups, \
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8226.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8226.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8660.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8660.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8909.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8909.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8916.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8916.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8917.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8917.c
···
1302
1302
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
1303
1303
MSM_PIN_FUNCTION(gcc_plltest),
1304
1304
MSM_PIN_FUNCTION(gcc_tlmm),
1305
-
MSM_PIN_FUNCTION(gpio),
1305
+
MSM_GPIO_PIN_FUNCTION(gpio),
1306
1306
MSM_PIN_FUNCTION(gsm0_tx),
1307
1307
MSM_PIN_FUNCTION(key_focus),
1308
1308
MSM_PIN_FUNCTION(key_snapshot),
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8953.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8953.c
···
1533
1533
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
1534
1534
MSM_PIN_FUNCTION(gcc_plltest),
1535
1535
MSM_PIN_FUNCTION(gcc_tlmm),
1536
-
MSM_PIN_FUNCTION(gpio),
1536
+
MSM_GPIO_PIN_FUNCTION(gpio),
1537
1537
MSM_PIN_FUNCTION(gsm0_tx),
1538
1538
MSM_PIN_FUNCTION(gsm1_tx),
1539
1539
MSM_PIN_FUNCTION(gyro_int),
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8960.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8960.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8976.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8976.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8994.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8994.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8996.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8996.c
···
1532
1532
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
1533
1533
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
1534
1534
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
1535
-
MSM_PIN_FUNCTION(gpio),
1535
+
MSM_GPIO_PIN_FUNCTION(gpio),
1536
1536
MSM_PIN_FUNCTION(gsm_tx),
1537
1537
MSM_PIN_FUNCTION(hdmi_cec),
1538
1538
MSM_PIN_FUNCTION(hdmi_ddc),
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8998.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8998.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8x74.c
+1
-1
drivers/pinctrl/qcom/pinctrl-msm8x74.c
···
778
778
static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" };
779
779
780
780
static const struct pinfunction msm8x74_functions[] = {
781
-
MSM_PIN_FUNCTION(gpio),
781
+
MSM_GPIO_PIN_FUNCTION(gpio),
782
782
MSM_PIN_FUNCTION(cci_i2c0),
783
783
MSM_PIN_FUNCTION(cci_i2c1),
784
784
MSM_PIN_FUNCTION(uim1),
+2
-2
drivers/pinctrl/qcom/pinctrl-qcm2290.c
+2
-2
drivers/pinctrl/qcom/pinctrl-qcm2290.c
···
870
870
MSM_PIN_FUNCTION(ddr_pxi1),
871
871
MSM_PIN_FUNCTION(ddr_pxi2),
872
872
MSM_PIN_FUNCTION(ddr_pxi3),
873
-
MSM_PIN_FUNCTION(egpio),
873
+
MSM_GPIO_PIN_FUNCTION(egpio),
874
874
MSM_PIN_FUNCTION(gcc_gp1),
875
875
MSM_PIN_FUNCTION(gcc_gp2),
876
876
MSM_PIN_FUNCTION(gcc_gp3),
877
-
MSM_PIN_FUNCTION(gpio),
877
+
MSM_GPIO_PIN_FUNCTION(gpio),
878
878
MSM_PIN_FUNCTION(gp_pdm0),
879
879
MSM_PIN_FUNCTION(gp_pdm1),
880
880
MSM_PIN_FUNCTION(gp_pdm2),
+1
-1
drivers/pinctrl/qcom/pinctrl-qcs404.c
+1
-1
drivers/pinctrl/qcom/pinctrl-qcs404.c
+1
-1
drivers/pinctrl/qcom/pinctrl-qcs615.c
+1
-1
drivers/pinctrl/qcom/pinctrl-qcs615.c
+2
-2
drivers/pinctrl/qcom/pinctrl-qcs8300.c
+2
-2
drivers/pinctrl/qcom/pinctrl-qcs8300.c
···
929
929
};
930
930
931
931
static const struct pinfunction qcs8300_functions[] = {
932
-
MSM_PIN_FUNCTION(gpio),
932
+
MSM_GPIO_PIN_FUNCTION(gpio),
933
933
MSM_PIN_FUNCTION(aoss_cti),
934
934
MSM_PIN_FUNCTION(atest_char),
935
935
MSM_PIN_FUNCTION(atest_usb2),
···
949
949
MSM_PIN_FUNCTION(edp0_hot),
950
950
MSM_PIN_FUNCTION(edp0_lcd),
951
951
MSM_PIN_FUNCTION(edp1_lcd),
952
-
MSM_PIN_FUNCTION(egpio),
952
+
MSM_GPIO_PIN_FUNCTION(egpio),
953
953
MSM_PIN_FUNCTION(emac0_mcg0),
954
954
MSM_PIN_FUNCTION(emac0_mcg1),
955
955
MSM_PIN_FUNCTION(emac0_mcg2),
+1
-1
drivers/pinctrl/qcom/pinctrl-qdu1000.c
+1
-1
drivers/pinctrl/qcom/pinctrl-qdu1000.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sa8775p.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sa8775p.c
···
1181
1181
};
1182
1182
1183
1183
static const struct pinfunction sa8775p_functions[] = {
1184
-
MSM_PIN_FUNCTION(gpio),
1184
+
MSM_GPIO_PIN_FUNCTION(gpio),
1185
1185
MSM_PIN_FUNCTION(atest_char),
1186
1186
MSM_PIN_FUNCTION(atest_usb2),
1187
1187
MSM_PIN_FUNCTION(audio_ref),
···
1217
1217
MSM_PIN_FUNCTION(edp2_lcd),
1218
1218
MSM_PIN_FUNCTION(edp3_hot),
1219
1219
MSM_PIN_FUNCTION(edp3_lcd),
1220
-
MSM_PIN_FUNCTION(egpio),
1220
+
MSM_GPIO_PIN_FUNCTION(egpio),
1221
1221
MSM_PIN_FUNCTION(emac0_mcg0),
1222
1222
MSM_PIN_FUNCTION(emac0_mcg1),
1223
1223
MSM_PIN_FUNCTION(emac0_mcg2),
+1
-1
drivers/pinctrl/qcom/pinctrl-sar2130p.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sar2130p.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sc7180.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sc7180.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sc7280.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sc7280.c
···
1153
1153
MSM_PIN_FUNCTION(dp_lcd),
1154
1154
MSM_PIN_FUNCTION(edp_hot),
1155
1155
MSM_PIN_FUNCTION(edp_lcd),
1156
-
MSM_PIN_FUNCTION(egpio),
1156
+
MSM_GPIO_PIN_FUNCTION(egpio),
1157
1157
MSM_PIN_FUNCTION(gcc_gp1),
1158
1158
MSM_PIN_FUNCTION(gcc_gp2),
1159
1159
MSM_PIN_FUNCTION(gcc_gp3),
1160
-
MSM_PIN_FUNCTION(gpio),
1160
+
MSM_GPIO_PIN_FUNCTION(gpio),
1161
1161
MSM_PIN_FUNCTION(host2wlan_sol),
1162
1162
MSM_PIN_FUNCTION(ibi_i3c),
1163
1163
MSM_PIN_FUNCTION(jitter_bist),
+2
-2
drivers/pinctrl/qcom/pinctrl-sc8180x.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sc8180x.c
···
1272
1272
MSM_PIN_FUNCTION(gcc_gp3),
1273
1273
MSM_PIN_FUNCTION(gcc_gp4),
1274
1274
MSM_PIN_FUNCTION(gcc_gp5),
1275
-
MSM_PIN_FUNCTION(gpio),
1275
+
MSM_GPIO_PIN_FUNCTION(gpio),
1276
1276
MSM_PIN_FUNCTION(gps),
1277
1277
MSM_PIN_FUNCTION(grfc),
1278
1278
MSM_PIN_FUNCTION(hs1_mi2s),
···
1634
1634
return 0;
1635
1635
1636
1636
/* Allocate for new resources */
1637
-
nres = devm_kzalloc(&pdev->dev, sizeof(*nres) * nres_num, GFP_KERNEL);
1637
+
nres = devm_kcalloc(&pdev->dev, nres_num, sizeof(*nres), GFP_KERNEL);
1638
1638
if (!nres)
1639
1639
return -ENOMEM;
1640
1640
+2
-2
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
···
1506
1506
MSM_PIN_FUNCTION(edp2_lcd),
1507
1507
MSM_PIN_FUNCTION(edp3_lcd),
1508
1508
MSM_PIN_FUNCTION(edp_hot),
1509
-
MSM_PIN_FUNCTION(egpio),
1509
+
MSM_GPIO_PIN_FUNCTION(egpio),
1510
1510
MSM_PIN_FUNCTION(emac0_dll),
1511
1511
MSM_PIN_FUNCTION(emac0_mcg0),
1512
1512
MSM_PIN_FUNCTION(emac0_mcg1),
···
1527
1527
MSM_PIN_FUNCTION(gcc_gp3),
1528
1528
MSM_PIN_FUNCTION(gcc_gp4),
1529
1529
MSM_PIN_FUNCTION(gcc_gp5),
1530
-
MSM_PIN_FUNCTION(gpio),
1530
+
MSM_GPIO_PIN_FUNCTION(gpio),
1531
1531
MSM_PIN_FUNCTION(hs1_mi2s),
1532
1532
MSM_PIN_FUNCTION(hs2_mi2s),
1533
1533
MSM_PIN_FUNCTION(hs3_mi2s),
+160
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
+160
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* This driver is solely based on the limited information in downstream code.
4
+
* Any verification with schematics would be greatly appreciated.
5
+
*
6
+
* Copyright (c) 2023, Richard Acayan. All rights reserved.
7
+
*/
8
+
9
+
#include <linux/kernel.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/pinctrl/pinctrl.h>
14
+
15
+
#include "pinctrl-lpass-lpi.h"
16
+
17
+
enum lpass_lpi_functions {
18
+
LPI_MUX_comp_rx,
19
+
LPI_MUX_dmic1_clk,
20
+
LPI_MUX_dmic1_data,
21
+
LPI_MUX_dmic2_clk,
22
+
LPI_MUX_dmic2_data,
23
+
LPI_MUX_mclk0,
24
+
LPI_MUX_pdm_tx,
25
+
LPI_MUX_pdm_clk,
26
+
LPI_MUX_pdm_rx,
27
+
LPI_MUX_pdm_sync,
28
+
29
+
LPI_MUX_gpio,
30
+
LPI_MUX__,
31
+
};
32
+
33
+
static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] = {
34
+
PINCTRL_PIN(0, "gpio0"),
35
+
PINCTRL_PIN(1, "gpio1"),
36
+
PINCTRL_PIN(2, "gpio2"),
37
+
PINCTRL_PIN(3, "gpio3"),
38
+
PINCTRL_PIN(4, "gpio4"),
39
+
PINCTRL_PIN(5, "gpio5"),
40
+
PINCTRL_PIN(6, "gpio6"),
41
+
PINCTRL_PIN(7, "gpio7"),
42
+
PINCTRL_PIN(8, "gpio8"),
43
+
PINCTRL_PIN(9, "gpio9"),
44
+
PINCTRL_PIN(10, "gpio10"),
45
+
PINCTRL_PIN(11, "gpio11"),
46
+
PINCTRL_PIN(12, "gpio12"),
47
+
PINCTRL_PIN(13, "gpio13"),
48
+
PINCTRL_PIN(14, "gpio14"),
49
+
PINCTRL_PIN(15, "gpio15"),
50
+
PINCTRL_PIN(16, "gpio16"),
51
+
PINCTRL_PIN(17, "gpio17"),
52
+
PINCTRL_PIN(18, "gpio18"),
53
+
PINCTRL_PIN(19, "gpio19"),
54
+
PINCTRL_PIN(20, "gpio20"),
55
+
PINCTRL_PIN(21, "gpio21"),
56
+
PINCTRL_PIN(22, "gpio22"),
57
+
PINCTRL_PIN(23, "gpio23"),
58
+
PINCTRL_PIN(24, "gpio24"),
59
+
PINCTRL_PIN(25, "gpio25"),
60
+
PINCTRL_PIN(26, "gpio26"),
61
+
PINCTRL_PIN(27, "gpio27"),
62
+
PINCTRL_PIN(28, "gpio28"),
63
+
PINCTRL_PIN(29, "gpio29"),
64
+
PINCTRL_PIN(30, "gpio30"),
65
+
PINCTRL_PIN(31, "gpio31"),
66
+
};
67
+
68
+
static const char * const comp_rx_groups[] = { "gpio22", "gpio24" };
69
+
static const char * const dmic1_clk_groups[] = { "gpio26" };
70
+
static const char * const dmic1_data_groups[] = { "gpio27" };
71
+
static const char * const dmic2_clk_groups[] = { "gpio28" };
72
+
static const char * const dmic2_data_groups[] = { "gpio29" };
73
+
static const char * const mclk0_groups[] = { "gpio18" };
74
+
static const char * const pdm_tx_groups[] = { "gpio20" };
75
+
static const char * const pdm_clk_groups[] = { "gpio18" };
76
+
static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" };
77
+
static const char * const pdm_sync_groups[] = { "gpio19" };
78
+
79
+
const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = {
80
+
LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000),
81
+
LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000),
82
+
LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000),
83
+
LPI_PINGROUP_OFFSET(3, LPI_NO_SLEW, _, _, _, _, 0x2010),
84
+
LPI_PINGROUP_OFFSET(4, LPI_NO_SLEW, _, _, _, _, 0x3000),
85
+
LPI_PINGROUP_OFFSET(5, LPI_NO_SLEW, _, _, _, _, 0x3010),
86
+
LPI_PINGROUP_OFFSET(6, LPI_NO_SLEW, _, _, _, _, 0x4000),
87
+
LPI_PINGROUP_OFFSET(7, LPI_NO_SLEW, _, _, _, _, 0x4010),
88
+
LPI_PINGROUP_OFFSET(8, LPI_NO_SLEW, _, _, _, _, 0x5000),
89
+
LPI_PINGROUP_OFFSET(9, LPI_NO_SLEW, _, _, _, _, 0x5010),
90
+
LPI_PINGROUP_OFFSET(10, LPI_NO_SLEW, _, _, _, _, 0x5020),
91
+
LPI_PINGROUP_OFFSET(11, LPI_NO_SLEW, _, _, _, _, 0x5030),
92
+
LPI_PINGROUP_OFFSET(12, LPI_NO_SLEW, _, _, _, _, 0x6000),
93
+
LPI_PINGROUP_OFFSET(13, LPI_NO_SLEW, _, _, _, _, 0x6010),
94
+
LPI_PINGROUP_OFFSET(14, LPI_NO_SLEW, _, _, _, _, 0x7000),
95
+
LPI_PINGROUP_OFFSET(15, LPI_NO_SLEW, _, _, _, _, 0x7010),
96
+
LPI_PINGROUP_OFFSET(16, LPI_NO_SLEW, _, _, _, _, 0x5040),
97
+
LPI_PINGROUP_OFFSET(17, LPI_NO_SLEW, _, _, _, _, 0x5050),
98
+
99
+
LPI_PINGROUP_OFFSET(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _, 0x8000),
100
+
LPI_PINGROUP_OFFSET(19, LPI_NO_SLEW, pdm_sync, _, _, _, 0x8010),
101
+
LPI_PINGROUP_OFFSET(20, LPI_NO_SLEW, pdm_tx, _, _, _, 0x8020),
102
+
LPI_PINGROUP_OFFSET(21, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8030),
103
+
LPI_PINGROUP_OFFSET(22, LPI_NO_SLEW, comp_rx, _, _, _, 0x8040),
104
+
LPI_PINGROUP_OFFSET(23, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8050),
105
+
LPI_PINGROUP_OFFSET(24, LPI_NO_SLEW, comp_rx, _, _, _, 0x8060),
106
+
LPI_PINGROUP_OFFSET(25, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8070),
107
+
LPI_PINGROUP_OFFSET(26, LPI_NO_SLEW, dmic1_clk, _, _, _, 0x9000),
108
+
LPI_PINGROUP_OFFSET(27, LPI_NO_SLEW, dmic1_data, _, _, _, 0x9010),
109
+
LPI_PINGROUP_OFFSET(28, LPI_NO_SLEW, dmic2_clk, _, _, _, 0xa000),
110
+
LPI_PINGROUP_OFFSET(29, LPI_NO_SLEW, dmic2_data, _, _, _, 0xa010),
111
+
112
+
LPI_PINGROUP_OFFSET(30, LPI_NO_SLEW, _, _, _, _, 0xb000),
113
+
LPI_PINGROUP_OFFSET(31, LPI_NO_SLEW, _, _, _, _, 0xb010),
114
+
};
115
+
116
+
const struct lpi_function sdm660_lpi_pinctrl_functions[] = {
117
+
LPI_FUNCTION(comp_rx),
118
+
LPI_FUNCTION(dmic1_clk),
119
+
LPI_FUNCTION(dmic1_data),
120
+
LPI_FUNCTION(dmic2_clk),
121
+
LPI_FUNCTION(dmic2_data),
122
+
LPI_FUNCTION(mclk0),
123
+
LPI_FUNCTION(pdm_tx),
124
+
LPI_FUNCTION(pdm_clk),
125
+
LPI_FUNCTION(pdm_rx),
126
+
LPI_FUNCTION(pdm_sync),
127
+
};
128
+
129
+
static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data = {
130
+
.pins = sdm660_lpi_pinctrl_pins,
131
+
.npins = ARRAY_SIZE(sdm660_lpi_pinctrl_pins),
132
+
.groups = sdm660_lpi_pinctrl_groups,
133
+
.ngroups = ARRAY_SIZE(sdm660_lpi_pinctrl_groups),
134
+
.functions = sdm660_lpi_pinctrl_functions,
135
+
.nfunctions = ARRAY_SIZE(sdm660_lpi_pinctrl_functions),
136
+
.flags = LPI_FLAG_SLEW_RATE_SAME_REG | LPI_FLAG_USE_PREDEFINED_PIN_OFFSET
137
+
};
138
+
139
+
static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = {
140
+
{
141
+
.compatible = "qcom,sdm660-lpass-lpi-pinctrl",
142
+
.data = &sdm660_lpi_pinctrl_data,
143
+
},
144
+
{ }
145
+
};
146
+
MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match);
147
+
148
+
static struct platform_driver sdm660_lpi_pinctrl_driver = {
149
+
.driver = {
150
+
.name = "qcom-sdm660-lpass-lpi-pinctrl",
151
+
.of_match_table = sdm660_lpi_pinctrl_of_match,
152
+
},
153
+
.probe = lpi_pinctrl_probe,
154
+
.remove = lpi_pinctrl_remove,
155
+
};
156
+
module_platform_driver(sdm660_lpi_pinctrl_driver);
157
+
158
+
MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>");
159
+
MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver");
160
+
MODULE_LICENSE("GPL");
+1
-1
drivers/pinctrl/qcom/pinctrl-sdm660.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdm660.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdm670.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdm670.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdm845.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdm845.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdx55.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdx55.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdx65.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdx65.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdx75.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sdx75.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm4450.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm4450.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6115.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6115.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6125.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6125.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6350.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6350.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6375.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm6375.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm7150.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm7150.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8150.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8150.c
+48
-35
drivers/pinctrl/qcom/pinctrl-sm8250.c
+48
-35
drivers/pinctrl/qcom/pinctrl-sm8250.c
···
49
49
.mux_bit = 2, \
50
50
.pull_bit = 0, \
51
51
.drv_bit = 6, \
52
+
.egpio_enable = 12, \
53
+
.egpio_present = 11, \
52
54
.oe_bit = 9, \
53
55
.in_bit = 0, \
54
56
.out_bit = 1, \
···
513
511
msm_mux_ddr_pxi2,
514
512
msm_mux_ddr_pxi3,
515
513
msm_mux_dp_hot,
514
+
msm_mux_egpio,
516
515
msm_mux_dp_lcd,
517
516
msm_mux_gcc_gp1,
518
517
msm_mux_gcc_gp2,
···
833
830
"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
834
831
"gpio177", "gpio178", "gpio179",
835
832
};
833
+
static const char * const egpio_groups[] = {
834
+
"gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151",
835
+
"gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157",
836
+
"gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163",
837
+
"gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169",
838
+
"gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175",
839
+
"gpio176", "gpio177", "gpio178", "gpio179",
840
+
};
836
841
static const char * const qdss_cti_groups[] = {
837
842
"gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92",
838
843
"gpio93",
···
1029
1018
MSM_PIN_FUNCTION(ddr_pxi3),
1030
1019
MSM_PIN_FUNCTION(dp_hot),
1031
1020
MSM_PIN_FUNCTION(dp_lcd),
1021
+
MSM_PIN_FUNCTION(egpio),
1032
1022
MSM_PIN_FUNCTION(gcc_gp1),
1033
1023
MSM_PIN_FUNCTION(gcc_gp2),
1034
1024
MSM_PIN_FUNCTION(gcc_gp3),
1035
-
MSM_PIN_FUNCTION(gpio),
1025
+
MSM_GPIO_PIN_FUNCTION(gpio),
1036
1026
MSM_PIN_FUNCTION(ibi_i3c),
1037
1027
MSM_PIN_FUNCTION(jitter_bist),
1038
1028
MSM_PIN_FUNCTION(lpass_slimbus),
···
1277
1265
[143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _),
1278
1266
[144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _),
1279
1267
[145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _),
1280
-
[146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1281
-
[147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1282
-
[148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1283
-
[149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1284
-
[150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _),
1285
-
[151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _),
1286
-
[152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _),
1287
-
[153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _),
1288
-
[154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _),
1289
-
[155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _),
1290
-
[156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _),
1291
-
[157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _),
1292
-
[158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _),
1293
-
[159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _),
1294
-
[160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _),
1295
-
[161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _),
1296
-
[162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _),
1297
-
[163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _),
1298
-
[164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1299
-
[165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1300
-
[166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1301
-
[167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1302
-
[168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1303
-
[169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1304
-
[170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1305
-
[171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1306
-
[172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1307
-
[173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1308
-
[174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1309
-
[175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1310
-
[176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1311
-
[177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1312
-
[178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),
1313
-
[179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),
1268
+
[146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, egpio),
1269
+
[147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, egpio),
1270
+
[148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, egpio),
1271
+
[149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, egpio),
1272
+
[150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, egpio),
1273
+
[151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, egpio),
1274
+
[152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, egpio),
1275
+
[153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, egpio),
1276
+
[154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, egpio),
1277
+
[155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, egpio),
1278
+
[156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, egpio),
1279
+
[157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, egpio),
1280
+
[158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, egpio),
1281
+
[159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, egpio),
1282
+
[160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, egpio),
1283
+
[161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, egpio),
1284
+
[162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, egpio),
1285
+
[163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, egpio),
1286
+
[164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1287
+
[165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1288
+
[166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1289
+
[167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1290
+
[168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1291
+
[169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1292
+
[170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1293
+
[171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1294
+
[172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1295
+
[173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1296
+
[174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1297
+
[175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1298
+
[176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1299
+
[177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1300
+
[178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, egpio),
1301
+
[179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, egpio),
1314
1302
[180] = UFS_RESET(ufs_reset, 0xb8000),
1315
1303
[181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
1316
1304
[182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
···
1345
1333
.ntiles = ARRAY_SIZE(sm8250_tiles),
1346
1334
.wakeirq_map = sm8250_pdc_map,
1347
1335
.nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map),
1336
+
.egpio_func = 9,
1348
1337
};
1349
1338
1350
1339
static int sm8250_pinctrl_probe(struct platform_device *pdev)
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8350.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8350.c
···
1267
1267
MSM_PIN_FUNCTION(gcc_gp1),
1268
1268
MSM_PIN_FUNCTION(gcc_gp2),
1269
1269
MSM_PIN_FUNCTION(gcc_gp3),
1270
-
MSM_PIN_FUNCTION(gpio),
1270
+
MSM_GPIO_PIN_FUNCTION(gpio),
1271
1271
MSM_PIN_FUNCTION(ibi_i3c),
1272
1272
MSM_PIN_FUNCTION(jitter_bist),
1273
1273
MSM_PIN_FUNCTION(lpass_slimbus),
+2
-2
drivers/pinctrl/qcom/pinctrl-sm8450.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sm8450.c
···
1269
1269
};
1270
1270
1271
1271
static const struct pinfunction sm8450_functions[] = {
1272
-
MSM_PIN_FUNCTION(gpio),
1272
+
MSM_GPIO_PIN_FUNCTION(gpio),
1273
1273
MSM_PIN_FUNCTION(aon_cam),
1274
1274
MSM_PIN_FUNCTION(atest_char),
1275
1275
MSM_PIN_FUNCTION(atest_usb),
···
1291
1291
MSM_PIN_FUNCTION(ddr_pxi2),
1292
1292
MSM_PIN_FUNCTION(ddr_pxi3),
1293
1293
MSM_PIN_FUNCTION(dp_hot),
1294
-
MSM_PIN_FUNCTION(egpio),
1294
+
MSM_GPIO_PIN_FUNCTION(egpio),
1295
1295
MSM_PIN_FUNCTION(gcc_gp1),
1296
1296
MSM_PIN_FUNCTION(gcc_gp2),
1297
1297
MSM_PIN_FUNCTION(gcc_gp3),
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8550.c
+1
-1
drivers/pinctrl/qcom/pinctrl-sm8550.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sm8650.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sm8650.c
···
1328
1328
};
1329
1329
1330
1330
static const struct pinfunction sm8650_functions[] = {
1331
-
MSM_PIN_FUNCTION(gpio),
1331
+
MSM_GPIO_PIN_FUNCTION(gpio),
1332
1332
MSM_PIN_FUNCTION(aoss_cti),
1333
1333
MSM_PIN_FUNCTION(atest_char),
1334
1334
MSM_PIN_FUNCTION(atest_usb),
···
1359
1359
MSM_PIN_FUNCTION(ddr_pxi3),
1360
1360
MSM_PIN_FUNCTION(do_not),
1361
1361
MSM_PIN_FUNCTION(dp_hot),
1362
-
MSM_PIN_FUNCTION(egpio),
1362
+
MSM_GPIO_PIN_FUNCTION(egpio),
1363
1363
MSM_PIN_FUNCTION(gcc_gp1),
1364
1364
MSM_PIN_FUNCTION(gcc_gp2),
1365
1365
MSM_PIN_FUNCTION(gcc_gp3),
+2
-2
drivers/pinctrl/qcom/pinctrl-sm8750.c
+2
-2
drivers/pinctrl/qcom/pinctrl-sm8750.c
···
1290
1290
};
1291
1291
1292
1292
static const struct pinfunction sm8750_functions[] = {
1293
-
MSM_PIN_FUNCTION(gpio),
1293
+
MSM_GPIO_PIN_FUNCTION(gpio),
1294
1294
MSM_PIN_FUNCTION(aoss_cti),
1295
1295
MSM_PIN_FUNCTION(atest_char),
1296
1296
MSM_PIN_FUNCTION(atest_usb),
···
1319
1319
MSM_PIN_FUNCTION(ddr_pxi2),
1320
1320
MSM_PIN_FUNCTION(ddr_pxi3),
1321
1321
MSM_PIN_FUNCTION(dp_hot),
1322
-
MSM_PIN_FUNCTION(egpio),
1322
+
MSM_GPIO_PIN_FUNCTION(egpio),
1323
1323
MSM_PIN_FUNCTION(gcc_gp1),
1324
1324
MSM_PIN_FUNCTION(gcc_gp2),
1325
1325
MSM_PIN_FUNCTION(gcc_gp3),
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
···
438
438
case PIN_CONFIG_OUTPUT_ENABLE:
439
439
arg = pad->output_enabled;
440
440
break;
441
-
case PIN_CONFIG_OUTPUT:
441
+
case PIN_CONFIG_LEVEL:
442
442
arg = pad->out_value;
443
443
break;
444
444
case PMIC_GPIO_CONF_PULL_UP:
···
530
530
case PIN_CONFIG_OUTPUT_ENABLE:
531
531
pad->output_enabled = arg ? true : false;
532
532
break;
533
-
case PIN_CONFIG_OUTPUT:
533
+
case PIN_CONFIG_LEVEL:
534
534
pad->output_enabled = true;
535
535
pad->out_value = arg;
536
536
break;
···
737
737
struct pmic_gpio_state *state = gpiochip_get_data(chip);
738
738
unsigned long config;
739
739
740
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
740
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
741
741
742
742
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
743
743
}
···
769
769
struct pmic_gpio_state *state = gpiochip_get_data(chip);
770
770
unsigned long config;
771
771
772
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
772
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
773
773
774
774
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
775
775
}
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
···
370
370
return -EINVAL;
371
371
arg = 1;
372
372
break;
373
-
case PIN_CONFIG_OUTPUT:
373
+
case PIN_CONFIG_LEVEL:
374
374
arg = pad->out_value;
375
375
break;
376
376
case PMIC_MPP_CONF_DTEST_SELECTOR:
···
447
447
case PIN_CONFIG_INPUT_ENABLE:
448
448
pad->input_enabled = arg ? true : false;
449
449
break;
450
-
case PIN_CONFIG_OUTPUT:
450
+
case PIN_CONFIG_LEVEL:
451
451
pad->output_enabled = true;
452
452
pad->out_value = arg;
453
453
break;
···
576
576
struct pmic_mpp_state *state = gpiochip_get_data(chip);
577
577
unsigned long config;
578
578
579
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
579
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
580
580
581
581
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
582
582
}
···
605
605
struct pmic_mpp_state *state = gpiochip_get_data(chip);
606
606
unsigned long config;
607
607
608
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
608
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
609
609
610
610
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
611
611
}
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
···
282
282
return -EINVAL;
283
283
arg = 1;
284
284
break;
285
-
case PIN_CONFIG_OUTPUT:
285
+
case PIN_CONFIG_LEVEL:
286
286
if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
287
287
arg = pin->output_value;
288
288
else
···
364
364
pin->mode = PM8XXX_GPIO_MODE_INPUT;
365
365
banks |= BIT(0) | BIT(1);
366
366
break;
367
-
case PIN_CONFIG_OUTPUT:
367
+
case PIN_CONFIG_LEVEL:
368
368
pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
369
369
pin->output_value = !!arg;
370
370
banks |= BIT(0) | BIT(1);
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
···
337
337
case PIN_CONFIG_INPUT_ENABLE:
338
338
arg = pin->input;
339
339
break;
340
-
case PIN_CONFIG_OUTPUT:
340
+
case PIN_CONFIG_LEVEL:
341
341
arg = pin->output_value;
342
342
break;
343
343
case PIN_CONFIG_POWER_SOURCE:
···
392
392
case PIN_CONFIG_INPUT_ENABLE:
393
393
pin->input = true;
394
394
break;
395
-
case PIN_CONFIG_OUTPUT:
395
+
case PIN_CONFIG_LEVEL:
396
396
pin->output = true;
397
397
pin->output_value = !!arg;
398
398
break;
+1
-1
drivers/pinctrl/qcom/pinctrl-x1e80100.c
+1
-1
drivers/pinctrl/qcom/pinctrl-x1e80100.c
+13
drivers/pinctrl/renesas/Kconfig
+13
drivers/pinctrl/renesas/Kconfig
···
44
44
select PINCTRL_RZG2L if ARCH_R9A09G047
45
45
select PINCTRL_RZG2L if ARCH_R9A09G056
46
46
select PINCTRL_RZG2L if ARCH_R9A09G057
47
+
select PINCTRL_RZT2H if ARCH_R9A09G077
48
+
select PINCTRL_RZT2H if ARCH_R9A09G087
47
49
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
48
50
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
49
51
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
···
303
301
select PINMUX
304
302
help
305
303
This selects pinctrl driver for Renesas RZ/N1 devices.
304
+
305
+
config PINCTRL_RZT2H
306
+
bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST
307
+
depends on 64BIT && OF
308
+
select GPIOLIB
309
+
select GENERIC_PINCTRL_GROUPS
310
+
select GENERIC_PINMUX_FUNCTIONS
311
+
select GENERIC_PINCONF
312
+
help
313
+
This selects GPIO and pinctrl driver for Renesas RZ/T2H
314
+
platforms.
306
315
307
316
config PINCTRL_RZV2M
308
317
bool "pin control support for RZ/V2M" if COMPILE_TEST
+1
drivers/pinctrl/renesas/Makefile
+1
drivers/pinctrl/renesas/Makefile
···
50
50
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
51
51
obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o
52
52
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
53
+
obj-$(CONFIG_PINCTRL_RZT2H) += pinctrl-rzt2h.o
53
54
obj-$(CONFIG_PINCTRL_RZV2M) += pinctrl-rzv2m.o
54
55
55
56
ifeq ($(CONFIG_COMPILE_TEST),y)
+1
-1
drivers/pinctrl/renesas/pfc-r8a779g0.c
+1
-1
drivers/pinctrl/renesas/pfc-r8a779g0.c
+2
-2
drivers/pinctrl/renesas/pinctrl-rza1.c
+2
-2
drivers/pinctrl/renesas/pinctrl-rza1.c
···
933
933
case PIN_CONFIG_INPUT_ENABLE:
934
934
pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
935
935
break;
936
-
case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
936
+
case PIN_CONFIG_LEVEL: /* for DT backwards compatibility */
937
937
case PIN_CONFIG_OUTPUT_ENABLE:
938
938
pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
939
939
break;
···
1120
1120
{
1121
1121
struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1122
1122
struct rza1_mux_conf *mux_confs;
1123
-
struct function_desc *func;
1123
+
const struct function_desc *func;
1124
1124
struct group_desc *grp;
1125
1125
int i;
1126
1126
+1
-1
drivers/pinctrl/renesas/pinctrl-rza2.c
+1
-1
drivers/pinctrl/renesas/pinctrl-rza2.c
+113
-109
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+113
-109
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
146
146
#define SD_CH(off, ch) ((off) + (ch) * 4)
147
147
#define ETH_POC(off, ch) ((off) + (ch) * 4)
148
148
#define QSPI (0x3008)
149
-
#define ETH_MODE (0x3018)
150
-
#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
151
149
152
150
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
153
151
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
···
219
221
* @pwpr: PWPR register offset
220
222
* @sd_ch: SD_CH register offset
221
223
* @eth_poc: ETH_POC register offset
224
+
* @oen: OEN register offset
222
225
*/
223
226
struct rzg2l_register_offsets {
224
227
u16 pwpr;
225
228
u16 sd_ch;
226
229
u16 eth_poc;
230
+
u16 oen;
227
231
};
228
232
229
233
/**
···
254
254
* @iolh_groupb_oi: IOLH group B output impedance specific values
255
255
* @tint_start_index: the start index for the TINT interrupts
256
256
* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
257
+
* @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR
257
258
* @func_base: base number for port function (see register PFC)
258
259
* @oen_max_pin: the maximum pin number supporting output enable
259
260
* @oen_max_port: the maximum port number supporting output enable
···
267
266
u16 iolh_groupb_oi[4];
268
267
u16 tint_start_index;
269
268
bool drive_strength_ua;
269
+
bool oen_pwpr_lock;
270
270
u8 func_base;
271
271
u8 oen_max_pin;
272
272
u8 oen_max_port;
···
297
295
#endif
298
296
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
299
297
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
300
-
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
301
-
int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
298
+
int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
302
299
int (*hw_to_bias_param)(unsigned int val);
303
300
int (*bias_param_to_hw)(enum pin_config_param param);
304
301
};
···
321
320
* @iolh: IOLH registers cache
322
321
* @pupd: PUPD registers cache
323
322
* @ien: IEN registers cache
323
+
* @smt: SMT registers cache
324
324
* @sd_ch: SD_CH registers cache
325
325
* @eth_poc: ET_POC registers cache
326
-
* @eth_mode: ETH_MODE register cache
326
+
* @oen: Output Enable register cache
327
327
* @qspi: QSPI registers cache
328
328
*/
329
329
struct rzg2l_pinctrl_reg_cache {
···
335
333
u32 *iolh[2];
336
334
u32 *ien[2];
337
335
u32 *pupd[2];
336
+
u32 *smt;
338
337
u8 sd_ch[2];
339
338
u8 eth_poc[2];
340
-
u8 eth_mode;
339
+
u8 oen;
341
340
u8 qspi;
342
341
};
343
342
···
397
394
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
398
395
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
399
396
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
397
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS),
398
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
399
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS),
400
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS),
401
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS),
402
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS),
403
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS),
404
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS),
400
405
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
401
406
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
402
407
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
···
413
402
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
414
403
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
415
404
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
405
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS),
406
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
407
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS),
408
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS),
409
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS),
410
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS),
411
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS),
412
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS),
416
413
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
417
414
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
418
415
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
···
440
421
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
441
422
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
442
423
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
424
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
425
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
426
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
427
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS),
428
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
429
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS),
430
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS),
431
+
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS),
443
432
};
444
433
445
434
static const u64 r9a09g057_variable_pin_cfg[] = {
···
576
549
{
577
550
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
578
551
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
579
-
struct function_desc *func;
552
+
const struct function_desc *func;
580
553
unsigned int i, *psel_val;
581
554
struct group_desc *group;
582
555
const unsigned int *pins;
···
1092
1065
return -EINVAL;
1093
1066
}
1094
1067
1095
-
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1068
+
static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1096
1069
{
1097
1070
int bit;
1098
1071
1099
-
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1100
-
if (bit < 0)
1101
-
return 0;
1072
+
if (!pctrl->data->pin_to_oen_bit)
1073
+
return -EOPNOTSUPP;
1102
1074
1103
-
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1075
+
bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
1076
+
if (bit < 0)
1077
+
return -EINVAL;
1078
+
1079
+
return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
1104
1080
}
1105
1081
1106
1082
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1107
1083
{
1084
+
const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
1085
+
u16 oen_offset = pctrl->data->hwcfg->regs.oen;
1108
1086
unsigned long flags;
1087
+
u8 val, pwpr;
1109
1088
int bit;
1110
-
u8 val;
1111
1089
1112
-
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1090
+
if (!pctrl->data->pin_to_oen_bit)
1091
+
return -EOPNOTSUPP;
1092
+
1093
+
bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
1113
1094
if (bit < 0)
1114
-
return bit;
1095
+
return -EINVAL;
1115
1096
1116
1097
spin_lock_irqsave(&pctrl->lock, flags);
1117
-
val = readb(pctrl->base + ETH_MODE);
1098
+
val = readb(pctrl->base + oen_offset);
1118
1099
if (oen)
1119
1100
val &= ~BIT(bit);
1120
1101
else
1121
1102
val |= BIT(bit);
1122
-
writeb(val, pctrl->base + ETH_MODE);
1103
+
if (pctrl->data->hwcfg->oen_pwpr_lock) {
1104
+
pwpr = readb(pctrl->base + regs->pwpr);
1105
+
writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
1106
+
}
1107
+
writeb(val, pctrl->base + oen_offset);
1108
+
if (pctrl->data->hwcfg->oen_pwpr_lock)
1109
+
writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
1123
1110
spin_unlock_irqrestore(&pctrl->lock, flags);
1124
1111
1125
1112
return 0;
···
1157
1116
bit += 1;
1158
1117
1159
1118
return bit;
1160
-
}
1161
-
1162
-
static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1163
-
{
1164
-
int bit;
1165
-
1166
-
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1167
-
if (bit < 0)
1168
-
return bit;
1169
-
1170
-
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1171
-
}
1172
-
1173
-
static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1174
-
{
1175
-
unsigned long flags;
1176
-
int bit;
1177
-
u8 val;
1178
-
1179
-
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1180
-
if (bit < 0)
1181
-
return bit;
1182
-
1183
-
spin_lock_irqsave(&pctrl->lock, flags);
1184
-
val = readb(pctrl->base + ETH_MODE);
1185
-
if (oen)
1186
-
val &= ~BIT(bit);
1187
-
else
1188
-
val |= BIT(bit);
1189
-
writeb(val, pctrl->base + ETH_MODE);
1190
-
spin_unlock_irqrestore(&pctrl->lock, flags);
1191
-
1192
-
return 0;
1193
1119
}
1194
1120
1195
1121
static int rzg2l_hw_to_bias_param(unsigned int bias)
···
1224
1216
return -EINVAL;
1225
1217
}
1226
1218
1227
-
static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1219
+
static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin,
1220
+
const char * const pin_names[], unsigned int count)
1228
1221
{
1229
-
static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
1230
-
"XSPI0_RESET0N", "XSPI0_CS0N",
1231
-
"XSPI0_CKN", "XSPI0_CKP" };
1232
1222
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
1233
1223
unsigned int i;
1234
1224
1235
-
for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
1225
+
for (i = 0; i < count; i++) {
1236
1226
if (!strcmp(pin_desc->name, pin_names[i]))
1237
1227
return i;
1238
1228
}
1239
1229
1240
-
/* Should not happen. */
1241
-
return 0;
1230
+
return -EINVAL;
1242
1231
}
1243
1232
1244
-
static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1233
+
static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1245
1234
{
1246
-
u8 bit;
1235
+
static const char * const pin_names[] = {
1236
+
"ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N",
1237
+
"XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP"
1238
+
};
1247
1239
1248
-
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1249
-
1250
-
return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
1240
+
return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names));
1251
1241
}
1252
1242
1253
-
static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1243
+
static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1254
1244
{
1255
-
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1256
-
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1257
-
unsigned long flags;
1258
-
u8 val, bit;
1259
-
u8 pwpr;
1245
+
static const char * const pin_names[] = {
1246
+
"PB1", "PE1", "PL4", "PL1", "PL2", "PL0"
1247
+
};
1260
1248
1261
-
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1262
-
spin_lock_irqsave(&pctrl->lock, flags);
1263
-
val = readb(pctrl->base + PFC_OEN);
1264
-
if (oen)
1265
-
val &= ~BIT(bit);
1266
-
else
1267
-
val |= BIT(bit);
1268
-
1269
-
pwpr = readb(pctrl->base + regs->pwpr);
1270
-
writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
1271
-
writeb(val, pctrl->base + PFC_OEN);
1272
-
writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
1273
-
spin_unlock_irqrestore(&pctrl->lock, flags);
1274
-
1275
-
return 0;
1249
+
return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names));
1276
1250
}
1277
1251
1278
1252
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
···
1298
1308
case PIN_CONFIG_OUTPUT_ENABLE:
1299
1309
if (!(cfg & PIN_CFG_OEN))
1300
1310
return -EINVAL;
1301
-
if (!pctrl->data->oen_read)
1302
-
return -EOPNOTSUPP;
1303
-
arg = pctrl->data->oen_read(pctrl, _pin);
1304
-
if (!arg)
1305
-
return -EINVAL;
1311
+
ret = rzg2l_read_oen(pctrl, _pin);
1312
+
if (ret < 0)
1313
+
return ret;
1314
+
arg = ret;
1306
1315
break;
1307
1316
1308
1317
case PIN_CONFIG_POWER_SOURCE:
···
1460
1471
case PIN_CONFIG_OUTPUT_ENABLE:
1461
1472
if (!(cfg & PIN_CFG_OEN))
1462
1473
return -EINVAL;
1463
-
if (!pctrl->data->oen_write)
1464
-
return -EOPNOTSUPP;
1465
-
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
1474
+
ret = rzg2l_write_oen(pctrl, _pin, !!arg);
1466
1475
if (ret)
1467
1476
return ret;
1468
1477
break;
···
2045
2058
RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
2046
2059
0x0,
2047
2060
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
2048
-
RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
2061
+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */
2049
2062
RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
2050
2063
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
2051
-
RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
2064
+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */
2052
2065
RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
2053
2066
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
2054
2067
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
2055
2068
0x0,
2056
2069
RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
2057
2070
RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
2058
-
RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
2071
+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */
2059
2072
RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
2060
2073
0x0,
2061
2074
0x0,
···
2706
2719
if (!cache->pfc)
2707
2720
return -ENOMEM;
2708
2721
2722
+
cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL);
2723
+
if (!cache->smt)
2724
+
return -ENOMEM;
2725
+
2709
2726
for (u8 i = 0; i < 2; i++) {
2710
2727
u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
2711
2728
···
2971
2980
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2972
2981
2973
2982
for (u32 port = 0; port < nports; port++) {
2974
-
bool has_iolh, has_ien, has_pupd;
2983
+
bool has_iolh, has_ien, has_pupd, has_smt;
2975
2984
u32 off, caps;
2976
2985
u8 pincnt;
2977
2986
u64 cfg;
···
2984
2993
has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
2985
2994
has_ien = !!(caps & PIN_CFG_IEN);
2986
2995
has_pupd = !!(caps & PIN_CFG_PUPD);
2996
+
has_smt = !!(caps & PIN_CFG_SMT);
2987
2997
2988
2998
if (suspend)
2989
2999
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
···
3023
3031
cache->ien[1][port]);
3024
3032
}
3025
3033
}
3034
+
3035
+
if (has_smt)
3036
+
RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);
3026
3037
}
3027
3038
}
3028
3039
···
3159
3164
}
3160
3165
3161
3166
cache->qspi = readb(pctrl->base + QSPI);
3162
-
cache->eth_mode = readb(pctrl->base + ETH_MODE);
3167
+
cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
3163
3168
3164
3169
if (!atomic_read(&pctrl->wakeup_path))
3165
3170
clk_disable_unprepare(pctrl->clk);
···
3175
3180
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3176
3181
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3177
3182
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3183
+
unsigned long flags;
3184
+
u8 pwpr;
3178
3185
int ret;
3179
3186
3180
3187
if (!atomic_read(&pctrl->wakeup_path)) {
···
3186
3189
}
3187
3190
3188
3191
writeb(cache->qspi, pctrl->base + QSPI);
3189
-
writeb(cache->eth_mode, pctrl->base + ETH_MODE);
3192
+
if (pctrl->data->hwcfg->oen_pwpr_lock) {
3193
+
spin_lock_irqsave(&pctrl->lock, flags);
3194
+
pwpr = readb(pctrl->base + regs->pwpr);
3195
+
writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
3196
+
}
3197
+
writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
3198
+
if (pctrl->data->hwcfg->oen_pwpr_lock) {
3199
+
writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
3200
+
spin_unlock_irqrestore(&pctrl->lock, flags);
3201
+
}
3190
3202
for (u8 i = 0; i < 2; i++) {
3191
3203
if (regs->sd_ch)
3192
3204
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
···
3247
3241
.pwpr = 0x3014,
3248
3242
.sd_ch = 0x3000,
3249
3243
.eth_poc = 0x300c,
3244
+
.oen = 0x3018,
3250
3245
},
3251
3246
.iolh_groupa_ua = {
3252
3247
/* 3v3 power source */
···
3263
3256
.pwpr = 0x3000,
3264
3257
.sd_ch = 0x3004,
3265
3258
.eth_poc = 0x3010,
3259
+
.oen = 0x3018,
3266
3260
},
3267
3261
.iolh_groupa_ua = {
3268
3262
/* 1v8 power source */
···
3295
3287
static const struct rzg2l_hwcfg rzv2h_hwcfg = {
3296
3288
.regs = {
3297
3289
.pwpr = 0x3c04,
3290
+
.oen = 0x3c40,
3298
3291
},
3299
3292
.tint_start_index = 17,
3293
+
.oen_pwpr_lock = true,
3300
3294
};
3301
3295
3302
3296
static struct rzg2l_pinctrl_data r9a07g043_data = {
···
3315
3305
#endif
3316
3306
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3317
3307
.pmc_writeb = &rzg2l_pmc_writeb,
3318
-
.oen_read = &rzg2l_read_oen,
3319
-
.oen_write = &rzg2l_write_oen,
3308
+
.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
3320
3309
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
3321
3310
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
3322
3311
};
···
3331
3322
.hwcfg = &rzg2l_hwcfg,
3332
3323
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3333
3324
.pmc_writeb = &rzg2l_pmc_writeb,
3334
-
.oen_read = &rzg2l_read_oen,
3335
-
.oen_write = &rzg2l_write_oen,
3325
+
.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
3336
3326
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
3337
3327
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
3338
3328
};
···
3346
3338
.hwcfg = &rzg3s_hwcfg,
3347
3339
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3348
3340
.pmc_writeb = &rzg2l_pmc_writeb,
3349
-
.oen_read = &rzg3s_oen_read,
3350
-
.oen_write = &rzg3s_oen_write,
3341
+
.pin_to_oen_bit = &rzg3s_pin_to_oen_bit,
3351
3342
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
3352
3343
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
3353
3344
};
···
3368
3361
#endif
3369
3362
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3370
3363
.pmc_writeb = &rzv2h_pmc_writeb,
3371
-
.oen_read = &rzv2h_oen_read,
3372
-
.oen_write = &rzv2h_oen_write,
3364
+
.pin_to_oen_bit = &rzg3e_pin_to_oen_bit,
3373
3365
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
3374
3366
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
3375
3367
};
···
3390
3384
#endif
3391
3385
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3392
3386
.pmc_writeb = &rzv2h_pmc_writeb,
3393
-
.oen_read = &rzv2h_oen_read,
3394
-
.oen_write = &rzv2h_oen_write,
3387
+
.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
3395
3388
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
3396
3389
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
3397
3390
};
···
3413
3408
#endif
3414
3409
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3415
3410
.pmc_writeb = &rzv2h_pmc_writeb,
3416
-
.oen_read = &rzv2h_oen_read,
3417
-
.oen_write = &rzv2h_oen_write,
3411
+
.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
3418
3412
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
3419
3413
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
3420
3414
};
+813
drivers/pinctrl/renesas/pinctrl-rzt2h.c
+813
drivers/pinctrl/renesas/pinctrl-rzt2h.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Renesas RZ/T2H Pin Control and GPIO driver core
4
+
*
5
+
* Based on drivers/pinctrl/renesas/pinctrl-rzg2l.c
6
+
*
7
+
* Copyright (C) 2025 Renesas Electronics Corporation.
8
+
*/
9
+
10
+
#include <linux/bitfield.h>
11
+
#include <linux/bitops.h>
12
+
#include <linux/bits.h>
13
+
#include <linux/cleanup.h>
14
+
#include <linux/clk.h>
15
+
#include <linux/gpio/driver.h>
16
+
#include <linux/io.h>
17
+
#include <linux/ioport.h>
18
+
#include <linux/module.h>
19
+
#include <linux/mutex.h>
20
+
#include <linux/of_device.h>
21
+
#include <linux/platform_device.h>
22
+
#include <linux/pm_runtime.h>
23
+
#include <linux/spinlock.h>
24
+
#include <linux/types.h>
25
+
26
+
#include <linux/pinctrl/consumer.h>
27
+
#include <linux/pinctrl/pinconf-generic.h>
28
+
#include <linux/pinctrl/pinconf.h>
29
+
#include <linux/pinctrl/pinctrl.h>
30
+
#include <linux/pinctrl/pinmux.h>
31
+
32
+
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
33
+
34
+
#include "../core.h"
35
+
#include "../pinconf.h"
36
+
#include "../pinmux.h"
37
+
38
+
#define DRV_NAME "pinctrl-rzt2h"
39
+
40
+
#define P(m) (0x001 * (m))
41
+
#define PM(m) (0x200 + 2 * (m))
42
+
#define PMC(m) (0x400 + (m))
43
+
#define PFC(m) (0x600 + 8 * (m))
44
+
#define PIN(m) (0x800 + (m))
45
+
#define RSELP(m) (0xc00 + (m))
46
+
47
+
#define PM_MASK GENMASK(1, 0)
48
+
#define PM_PIN_MASK(pin) (PM_MASK << ((pin) * 2))
49
+
#define PM_INPUT BIT(0)
50
+
#define PM_OUTPUT BIT(1)
51
+
52
+
#define PFC_MASK GENMASK_ULL(5, 0)
53
+
#define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8))
54
+
55
+
/*
56
+
* Use 16 lower bits [15:0] for pin identifier
57
+
* Use 8 higher bits [23:16] for pin mux function
58
+
*/
59
+
#define MUX_PIN_ID_MASK GENMASK(15, 0)
60
+
#define MUX_FUNC_MASK GENMASK(23, 16)
61
+
62
+
#define RZT2H_PIN_ID_TO_PORT(id) ((id) / RZT2H_PINS_PER_PORT)
63
+
#define RZT2H_PIN_ID_TO_PIN(id) ((id) % RZT2H_PINS_PER_PORT)
64
+
65
+
#define RZT2H_MAX_SAFETY_PORTS 12
66
+
67
+
struct rzt2h_pinctrl_data {
68
+
unsigned int n_port_pins;
69
+
const u8 *port_pin_configs;
70
+
unsigned int n_ports;
71
+
};
72
+
73
+
struct rzt2h_pinctrl {
74
+
struct pinctrl_dev *pctl;
75
+
struct pinctrl_desc desc;
76
+
struct pinctrl_pin_desc *pins;
77
+
const struct rzt2h_pinctrl_data *data;
78
+
void __iomem *base0, *base1;
79
+
struct device *dev;
80
+
struct gpio_chip gpio_chip;
81
+
struct pinctrl_gpio_range gpio_range;
82
+
spinlock_t lock; /* lock read/write registers */
83
+
struct mutex mutex; /* serialize adding groups and functions */
84
+
bool safety_port_enabled;
85
+
};
86
+
87
+
#define RZT2H_GET_BASE(pctrl, port) \
88
+
((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1)
89
+
90
+
#define RZT2H_PINCTRL_REG_ACCESS(size, type) \
91
+
static inline void rzt2h_pinctrl_write##size(struct rzt2h_pinctrl *pctrl, u8 port, \
92
+
type val, unsigned int offset) \
93
+
{ \
94
+
write##size(val, RZT2H_GET_BASE(pctrl, port) + offset); \
95
+
} \
96
+
static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port, \
97
+
unsigned int offset) \
98
+
{ \
99
+
return read##size(RZT2H_GET_BASE(pctrl, port) + offset); \
100
+
}
101
+
102
+
RZT2H_PINCTRL_REG_ACCESS(b, u8)
103
+
RZT2H_PINCTRL_REG_ACCESS(w, u16)
104
+
RZT2H_PINCTRL_REG_ACCESS(q, u64)
105
+
106
+
static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
107
+
{
108
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
109
+
u8 pin = RZT2H_PIN_ID_TO_PIN(offset);
110
+
u8 pincfg;
111
+
112
+
if (offset >= pctrl->data->n_port_pins || port >= pctrl->data->n_ports)
113
+
return -EINVAL;
114
+
115
+
if (!pctrl->safety_port_enabled && port <= RZT2H_MAX_SAFETY_PORTS)
116
+
return -EINVAL;
117
+
118
+
pincfg = pctrl->data->port_pin_configs[port];
119
+
return (pincfg & BIT(pin)) ? 0 : -EINVAL;
120
+
}
121
+
122
+
static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
123
+
u8 port, u8 pin, u8 func)
124
+
{
125
+
u64 reg64;
126
+
u16 reg16;
127
+
128
+
guard(spinlock_irqsave)(&pctrl->lock);
129
+
130
+
/* Set pin to 'Non-use (Hi-Z input protection)' */
131
+
reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port));
132
+
reg16 &= ~PM_PIN_MASK(pin);
133
+
rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port));
134
+
135
+
/* Temporarily switch to GPIO mode with PMC register */
136
+
reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
137
+
rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port));
138
+
139
+
/* Select Pin function mode with PFC register */
140
+
reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
141
+
reg64 &= ~PFC_PIN_MASK(pin);
142
+
rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port));
143
+
144
+
/* Switch to Peripheral pin function with PMC register */
145
+
reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
146
+
rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port));
147
+
};
148
+
149
+
static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev,
150
+
unsigned int func_selector,
151
+
unsigned int group_selector)
152
+
{
153
+
struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
154
+
const struct function_desc *func;
155
+
struct group_desc *group;
156
+
const unsigned int *pins;
157
+
unsigned int i;
158
+
u8 *psel_val;
159
+
int ret;
160
+
161
+
func = pinmux_generic_get_function(pctldev, func_selector);
162
+
if (!func)
163
+
return -EINVAL;
164
+
165
+
group = pinctrl_generic_get_group(pctldev, group_selector);
166
+
if (!group)
167
+
return -EINVAL;
168
+
169
+
psel_val = func->data;
170
+
pins = group->grp.pins;
171
+
172
+
for (i = 0; i < group->grp.npins; i++) {
173
+
dev_dbg(pctrl->dev, "port:%u pin:%u PSEL:%u\n",
174
+
RZT2H_PIN_ID_TO_PORT(pins[i]), RZT2H_PIN_ID_TO_PIN(pins[i]),
175
+
psel_val[i]);
176
+
ret = rzt2h_validate_pin(pctrl, pins[i]);
177
+
if (ret)
178
+
return ret;
179
+
180
+
rzt2h_pinctrl_set_pfc_mode(pctrl, RZT2H_PIN_ID_TO_PORT(pins[i]),
181
+
RZT2H_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
182
+
}
183
+
184
+
return 0;
185
+
};
186
+
187
+
static int rzt2h_map_add_config(struct pinctrl_map *map,
188
+
const char *group_or_pin,
189
+
enum pinctrl_map_type type,
190
+
unsigned long *configs,
191
+
unsigned int num_configs)
192
+
{
193
+
unsigned long *cfgs;
194
+
195
+
cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
196
+
if (!cfgs)
197
+
return -ENOMEM;
198
+
199
+
map->type = type;
200
+
map->data.configs.group_or_pin = group_or_pin;
201
+
map->data.configs.configs = cfgs;
202
+
map->data.configs.num_configs = num_configs;
203
+
204
+
return 0;
205
+
}
206
+
207
+
static int rzt2h_dt_subnode_to_map(struct pinctrl_dev *pctldev,
208
+
struct device_node *np,
209
+
struct device_node *parent,
210
+
struct pinctrl_map **map,
211
+
unsigned int *num_maps,
212
+
unsigned int *index)
213
+
{
214
+
struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
215
+
struct pinctrl_map *maps = *map;
216
+
unsigned int nmaps = *num_maps;
217
+
unsigned long *configs = NULL;
218
+
unsigned int num_pinmux = 0;
219
+
unsigned int idx = *index;
220
+
unsigned int num_pins, i;
221
+
unsigned int num_configs;
222
+
struct property *pinmux;
223
+
struct property *prop;
224
+
int ret, gsel, fsel;
225
+
const char **pin_fn;
226
+
unsigned int *pins;
227
+
const char *name;
228
+
const char *pin;
229
+
u8 *psel_val;
230
+
231
+
pinmux = of_find_property(np, "pinmux", NULL);
232
+
if (pinmux)
233
+
num_pinmux = pinmux->length / sizeof(u32);
234
+
235
+
ret = of_property_count_strings(np, "pins");
236
+
if (ret == -EINVAL) {
237
+
num_pins = 0;
238
+
} else if (ret < 0) {
239
+
dev_err(pctrl->dev, "Invalid pins list in DT\n");
240
+
return ret;
241
+
} else {
242
+
num_pins = ret;
243
+
}
244
+
245
+
if (!num_pinmux && !num_pins)
246
+
return 0;
247
+
248
+
if (num_pinmux && num_pins) {
249
+
dev_err(pctrl->dev,
250
+
"DT node must contain either a pinmux or pins and not both\n");
251
+
return -EINVAL;
252
+
}
253
+
254
+
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
255
+
if (ret < 0)
256
+
return ret;
257
+
258
+
if (num_pins && !num_configs) {
259
+
dev_err(pctrl->dev, "DT node must contain a config\n");
260
+
ret = -ENODEV;
261
+
goto done;
262
+
}
263
+
264
+
if (num_pinmux) {
265
+
nmaps += 1;
266
+
if (num_configs)
267
+
nmaps += 1;
268
+
}
269
+
270
+
if (num_pins)
271
+
nmaps += num_pins;
272
+
273
+
maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
274
+
if (!maps) {
275
+
ret = -ENOMEM;
276
+
goto done;
277
+
}
278
+
279
+
*map = maps;
280
+
*num_maps = nmaps;
281
+
if (num_pins) {
282
+
of_property_for_each_string(np, "pins", prop, pin) {
283
+
ret = rzt2h_map_add_config(&maps[idx], pin,
284
+
PIN_MAP_TYPE_CONFIGS_PIN,
285
+
configs, num_configs);
286
+
if (ret < 0)
287
+
goto done;
288
+
289
+
idx++;
290
+
}
291
+
ret = 0;
292
+
goto done;
293
+
}
294
+
295
+
pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
296
+
psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
297
+
GFP_KERNEL);
298
+
pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
299
+
if (!pins || !psel_val || !pin_fn) {
300
+
ret = -ENOMEM;
301
+
goto done;
302
+
}
303
+
304
+
/* Collect pin locations and mux settings from DT properties */
305
+
for (i = 0; i < num_pinmux; ++i) {
306
+
u32 value;
307
+
308
+
ret = of_property_read_u32_index(np, "pinmux", i, &value);
309
+
if (ret)
310
+
goto done;
311
+
pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
312
+
psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
313
+
}
314
+
315
+
if (parent) {
316
+
name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
317
+
parent, np);
318
+
if (!name) {
319
+
ret = -ENOMEM;
320
+
goto done;
321
+
}
322
+
} else {
323
+
name = np->name;
324
+
}
325
+
326
+
if (num_configs) {
327
+
ret = rzt2h_map_add_config(&maps[idx], name,
328
+
PIN_MAP_TYPE_CONFIGS_GROUP,
329
+
configs, num_configs);
330
+
if (ret < 0)
331
+
goto done;
332
+
333
+
idx++;
334
+
}
335
+
336
+
scoped_guard(mutex, &pctrl->mutex) {
337
+
/* Register a single pin group listing all the pins we read from DT */
338
+
gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
339
+
if (gsel < 0) {
340
+
ret = gsel;
341
+
goto done;
342
+
}
343
+
344
+
/*
345
+
* Register a single group function where the 'data' is an array PSEL
346
+
* register values read from DT.
347
+
*/
348
+
pin_fn[0] = name;
349
+
fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
350
+
if (fsel < 0) {
351
+
ret = fsel;
352
+
goto remove_group;
353
+
}
354
+
}
355
+
356
+
maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
357
+
maps[idx].data.mux.group = name;
358
+
maps[idx].data.mux.function = name;
359
+
idx++;
360
+
361
+
dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
362
+
ret = 0;
363
+
goto done;
364
+
365
+
remove_group:
366
+
pinctrl_generic_remove_group(pctldev, gsel);
367
+
done:
368
+
*index = idx;
369
+
kfree(configs);
370
+
return ret;
371
+
}
372
+
373
+
static void rzt2h_dt_free_map(struct pinctrl_dev *pctldev,
374
+
struct pinctrl_map *map,
375
+
unsigned int num_maps)
376
+
{
377
+
unsigned int i;
378
+
379
+
if (!map)
380
+
return;
381
+
382
+
for (i = 0; i < num_maps; ++i) {
383
+
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
384
+
map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
385
+
kfree(map[i].data.configs.configs);
386
+
}
387
+
kfree(map);
388
+
}
389
+
390
+
static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev,
391
+
struct device_node *np,
392
+
struct pinctrl_map **map,
393
+
unsigned int *num_maps)
394
+
{
395
+
struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
396
+
unsigned int index;
397
+
int ret;
398
+
399
+
*map = NULL;
400
+
*num_maps = 0;
401
+
index = 0;
402
+
403
+
for_each_child_of_node_scoped(np, child) {
404
+
ret = rzt2h_dt_subnode_to_map(pctldev, child, np, map,
405
+
num_maps, &index);
406
+
if (ret < 0)
407
+
goto done;
408
+
}
409
+
410
+
if (*num_maps == 0) {
411
+
ret = rzt2h_dt_subnode_to_map(pctldev, np, NULL, map,
412
+
num_maps, &index);
413
+
if (ret < 0)
414
+
goto done;
415
+
}
416
+
417
+
if (*num_maps)
418
+
return 0;
419
+
420
+
dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
421
+
ret = -EINVAL;
422
+
423
+
done:
424
+
rzt2h_dt_free_map(pctldev, *map, *num_maps);
425
+
return ret;
426
+
}
427
+
428
+
static const struct pinctrl_ops rzt2h_pinctrl_pctlops = {
429
+
.get_groups_count = pinctrl_generic_get_group_count,
430
+
.get_group_name = pinctrl_generic_get_group_name,
431
+
.get_group_pins = pinctrl_generic_get_group_pins,
432
+
.dt_node_to_map = rzt2h_dt_node_to_map,
433
+
.dt_free_map = rzt2h_dt_free_map,
434
+
};
435
+
436
+
static const struct pinmux_ops rzt2h_pinctrl_pmxops = {
437
+
.get_functions_count = pinmux_generic_get_function_count,
438
+
.get_function_name = pinmux_generic_get_function_name,
439
+
.get_function_groups = pinmux_generic_get_function_groups,
440
+
.set_mux = rzt2h_pinctrl_set_mux,
441
+
.strict = true,
442
+
};
443
+
444
+
static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
445
+
{
446
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
447
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
448
+
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
449
+
int ret;
450
+
u8 reg;
451
+
452
+
ret = rzt2h_validate_pin(pctrl, offset);
453
+
if (ret)
454
+
return ret;
455
+
456
+
ret = pinctrl_gpio_request(chip, offset);
457
+
if (ret)
458
+
return ret;
459
+
460
+
guard(spinlock_irqsave)(&pctrl->lock);
461
+
462
+
/* Select GPIO mode in PMC Register */
463
+
reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
464
+
reg &= ~BIT(bit);
465
+
rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
466
+
467
+
return 0;
468
+
}
469
+
470
+
static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port,
471
+
u8 bit, bool output)
472
+
{
473
+
u16 reg;
474
+
475
+
guard(spinlock_irqsave)(&pctrl->lock);
476
+
477
+
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
478
+
reg &= ~PM_PIN_MASK(bit);
479
+
480
+
reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
481
+
rzt2h_pinctrl_writew(pctrl, port, reg, PM(port));
482
+
}
483
+
484
+
static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
485
+
{
486
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
487
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
488
+
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
489
+
u16 reg;
490
+
int ret;
491
+
492
+
ret = rzt2h_validate_pin(pctrl, offset);
493
+
if (ret)
494
+
return ret;
495
+
496
+
if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit))
497
+
return -EINVAL;
498
+
499
+
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
500
+
reg = (reg >> (bit * 2)) & PM_MASK;
501
+
if (reg & PM_OUTPUT)
502
+
return GPIO_LINE_DIRECTION_OUT;
503
+
if (reg & PM_INPUT)
504
+
return GPIO_LINE_DIRECTION_IN;
505
+
506
+
return -EINVAL;
507
+
}
508
+
509
+
static int rzt2h_gpio_set(struct gpio_chip *chip, unsigned int offset,
510
+
int value)
511
+
{
512
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
513
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
514
+
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
515
+
u8 reg;
516
+
517
+
guard(spinlock_irqsave)(&pctrl->lock);
518
+
519
+
reg = rzt2h_pinctrl_readb(pctrl, port, P(port));
520
+
if (value)
521
+
rzt2h_pinctrl_writeb(pctrl, port, reg | BIT(bit), P(port));
522
+
else
523
+
rzt2h_pinctrl_writeb(pctrl, port, reg & ~BIT(bit), P(port));
524
+
525
+
return 0;
526
+
}
527
+
528
+
static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset)
529
+
{
530
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
531
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
532
+
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
533
+
u16 reg;
534
+
535
+
reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
536
+
reg = (reg >> (bit * 2)) & PM_MASK;
537
+
if (reg & PM_INPUT)
538
+
return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit));
539
+
if (reg & PM_OUTPUT)
540
+
return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit));
541
+
542
+
return -EINVAL;
543
+
}
544
+
545
+
static int rzt2h_gpio_direction_input(struct gpio_chip *chip,
546
+
unsigned int offset)
547
+
{
548
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
549
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
550
+
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
551
+
552
+
rzt2h_gpio_set_direction(pctrl, port, bit, false);
553
+
554
+
return 0;
555
+
}
556
+
557
+
static int rzt2h_gpio_direction_output(struct gpio_chip *chip,
558
+
unsigned int offset, int value)
559
+
{
560
+
struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
561
+
u8 port = RZT2H_PIN_ID_TO_PORT(offset);
562
+
u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
563
+
564
+
rzt2h_gpio_set(chip, offset, value);
565
+
rzt2h_gpio_set_direction(pctrl, port, bit, true);
566
+
567
+
return 0;
568
+
}
569
+
570
+
static void rzt2h_gpio_free(struct gpio_chip *chip, unsigned int offset)
571
+
{
572
+
pinctrl_gpio_free(chip, offset);
573
+
574
+
/*
575
+
* Set the GPIO as an input to ensure that the next GPIO request won't
576
+
* drive the GPIO pin as an output.
577
+
*/
578
+
rzt2h_gpio_direction_input(chip, offset);
579
+
}
580
+
581
+
static const char * const rzt2h_gpio_names[] = {
582
+
"P00_0", "P00_1", "P00_2", "P00_3", "P00_4", "P00_5", "P00_6", "P00_7",
583
+
"P01_0", "P01_1", "P01_2", "P01_3", "P01_4", "P01_5", "P01_6", "P01_7",
584
+
"P02_0", "P02_1", "P02_2", "P02_3", "P02_4", "P02_5", "P02_6", "P02_7",
585
+
"P03_0", "P03_1", "P03_2", "P03_3", "P03_4", "P03_5", "P03_6", "P03_7",
586
+
"P04_0", "P04_1", "P04_2", "P04_3", "P04_4", "P04_5", "P04_6", "P04_7",
587
+
"P05_0", "P05_1", "P05_2", "P05_3", "P05_4", "P05_5", "P05_6", "P05_7",
588
+
"P06_0", "P06_1", "P06_2", "P06_3", "P06_4", "P06_5", "P06_6", "P06_7",
589
+
"P07_0", "P07_1", "P07_2", "P07_3", "P07_4", "P07_5", "P07_6", "P07_7",
590
+
"P08_0", "P08_1", "P08_2", "P08_3", "P08_4", "P08_5", "P08_6", "P08_7",
591
+
"P09_0", "P09_1", "P09_2", "P09_3", "P09_4", "P09_5", "P09_6", "P09_7",
592
+
"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
593
+
"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
594
+
"P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
595
+
"P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
596
+
"P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
597
+
"P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
598
+
"P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
599
+
"P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
600
+
"P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
601
+
"P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
602
+
"P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
603
+
"P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
604
+
"P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
605
+
"P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
606
+
"P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
607
+
"P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
608
+
"P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
609
+
"P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
610
+
"P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
611
+
"P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
612
+
"P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
613
+
"P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
614
+
"P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
615
+
"P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
616
+
"P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
617
+
"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
618
+
};
619
+
620
+
static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
621
+
{
622
+
struct pinctrl_gpio_range *range = &pctrl->gpio_range;
623
+
struct gpio_chip *chip = &pctrl->gpio_chip;
624
+
struct device *dev = pctrl->dev;
625
+
struct of_phandle_args of_args;
626
+
int ret;
627
+
628
+
ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args);
629
+
if (ret)
630
+
return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n");
631
+
632
+
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
633
+
of_args.args[2] != pctrl->data->n_port_pins)
634
+
return dev_err_probe(dev, -EINVAL,
635
+
"gpio-ranges does not match selected SOC\n");
636
+
637
+
chip->base = -1;
638
+
chip->parent = dev;
639
+
chip->owner = THIS_MODULE;
640
+
chip->ngpio = of_args.args[2];
641
+
chip->names = rzt2h_gpio_names;
642
+
chip->request = rzt2h_gpio_request;
643
+
chip->free = rzt2h_gpio_free;
644
+
chip->get_direction = rzt2h_gpio_get_direction;
645
+
chip->direction_input = rzt2h_gpio_direction_input;
646
+
chip->direction_output = rzt2h_gpio_direction_output;
647
+
chip->get = rzt2h_gpio_get;
648
+
chip->set = rzt2h_gpio_set;
649
+
chip->label = dev_name(dev);
650
+
651
+
range->id = 0;
652
+
range->pin_base = 0;
653
+
range->base = 0;
654
+
range->npins = chip->ngpio;
655
+
range->name = chip->label;
656
+
range->gc = chip;
657
+
658
+
ret = devm_gpiochip_add_data(dev, chip, pctrl);
659
+
if (ret)
660
+
return dev_err_probe(dev, ret, "gpiochip registration failed\n");
661
+
662
+
return ret;
663
+
}
664
+
665
+
static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl)
666
+
{
667
+
struct pinctrl_desc *desc = &pctrl->desc;
668
+
struct device *dev = pctrl->dev;
669
+
struct pinctrl_pin_desc *pins;
670
+
unsigned int i, j;
671
+
int ret;
672
+
673
+
desc->name = DRV_NAME;
674
+
desc->npins = pctrl->data->n_port_pins;
675
+
desc->pctlops = &rzt2h_pinctrl_pctlops;
676
+
desc->pmxops = &rzt2h_pinctrl_pmxops;
677
+
desc->owner = THIS_MODULE;
678
+
679
+
pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);
680
+
if (!pins)
681
+
return -ENOMEM;
682
+
683
+
pctrl->pins = pins;
684
+
desc->pins = pins;
685
+
686
+
for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
687
+
pins[i].number = i;
688
+
pins[i].name = rzt2h_gpio_names[i];
689
+
if (i && !(i % RZT2H_PINS_PER_PORT))
690
+
j++;
691
+
}
692
+
693
+
ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl);
694
+
if (ret)
695
+
return dev_err_probe(dev, ret, "pinctrl registration failed\n");
696
+
697
+
ret = pinctrl_enable(pctrl->pctl);
698
+
if (ret)
699
+
return dev_err_probe(dev, ret, "pinctrl enable failed\n");
700
+
701
+
return rzt2h_gpio_register(pctrl);
702
+
}
703
+
704
+
static int rzt2h_pinctrl_cfg_regions(struct platform_device *pdev,
705
+
struct rzt2h_pinctrl *pctrl)
706
+
{
707
+
struct resource *res;
708
+
709
+
pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr");
710
+
if (IS_ERR(pctrl->base0))
711
+
return PTR_ERR(pctrl->base0);
712
+
713
+
/*
714
+
* Open-coded instead of using devm_platform_ioremap_resource_byname()
715
+
* because the "srs" region is optional.
716
+
*/
717
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "srs");
718
+
if (res) {
719
+
u8 port;
720
+
721
+
pctrl->base1 = devm_ioremap_resource(&pdev->dev, res);
722
+
if (IS_ERR(pctrl->base1))
723
+
return PTR_ERR(pctrl->base1);
724
+
725
+
pctrl->safety_port_enabled = true;
726
+
727
+
/* Configure to select safety region 0x812c0xxx */
728
+
for (port = 0; port <= RZT2H_MAX_SAFETY_PORTS; port++)
729
+
writeb(0x0, pctrl->base1 + RSELP(port));
730
+
}
731
+
732
+
return 0;
733
+
}
734
+
735
+
static int rzt2h_pinctrl_probe(struct platform_device *pdev)
736
+
{
737
+
struct device *dev = &pdev->dev;
738
+
struct rzt2h_pinctrl *pctrl;
739
+
int ret;
740
+
741
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
742
+
if (!pctrl)
743
+
return -ENOMEM;
744
+
745
+
pctrl->dev = dev;
746
+
pctrl->data = of_device_get_match_data(dev);
747
+
748
+
ret = rzt2h_pinctrl_cfg_regions(pdev, pctrl);
749
+
if (ret)
750
+
return ret;
751
+
752
+
spin_lock_init(&pctrl->lock);
753
+
mutex_init(&pctrl->mutex);
754
+
platform_set_drvdata(pdev, pctrl);
755
+
756
+
return rzt2h_pinctrl_register(pctrl);
757
+
}
758
+
759
+
static const u8 r9a09g077_gpio_configs[] = {
760
+
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
761
+
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
762
+
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
763
+
};
764
+
765
+
static const u8 r9a09g087_gpio_configs[] = {
766
+
0x1f, 0xff, 0xff, 0x1f, 0x00, 0xfe, 0xff, 0x00, 0x7e, 0xf0, 0xff, 0x01,
767
+
0xff, 0xff, 0xff, 0x00, 0xe0, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x01,
768
+
0xe0, 0xff, 0xff, 0x7f, 0x00, 0xfe, 0xff, 0x7f, 0x00, 0xfc, 0x7f,
769
+
};
770
+
771
+
static struct rzt2h_pinctrl_data r9a09g077_data = {
772
+
.n_port_pins = ARRAY_SIZE(r9a09g077_gpio_configs) * RZT2H_PINS_PER_PORT,
773
+
.port_pin_configs = r9a09g077_gpio_configs,
774
+
.n_ports = ARRAY_SIZE(r9a09g077_gpio_configs),
775
+
};
776
+
777
+
static struct rzt2h_pinctrl_data r9a09g087_data = {
778
+
.n_port_pins = ARRAY_SIZE(r9a09g087_gpio_configs) * RZT2H_PINS_PER_PORT,
779
+
.port_pin_configs = r9a09g087_gpio_configs,
780
+
.n_ports = ARRAY_SIZE(r9a09g087_gpio_configs),
781
+
};
782
+
783
+
static const struct of_device_id rzt2h_pinctrl_of_table[] = {
784
+
{
785
+
.compatible = "renesas,r9a09g077-pinctrl",
786
+
.data = &r9a09g077_data,
787
+
},
788
+
{
789
+
.compatible = "renesas,r9a09g087-pinctrl",
790
+
.data = &r9a09g087_data,
791
+
},
792
+
{ /* sentinel */ }
793
+
};
794
+
795
+
static struct platform_driver rzt2h_pinctrl_driver = {
796
+
.driver = {
797
+
.name = DRV_NAME,
798
+
.of_match_table = of_match_ptr(rzt2h_pinctrl_of_table),
799
+
.suppress_bind_attrs = true,
800
+
},
801
+
.probe = rzt2h_pinctrl_probe,
802
+
};
803
+
804
+
static int __init rzt2h_pinctrl_init(void)
805
+
{
806
+
return platform_driver_register(&rzt2h_pinctrl_driver);
807
+
}
808
+
core_initcall(rzt2h_pinctrl_init);
809
+
810
+
MODULE_LICENSE("GPL");
811
+
MODULE_AUTHOR("Thierry Bultel <thierry.bultel.yh@bp.renesas.com>");
812
+
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
813
+
MODULE_DESCRIPTION("Pin and gpio controller driver for the RZ/T2H family");
+1
-1
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+1
-1
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+2
-1
drivers/pinctrl/renesas/pinctrl.c
+2
-1
drivers/pinctrl/renesas/pinctrl.c
···
726
726
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
727
727
const unsigned int *pins;
728
728
unsigned int num_pins;
729
-
unsigned int i, ret;
729
+
unsigned int i;
730
+
int ret;
730
731
731
732
pins = pmx->pfc->info->groups[group].pins;
732
733
num_pins = pmx->pfc->info->groups[group].nr_pins;
+50
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+50
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
···
76
76
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
77
77
};
78
78
79
+
/*
80
+
* Bank type for non-alive type. Bit fields:
81
+
* CON: 4, DAT: 1, PUD: 4, DRV: 4
82
+
*/
83
+
static const struct samsung_pin_bank_type artpec_bank_type_off = {
84
+
.fld_width = { 4, 1, 4, 4, },
85
+
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
86
+
};
87
+
79
88
/* Pad retention control code for accessing PMU regmap */
80
89
static atomic_t exynos_shared_retention_refcnt;
81
90
···
1824
1815
const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
1825
1816
.ctrl = gs101_pin_ctrl,
1826
1817
.num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
1818
+
};
1819
+
1820
+
/* pin banks of artpec8 pin-controller (FSYS0) */
1821
+
static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = {
1822
+
ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00),
1823
+
ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04),
1824
+
ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08),
1825
+
ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c),
1826
+
ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10),
1827
+
ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14),
1828
+
ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18),
1829
+
ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c),
1830
+
ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20),
1831
+
ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24),
1832
+
};
1833
+
1834
+
/* pin banks of artpec8 pin-controller (PERIC) */
1835
+
static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = {
1836
+
ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1837
+
ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
1838
+
ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1839
+
ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c),
1840
+
};
1841
+
1842
+
static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = {
1843
+
{
1844
+
/* pin-controller instance 0 FSYS data */
1845
+
.pin_banks = artpec8_pin_banks0,
1846
+
.nr_banks = ARRAY_SIZE(artpec8_pin_banks0),
1847
+
.eint_gpio_init = exynos_eint_gpio_init,
1848
+
}, {
1849
+
/* pin-controller instance 1 PERIC data */
1850
+
.pin_banks = artpec8_pin_banks1,
1851
+
.nr_banks = ARRAY_SIZE(artpec8_pin_banks1),
1852
+
.eint_gpio_init = exynos_eint_gpio_init,
1853
+
},
1854
+
};
1855
+
1856
+
const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
1857
+
.ctrl = artpec8_pin_ctrl,
1858
+
.num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl),
1827
1859
};
+10
drivers/pinctrl/samsung/pinctrl-exynos.h
+10
drivers/pinctrl/samsung/pinctrl-exynos.h
···
236
236
.name = id \
237
237
}
238
238
239
+
#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \
240
+
{ \
241
+
.type = &artpec_bank_type_off, \
242
+
.pctl_offset = reg, \
243
+
.nr_pins = pins, \
244
+
.eint_type = EINT_TYPE_GPIO, \
245
+
.eint_offset = offs, \
246
+
.name = id \
247
+
}
248
+
239
249
/**
240
250
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
241
251
* generated by the external wakeup interrupt controller.
+2
drivers/pinctrl/samsung/pinctrl-samsung.c
+2
drivers/pinctrl/samsung/pinctrl-samsung.c
···
1482
1482
.data = &s5pv210_of_data },
1483
1483
#endif
1484
1484
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
1485
+
{ .compatible = "axis,artpec8-pinctrl",
1486
+
.data = &artpec8_of_data },
1485
1487
{ .compatible = "google,gs101-pinctrl",
1486
1488
.data = &gs101_of_data },
1487
1489
{ .compatible = "samsung,exynos2200-pinctrl",
+1
-4
drivers/pinctrl/samsung/pinctrl-samsung.h
+1
-4
drivers/pinctrl/samsung/pinctrl-samsung.h
···
381
381
};
382
382
383
383
/* list of all exported SoC specific data */
384
+
extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
384
385
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
385
386
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
386
387
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
···
403
402
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
404
403
extern const struct samsung_pinctrl_of_match_data gs101_of_data;
405
404
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
406
-
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
407
-
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
408
-
extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;
409
-
extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;
410
405
extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
411
406
412
407
#endif /* __PINCTRL_SAMSUNG_H */
+2
-2
drivers/pinctrl/spacemit/pinctrl-k1.c
+2
-2
drivers/pinctrl/spacemit/pinctrl-k1.c
···
707
707
spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp),
708
708
spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp));
709
709
710
-
seq_printf(seq, ", register (0x%04x)\n", value);
710
+
seq_printf(seq, ", register (0x%04x)", value);
711
711
}
712
712
713
713
static const struct pinconf_ops spacemit_pinconf_ops = {
···
847
847
PINCTRL_PIN(67, "GPIO_67"),
848
848
PINCTRL_PIN(68, "GPIO_68"),
849
849
PINCTRL_PIN(69, "GPIO_69"),
850
-
PINCTRL_PIN(70, "GPIO_70/PRI_DTI"),
850
+
PINCTRL_PIN(70, "GPIO_70/PRI_TDI"),
851
851
PINCTRL_PIN(71, "GPIO_71/PRI_TMS"),
852
852
PINCTRL_PIN(72, "GPIO_72/PRI_TCK"),
853
853
PINCTRL_PIN(73, "GPIO_73/PRI_TDO"),
+3
-6
drivers/pinctrl/sprd/pinctrl-sprd.c
+3
-6
drivers/pinctrl/sprd/pinctrl-sprd.c
···
258
258
259
259
grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
260
260
if (!grp) {
261
-
dev_err(pctl->dev, "unable to find group for node %s\n",
262
-
of_node_full_name(np));
261
+
dev_err(pctl->dev, "unable to find group for node %pOF\n", np);
263
262
return -EINVAL;
264
263
}
265
264
···
275
276
if (ret < 0) {
276
277
if (ret != -EINVAL)
277
278
dev_err(pctl->dev,
278
-
"%s: could not parse property function\n",
279
-
of_node_full_name(np));
279
+
"%pOF: could not parse property function\n", np);
280
280
function = NULL;
281
281
}
282
282
283
283
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
284
284
&num_configs);
285
285
if (ret < 0) {
286
-
dev_err(pctl->dev, "%s: could not parse node property\n",
287
-
of_node_full_name(np));
286
+
dev_err(pctl->dev, "%pOF: could not parse node property\n", np);
288
287
return ret;
289
288
}
290
289
+2
-2
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
+2
-2
drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
···
576
576
.gpio_set_direction = NULL,
577
577
};
578
578
579
-
static struct pinctrl_desc stm32_hdp_pdesc = {
579
+
static const struct pinctrl_desc stm32_hdp_pdesc = {
580
580
.name = DRIVER_NAME,
581
581
.pins = stm32_hdp_pins,
582
582
.npins = ARRAY_SIZE(stm32_hdp_pins),
···
642
642
hdp->gpio_chip.gc.can_sleep = true;
643
643
hdp->gpio_chip.gc.names = stm32_hdp_pins_group;
644
644
645
-
config = (typeof(config)){
645
+
config = (struct gpio_generic_chip_config) {
646
646
.dev = dev,
647
647
.sz = 4,
648
648
.dat = hdp->base + HDP_GPOVAL,
+1
-1
drivers/pinctrl/stm32/pinctrl-stm32.c
+1
-1
drivers/pinctrl/stm32/pinctrl-stm32.c
···
1236
1236
case PIN_CONFIG_BIAS_PULL_DOWN:
1237
1237
ret = stm32_pconf_set_bias(bank, offset, 2);
1238
1238
break;
1239
-
case PIN_CONFIG_OUTPUT:
1239
+
case PIN_CONFIG_LEVEL:
1240
1240
__stm32_gpio_set(bank, offset, arg);
1241
1241
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1242
1242
break;
+2
-2
drivers/pinctrl/sunplus/sppctl.c
+2
-2
drivers/pinctrl/sunplus/sppctl.c
···
488
488
case PIN_CONFIG_INPUT_ENABLE:
489
489
break;
490
490
491
-
case PIN_CONFIG_OUTPUT:
491
+
case PIN_CONFIG_LEVEL:
492
492
return sppctl_gpio_direction_output(chip, offset, 0);
493
493
494
494
case PIN_CONFIG_PERSIST_STATE:
···
580
580
arg = 0;
581
581
break;
582
582
583
-
case PIN_CONFIG_OUTPUT:
583
+
case PIN_CONFIG_LEVEL:
584
584
if (!sppctl_first_get(&pctl->spp_gchip->chip, pin))
585
585
return -EINVAL;
586
586
if (!sppctl_master_get(&pctl->spp_gchip->chip, pin))
+5
-6
drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
+5
-6
drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c
···
103
103
return ERR_PTR(-EINVAL);
104
104
}
105
105
106
-
pins = devm_kzalloc(dev, desc->npins * sizeof(*pins), GFP_KERNEL);
106
+
pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);
107
107
if (!pins)
108
108
return ERR_PTR(-ENOMEM);
109
109
···
199
199
* Allocate the memory needed for the functions in one table.
200
200
* We later use pointers into this table to mark each pin.
201
201
*/
202
-
func = devm_kzalloc(dev, num_funcs * sizeof(*func), GFP_KERNEL);
202
+
func = devm_kcalloc(dev, num_funcs, sizeof(*func), GFP_KERNEL);
203
203
if (!func)
204
204
return -ENOMEM;
205
205
···
274
274
if (!strcmp(pins[pin].pin.name, name))
275
275
break;
276
276
if (pin == npins) {
277
-
dev_warn(dev, "%s: cannot find pin %s\n",
278
-
of_node_full_name(node), name);
277
+
dev_warn(dev, "%pOF: cannot find pin %s\n", node, name);
279
278
index++;
280
279
continue;
281
280
}
···
282
283
/* Read the associated mux value. */
283
284
muxval = sunxi_pinctrl_dt_read_pinmux(node, index);
284
285
if (muxval == INVALID_MUX) {
285
-
dev_warn(dev, "%s: invalid mux value for pin %s\n",
286
-
of_node_full_name(node), name);
286
+
dev_warn(dev, "%pOF: invalid mux value for pin %s\n",
287
+
node, name);
287
288
index++;
288
289
continue;
289
290
}
+4
drivers/pinctrl/tegra/Kconfig
+4
drivers/pinctrl/tegra/Kconfig
+1
drivers/pinctrl/tegra/Makefile
+1
drivers/pinctrl/tegra/Makefile
···
5
5
obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
6
6
obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
7
7
obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
8
+
obj-$(CONFIG_PINCTRL_TEGRA186) += pinctrl-tegra186.o
8
9
obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o
9
10
obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o
10
11
obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
+1979
drivers/pinctrl/tegra/pinctrl-tegra186.c
+1979
drivers/pinctrl/tegra/pinctrl-tegra186.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Pinctrl data for the NVIDIA Tegra186 pinmux
4
+
*
5
+
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify it
8
+
* under the terms and conditions of the GNU General Public License,
9
+
* version 2, as published by the Free Software Foundation.
10
+
*
11
+
* This program is distributed in the hope it will be useful, but WITHOUT
12
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14
+
* more details.
15
+
*/
16
+
17
+
#include <linux/init.h>
18
+
#include <linux/of.h>
19
+
#include <linux/platform_device.h>
20
+
#include <linux/pinctrl/pinctrl.h>
21
+
#include <linux/pinctrl/pinmux.h>
22
+
23
+
#include "pinctrl-tegra.h"
24
+
25
+
/* Define unique ID for each pins */
26
+
enum {
27
+
TEGRA_PIN_PEX_L0_RST_N_PA0,
28
+
TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
29
+
TEGRA_PIN_PEX_WAKE_N_PA2,
30
+
TEGRA_PIN_PEX_L1_RST_N_PA3,
31
+
TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
32
+
TEGRA_PIN_PEX_L2_RST_N_PA5,
33
+
TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
34
+
TEGRA_PIN_UART4_TX_PB0,
35
+
TEGRA_PIN_UART4_RX_PB1,
36
+
TEGRA_PIN_UART4_RTS_PB2,
37
+
TEGRA_PIN_UART4_CTS_PB3,
38
+
TEGRA_PIN_GPIO_WAN1_PB4,
39
+
TEGRA_PIN_GPIO_WAN2_PB5,
40
+
TEGRA_PIN_GPIO_WAN3_PB6,
41
+
TEGRA_PIN_GPIO_WAN4_PC0,
42
+
TEGRA_PIN_DAP2_SCLK_PC1,
43
+
TEGRA_PIN_DAP2_DOUT_PC2,
44
+
TEGRA_PIN_DAP2_DIN_PC3,
45
+
TEGRA_PIN_DAP2_FS_PC4,
46
+
TEGRA_PIN_GEN1_I2C_SCL_PC5,
47
+
TEGRA_PIN_GEN1_I2C_SDA_PC6,
48
+
TEGRA_PIN_SDMMC1_CLK_PD0,
49
+
TEGRA_PIN_SDMMC1_CMD_PD1,
50
+
TEGRA_PIN_SDMMC1_DAT0_PD2,
51
+
TEGRA_PIN_SDMMC1_DAT1_PD3,
52
+
TEGRA_PIN_SDMMC1_DAT2_PD4,
53
+
TEGRA_PIN_SDMMC1_DAT3_PD5,
54
+
TEGRA_PIN_EQOS_TXC_PE0,
55
+
TEGRA_PIN_EQOS_TD0_PE1,
56
+
TEGRA_PIN_EQOS_TD1_PE2,
57
+
TEGRA_PIN_EQOS_TD2_PE3,
58
+
TEGRA_PIN_EQOS_TD3_PE4,
59
+
TEGRA_PIN_EQOS_TX_CTL_PE5,
60
+
TEGRA_PIN_EQOS_RD0_PE6,
61
+
TEGRA_PIN_EQOS_RD1_PE7,
62
+
TEGRA_PIN_EQOS_RD2_PF0,
63
+
TEGRA_PIN_EQOS_RD3_PF1,
64
+
TEGRA_PIN_EQOS_RX_CTL_PF2,
65
+
TEGRA_PIN_EQOS_RXC_PF3,
66
+
TEGRA_PIN_EQOS_MDIO_PF4,
67
+
TEGRA_PIN_EQOS_MDC_PF5,
68
+
TEGRA_PIN_SDMMC3_CLK_PG0,
69
+
TEGRA_PIN_SDMMC3_CMD_PG1,
70
+
TEGRA_PIN_SDMMC3_DAT0_PG2,
71
+
TEGRA_PIN_SDMMC3_DAT1_PG3,
72
+
TEGRA_PIN_SDMMC3_DAT2_PG4,
73
+
TEGRA_PIN_SDMMC3_DAT3_PG5,
74
+
TEGRA_PIN_GPIO_WAN5_PH0,
75
+
TEGRA_PIN_GPIO_WAN6_PH1,
76
+
TEGRA_PIN_GPIO_WAN7_PH2,
77
+
TEGRA_PIN_GPIO_WAN8_PH3,
78
+
TEGRA_PIN_BCPU_PWR_REQ_PH4,
79
+
TEGRA_PIN_MCPU_PWR_REQ_PH5,
80
+
TEGRA_PIN_GPU_PWR_REQ_PH6,
81
+
TEGRA_PIN_GPIO_PQ0_PI0,
82
+
TEGRA_PIN_GPIO_PQ1_PI1,
83
+
TEGRA_PIN_GPIO_PQ2_PI2,
84
+
TEGRA_PIN_GPIO_PQ3_PI3,
85
+
TEGRA_PIN_GPIO_PQ4_PI4,
86
+
TEGRA_PIN_GPIO_PQ5_PI5,
87
+
TEGRA_PIN_GPIO_PQ6_PI6,
88
+
TEGRA_PIN_GPIO_PQ7_PI7,
89
+
TEGRA_PIN_DAP1_SCLK_PJ0,
90
+
TEGRA_PIN_DAP1_DOUT_PJ1,
91
+
TEGRA_PIN_DAP1_DIN_PJ2,
92
+
TEGRA_PIN_DAP1_FS_PJ3,
93
+
TEGRA_PIN_AUD_MCLK_PJ4,
94
+
TEGRA_PIN_GPIO_AUD0_PJ5,
95
+
TEGRA_PIN_GPIO_AUD1_PJ6,
96
+
TEGRA_PIN_GPIO_AUD2_PJ7,
97
+
TEGRA_PIN_GPIO_AUD3_PK0,
98
+
TEGRA_PIN_GEN7_I2C_SCL_PL0,
99
+
TEGRA_PIN_GEN7_I2C_SDA_PL1,
100
+
TEGRA_PIN_GEN9_I2C_SCL_PL2,
101
+
TEGRA_PIN_GEN9_I2C_SDA_PL3,
102
+
TEGRA_PIN_USB_VBUS_EN0_PL4,
103
+
TEGRA_PIN_USB_VBUS_EN1_PL5,
104
+
TEGRA_PIN_GP_PWM6_PL6,
105
+
TEGRA_PIN_GP_PWM7_PL7,
106
+
TEGRA_PIN_DMIC1_DAT_PM0,
107
+
TEGRA_PIN_DMIC1_CLK_PM1,
108
+
TEGRA_PIN_DMIC2_DAT_PM2,
109
+
TEGRA_PIN_DMIC2_CLK_PM3,
110
+
TEGRA_PIN_DMIC4_DAT_PM4,
111
+
TEGRA_PIN_DMIC4_CLK_PM5,
112
+
TEGRA_PIN_GPIO_CAM1_PN0,
113
+
TEGRA_PIN_GPIO_CAM2_PN1,
114
+
TEGRA_PIN_GPIO_CAM3_PN2,
115
+
TEGRA_PIN_GPIO_CAM4_PN3,
116
+
TEGRA_PIN_GPIO_CAM5_PN4,
117
+
TEGRA_PIN_GPIO_CAM6_PN5,
118
+
TEGRA_PIN_GPIO_CAM7_PN6,
119
+
TEGRA_PIN_EXTPERIPH1_CLK_PO0,
120
+
TEGRA_PIN_EXTPERIPH2_CLK_PO1,
121
+
TEGRA_PIN_CAM_I2C_SCL_PO2,
122
+
TEGRA_PIN_CAM_I2C_SDA_PO3,
123
+
TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
124
+
TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
125
+
TEGRA_PIN_HDMI_CEC_PP2,
126
+
TEGRA_PIN_GPIO_EDP0_PP3,
127
+
TEGRA_PIN_GPIO_EDP1_PP4,
128
+
TEGRA_PIN_GPIO_EDP2_PP5,
129
+
TEGRA_PIN_GPIO_EDP3_PP6,
130
+
TEGRA_PIN_DIRECTDC1_CLK_PQ0,
131
+
TEGRA_PIN_DIRECTDC1_IN_PQ1,
132
+
TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
133
+
TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
134
+
TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
135
+
TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
136
+
TEGRA_PIN_QSPI_SCK_PR0,
137
+
TEGRA_PIN_QSPI_IO0_PR1,
138
+
TEGRA_PIN_QSPI_IO1_PR2,
139
+
TEGRA_PIN_QSPI_IO2_PR3,
140
+
TEGRA_PIN_QSPI_IO3_PR4,
141
+
TEGRA_PIN_QSPI_CS_N_PR5,
142
+
TEGRA_PIN_UART1_TX_PT0,
143
+
TEGRA_PIN_UART1_RX_PT1,
144
+
TEGRA_PIN_UART1_RTS_PT2,
145
+
TEGRA_PIN_UART1_CTS_PT3,
146
+
TEGRA_PIN_UART2_TX_PX0,
147
+
TEGRA_PIN_UART2_RX_PX1,
148
+
TEGRA_PIN_UART2_RTS_PX2,
149
+
TEGRA_PIN_UART2_CTS_PX3,
150
+
TEGRA_PIN_UART5_TX_PX4,
151
+
TEGRA_PIN_UART5_RX_PX5,
152
+
TEGRA_PIN_UART5_RTS_PX6,
153
+
TEGRA_PIN_UART5_CTS_PX7,
154
+
TEGRA_PIN_GPIO_MDM1_PY0,
155
+
TEGRA_PIN_GPIO_MDM2_PY1,
156
+
TEGRA_PIN_GPIO_MDM3_PY2,
157
+
TEGRA_PIN_GPIO_MDM4_PY3,
158
+
TEGRA_PIN_GPIO_MDM5_PY4,
159
+
TEGRA_PIN_GPIO_MDM6_PY5,
160
+
TEGRA_PIN_GPIO_MDM7_PY6,
161
+
TEGRA_PIN_UFS0_REF_CLK_PBB0,
162
+
TEGRA_PIN_UFS0_RST_PBB1,
163
+
TEGRA_PIN_DAP4_SCLK_PCC0,
164
+
TEGRA_PIN_DAP4_DOUT_PCC1,
165
+
TEGRA_PIN_DAP4_DIN_PCC2,
166
+
TEGRA_PIN_DAP4_FS_PCC3,
167
+
TEGRA_PIN_DIRECTDC_COMP,
168
+
TEGRA_PIN_SDMMC1_COMP,
169
+
TEGRA_PIN_EQOS_COMP,
170
+
TEGRA_PIN_SDMMC3_COMP,
171
+
TEGRA_PIN_QSPI_COMP,
172
+
};
173
+
174
+
enum {
175
+
TEGRA_PIN_PWR_I2C_SCL_PS0,
176
+
TEGRA_PIN_PWR_I2C_SDA_PS1,
177
+
TEGRA_PIN_BATT_OC_PS2,
178
+
TEGRA_PIN_SAFE_STATE_PS3,
179
+
TEGRA_PIN_VCOMP_ALERT_PS4,
180
+
TEGRA_PIN_GPIO_DIS0_PU0,
181
+
TEGRA_PIN_GPIO_DIS1_PU1,
182
+
TEGRA_PIN_GPIO_DIS2_PU2,
183
+
TEGRA_PIN_GPIO_DIS3_PU3,
184
+
TEGRA_PIN_GPIO_DIS4_PU4,
185
+
TEGRA_PIN_GPIO_DIS5_PU5,
186
+
TEGRA_PIN_GPIO_SEN0_PV0,
187
+
TEGRA_PIN_GPIO_SEN1_PV1,
188
+
TEGRA_PIN_GPIO_SEN2_PV2,
189
+
TEGRA_PIN_GPIO_SEN3_PV3,
190
+
TEGRA_PIN_GPIO_SEN4_PV4,
191
+
TEGRA_PIN_GPIO_SEN5_PV5,
192
+
TEGRA_PIN_GPIO_SEN6_PV6,
193
+
TEGRA_PIN_GPIO_SEN7_PV7,
194
+
TEGRA_PIN_GEN8_I2C_SCL_PW0,
195
+
TEGRA_PIN_GEN8_I2C_SDA_PW1,
196
+
TEGRA_PIN_UART3_TX_PW2,
197
+
TEGRA_PIN_UART3_RX_PW3,
198
+
TEGRA_PIN_UART3_RTS_PW4,
199
+
TEGRA_PIN_UART3_CTS_PW5,
200
+
TEGRA_PIN_UART7_TX_PW6,
201
+
TEGRA_PIN_UART7_RX_PW7,
202
+
TEGRA_PIN_CAN1_DOUT_PZ0,
203
+
TEGRA_PIN_CAN1_DIN_PZ1,
204
+
TEGRA_PIN_CAN0_DOUT_PZ2,
205
+
TEGRA_PIN_CAN0_DIN_PZ3,
206
+
TEGRA_PIN_CAN_GPIO0_PAA0,
207
+
TEGRA_PIN_CAN_GPIO1_PAA1,
208
+
TEGRA_PIN_CAN_GPIO2_PAA2,
209
+
TEGRA_PIN_CAN_GPIO3_PAA3,
210
+
TEGRA_PIN_CAN_GPIO4_PAA4,
211
+
TEGRA_PIN_CAN_GPIO5_PAA5,
212
+
TEGRA_PIN_CAN_GPIO6_PAA6,
213
+
TEGRA_PIN_CAN_GPIO7_PAA7,
214
+
TEGRA_PIN_GPIO_SEN8_PEE0,
215
+
TEGRA_PIN_GPIO_SEN9_PEE1,
216
+
TEGRA_PIN_TOUCH_CLK_PEE2,
217
+
TEGRA_PIN_POWER_ON_PFF0,
218
+
TEGRA_PIN_GPIO_SW1_PFF1,
219
+
TEGRA_PIN_GPIO_SW2_PFF2,
220
+
TEGRA_PIN_GPIO_SW3_PFF3,
221
+
TEGRA_PIN_GPIO_SW4_PFF4,
222
+
TEGRA_PIN_SHUTDOWN,
223
+
TEGRA_PIN_PMU_INT,
224
+
TEGRA_PIN_SOC_PWR_REQ,
225
+
TEGRA_PIN_CLK_32K_IN,
226
+
};
227
+
228
+
/* Table for pin descriptor */
229
+
static const struct pinctrl_pin_desc tegra186_pins[] = {
230
+
PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N_PA0"),
231
+
PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N_PA1"),
232
+
PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N_PA2"),
233
+
PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N_PA3"),
234
+
PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N_PA4"),
235
+
PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PA5, "PEX_L2_RST_N_PA5"),
236
+
PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PA6, "PEX_L2_CLKREQ_N_PA6"),
237
+
PINCTRL_PIN(TEGRA_PIN_UART4_TX_PB0, "UART4_TX_PB0"),
238
+
PINCTRL_PIN(TEGRA_PIN_UART4_RX_PB1, "UART4_RX_PB1"),
239
+
PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PB2, "UART4_RTS_PB2"),
240
+
PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PB3, "UART4_CTS_PB3"),
241
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN1_PB4, "GPIO_WAN1_PB4"),
242
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN2_PB5, "GPIO_WAN2_PB5"),
243
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN3_PB6, "GPIO_WAN3_PB6"),
244
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN4_PC0, "GPIO_WAN4_PC0"),
245
+
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PC1, "DAP2_SCLK_PC1"),
246
+
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PC2, "DAP2_DOUT_PC2"),
247
+
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PC3, "DAP2_DIN_PC3"),
248
+
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PC4, "DAP2_FS_PC4"),
249
+
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC5, "GEN1_I2C_SCL_PC5"),
250
+
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC6, "GEN1_I2C_SDA_PC6"),
251
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PD0, "SDMMC1_CLK_PD0"),
252
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PD1, "SDMMC1_CMD_PD1"),
253
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PD2, "SDMMC1_DAT0_PD2"),
254
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PD3, "SDMMC1_DAT1_PD3"),
255
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PD4, "SDMMC1_DAT2_PD4"),
256
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PD5, "SDMMC1_DAT3_PD5"),
257
+
PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
258
+
PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
259
+
PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
260
+
PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
261
+
PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
262
+
PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
263
+
PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
264
+
PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
265
+
PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
266
+
PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
267
+
PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
268
+
PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
269
+
PINCTRL_PIN(TEGRA_PIN_EQOS_MDIO_PF4, "EQOS_MDIO_PF4"),
270
+
PINCTRL_PIN(TEGRA_PIN_EQOS_MDC_PF5, "EQOS_MDC_PF5"),
271
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PG0, "SDMMC3_CLK_PG0"),
272
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PG1, "SDMMC3_CMD_PG1"),
273
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PG2, "SDMMC3_DAT0_PG2"),
274
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PG3, "SDMMC3_DAT1_PG3"),
275
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PG4, "SDMMC3_DAT2_PG4"),
276
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PG5, "SDMMC3_DAT3_PG5"),
277
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN5_PH0, "GPIO_WAN5_PH0"),
278
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN6_PH1, "GPIO_WAN6_PH1"),
279
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN7_PH2, "GPIO_WAN7_PH2"),
280
+
PINCTRL_PIN(TEGRA_PIN_GPIO_WAN8_PH3, "GPIO_WAN8_PH3"),
281
+
PINCTRL_PIN(TEGRA_PIN_BCPU_PWR_REQ_PH4, "BCPU_PWR_REQ_PH4"),
282
+
PINCTRL_PIN(TEGRA_PIN_MCPU_PWR_REQ_PH5, "MCPU_PWR_REQ_PH5"),
283
+
PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH6, "GPU_PWR_REQ_PH6"),
284
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ0_PI0, "GPIO_PQ0_PI0"),
285
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ1_PI1, "GPIO_PQ1_PI1"),
286
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ2_PI2, "GPIO_PQ2_PI2"),
287
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ3_PI3, "GPIO_PQ3_PI3"),
288
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ4_PI4, "GPIO_PQ4_PI4"),
289
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ5_PI5, "GPIO_PQ5_PI5"),
290
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ6_PI6, "GPIO_PQ6_PI6"),
291
+
PINCTRL_PIN(TEGRA_PIN_GPIO_PQ7_PI7, "GPIO_PQ7_PI7"),
292
+
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PJ0, "DAP1_SCLK_PJ0"),
293
+
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PJ1, "DAP1_DOUT_PJ1"),
294
+
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PJ2, "DAP1_DIN_PJ2"),
295
+
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PJ3, "DAP1_FS_PJ3"),
296
+
PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PJ4, "AUD_MCLK_PJ4"),
297
+
PINCTRL_PIN(TEGRA_PIN_GPIO_AUD0_PJ5, "GPIO_AUD0_PJ5"),
298
+
PINCTRL_PIN(TEGRA_PIN_GPIO_AUD1_PJ6, "GPIO_AUD1_PJ6"),
299
+
PINCTRL_PIN(TEGRA_PIN_GPIO_AUD2_PJ7, "GPIO_AUD2_PJ7"),
300
+
PINCTRL_PIN(TEGRA_PIN_GPIO_AUD3_PK0, "GPIO_AUD3_PK0"),
301
+
PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PL0, "GEN7_I2C_SCL_PL0"),
302
+
PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PL1, "GEN7_I2C_SDA_PL1"),
303
+
PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PL2, "GEN9_I2C_SCL_PL2"),
304
+
PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PL3, "GEN9_I2C_SDA_PL3"),
305
+
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PL4, "USB_VBUS_EN0_PL4"),
306
+
PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PL5, "USB_VBUS_EN1_PL5"),
307
+
PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PL6, "GP_PWM6_PL6"),
308
+
PINCTRL_PIN(TEGRA_PIN_GP_PWM7_PL7, "GP_PWM7_PL7"),
309
+
PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PM0, "DMIC1_DAT_PM0"),
310
+
PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PM1, "DMIC1_CLK_PM1"),
311
+
PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PM2, "DMIC2_DAT_PM2"),
312
+
PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PM3, "DMIC2_CLK_PM3"),
313
+
PINCTRL_PIN(TEGRA_PIN_DMIC4_DAT_PM4, "DMIC4_DAT_PM4"),
314
+
PINCTRL_PIN(TEGRA_PIN_DMIC4_CLK_PM5, "DMIC4_CLK_PM5"),
315
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM1_PN0, "GPIO_CAM1_PN0"),
316
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM2_PN1, "GPIO_CAM2_PN1"),
317
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM3_PN2, "GPIO_CAM3_PN2"),
318
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM4_PN3, "GPIO_CAM4_PN3"),
319
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM5_PN4, "GPIO_CAM6_PN5"),
320
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM6_PN5, "GPIO_CAM6_PN5"),
321
+
PINCTRL_PIN(TEGRA_PIN_GPIO_CAM7_PN6, "GPIO_CAM7_PN6"),
322
+
PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PO0, "EXTPERIPH1_CLK_PO0"),
323
+
PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PO1, "EXTPERIPH2_CLK_PO1"),
324
+
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PO2, "CAM_I2C_SCL_PO2"),
325
+
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PO3, "CAM_I2C_SDA_PO3"),
326
+
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PP0, "DP_AUX_CH0_HPD_PP0"),
327
+
PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PP1, "DP_AUX_CH1_HPD_PP1"),
328
+
PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PP2, "HDMI_CEC_PP2"),
329
+
PINCTRL_PIN(TEGRA_PIN_GPIO_EDP0_PP3, "GPIO_EDP0_PP3"),
330
+
PINCTRL_PIN(TEGRA_PIN_GPIO_EDP1_PP4, "GPIO_EDP1_PP4"),
331
+
PINCTRL_PIN(TEGRA_PIN_GPIO_EDP2_PP5, "GPIO_EDP2_PP5"),
332
+
PINCTRL_PIN(TEGRA_PIN_GPIO_EDP3_PP6, "GPIO_EDP3_PP6"),
333
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PQ0, "DIRECTDC1_CLK_PQ0"),
334
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PQ1, "DIRECTDC1_IN_PQ1"),
335
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PQ2, "DIRECTDC1_OUT0_PQ2"),
336
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PQ3, "DIRECTDC1_OUT1_PQ3"),
337
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PQ4, "DIRECTDC1_OUT2_PQ4"),
338
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PQ5, "DIRECTDC1_OUT3_PQ5"),
339
+
PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PR0, "QSPI_SCK_PR0"),
340
+
PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PR1, "QSPI_IO0_PR1"),
341
+
PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PR2, "QSPI_IO1_PR2"),
342
+
PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PR3, "QSPI_IO2_PR3"),
343
+
PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PR4, "QSPI_IO3_PR4"),
344
+
PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PR5, "QSPI_CS_N_PR5"),
345
+
PINCTRL_PIN(TEGRA_PIN_UART1_TX_PT0, "UART1_TX_PT0"),
346
+
PINCTRL_PIN(TEGRA_PIN_UART1_RX_PT1, "UART1_RX_PT1"),
347
+
PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PT2, "UART1_RTS_PT2"),
348
+
PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PT3, "UART1_CTS_PT3"),
349
+
PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX0, "UART2_TX_PX0"),
350
+
PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX1, "UART2_RX_PX1"),
351
+
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX2, "UART2_RTS_PX2"),
352
+
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX3, "UART2_CTS_PX3"),
353
+
PINCTRL_PIN(TEGRA_PIN_UART5_TX_PX4, "UART5_TX_PX4"),
354
+
PINCTRL_PIN(TEGRA_PIN_UART5_RX_PX5, "UART5_RX_PX5"),
355
+
PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PX6, "UART5_RTS_PX6"),
356
+
PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PX7, "UART5_CTS_PX7"),
357
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM1_PY0, "GPIO_MDM1_PY0"),
358
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM2_PY1, "GPIO_MDM2_PY1"),
359
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM3_PY2, "GPIO_MDM3_PY2"),
360
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM4_PY3, "GPIO_MDM4_PY3"),
361
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM5_PY4, "GPIO_MDM5_PY4"),
362
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM6_PY5, "GPIO_MDM6_PY5"),
363
+
PINCTRL_PIN(TEGRA_PIN_GPIO_MDM7_PY6, "GPIO_MDM7_PY6"),
364
+
PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PBB0, "UFS0_REF_CLK_PBB0"),
365
+
PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PBB1, "UFS0_RST_PBB1"),
366
+
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PCC0, "DAP4_SCLK_PCC0"),
367
+
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PCC1, "DAP4_DOUT_PCC1"),
368
+
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PCC2, "DAP4_DIN_PCC2"),
369
+
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PCC3, "DAP4_FS_PCC3"),
370
+
PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
371
+
PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
372
+
PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
373
+
PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
374
+
PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
375
+
};
376
+
377
+
static const unsigned int pex_l0_rst_n_pa0_pins[] = {
378
+
TEGRA_PIN_PEX_L0_RST_N_PA0,
379
+
};
380
+
381
+
static const unsigned int pex_l0_clkreq_n_pa1_pins[] = {
382
+
TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
383
+
};
384
+
385
+
static const unsigned int pex_wake_n_pa2_pins[] = {
386
+
TEGRA_PIN_PEX_WAKE_N_PA2,
387
+
};
388
+
389
+
static const unsigned int pex_l1_rst_n_pa3_pins[] = {
390
+
TEGRA_PIN_PEX_L1_RST_N_PA3,
391
+
};
392
+
393
+
static const unsigned int pex_l1_clkreq_n_pa4_pins[] = {
394
+
TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
395
+
};
396
+
397
+
static const unsigned int pex_l2_rst_n_pa5_pins[] = {
398
+
TEGRA_PIN_PEX_L2_RST_N_PA5,
399
+
};
400
+
401
+
static const unsigned int pex_l2_clkreq_n_pa6_pins[] = {
402
+
TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
403
+
};
404
+
405
+
static const unsigned int uart4_tx_pb0_pins[] = {
406
+
TEGRA_PIN_UART4_TX_PB0,
407
+
};
408
+
409
+
static const unsigned int uart4_rx_pb1_pins[] = {
410
+
TEGRA_PIN_UART4_RX_PB1,
411
+
};
412
+
413
+
static const unsigned int uart4_rts_pb2_pins[] = {
414
+
TEGRA_PIN_UART4_RTS_PB2,
415
+
};
416
+
417
+
static const unsigned int uart4_cts_pb3_pins[] = {
418
+
TEGRA_PIN_UART4_CTS_PB3,
419
+
};
420
+
421
+
static const unsigned int gpio_wan1_pb4_pins[] = {
422
+
TEGRA_PIN_GPIO_WAN1_PB4,
423
+
};
424
+
425
+
static const unsigned int gpio_wan2_pb5_pins[] = {
426
+
TEGRA_PIN_GPIO_WAN2_PB5,
427
+
};
428
+
429
+
static const unsigned int gpio_wan3_pb6_pins[] = {
430
+
TEGRA_PIN_GPIO_WAN3_PB6,
431
+
};
432
+
433
+
static const unsigned int gpio_wan4_pc0_pins[] = {
434
+
TEGRA_PIN_GPIO_WAN4_PC0,
435
+
};
436
+
437
+
static const unsigned int dap2_sclk_pc1_pins[] = {
438
+
TEGRA_PIN_DAP2_SCLK_PC1,
439
+
};
440
+
441
+
static const unsigned int dap2_dout_pc2_pins[] = {
442
+
TEGRA_PIN_DAP2_DOUT_PC2,
443
+
};
444
+
445
+
static const unsigned int dap2_din_pc3_pins[] = {
446
+
TEGRA_PIN_DAP2_DIN_PC3,
447
+
};
448
+
449
+
static const unsigned int dap2_fs_pc4_pins[] = {
450
+
TEGRA_PIN_DAP2_FS_PC4,
451
+
};
452
+
453
+
static const unsigned int gen1_i2c_scl_pc5_pins[] = {
454
+
TEGRA_PIN_GEN1_I2C_SCL_PC5,
455
+
};
456
+
457
+
static const unsigned int gen1_i2c_sda_pc6_pins[] = {
458
+
TEGRA_PIN_GEN1_I2C_SDA_PC6,
459
+
};
460
+
461
+
static const unsigned int sdmmc1_clk_pd0_pins[] = {
462
+
TEGRA_PIN_SDMMC1_CLK_PD0,
463
+
};
464
+
465
+
static const unsigned int sdmmc1_cmd_pd1_pins[] = {
466
+
TEGRA_PIN_SDMMC1_CMD_PD1,
467
+
};
468
+
469
+
static const unsigned int sdmmc1_dat0_pd2_pins[] = {
470
+
TEGRA_PIN_SDMMC1_DAT0_PD2,
471
+
};
472
+
473
+
static const unsigned int sdmmc1_dat1_pd3_pins[] = {
474
+
TEGRA_PIN_SDMMC1_DAT1_PD3,
475
+
};
476
+
477
+
static const unsigned int sdmmc1_dat2_pd4_pins[] = {
478
+
TEGRA_PIN_SDMMC1_DAT2_PD4,
479
+
};
480
+
481
+
static const unsigned int sdmmc1_dat3_pd5_pins[] = {
482
+
TEGRA_PIN_SDMMC1_DAT3_PD5,
483
+
};
484
+
485
+
static const unsigned int eqos_txc_pe0_pins[] = {
486
+
TEGRA_PIN_EQOS_TXC_PE0,
487
+
};
488
+
489
+
static const unsigned int eqos_td0_pe1_pins[] = {
490
+
TEGRA_PIN_EQOS_TD0_PE1,
491
+
};
492
+
493
+
static const unsigned int eqos_td1_pe2_pins[] = {
494
+
TEGRA_PIN_EQOS_TD1_PE2,
495
+
};
496
+
497
+
static const unsigned int eqos_td2_pe3_pins[] = {
498
+
TEGRA_PIN_EQOS_TD2_PE3,
499
+
};
500
+
501
+
static const unsigned int eqos_td3_pe4_pins[] = {
502
+
TEGRA_PIN_EQOS_TD3_PE4,
503
+
};
504
+
505
+
static const unsigned int eqos_tx_ctl_pe5_pins[] = {
506
+
TEGRA_PIN_EQOS_TX_CTL_PE5,
507
+
};
508
+
509
+
static const unsigned int eqos_rd0_pe6_pins[] = {
510
+
TEGRA_PIN_EQOS_RD0_PE6,
511
+
};
512
+
513
+
static const unsigned int eqos_rd1_pe7_pins[] = {
514
+
TEGRA_PIN_EQOS_RD1_PE7,
515
+
};
516
+
517
+
static const unsigned int eqos_rd2_pf0_pins[] = {
518
+
TEGRA_PIN_EQOS_RD2_PF0,
519
+
};
520
+
521
+
static const unsigned int eqos_rd3_pf1_pins[] = {
522
+
TEGRA_PIN_EQOS_RD3_PF1,
523
+
};
524
+
525
+
static const unsigned int eqos_rx_ctl_pf2_pins[] = {
526
+
TEGRA_PIN_EQOS_RX_CTL_PF2,
527
+
};
528
+
529
+
static const unsigned int eqos_rxc_pf3_pins[] = {
530
+
TEGRA_PIN_EQOS_RXC_PF3,
531
+
};
532
+
533
+
static const unsigned int eqos_mdio_pf4_pins[] = {
534
+
TEGRA_PIN_EQOS_MDIO_PF4,
535
+
};
536
+
537
+
static const unsigned int eqos_mdc_pf5_pins[] = {
538
+
TEGRA_PIN_EQOS_MDC_PF5,
539
+
};
540
+
541
+
static const unsigned int sdmmc3_clk_pg0_pins[] = {
542
+
TEGRA_PIN_SDMMC3_CLK_PG0,
543
+
};
544
+
545
+
static const unsigned int sdmmc3_cmd_pg1_pins[] = {
546
+
TEGRA_PIN_SDMMC3_CMD_PG1,
547
+
};
548
+
549
+
static const unsigned int sdmmc3_dat0_pg2_pins[] = {
550
+
TEGRA_PIN_SDMMC3_DAT0_PG2,
551
+
};
552
+
553
+
static const unsigned int sdmmc3_dat1_pg3_pins[] = {
554
+
TEGRA_PIN_SDMMC3_DAT1_PG3,
555
+
};
556
+
557
+
static const unsigned int sdmmc3_dat2_pg4_pins[] = {
558
+
TEGRA_PIN_SDMMC3_DAT2_PG4,
559
+
};
560
+
561
+
static const unsigned int sdmmc3_dat3_pg5_pins[] = {
562
+
TEGRA_PIN_SDMMC3_DAT3_PG5,
563
+
};
564
+
565
+
static const unsigned int gpio_wan5_ph0_pins[] = {
566
+
TEGRA_PIN_GPIO_WAN5_PH0,
567
+
};
568
+
569
+
static const unsigned int gpio_wan6_ph1_pins[] = {
570
+
TEGRA_PIN_GPIO_WAN6_PH1,
571
+
};
572
+
573
+
static const unsigned int gpio_wan7_ph2_pins[] = {
574
+
TEGRA_PIN_GPIO_WAN7_PH2,
575
+
};
576
+
577
+
static const unsigned int gpio_wan8_ph3_pins[] = {
578
+
TEGRA_PIN_GPIO_WAN8_PH3,
579
+
};
580
+
581
+
static const unsigned int bcpu_pwr_req_ph4_pins[] = {
582
+
TEGRA_PIN_BCPU_PWR_REQ_PH4,
583
+
};
584
+
585
+
static const unsigned int mcpu_pwr_req_ph5_pins[] = {
586
+
TEGRA_PIN_MCPU_PWR_REQ_PH5,
587
+
};
588
+
589
+
static const unsigned int gpu_pwr_req_ph6_pins[] = {
590
+
TEGRA_PIN_GPU_PWR_REQ_PH6,
591
+
};
592
+
593
+
static const unsigned int gpio_pq0_pi0_pins[] = {
594
+
TEGRA_PIN_GPIO_PQ0_PI0,
595
+
};
596
+
597
+
static const unsigned int gpio_pq1_pi1_pins[] = {
598
+
TEGRA_PIN_GPIO_PQ1_PI1,
599
+
};
600
+
601
+
static const unsigned int gpio_pq2_pi2_pins[] = {
602
+
TEGRA_PIN_GPIO_PQ2_PI2,
603
+
};
604
+
605
+
static const unsigned int gpio_pq3_pi3_pins[] = {
606
+
TEGRA_PIN_GPIO_PQ3_PI3,
607
+
};
608
+
609
+
static const unsigned int gpio_pq4_pi4_pins[] = {
610
+
TEGRA_PIN_GPIO_PQ4_PI4,
611
+
};
612
+
613
+
static const unsigned int gpio_pq5_pi5_pins[] = {
614
+
TEGRA_PIN_GPIO_PQ5_PI5,
615
+
};
616
+
617
+
static const unsigned int gpio_pq6_pi6_pins[] = {
618
+
TEGRA_PIN_GPIO_PQ6_PI6,
619
+
};
620
+
621
+
static const unsigned int gpio_pq7_pi7_pins[] = {
622
+
TEGRA_PIN_GPIO_PQ7_PI7,
623
+
};
624
+
625
+
static const unsigned int dap1_sclk_pj0_pins[] = {
626
+
TEGRA_PIN_DAP1_SCLK_PJ0,
627
+
};
628
+
629
+
static const unsigned int dap1_dout_pj1_pins[] = {
630
+
TEGRA_PIN_DAP1_DOUT_PJ1,
631
+
};
632
+
633
+
static const unsigned int dap1_din_pj2_pins[] = {
634
+
TEGRA_PIN_DAP1_DIN_PJ2,
635
+
};
636
+
637
+
static const unsigned int dap1_fs_pj3_pins[] = {
638
+
TEGRA_PIN_DAP1_FS_PJ3,
639
+
};
640
+
641
+
static const unsigned int aud_mclk_pj4_pins[] = {
642
+
TEGRA_PIN_AUD_MCLK_PJ4,
643
+
};
644
+
645
+
static const unsigned int gpio_aud0_pj5_pins[] = {
646
+
TEGRA_PIN_GPIO_AUD0_PJ5,
647
+
};
648
+
649
+
static const unsigned int gpio_aud1_pj6_pins[] = {
650
+
TEGRA_PIN_GPIO_AUD1_PJ6,
651
+
};
652
+
653
+
static const unsigned int gpio_aud2_pj7_pins[] = {
654
+
TEGRA_PIN_GPIO_AUD2_PJ7,
655
+
};
656
+
657
+
static const unsigned int gpio_aud3_pk0_pins[] = {
658
+
TEGRA_PIN_GPIO_AUD3_PK0,
659
+
};
660
+
661
+
static const unsigned int gen7_i2c_scl_pl0_pins[] = {
662
+
TEGRA_PIN_GEN7_I2C_SCL_PL0,
663
+
};
664
+
665
+
static const unsigned int gen7_i2c_sda_pl1_pins[] = {
666
+
TEGRA_PIN_GEN7_I2C_SDA_PL1,
667
+
};
668
+
669
+
static const unsigned int gen9_i2c_scl_pl2_pins[] = {
670
+
TEGRA_PIN_GEN9_I2C_SCL_PL2,
671
+
};
672
+
673
+
static const unsigned int gen9_i2c_sda_pl3_pins[] = {
674
+
TEGRA_PIN_GEN9_I2C_SDA_PL3,
675
+
};
676
+
677
+
static const unsigned int usb_vbus_en0_pl4_pins[] = {
678
+
TEGRA_PIN_USB_VBUS_EN0_PL4,
679
+
};
680
+
681
+
static const unsigned int usb_vbus_en1_pl5_pins[] = {
682
+
TEGRA_PIN_USB_VBUS_EN1_PL5,
683
+
};
684
+
685
+
static const unsigned int gp_pwm6_pl6_pins[] = {
686
+
TEGRA_PIN_GP_PWM6_PL6,
687
+
};
688
+
689
+
static const unsigned int gp_pwm7_pl7_pins[] = {
690
+
TEGRA_PIN_GP_PWM7_PL7,
691
+
};
692
+
693
+
static const unsigned int dmic1_dat_pm0_pins[] = {
694
+
TEGRA_PIN_DMIC1_DAT_PM0,
695
+
};
696
+
697
+
static const unsigned int dmic1_clk_pm1_pins[] = {
698
+
TEGRA_PIN_DMIC1_CLK_PM1,
699
+
};
700
+
701
+
static const unsigned int dmic2_dat_pm2_pins[] = {
702
+
TEGRA_PIN_DMIC2_DAT_PM2,
703
+
};
704
+
705
+
static const unsigned int dmic2_clk_pm3_pins[] = {
706
+
TEGRA_PIN_DMIC2_CLK_PM3,
707
+
};
708
+
709
+
static const unsigned int dmic4_dat_pm4_pins[] = {
710
+
TEGRA_PIN_DMIC4_DAT_PM4,
711
+
};
712
+
713
+
static const unsigned int dmic4_clk_pm5_pins[] = {
714
+
TEGRA_PIN_DMIC4_CLK_PM5,
715
+
};
716
+
717
+
static const unsigned int gpio_cam1_pn0_pins[] = {
718
+
TEGRA_PIN_GPIO_CAM1_PN0,
719
+
};
720
+
721
+
static const unsigned int gpio_cam2_pn1_pins[] = {
722
+
TEGRA_PIN_GPIO_CAM2_PN1,
723
+
};
724
+
725
+
static const unsigned int gpio_cam3_pn2_pins[] = {
726
+
TEGRA_PIN_GPIO_CAM3_PN2,
727
+
};
728
+
729
+
static const unsigned int gpio_cam4_pn3_pins[] = {
730
+
TEGRA_PIN_GPIO_CAM4_PN3,
731
+
};
732
+
733
+
static const unsigned int gpio_cam5_pn4_pins[] = {
734
+
TEGRA_PIN_GPIO_CAM5_PN4,
735
+
};
736
+
737
+
static const unsigned int gpio_cam6_pn5_pins[] = {
738
+
TEGRA_PIN_GPIO_CAM6_PN5,
739
+
};
740
+
741
+
static const unsigned int gpio_cam7_pn6_pins[] = {
742
+
TEGRA_PIN_GPIO_CAM7_PN6,
743
+
};
744
+
745
+
static const unsigned int extperiph1_clk_po0_pins[] = {
746
+
TEGRA_PIN_EXTPERIPH1_CLK_PO0,
747
+
};
748
+
749
+
static const unsigned int extperiph2_clk_po1_pins[] = {
750
+
TEGRA_PIN_EXTPERIPH2_CLK_PO1,
751
+
};
752
+
753
+
static const unsigned int cam_i2c_scl_po2_pins[] = {
754
+
TEGRA_PIN_CAM_I2C_SCL_PO2,
755
+
};
756
+
757
+
static const unsigned int cam_i2c_sda_po3_pins[] = {
758
+
TEGRA_PIN_CAM_I2C_SDA_PO3,
759
+
};
760
+
761
+
static const unsigned int dp_aux_ch0_hpd_pp0_pins[] = {
762
+
TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
763
+
};
764
+
765
+
static const unsigned int dp_aux_ch1_hpd_pp1_pins[] = {
766
+
TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
767
+
};
768
+
769
+
static const unsigned int hdmi_cec_pp2_pins[] = {
770
+
TEGRA_PIN_HDMI_CEC_PP2,
771
+
};
772
+
773
+
static const unsigned int gpio_edp0_pp3_pins[] = {
774
+
TEGRA_PIN_GPIO_EDP0_PP3,
775
+
};
776
+
777
+
static const unsigned int gpio_edp1_pp4_pins[] = {
778
+
TEGRA_PIN_GPIO_EDP1_PP4,
779
+
};
780
+
781
+
static const unsigned int gpio_edp2_pp5_pins[] = {
782
+
TEGRA_PIN_GPIO_EDP2_PP5,
783
+
};
784
+
785
+
static const unsigned int gpio_edp3_pp6_pins[] = {
786
+
TEGRA_PIN_GPIO_EDP3_PP6,
787
+
};
788
+
789
+
static const unsigned int directdc1_clk_pq0_pins[] = {
790
+
TEGRA_PIN_DIRECTDC1_CLK_PQ0,
791
+
};
792
+
793
+
static const unsigned int directdc1_in_pq1_pins[] = {
794
+
TEGRA_PIN_DIRECTDC1_IN_PQ1,
795
+
};
796
+
797
+
static const unsigned int directdc1_out0_pq2_pins[] = {
798
+
TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
799
+
};
800
+
801
+
static const unsigned int directdc1_out1_pq3_pins[] = {
802
+
TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
803
+
};
804
+
805
+
static const unsigned int directdc1_out2_pq4_pins[] = {
806
+
TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
807
+
};
808
+
809
+
static const unsigned int directdc1_out3_pq5_pins[] = {
810
+
TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
811
+
};
812
+
813
+
static const unsigned int qspi_sck_pr0_pins[] = {
814
+
TEGRA_PIN_QSPI_SCK_PR0,
815
+
};
816
+
817
+
static const unsigned int qspi_io0_pr1_pins[] = {
818
+
TEGRA_PIN_QSPI_IO0_PR1,
819
+
};
820
+
821
+
static const unsigned int qspi_io1_pr2_pins[] = {
822
+
TEGRA_PIN_QSPI_IO1_PR2,
823
+
};
824
+
825
+
static const unsigned int qspi_io2_pr3_pins[] = {
826
+
TEGRA_PIN_QSPI_IO2_PR3,
827
+
};
828
+
829
+
static const unsigned int qspi_io3_pr4_pins[] = {
830
+
TEGRA_PIN_QSPI_IO3_PR4,
831
+
};
832
+
833
+
static const unsigned int qspi_cs_n_pr5_pins[] = {
834
+
TEGRA_PIN_QSPI_CS_N_PR5,
835
+
};
836
+
837
+
static const unsigned int pwr_i2c_scl_ps0_pins[] = {
838
+
TEGRA_PIN_PWR_I2C_SCL_PS0,
839
+
};
840
+
841
+
static const unsigned int pwr_i2c_sda_ps1_pins[] = {
842
+
TEGRA_PIN_PWR_I2C_SDA_PS1,
843
+
};
844
+
845
+
static const unsigned int batt_oc_ps2_pins[] = {
846
+
TEGRA_PIN_BATT_OC_PS2,
847
+
};
848
+
849
+
static const unsigned int safe_state_ps3_pins[] = {
850
+
TEGRA_PIN_SAFE_STATE_PS3,
851
+
};
852
+
853
+
static const unsigned int vcomp_alert_ps4_pins[] = {
854
+
TEGRA_PIN_VCOMP_ALERT_PS4,
855
+
};
856
+
857
+
static const unsigned int uart1_tx_pt0_pins[] = {
858
+
TEGRA_PIN_UART1_TX_PT0,
859
+
};
860
+
861
+
static const unsigned int uart1_rx_pt1_pins[] = {
862
+
TEGRA_PIN_UART1_RX_PT1,
863
+
};
864
+
865
+
static const unsigned int uart1_rts_pt2_pins[] = {
866
+
TEGRA_PIN_UART1_RTS_PT2,
867
+
};
868
+
869
+
static const unsigned int uart1_cts_pt3_pins[] = {
870
+
TEGRA_PIN_UART1_CTS_PT3,
871
+
};
872
+
873
+
static const unsigned int gpio_dis0_pu0_pins[] = {
874
+
TEGRA_PIN_GPIO_DIS0_PU0,
875
+
};
876
+
877
+
static const unsigned int gpio_dis1_pu1_pins[] = {
878
+
TEGRA_PIN_GPIO_DIS1_PU1,
879
+
};
880
+
881
+
static const unsigned int gpio_dis2_pu2_pins[] = {
882
+
TEGRA_PIN_GPIO_DIS2_PU2,
883
+
};
884
+
885
+
static const unsigned int gpio_dis3_pu3_pins[] = {
886
+
TEGRA_PIN_GPIO_DIS3_PU3,
887
+
};
888
+
889
+
static const unsigned int gpio_dis4_pu4_pins[] = {
890
+
TEGRA_PIN_GPIO_DIS4_PU4,
891
+
};
892
+
893
+
static const unsigned int gpio_dis5_pu5_pins[] = {
894
+
TEGRA_PIN_GPIO_DIS5_PU5,
895
+
};
896
+
897
+
static const unsigned int gpio_sen0_pv0_pins[] = {
898
+
TEGRA_PIN_GPIO_SEN0_PV0,
899
+
};
900
+
901
+
static const unsigned int gpio_sen1_pv1_pins[] = {
902
+
TEGRA_PIN_GPIO_SEN1_PV1,
903
+
};
904
+
905
+
static const unsigned int gpio_sen2_pv2_pins[] = {
906
+
TEGRA_PIN_GPIO_SEN2_PV2,
907
+
};
908
+
909
+
static const unsigned int gpio_sen3_pv3_pins[] = {
910
+
TEGRA_PIN_GPIO_SEN3_PV3,
911
+
};
912
+
913
+
static const unsigned int gpio_sen4_pv4_pins[] = {
914
+
TEGRA_PIN_GPIO_SEN4_PV4,
915
+
};
916
+
917
+
static const unsigned int gpio_sen5_pv5_pins[] = {
918
+
TEGRA_PIN_GPIO_SEN5_PV5,
919
+
};
920
+
921
+
static const unsigned int gpio_sen6_pv6_pins[] = {
922
+
TEGRA_PIN_GPIO_SEN6_PV6,
923
+
};
924
+
925
+
static const unsigned int gpio_sen7_pv7_pins[] = {
926
+
TEGRA_PIN_GPIO_SEN7_PV7,
927
+
};
928
+
929
+
static const unsigned int gen8_i2c_scl_pw0_pins[] = {
930
+
TEGRA_PIN_GEN8_I2C_SCL_PW0,
931
+
};
932
+
933
+
static const unsigned int gen8_i2c_sda_pw1_pins[] = {
934
+
TEGRA_PIN_GEN8_I2C_SDA_PW1,
935
+
};
936
+
937
+
static const unsigned int uart3_tx_pw2_pins[] = {
938
+
TEGRA_PIN_UART3_TX_PW2,
939
+
};
940
+
941
+
static const unsigned int uart3_rx_pw3_pins[] = {
942
+
TEGRA_PIN_UART3_RX_PW3,
943
+
};
944
+
945
+
static const unsigned int uart3_rts_pw4_pins[] = {
946
+
TEGRA_PIN_UART3_RTS_PW4,
947
+
};
948
+
949
+
static const unsigned int uart3_cts_pw5_pins[] = {
950
+
TEGRA_PIN_UART3_CTS_PW5,
951
+
};
952
+
953
+
static const unsigned int uart7_tx_pw6_pins[] = {
954
+
TEGRA_PIN_UART7_TX_PW6,
955
+
};
956
+
957
+
static const unsigned int uart7_rx_pw7_pins[] = {
958
+
TEGRA_PIN_UART7_RX_PW7,
959
+
};
960
+
961
+
static const unsigned int uart2_tx_px0_pins[] = {
962
+
TEGRA_PIN_UART2_TX_PX0,
963
+
};
964
+
965
+
static const unsigned int uart2_rx_px1_pins[] = {
966
+
TEGRA_PIN_UART2_RX_PX1,
967
+
};
968
+
969
+
static const unsigned int uart2_rts_px2_pins[] = {
970
+
TEGRA_PIN_UART2_RTS_PX2,
971
+
};
972
+
973
+
static const unsigned int uart2_cts_px3_pins[] = {
974
+
TEGRA_PIN_UART2_CTS_PX3,
975
+
};
976
+
977
+
static const unsigned int uart5_tx_px4_pins[] = {
978
+
TEGRA_PIN_UART5_TX_PX4,
979
+
};
980
+
981
+
static const unsigned int uart5_rx_px5_pins[] = {
982
+
TEGRA_PIN_UART5_RX_PX5,
983
+
};
984
+
985
+
static const unsigned int uart5_rts_px6_pins[] = {
986
+
TEGRA_PIN_UART5_RTS_PX6,
987
+
};
988
+
989
+
static const unsigned int uart5_cts_px7_pins[] = {
990
+
TEGRA_PIN_UART5_CTS_PX7,
991
+
};
992
+
993
+
static const unsigned int gpio_mdm1_py0_pins[] = {
994
+
TEGRA_PIN_GPIO_MDM1_PY0,
995
+
};
996
+
997
+
static const unsigned int gpio_mdm2_py1_pins[] = {
998
+
TEGRA_PIN_GPIO_MDM2_PY1,
999
+
};
1000
+
1001
+
static const unsigned int gpio_mdm3_py2_pins[] = {
1002
+
TEGRA_PIN_GPIO_MDM3_PY2,
1003
+
};
1004
+
1005
+
static const unsigned int gpio_mdm4_py3_pins[] = {
1006
+
TEGRA_PIN_GPIO_MDM4_PY3,
1007
+
};
1008
+
1009
+
static const unsigned int gpio_mdm5_py4_pins[] = {
1010
+
TEGRA_PIN_GPIO_MDM5_PY4,
1011
+
};
1012
+
1013
+
static const unsigned int gpio_mdm6_py5_pins[] = {
1014
+
TEGRA_PIN_GPIO_MDM6_PY5,
1015
+
};
1016
+
1017
+
static const unsigned int gpio_mdm7_py6_pins[] = {
1018
+
TEGRA_PIN_GPIO_MDM7_PY6,
1019
+
};
1020
+
1021
+
static const unsigned int can1_dout_pz0_pins[] = {
1022
+
TEGRA_PIN_CAN1_DOUT_PZ0,
1023
+
};
1024
+
1025
+
static const unsigned int can1_din_pz1_pins[] = {
1026
+
TEGRA_PIN_CAN1_DIN_PZ1,
1027
+
};
1028
+
1029
+
static const unsigned int can0_dout_pz2_pins[] = {
1030
+
TEGRA_PIN_CAN0_DOUT_PZ2,
1031
+
};
1032
+
1033
+
static const unsigned int can0_din_pz3_pins[] = {
1034
+
TEGRA_PIN_CAN0_DIN_PZ3,
1035
+
};
1036
+
1037
+
static const unsigned int can_gpio0_paa0_pins[] = {
1038
+
TEGRA_PIN_CAN_GPIO0_PAA0,
1039
+
};
1040
+
1041
+
static const unsigned int can_gpio1_paa1_pins[] = {
1042
+
TEGRA_PIN_CAN_GPIO1_PAA1,
1043
+
};
1044
+
1045
+
static const unsigned int can_gpio2_paa2_pins[] = {
1046
+
TEGRA_PIN_CAN_GPIO2_PAA2,
1047
+
};
1048
+
1049
+
static const unsigned int can_gpio3_paa3_pins[] = {
1050
+
TEGRA_PIN_CAN_GPIO3_PAA3,
1051
+
};
1052
+
1053
+
static const unsigned int can_gpio4_paa4_pins[] = {
1054
+
TEGRA_PIN_CAN_GPIO4_PAA4,
1055
+
};
1056
+
1057
+
static const unsigned int can_gpio5_paa5_pins[] = {
1058
+
TEGRA_PIN_CAN_GPIO5_PAA5,
1059
+
};
1060
+
1061
+
static const unsigned int can_gpio6_paa6_pins[] = {
1062
+
TEGRA_PIN_CAN_GPIO6_PAA6,
1063
+
};
1064
+
1065
+
static const unsigned int can_gpio7_paa7_pins[] = {
1066
+
TEGRA_PIN_CAN_GPIO7_PAA7,
1067
+
};
1068
+
1069
+
static const unsigned int ufs0_ref_clk_pbb0_pins[] = {
1070
+
TEGRA_PIN_UFS0_REF_CLK_PBB0,
1071
+
};
1072
+
1073
+
static const unsigned int ufs0_rst_pbb1_pins[] = {
1074
+
TEGRA_PIN_UFS0_RST_PBB1,
1075
+
};
1076
+
1077
+
static const unsigned int dap4_sclk_pcc0_pins[] = {
1078
+
TEGRA_PIN_DAP4_SCLK_PCC0,
1079
+
};
1080
+
1081
+
static const unsigned int dap4_dout_pcc1_pins[] = {
1082
+
TEGRA_PIN_DAP4_DOUT_PCC1,
1083
+
};
1084
+
1085
+
static const unsigned int dap4_din_pcc2_pins[] = {
1086
+
TEGRA_PIN_DAP4_DIN_PCC2,
1087
+
};
1088
+
1089
+
static const unsigned int dap4_fs_pcc3_pins[] = {
1090
+
TEGRA_PIN_DAP4_FS_PCC3,
1091
+
};
1092
+
1093
+
static const unsigned int gpio_sen8_pee0_pins[] = {
1094
+
TEGRA_PIN_GPIO_SEN8_PEE0,
1095
+
};
1096
+
1097
+
static const unsigned int gpio_sen9_pee1_pins[] = {
1098
+
TEGRA_PIN_GPIO_SEN9_PEE1,
1099
+
};
1100
+
1101
+
static const unsigned int touch_clk_pee2_pins[] = {
1102
+
TEGRA_PIN_TOUCH_CLK_PEE2,
1103
+
};
1104
+
1105
+
static const unsigned int power_on_pff0_pins[] = {
1106
+
TEGRA_PIN_POWER_ON_PFF0,
1107
+
};
1108
+
1109
+
static const unsigned int gpio_sw1_pff1_pins[] = {
1110
+
TEGRA_PIN_GPIO_SW1_PFF1,
1111
+
};
1112
+
1113
+
static const unsigned int gpio_sw2_pff2_pins[] = {
1114
+
TEGRA_PIN_GPIO_SW2_PFF2,
1115
+
};
1116
+
1117
+
static const unsigned int gpio_sw3_pff3_pins[] = {
1118
+
TEGRA_PIN_GPIO_SW3_PFF3,
1119
+
};
1120
+
1121
+
static const unsigned int gpio_sw4_pff4_pins[] = {
1122
+
TEGRA_PIN_GPIO_SW4_PFF4,
1123
+
};
1124
+
1125
+
static const unsigned int directdc_comp_pins[] = {
1126
+
TEGRA_PIN_DIRECTDC_COMP,
1127
+
};
1128
+
1129
+
static const unsigned int sdmmc1_comp_pins[] = {
1130
+
TEGRA_PIN_SDMMC1_COMP,
1131
+
};
1132
+
1133
+
static const unsigned int eqos_comp_pins[] = {
1134
+
TEGRA_PIN_EQOS_COMP,
1135
+
};
1136
+
1137
+
static const unsigned int sdmmc3_comp_pins[] = {
1138
+
TEGRA_PIN_SDMMC3_COMP,
1139
+
};
1140
+
1141
+
static const unsigned int qspi_comp_pins[] = {
1142
+
TEGRA_PIN_QSPI_COMP,
1143
+
};
1144
+
1145
+
static const unsigned int shutdown_pins[] = {
1146
+
TEGRA_PIN_SHUTDOWN,
1147
+
};
1148
+
1149
+
static const unsigned int pmu_int_pins[] = {
1150
+
TEGRA_PIN_PMU_INT,
1151
+
};
1152
+
1153
+
static const unsigned int soc_pwr_req_pins[] = {
1154
+
TEGRA_PIN_SOC_PWR_REQ,
1155
+
};
1156
+
1157
+
static const unsigned int clk_32k_in_pins[] = {
1158
+
TEGRA_PIN_CLK_32K_IN,
1159
+
};
1160
+
1161
+
static const unsigned int sdmmc4_clk_pins[] = {};
1162
+
1163
+
static const unsigned int sdmmc4_cmd_pins[] = {};
1164
+
1165
+
static const unsigned int sdmmc4_dqs_pins[] = {};
1166
+
1167
+
static const unsigned int sdmmc4_dat7_pins[] = {};
1168
+
1169
+
static const unsigned int sdmmc4_dat6_pins[] = {};
1170
+
1171
+
static const unsigned int sdmmc4_dat5_pins[] = {};
1172
+
1173
+
static const unsigned int sdmmc4_dat4_pins[] = {};
1174
+
1175
+
static const unsigned int sdmmc4_dat3_pins[] = {};
1176
+
1177
+
static const unsigned int sdmmc4_dat2_pins[] = {};
1178
+
1179
+
static const unsigned int sdmmc4_dat1_pins[] = {};
1180
+
1181
+
static const unsigned int sdmmc4_dat0_pins[] = {};
1182
+
1183
+
/* Define unique ID for each function */
1184
+
enum tegra_mux_dt {
1185
+
TEGRA_MUX_RSVD0,
1186
+
TEGRA_MUX_RSVD1,
1187
+
TEGRA_MUX_RSVD2,
1188
+
TEGRA_MUX_RSVD3,
1189
+
TEGRA_MUX_TOUCH,
1190
+
TEGRA_MUX_UARTC,
1191
+
TEGRA_MUX_I2C8,
1192
+
TEGRA_MUX_UARTG,
1193
+
TEGRA_MUX_SPI2,
1194
+
TEGRA_MUX_GP,
1195
+
TEGRA_MUX_DCA,
1196
+
TEGRA_MUX_WDT,
1197
+
TEGRA_MUX_I2C2,
1198
+
TEGRA_MUX_CAN1,
1199
+
TEGRA_MUX_CAN0,
1200
+
TEGRA_MUX_DMIC3,
1201
+
TEGRA_MUX_DMIC5,
1202
+
TEGRA_MUX_GPIO,
1203
+
TEGRA_MUX_DSPK1,
1204
+
TEGRA_MUX_DSPK0,
1205
+
TEGRA_MUX_SPDIF,
1206
+
TEGRA_MUX_AUD,
1207
+
TEGRA_MUX_I2S1,
1208
+
TEGRA_MUX_DMIC1,
1209
+
TEGRA_MUX_DMIC2,
1210
+
TEGRA_MUX_I2S3,
1211
+
TEGRA_MUX_DMIC4,
1212
+
TEGRA_MUX_I2S4,
1213
+
TEGRA_MUX_EXTPERIPH2,
1214
+
TEGRA_MUX_EXTPERIPH1,
1215
+
TEGRA_MUX_I2C3,
1216
+
TEGRA_MUX_VGP1,
1217
+
TEGRA_MUX_VGP2,
1218
+
TEGRA_MUX_VGP3,
1219
+
TEGRA_MUX_VGP4,
1220
+
TEGRA_MUX_VGP5,
1221
+
TEGRA_MUX_VGP6,
1222
+
TEGRA_MUX_EXTPERIPH3,
1223
+
TEGRA_MUX_EXTPERIPH4,
1224
+
TEGRA_MUX_SPI4,
1225
+
TEGRA_MUX_I2S2,
1226
+
TEGRA_MUX_UARTD,
1227
+
TEGRA_MUX_I2C1,
1228
+
TEGRA_MUX_UARTA,
1229
+
TEGRA_MUX_DIRECTDC1,
1230
+
TEGRA_MUX_DIRECTDC,
1231
+
TEGRA_MUX_IQC0,
1232
+
TEGRA_MUX_IQC1,
1233
+
TEGRA_MUX_I2S6,
1234
+
TEGRA_MUX_DTV,
1235
+
TEGRA_MUX_UARTF,
1236
+
TEGRA_MUX_SDMMC3,
1237
+
TEGRA_MUX_SDMMC4,
1238
+
TEGRA_MUX_SDMMC1,
1239
+
TEGRA_MUX_DP,
1240
+
TEGRA_MUX_HDMI,
1241
+
TEGRA_MUX_PE2,
1242
+
TEGRA_MUX_SATA,
1243
+
TEGRA_MUX_PE,
1244
+
TEGRA_MUX_PE1,
1245
+
TEGRA_MUX_PE0,
1246
+
TEGRA_MUX_SOC,
1247
+
TEGRA_MUX_EQOS,
1248
+
TEGRA_MUX_SDMMC2,
1249
+
TEGRA_MUX_QSPI,
1250
+
TEGRA_MUX_SCE,
1251
+
TEGRA_MUX_I2C5,
1252
+
TEGRA_MUX_DISPLAYA,
1253
+
TEGRA_MUX_DISPLAYB,
1254
+
TEGRA_MUX_DCC,
1255
+
TEGRA_MUX_DCB,
1256
+
TEGRA_MUX_SPI1,
1257
+
TEGRA_MUX_UARTB,
1258
+
TEGRA_MUX_UARTE,
1259
+
TEGRA_MUX_SPI3,
1260
+
TEGRA_MUX_NV,
1261
+
TEGRA_MUX_CCLA,
1262
+
TEGRA_MUX_I2C7,
1263
+
TEGRA_MUX_I2C9,
1264
+
TEGRA_MUX_I2S5,
1265
+
TEGRA_MUX_USB,
1266
+
TEGRA_MUX_UFS0,
1267
+
};
1268
+
1269
+
/* Make list of each function name */
1270
+
#define TEGRA_PIN_FUNCTION(lid) #lid
1271
+
1272
+
static const char * const tegra186_functions[] = {
1273
+
TEGRA_PIN_FUNCTION(rsvd0),
1274
+
TEGRA_PIN_FUNCTION(rsvd1),
1275
+
TEGRA_PIN_FUNCTION(rsvd2),
1276
+
TEGRA_PIN_FUNCTION(rsvd3),
1277
+
TEGRA_PIN_FUNCTION(touch),
1278
+
TEGRA_PIN_FUNCTION(uartc),
1279
+
TEGRA_PIN_FUNCTION(i2c8),
1280
+
TEGRA_PIN_FUNCTION(uartg),
1281
+
TEGRA_PIN_FUNCTION(spi2),
1282
+
TEGRA_PIN_FUNCTION(gp),
1283
+
TEGRA_PIN_FUNCTION(dca),
1284
+
TEGRA_PIN_FUNCTION(wdt),
1285
+
TEGRA_PIN_FUNCTION(i2c2),
1286
+
TEGRA_PIN_FUNCTION(can1),
1287
+
TEGRA_PIN_FUNCTION(can0),
1288
+
TEGRA_PIN_FUNCTION(dmic3),
1289
+
TEGRA_PIN_FUNCTION(dmic5),
1290
+
TEGRA_PIN_FUNCTION(gpio),
1291
+
TEGRA_PIN_FUNCTION(dspk1),
1292
+
TEGRA_PIN_FUNCTION(dspk0),
1293
+
TEGRA_PIN_FUNCTION(spdif),
1294
+
TEGRA_PIN_FUNCTION(aud),
1295
+
TEGRA_PIN_FUNCTION(i2s1),
1296
+
TEGRA_PIN_FUNCTION(dmic1),
1297
+
TEGRA_PIN_FUNCTION(dmic2),
1298
+
TEGRA_PIN_FUNCTION(i2s3),
1299
+
TEGRA_PIN_FUNCTION(dmic4),
1300
+
TEGRA_PIN_FUNCTION(i2s4),
1301
+
TEGRA_PIN_FUNCTION(extperiph2),
1302
+
TEGRA_PIN_FUNCTION(extperiph1),
1303
+
TEGRA_PIN_FUNCTION(i2c3),
1304
+
TEGRA_PIN_FUNCTION(vgp1),
1305
+
TEGRA_PIN_FUNCTION(vgp2),
1306
+
TEGRA_PIN_FUNCTION(vgp3),
1307
+
TEGRA_PIN_FUNCTION(vgp4),
1308
+
TEGRA_PIN_FUNCTION(vgp5),
1309
+
TEGRA_PIN_FUNCTION(vgp6),
1310
+
TEGRA_PIN_FUNCTION(extperiph3),
1311
+
TEGRA_PIN_FUNCTION(extperiph4),
1312
+
TEGRA_PIN_FUNCTION(spi4),
1313
+
TEGRA_PIN_FUNCTION(i2s2),
1314
+
TEGRA_PIN_FUNCTION(uartd),
1315
+
TEGRA_PIN_FUNCTION(i2c1),
1316
+
TEGRA_PIN_FUNCTION(uarta),
1317
+
TEGRA_PIN_FUNCTION(directdc1),
1318
+
TEGRA_PIN_FUNCTION(directdc),
1319
+
TEGRA_PIN_FUNCTION(iqc0),
1320
+
TEGRA_PIN_FUNCTION(iqc1),
1321
+
TEGRA_PIN_FUNCTION(i2s6),
1322
+
TEGRA_PIN_FUNCTION(dtv),
1323
+
TEGRA_PIN_FUNCTION(uartf),
1324
+
TEGRA_PIN_FUNCTION(sdmmc3),
1325
+
TEGRA_PIN_FUNCTION(sdmmc4),
1326
+
TEGRA_PIN_FUNCTION(sdmmc1),
1327
+
TEGRA_PIN_FUNCTION(dp),
1328
+
TEGRA_PIN_FUNCTION(hdmi),
1329
+
TEGRA_PIN_FUNCTION(pe2),
1330
+
TEGRA_PIN_FUNCTION(sata),
1331
+
TEGRA_PIN_FUNCTION(pe),
1332
+
TEGRA_PIN_FUNCTION(pe1),
1333
+
TEGRA_PIN_FUNCTION(pe0),
1334
+
TEGRA_PIN_FUNCTION(soc),
1335
+
TEGRA_PIN_FUNCTION(eqos),
1336
+
TEGRA_PIN_FUNCTION(sdmmc2),
1337
+
TEGRA_PIN_FUNCTION(qspi),
1338
+
TEGRA_PIN_FUNCTION(sce),
1339
+
TEGRA_PIN_FUNCTION(i2c5),
1340
+
TEGRA_PIN_FUNCTION(displaya),
1341
+
TEGRA_PIN_FUNCTION(displayb),
1342
+
TEGRA_PIN_FUNCTION(dcc),
1343
+
TEGRA_PIN_FUNCTION(dcb),
1344
+
TEGRA_PIN_FUNCTION(spi1),
1345
+
TEGRA_PIN_FUNCTION(uartb),
1346
+
TEGRA_PIN_FUNCTION(uarte),
1347
+
TEGRA_PIN_FUNCTION(spi3),
1348
+
TEGRA_PIN_FUNCTION(nv),
1349
+
TEGRA_PIN_FUNCTION(ccla),
1350
+
TEGRA_PIN_FUNCTION(i2c7),
1351
+
TEGRA_PIN_FUNCTION(i2c9),
1352
+
TEGRA_PIN_FUNCTION(i2s5),
1353
+
TEGRA_PIN_FUNCTION(usb),
1354
+
TEGRA_PIN_FUNCTION(ufs0),
1355
+
};
1356
+
1357
+
#define PINGROUP_REG_Y(r) ((r))
1358
+
#define PINGROUP_REG_N(r) -1
1359
+
1360
+
#define DRV_PINGROUP_Y(r) ((r))
1361
+
#define DRV_PINGROUP_N(r) -1
1362
+
1363
+
#define DRV_PINGROUP_ENTRY_N(pg_name) \
1364
+
.drv_reg = -1, \
1365
+
.drv_bank = -1, \
1366
+
.drvdn_bit = -1, \
1367
+
.drvdn_width = -1, \
1368
+
.drvup_bit = -1, \
1369
+
.drvup_width = -1, \
1370
+
.slwr_bit = -1, \
1371
+
.slwr_width = -1, \
1372
+
.slwf_bit = -1, \
1373
+
.slwf_width = -1
1374
+
1375
+
#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
1376
+
drvup_w, slwr_b, slwr_w, slwf_b, \
1377
+
slwf_w, bank) \
1378
+
.drv_reg = ((r)), \
1379
+
.drv_bank = bank, \
1380
+
.drvdn_bit = drvdn_b, \
1381
+
.drvdn_width = drvdn_w, \
1382
+
.drvup_bit = drvup_b, \
1383
+
.drvup_width = drvup_w, \
1384
+
.slwr_bit = slwr_b, \
1385
+
.slwr_width = slwr_w, \
1386
+
.slwf_bit = slwf_b, \
1387
+
.slwf_width = slwf_w
1388
+
1389
+
#define PIN_PINGROUP_ENTRY_N(pg_name) \
1390
+
.mux_reg = -1, \
1391
+
.pupd_reg = -1, \
1392
+
.tri_reg = -1, \
1393
+
.einput_bit = -1, \
1394
+
.e_io_hv_bit = -1, \
1395
+
.odrain_bit = -1, \
1396
+
.lock_bit = -1, \
1397
+
.parked_bit = -1, \
1398
+
.lpmd_bit = -1, \
1399
+
.drvtype_bit = -1, \
1400
+
.lpdr_bit = -1, \
1401
+
.pbias_buf_bit = -1, \
1402
+
.preemp_bit = -1, \
1403
+
.rfu_in_bit = -1
1404
+
1405
+
#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
1406
+
e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1407
+
e_od, schmitt_b, drvtype, epreemp, \
1408
+
io_reset, rfu_in) \
1409
+
.mux_reg = PINGROUP_REG_Y(r), \
1410
+
.lpmd_bit = -1, \
1411
+
.lock_bit = -1, \
1412
+
.hsm_bit = -1, \
1413
+
.mux_bank = bank, \
1414
+
.mux_bit = 0, \
1415
+
.pupd_reg = PINGROUP_REG_##pupd(r), \
1416
+
.pupd_bank = bank, \
1417
+
.pupd_bit = 2, \
1418
+
.tri_reg = PINGROUP_REG_Y(r), \
1419
+
.tri_bank = bank, \
1420
+
.tri_bit = 4, \
1421
+
.einput_bit = e_input, \
1422
+
.sfsel_bit = gpio_sfio_sel, \
1423
+
.odrain_bit = e_od, \
1424
+
.schmitt_bit = schmitt_b, \
1425
+
.drvtype_bit = 13, \
1426
+
.lpdr_bit = e_lpdr, \
1427
+
1428
+
/* main drive pin groups */
1429
+
#define drive_gpio_aud3_pk0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1430
+
#define drive_gpio_aud2_pj7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1431
+
#define drive_gpio_aud1_pj6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1432
+
#define drive_gpio_aud0_pj5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1433
+
#define drive_aud_mclk_pj4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1434
+
#define drive_dap1_fs_pj3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1435
+
#define drive_dap1_din_pj2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1436
+
#define drive_dap1_dout_pj1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1437
+
#define drive_dap1_sclk_pj0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1438
+
#define drive_dmic1_clk_pm1 DRV_PINGROUP_ENTRY_Y(0x2004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1439
+
#define drive_dmic1_dat_pm0 DRV_PINGROUP_ENTRY_Y(0x200c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1440
+
#define drive_dmic2_dat_pm2 DRV_PINGROUP_ENTRY_Y(0x2014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1441
+
#define drive_dmic2_clk_pm3 DRV_PINGROUP_ENTRY_Y(0x201c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1442
+
#define drive_dmic4_dat_pm4 DRV_PINGROUP_ENTRY_Y(0x2024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1443
+
#define drive_dmic4_clk_pm5 DRV_PINGROUP_ENTRY_Y(0x202c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1444
+
#define drive_dap4_fs_pcc3 DRV_PINGROUP_ENTRY_Y(0x2034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1445
+
#define drive_dap4_din_pcc2 DRV_PINGROUP_ENTRY_Y(0x203c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1446
+
#define drive_dap4_dout_pcc1 DRV_PINGROUP_ENTRY_Y(0x2044, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1447
+
#define drive_dap4_sclk_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1448
+
#define drive_extperiph2_clk_po1 DRV_PINGROUP_ENTRY_Y(0x0004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449
+
#define drive_extperiph1_clk_po0 DRV_PINGROUP_ENTRY_Y(0x000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450
+
#define drive_cam_i2c_sda_po3 DRV_PINGROUP_ENTRY_Y(0x0014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451
+
#define drive_cam_i2c_scl_po2 DRV_PINGROUP_ENTRY_Y(0x001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452
+
#define drive_gpio_cam1_pn0 DRV_PINGROUP_ENTRY_Y(0x0024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453
+
#define drive_gpio_cam2_pn1 DRV_PINGROUP_ENTRY_Y(0x002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454
+
#define drive_gpio_cam3_pn2 DRV_PINGROUP_ENTRY_Y(0x0034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1455
+
#define drive_gpio_cam4_pn3 DRV_PINGROUP_ENTRY_Y(0x003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1456
+
#define drive_gpio_cam5_pn4 DRV_PINGROUP_ENTRY_Y(0x0044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1457
+
#define drive_gpio_cam6_pn5 DRV_PINGROUP_ENTRY_Y(0x004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1458
+
#define drive_gpio_cam7_pn6 DRV_PINGROUP_ENTRY_Y(0x0054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1459
+
#define drive_dap2_din_pc3 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1460
+
#define drive_dap2_dout_pc2 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1461
+
#define drive_dap2_fs_pc4 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1462
+
#define drive_dap2_sclk_pc1 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1463
+
#define drive_uart4_cts_pb3 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1464
+
#define drive_uart4_rts_pb2 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1465
+
#define drive_uart4_rx_pb1 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1466
+
#define drive_uart4_tx_pb0 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1467
+
#define drive_gpio_wan4_pc0 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1468
+
#define drive_gpio_wan3_pb6 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1469
+
#define drive_gpio_wan2_pb5 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1470
+
#define drive_gpio_wan1_pb4 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1471
+
#define drive_gen1_i2c_scl_pc5 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1472
+
#define drive_gen1_i2c_sda_pc6 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1473
+
#define drive_uart1_cts_pt3 DRV_PINGROUP_ENTRY_Y(0x5004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1474
+
#define drive_uart1_rts_pt2 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1475
+
#define drive_uart1_rx_pt1 DRV_PINGROUP_ENTRY_Y(0x5014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1476
+
#define drive_uart1_tx_pt0 DRV_PINGROUP_ENTRY_Y(0x501c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1477
+
#define drive_directdc1_out3_pq5 DRV_PINGROUP_ENTRY_Y(0x502c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1478
+
#define drive_directdc1_out2_pq4 DRV_PINGROUP_ENTRY_Y(0x5034, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1479
+
#define drive_directdc1_out1_pq3 DRV_PINGROUP_ENTRY_Y(0x503c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1480
+
#define drive_directdc1_out0_pq2 DRV_PINGROUP_ENTRY_Y(0x5044, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1481
+
#define drive_directdc1_in_pq1 DRV_PINGROUP_ENTRY_Y(0x504c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1482
+
#define drive_directdc1_clk_pq0 DRV_PINGROUP_ENTRY_Y(0x5054, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1483
+
#define drive_gpio_pq0_pi0 DRV_PINGROUP_ENTRY_Y(0x3004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1484
+
#define drive_gpio_pq1_pi1 DRV_PINGROUP_ENTRY_Y(0x300c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1485
+
#define drive_gpio_pq2_pi2 DRV_PINGROUP_ENTRY_Y(0x3014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1486
+
#define drive_gpio_pq3_pi3 DRV_PINGROUP_ENTRY_Y(0x301c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1487
+
#define drive_gpio_pq4_pi4 DRV_PINGROUP_ENTRY_Y(0x3024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1488
+
#define drive_gpio_pq5_pi5 DRV_PINGROUP_ENTRY_Y(0x302c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1489
+
#define drive_gpio_pq6_pi6 DRV_PINGROUP_ENTRY_Y(0x3034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1490
+
#define drive_gpio_pq7_pi7 DRV_PINGROUP_ENTRY_Y(0x303c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1491
+
#define drive_gpio_edp2_pp5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1492
+
#define drive_gpio_edp3_pp6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1493
+
#define drive_gpio_edp0_pp3 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1494
+
#define drive_gpio_edp1_pp4 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1495
+
#define drive_dp_aux_ch0_hpd_pp0 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1496
+
#define drive_dp_aux_ch1_hpd_pp1 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1497
+
#define drive_hdmi_cec_pp2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1498
+
#define drive_pex_l2_clkreq_n_pa6 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1499
+
#define drive_pex_wake_n_pa2 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1500
+
#define drive_pex_l1_clkreq_n_pa4 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1501
+
#define drive_pex_l1_rst_n_pa3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1502
+
#define drive_pex_l0_clkreq_n_pa1 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1503
+
#define drive_pex_l0_rst_n_pa0 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1504
+
#define drive_pex_l2_rst_n_pa5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1505
+
#define drive_sdmmc1_clk_pd0 DRV_PINGROUP_ENTRY_Y(0x8004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1506
+
#define drive_sdmmc1_cmd_pd1 DRV_PINGROUP_ENTRY_Y(0x800c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1507
+
#define drive_sdmmc1_dat3_pd5 DRV_PINGROUP_ENTRY_Y(0x8018, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1508
+
#define drive_sdmmc1_dat2_pd4 DRV_PINGROUP_ENTRY_Y(0x8020, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1509
+
#define drive_sdmmc1_dat1_pd3 DRV_PINGROUP_ENTRY_Y(0x8028, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1510
+
#define drive_sdmmc1_dat0_pd2 DRV_PINGROUP_ENTRY_Y(0x8030, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1511
+
#define drive_eqos_td3_pe4 DRV_PINGROUP_ENTRY_Y(0x9004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1512
+
#define drive_eqos_td2_pe3 DRV_PINGROUP_ENTRY_Y(0x900c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1513
+
#define drive_eqos_td1_pe2 DRV_PINGROUP_ENTRY_Y(0x9014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1514
+
#define drive_eqos_td0_pe1 DRV_PINGROUP_ENTRY_Y(0x901c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1515
+
#define drive_eqos_rd3_pf1 DRV_PINGROUP_ENTRY_Y(0x9024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1516
+
#define drive_eqos_rd2_pf0 DRV_PINGROUP_ENTRY_Y(0x902c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1517
+
#define drive_eqos_rd1_pe7 DRV_PINGROUP_ENTRY_Y(0x9034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1518
+
#define drive_eqos_mdio_pf4 DRV_PINGROUP_ENTRY_Y(0x903c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1519
+
#define drive_eqos_rd0_pe6 DRV_PINGROUP_ENTRY_Y(0x9044, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1520
+
#define drive_eqos_mdc_pf5 DRV_PINGROUP_ENTRY_Y(0x904c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1521
+
#define drive_eqos_txc_pe0 DRV_PINGROUP_ENTRY_Y(0x9058, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1522
+
#define drive_eqos_rxc_pf3 DRV_PINGROUP_ENTRY_Y(0x9060, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1523
+
#define drive_eqos_tx_ctl_pe5 DRV_PINGROUP_ENTRY_Y(0x9068, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1524
+
#define drive_eqos_rx_ctl_pf2 DRV_PINGROUP_ENTRY_Y(0x9070, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1525
+
#define drive_sdmmc3_dat3_pg5 DRV_PINGROUP_ENTRY_Y(0xa004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1526
+
#define drive_sdmmc3_dat2_pg4 DRV_PINGROUP_ENTRY_Y(0xa00c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1527
+
#define drive_sdmmc3_dat1_pg3 DRV_PINGROUP_ENTRY_Y(0xa014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1528
+
#define drive_sdmmc3_dat0_pg2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1529
+
#define drive_sdmmc3_cmd_pg1 DRV_PINGROUP_ENTRY_Y(0xa028, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1530
+
#define drive_sdmmc3_clk_pg0 DRV_PINGROUP_ENTRY_Y(0xa030, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1531
+
#define drive_qspi_io3_pr4 DRV_PINGROUP_ENTRY_Y(0xB004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1532
+
#define drive_qspi_io2_pr3 DRV_PINGROUP_ENTRY_Y(0xB00C, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1533
+
#define drive_qspi_io1_pr2 DRV_PINGROUP_ENTRY_Y(0xB014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1534
+
#define drive_qspi_io0_pr1 DRV_PINGROUP_ENTRY_Y(0xB01C, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1535
+
#define drive_qspi_sck_pr0 DRV_PINGROUP_ENTRY_Y(0xB024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1536
+
#define drive_qspi_cs_n_pr5 DRV_PINGROUP_ENTRY_Y(0xB02C, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1537
+
#define drive_gpio_wan8_ph3 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1538
+
#define drive_gpio_wan7_ph2 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1539
+
#define drive_gpio_wan6_ph1 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1540
+
#define drive_gpio_wan5_ph0 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1541
+
#define drive_uart2_tx_px0 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1542
+
#define drive_uart2_rx_px1 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1543
+
#define drive_uart2_rts_px2 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1544
+
#define drive_uart2_cts_px3 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1545
+
#define drive_uart5_rx_px5 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1546
+
#define drive_uart5_tx_px4 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1547
+
#define drive_uart5_rts_px6 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1548
+
#define drive_uart5_cts_px7 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1549
+
#define drive_gpio_mdm1_py0 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1550
+
#define drive_gpio_mdm2_py1 DRV_PINGROUP_ENTRY_Y(0xd06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1551
+
#define drive_gpio_mdm3_py2 DRV_PINGROUP_ENTRY_Y(0xd074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1552
+
#define drive_gpio_mdm4_py3 DRV_PINGROUP_ENTRY_Y(0xd07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1553
+
#define drive_gpio_mdm5_py4 DRV_PINGROUP_ENTRY_Y(0xd084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1554
+
#define drive_gpio_mdm6_py5 DRV_PINGROUP_ENTRY_Y(0xd08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1555
+
#define drive_gpio_mdm7_py6 DRV_PINGROUP_ENTRY_Y(0xd094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1556
+
#define drive_bcpu_pwr_req_ph4 DRV_PINGROUP_ENTRY_Y(0xd09c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1557
+
#define drive_mcpu_pwr_req_ph5 DRV_PINGROUP_ENTRY_Y(0xd0a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1558
+
#define drive_gpu_pwr_req_ph6 DRV_PINGROUP_ENTRY_Y(0xd0ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1559
+
#define drive_gen7_i2c_scl_pl0 DRV_PINGROUP_ENTRY_Y(0xd0b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1560
+
#define drive_gen7_i2c_sda_pl1 DRV_PINGROUP_ENTRY_Y(0xd0bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1561
+
#define drive_gen9_i2c_sda_pl3 DRV_PINGROUP_ENTRY_Y(0xd0c4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1562
+
#define drive_gen9_i2c_scl_pl2 DRV_PINGROUP_ENTRY_Y(0xd0cc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1563
+
#define drive_usb_vbus_en0_pl4 DRV_PINGROUP_ENTRY_Y(0xd0d4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1564
+
#define drive_usb_vbus_en1_pl5 DRV_PINGROUP_ENTRY_Y(0xd0dc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1565
+
#define drive_gp_pwm7_pl7 DRV_PINGROUP_ENTRY_Y(0xd0e4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1566
+
#define drive_gp_pwm6_pl6 DRV_PINGROUP_ENTRY_Y(0xd0ec, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1567
+
#define drive_ufs0_rst_pbb1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1568
+
#define drive_ufs0_ref_clk_pbb0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1569
+
1570
+
#define drive_directdc_comp DRV_PINGROUP_ENTRY_N(no_entry)
1571
+
#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N(no_entry)
1572
+
#define drive_eqos_comp DRV_PINGROUP_ENTRY_N(no_entry)
1573
+
#define drive_sdmmc3_comp DRV_PINGROUP_ENTRY_N(no_entry)
1574
+
#define drive_sdmmc4_clk DRV_PINGROUP_ENTRY_N(no_entry)
1575
+
#define drive_sdmmc4_cmd DRV_PINGROUP_ENTRY_N(no_entry)
1576
+
#define drive_sdmmc4_dqs DRV_PINGROUP_ENTRY_N(no_entry)
1577
+
#define drive_sdmmc4_dat7 DRV_PINGROUP_ENTRY_N(no_entry)
1578
+
#define drive_sdmmc4_dat6 DRV_PINGROUP_ENTRY_N(no_entry)
1579
+
#define drive_sdmmc4_dat5 DRV_PINGROUP_ENTRY_N(no_entry)
1580
+
#define drive_sdmmc4_dat4 DRV_PINGROUP_ENTRY_N(no_entry)
1581
+
#define drive_sdmmc4_dat3 DRV_PINGROUP_ENTRY_N(no_entry)
1582
+
#define drive_sdmmc4_dat2 DRV_PINGROUP_ENTRY_N(no_entry)
1583
+
#define drive_sdmmc4_dat1 DRV_PINGROUP_ENTRY_N(no_entry)
1584
+
#define drive_sdmmc4_dat0 DRV_PINGROUP_ENTRY_N(no_entry)
1585
+
#define drive_qspi_comp DRV_PINGROUP_ENTRY_N(no_entry)
1586
+
1587
+
/* AON drive pin groups */
1588
+
#define drive_touch_clk_pee2 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1589
+
#define drive_uart3_cts_pw5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1590
+
#define drive_uart3_rts_pw4 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1591
+
#define drive_uart3_rx_pw3 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1592
+
#define drive_uart3_tx_pw2 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1593
+
#define drive_gen8_i2c_sda_pw1 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1594
+
#define drive_gen8_i2c_scl_pw0 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1595
+
#define drive_uart7_rx_pw7 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1596
+
#define drive_uart7_tx_pw6 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1597
+
#define drive_gpio_sen0_pv0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1598
+
#define drive_gpio_sen1_pv1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1599
+
#define drive_gpio_sen2_pv2 DRV_PINGROUP_ENTRY_Y(0x205c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1600
+
#define drive_gpio_sen3_pv3 DRV_PINGROUP_ENTRY_Y(0x2064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1601
+
#define drive_gpio_sen4_pv4 DRV_PINGROUP_ENTRY_Y(0x206c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1602
+
#define drive_gpio_sen5_pv5 DRV_PINGROUP_ENTRY_Y(0x2074, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1603
+
#define drive_gpio_sen6_pv6 DRV_PINGROUP_ENTRY_Y(0x207c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1604
+
#define drive_gpio_sen7_pv7 DRV_PINGROUP_ENTRY_Y(0x2084, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1605
+
#define drive_gpio_sen8_pee0 DRV_PINGROUP_ENTRY_Y(0x208c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1606
+
#define drive_gpio_sen9_pee1 DRV_PINGROUP_ENTRY_Y(0x2094, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1607
+
#define drive_can_gpio7_paa7 DRV_PINGROUP_ENTRY_Y(0x3004, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1608
+
#define drive_can1_dout_pz0 DRV_PINGROUP_ENTRY_Y(0x300C, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1609
+
#define drive_can1_din_pz1 DRV_PINGROUP_ENTRY_Y(0x3014, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1610
+
#define drive_can0_dout_pz2 DRV_PINGROUP_ENTRY_Y(0x301c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1611
+
#define drive_can0_din_pz3 DRV_PINGROUP_ENTRY_Y(0x3024, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1612
+
#define drive_can_gpio0_paa0 DRV_PINGROUP_ENTRY_Y(0x302c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1613
+
#define drive_can_gpio1_paa1 DRV_PINGROUP_ENTRY_Y(0x3034, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1614
+
#define drive_can_gpio2_paa2 DRV_PINGROUP_ENTRY_Y(0x303c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1615
+
#define drive_can_gpio3_paa3 DRV_PINGROUP_ENTRY_Y(0x3044, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1616
+
#define drive_can_gpio4_paa4 DRV_PINGROUP_ENTRY_Y(0x304c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1617
+
#define drive_can_gpio5_paa5 DRV_PINGROUP_ENTRY_Y(0x3054, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1618
+
#define drive_can_gpio6_paa6 DRV_PINGROUP_ENTRY_Y(0x305c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1619
+
#define drive_gpio_sw1_pff1 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1620
+
#define drive_gpio_sw2_pff2 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1621
+
#define drive_gpio_sw3_pff3 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1622
+
#define drive_gpio_sw4_pff4 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1623
+
#define drive_shutdown DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1624
+
#define drive_pmu_int DRV_PINGROUP_ENTRY_Y(0x102C, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1625
+
#define drive_safe_state_ps3 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1626
+
#define drive_vcomp_alert_ps4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1627
+
#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1628
+
#define drive_batt_oc_ps2 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1629
+
#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1630
+
#define drive_power_on_pff0 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1631
+
#define drive_pwr_i2c_scl_ps0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1632
+
#define drive_pwr_i2c_sda_ps1 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1633
+
#define drive_gpio_dis0_pu0 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1634
+
#define drive_gpio_dis1_pu1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1635
+
#define drive_gpio_dis2_pu2 DRV_PINGROUP_ENTRY_Y(0x1094, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1636
+
#define drive_gpio_dis3_pu3 DRV_PINGROUP_ENTRY_Y(0x109c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1637
+
#define drive_gpio_dis4_pu4 DRV_PINGROUP_ENTRY_Y(0x10a4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1638
+
#define drive_gpio_dis5_pu5 DRV_PINGROUP_ENTRY_Y(0x10ac, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1639
+
1640
+
#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1641
+
gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in) \
1642
+
{ \
1643
+
.name = #pg_name, \
1644
+
.pins = pg_name##_pins, \
1645
+
.npins = ARRAY_SIZE(pg_name##_pins), \
1646
+
.funcs = { \
1647
+
TEGRA_MUX_##f0, \
1648
+
TEGRA_MUX_##f1, \
1649
+
TEGRA_MUX_##f2, \
1650
+
TEGRA_MUX_##f3, \
1651
+
}, \
1652
+
PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
1653
+
e_input, e_lpdr, e_pbias_buf, \
1654
+
gpio_sfio_sel, e_od, \
1655
+
schmitt_b, drvtype, \
1656
+
epreemp, io_reset, \
1657
+
rfu_in) \
1658
+
drive_##pg_name, \
1659
+
}
1660
+
1661
+
static const struct tegra_pingroup tegra186_groups[] = {
1662
+
PINGROUP(gpio_aud3_pk0, RSVD0, DSPK1, SPDIF, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1663
+
PINGROUP(gpio_aud2_pj7, RSVD0, DSPK1, SPDIF, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1664
+
PINGROUP(gpio_aud1_pj6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1665
+
PINGROUP(gpio_aud0_pj5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1666
+
PINGROUP(aud_mclk_pj4, AUD, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1667
+
PINGROUP(dap1_fs_pj3, I2S1, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1668
+
PINGROUP(dap1_din_pj2, I2S1, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1669
+
PINGROUP(dap1_dout_pj1, I2S1, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1670
+
PINGROUP(dap1_sclk_pj0, I2S1, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1671
+
PINGROUP(dmic1_clk_pm1, DMIC1, I2S3, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1672
+
PINGROUP(dmic1_dat_pm0, DMIC1, I2S3, RSVD2, RSVD3, 0x2008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1673
+
PINGROUP(dmic2_dat_pm2, DMIC2, I2S3, RSVD2, RSVD3, 0x2010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1674
+
PINGROUP(dmic2_clk_pm3, DMIC2, I2S3, RSVD2, RSVD3, 0x2018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1675
+
PINGROUP(dmic4_dat_pm4, DMIC4, DSPK0, RSVD2, RSVD3, 0x2020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1676
+
PINGROUP(dmic4_clk_pm5, DMIC4, DSPK0, RSVD2, RSVD3, 0x2028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1677
+
PINGROUP(dap4_fs_pcc3, I2S4, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1678
+
PINGROUP(dap4_din_pcc2, I2S4, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1679
+
PINGROUP(dap4_dout_pcc1, I2S4, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1680
+
PINGROUP(dap4_sclk_pcc0, I2S4, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1681
+
PINGROUP(extperiph2_clk_po1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1682
+
PINGROUP(extperiph1_clk_po0, EXTPERIPH1, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1683
+
PINGROUP(cam_i2c_sda_po3, I2C3, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1684
+
PINGROUP(cam_i2c_scl_po2, I2C3, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1685
+
PINGROUP(gpio_cam1_pn0, VGP1, RSVD1, RSVD2, RSVD3, 0x0020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1686
+
PINGROUP(gpio_cam2_pn1, VGP2, EXTPERIPH3, RSVD2, RSVD3, 0x0028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1687
+
PINGROUP(gpio_cam3_pn2, VGP3, EXTPERIPH4, RSVD2, RSVD3, 0x0030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1688
+
PINGROUP(gpio_cam4_pn3, VGP4, SPI4, RSVD2, RSVD3, 0x0038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1689
+
PINGROUP(gpio_cam5_pn4, VGP5, SPI4, RSVD2, RSVD3, 0x0040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1690
+
PINGROUP(gpio_cam6_pn5, VGP6, SPI4, RSVD2, RSVD3, 0x0048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1691
+
PINGROUP(gpio_cam7_pn6, RSVD0, SPI4, RSVD2, RSVD3, 0x0050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1692
+
PINGROUP(dap2_din_pc3, I2S2, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1693
+
PINGROUP(dap2_dout_pc2, I2S2, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1694
+
PINGROUP(dap2_fs_pc4, I2S2, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1695
+
PINGROUP(dap2_sclk_pc1, I2S2, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1696
+
PINGROUP(uart4_cts_pb3, UARTD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1697
+
PINGROUP(uart4_rts_pb2, UARTD, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1698
+
PINGROUP(uart4_rx_pb1, UARTD, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1699
+
PINGROUP(uart4_tx_pb0, UARTD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1700
+
PINGROUP(gpio_wan4_pc0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1701
+
PINGROUP(gpio_wan3_pb6, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1702
+
PINGROUP(gpio_wan2_pb5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1703
+
PINGROUP(gpio_wan1_pb4, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1704
+
PINGROUP(gen1_i2c_scl_pc5, I2C1, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1705
+
PINGROUP(gen1_i2c_sda_pc6, I2C1, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1706
+
PINGROUP(uart1_cts_pt3, UARTA, RSVD1, RSVD2, RSVD3, 0x5000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1707
+
PINGROUP(uart1_rts_pt2, UARTA, RSVD1, RSVD2, RSVD3, 0x5008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1708
+
PINGROUP(uart1_rx_pt1, UARTA, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1709
+
PINGROUP(uart1_tx_pt0, UARTA, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1710
+
PINGROUP(directdc1_out3_pq5, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1711
+
PINGROUP(directdc1_out2_pq4, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1712
+
PINGROUP(directdc1_out1_pq3, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1713
+
PINGROUP(directdc1_out0_pq2, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1714
+
PINGROUP(directdc1_in_pq1, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1715
+
PINGROUP(directdc1_clk_pq0, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1716
+
PINGROUP(directdc_comp, DIRECTDC, RSVD1, RSVD2, RSVD3, 0x5058, 0, Y, -1, -1, -1, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1717
+
PINGROUP(gpio_pq0_pi0, RSVD0, IQC0, I2S6, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1718
+
PINGROUP(gpio_pq1_pi1, RSVD0, IQC0, I2S6, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1719
+
PINGROUP(gpio_pq2_pi2, RSVD0, IQC0, I2S6, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1720
+
PINGROUP(gpio_pq3_pi3, RSVD0, IQC0, I2S6, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1721
+
PINGROUP(gpio_pq4_pi4, RSVD0, IQC1, DTV, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1722
+
PINGROUP(gpio_pq5_pi5, RSVD0, IQC1, DTV, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1723
+
PINGROUP(gpio_pq6_pi6, RSVD0, IQC1, DTV, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1724
+
PINGROUP(gpio_pq7_pi7, RSVD0, IQC1, DTV, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1725
+
PINGROUP(gpio_edp2_pp5, RSVD0, UARTF, SDMMC3, RSVD3, 0x10000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1726
+
PINGROUP(gpio_edp3_pp6, RSVD0, UARTF, SDMMC1, RSVD3, 0x10008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1727
+
PINGROUP(gpio_edp0_pp3, RSVD0, UARTF, SDMMC3, RSVD3, 0x10010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1728
+
PINGROUP(gpio_edp1_pp4, RSVD0, UARTF, SDMMC1, RSVD3, 0x10018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1729
+
PINGROUP(dp_aux_ch0_hpd_pp0, DP, RSVD1, RSVD2, RSVD3, 0x10020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1730
+
PINGROUP(dp_aux_ch1_hpd_pp1, DP, RSVD1, RSVD2, RSVD3, 0x10028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1731
+
PINGROUP(hdmi_cec_pp2, HDMI, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1732
+
PINGROUP(pex_l2_clkreq_n_pa6, PE2, GP, SATA, RSVD3, 0x7000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1733
+
PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1734
+
PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1735
+
PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1736
+
PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1737
+
PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1738
+
PINGROUP(pex_l2_rst_n_pa5, PE2, SOC, SATA, RSVD3, 0x7030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1739
+
PINGROUP(sdmmc1_clk_pd0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, 5, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1740
+
PINGROUP(sdmmc1_cmd_pd1, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1741
+
PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, N, -1, -1, N),
1742
+
PINGROUP(sdmmc1_dat3_pd5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8014, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1743
+
PINGROUP(sdmmc1_dat2_pd4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x801c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1744
+
PINGROUP(sdmmc1_dat1_pd3, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8024, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1745
+
PINGROUP(sdmmc1_dat0_pd2, SDMMC1, RSVD1, RSVD2, RSVD3, 0x802c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1746
+
PINGROUP(eqos_td3_pe4, EQOS, SDMMC2, RSVD2, RSVD3, 0x9000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1747
+
PINGROUP(eqos_td2_pe3, EQOS, SDMMC2, RSVD2, RSVD3, 0x9008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1748
+
PINGROUP(eqos_td1_pe2, EQOS, SDMMC2, RSVD2, RSVD3, 0x9010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1749
+
PINGROUP(eqos_td0_pe1, EQOS, SDMMC2, RSVD2, RSVD3, 0x9018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1750
+
PINGROUP(eqos_rd3_pf1, EQOS, SDMMC2, RSVD2, RSVD3, 0x9020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1751
+
PINGROUP(eqos_rd2_pf0, EQOS, SDMMC2, RSVD2, RSVD3, 0x9028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1752
+
PINGROUP(eqos_rd1_pe7, EQOS, SDMMC2, RSVD2, RSVD3, 0x9030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1753
+
PINGROUP(eqos_mdio_pf4, EQOS, SOC, RSVD2, RSVD3, 0x9038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1754
+
PINGROUP(eqos_rd0_pe6, EQOS, SDMMC2, RSVD2, RSVD3, 0x9040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1755
+
PINGROUP(eqos_mdc_pf5, EQOS, RSVD1, RSVD2, RSVD3, 0x9048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1756
+
PINGROUP(eqos_comp, EQOS, SDMMC2, RSVD2, RSVD3, 0x9050, 0, Y, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N),
1757
+
PINGROUP(eqos_txc_pe0, EQOS, SDMMC2, RSVD2, RSVD3, 0x9054, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1758
+
PINGROUP(eqos_rxc_pf3, EQOS, SDMMC2, RSVD2, RSVD3, 0x905c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1759
+
PINGROUP(eqos_tx_ctl_pe5, EQOS, SDMMC2, RSVD2, RSVD3, 0x9064, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1760
+
PINGROUP(eqos_rx_ctl_pf2, EQOS, SDMMC2, RSVD2, RSVD3, 0x906c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1761
+
PINGROUP(sdmmc3_dat3_pg5, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1762
+
PINGROUP(sdmmc3_dat2_pg4, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1763
+
PINGROUP(sdmmc3_dat1_pg3, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1764
+
PINGROUP(sdmmc3_dat0_pg2, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1765
+
PINGROUP(sdmmc3_comp, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa020, 0, Y, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N),
1766
+
PINGROUP(sdmmc3_cmd_pg1, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa024, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1767
+
PINGROUP(sdmmc3_clk_pg0, SDMMC3, RSVD1, RSVD1, RSVD3, 0xa02c, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1768
+
PINGROUP(sdmmc4_clk, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6004, 0, Y, -1, 5, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1769
+
PINGROUP(sdmmc4_cmd, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1770
+
PINGROUP(sdmmc4_dqs, SDMMC4, RSVD1, RSVD2, RSVD3, 0x600c, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1771
+
PINGROUP(sdmmc4_dat7, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1772
+
PINGROUP(sdmmc4_dat6, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6014, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1773
+
PINGROUP(sdmmc4_dat5, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1774
+
PINGROUP(sdmmc4_dat4, SDMMC4, RSVD1, RSVD2, RSVD3, 0x601c, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1775
+
PINGROUP(sdmmc4_dat3, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6020, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1776
+
PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6024, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1777
+
PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6028, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1778
+
PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x602c, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1779
+
PINGROUP(qspi_io3_pr4, QSPI, RSVD1, RSVD2, RSVD3, 0xB000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1780
+
PINGROUP(qspi_io2_pr3, QSPI, RSVD1, RSVD2, RSVD3, 0xB008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1781
+
PINGROUP(qspi_io1_pr2, QSPI, RSVD1, RSVD2, RSVD3, 0xB010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1782
+
PINGROUP(qspi_io0_pr1, QSPI, RSVD1, RSVD2, RSVD3, 0xB018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1783
+
PINGROUP(qspi_sck_pr0, QSPI, RSVD1, RSVD2, RSVD3, 0xB020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1784
+
PINGROUP(qspi_cs_n_pr5, QSPI, RSVD1, RSVD2, RSVD3, 0xB028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1785
+
PINGROUP(qspi_comp, QSPI, RSVD1, RSVD2, RSVD3, 0xB030, 0, Y, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y),
1786
+
PINGROUP(gpio_wan8_ph3, RSVD0, RSVD1, SPI1, RSVD3, 0xd000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1787
+
PINGROUP(gpio_wan7_ph2, RSVD0, RSVD1, SPI1, RSVD3, 0xd008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1788
+
PINGROUP(gpio_wan6_ph1, RSVD0, RSVD1, SPI1, RSVD3, 0xd010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1789
+
PINGROUP(gpio_wan5_ph0, RSVD0, RSVD1, SPI1, RSVD3, 0xd018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1790
+
PINGROUP(uart2_tx_px0, UARTB, RSVD1, RSVD2, RSVD3, 0xd020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1791
+
PINGROUP(uart2_rx_px1, UARTB, RSVD1, RSVD2, RSVD3, 0xd028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1792
+
PINGROUP(uart2_rts_px2, UARTB, RSVD1, RSVD2, RSVD3, 0xd030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1793
+
PINGROUP(uart2_cts_px3, UARTB, RSVD1, RSVD2, RSVD3, 0xd038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1794
+
PINGROUP(uart5_rx_px5, UARTE, SPI3, GP, RSVD3, 0xd040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1795
+
PINGROUP(uart5_tx_px4, UARTE, SPI3, NV, RSVD3, 0xd048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1796
+
PINGROUP(uart5_rts_px6, UARTE, SPI3, RSVD2, RSVD3, 0xd050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1797
+
PINGROUP(uart5_cts_px7, UARTE, SPI3, RSVD2, RSVD3, 0xd058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1798
+
PINGROUP(gpio_mdm1_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0xd060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1799
+
PINGROUP(gpio_mdm2_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0xd068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1800
+
PINGROUP(gpio_mdm3_py2, RSVD0, RSVD1, RSVD2, RSVD3, 0xd070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1801
+
PINGROUP(gpio_mdm4_py3, RSVD0, SPI1, CCLA, RSVD3, 0xd078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1802
+
PINGROUP(gpio_mdm5_py4, RSVD0, SPI1, RSVD2, RSVD3, 0xd080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1803
+
PINGROUP(gpio_mdm6_py5, SOC, RSVD1, RSVD2, RSVD3, 0xd088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1804
+
PINGROUP(gpio_mdm7_py6, RSVD0, RSVD1, RSVD2, RSVD3, 0xd090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1805
+
PINGROUP(bcpu_pwr_req_ph4, RSVD0, RSVD1, RSVD2, RSVD3, 0xd098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1806
+
PINGROUP(mcpu_pwr_req_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0xd0a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1807
+
PINGROUP(gpu_pwr_req_ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0xd0a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1808
+
PINGROUP(gen7_i2c_scl_pl0, I2C7, I2S5, RSVD2, RSVD3, 0xd0b0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1809
+
PINGROUP(gen7_i2c_sda_pl1, I2C7, I2S5, RSVD2, RSVD3, 0xd0b8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1810
+
PINGROUP(gen9_i2c_sda_pl3, I2C9, I2S5, RSVD2, RSVD3, 0xd0c0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1811
+
PINGROUP(gen9_i2c_scl_pl2, I2C9, I2S5, RSVD2, RSVD3, 0xd0c8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1812
+
PINGROUP(usb_vbus_en0_pl4, USB, RSVD1, RSVD2, RSVD3, 0xd0d0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1813
+
PINGROUP(usb_vbus_en1_pl5, USB, RSVD1, RSVD2, RSVD3, 0xd0d8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1814
+
PINGROUP(gp_pwm7_pl7, GP, RSVD1, RSVD2, RSVD3, 0xd0e0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1815
+
PINGROUP(gp_pwm6_pl6, GP, RSVD1, RSVD2, RSVD3, 0xd0e8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1816
+
PINGROUP(ufs0_rst_pbb1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1817
+
PINGROUP(ufs0_ref_clk_pbb0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1818
+
};
1819
+
1820
+
static const struct tegra_pinctrl_soc_data tegra186_pinctrl = {
1821
+
.pins = tegra186_pins,
1822
+
.npins = ARRAY_SIZE(tegra186_pins),
1823
+
.functions = tegra186_functions,
1824
+
.nfunctions = ARRAY_SIZE(tegra186_functions),
1825
+
.groups = tegra186_groups,
1826
+
.ngroups = ARRAY_SIZE(tegra186_groups),
1827
+
.hsm_in_mux = false,
1828
+
.schmitt_in_mux = true,
1829
+
.drvtype_in_mux = true,
1830
+
.sfsel_in_mux = true,
1831
+
};
1832
+
1833
+
static const struct pinctrl_pin_desc tegra186_aon_pins[] = {
1834
+
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PS0, "PWR_I2C_SCL_PS0"),
1835
+
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PS1, "PWR_I2C_SDA_PS1"),
1836
+
PINCTRL_PIN(TEGRA_PIN_BATT_OC_PS2, "BATT_OC_PS2"),
1837
+
PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PS3, "SAFE_STATE_PS3"),
1838
+
PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PS4, "VCOMP_ALERT_PS4"),
1839
+
PINCTRL_PIN(TEGRA_PIN_GPIO_DIS0_PU0, "GPIO_DIS0_PU0"),
1840
+
PINCTRL_PIN(TEGRA_PIN_GPIO_DIS1_PU1, "GPIO_DIS1_PU1"),
1841
+
PINCTRL_PIN(TEGRA_PIN_GPIO_DIS2_PU2, "GPIO_DIS2_PU2"),
1842
+
PINCTRL_PIN(TEGRA_PIN_GPIO_DIS3_PU3, "GPIO_DIS3_PU3"),
1843
+
PINCTRL_PIN(TEGRA_PIN_GPIO_DIS4_PU4, "GPIO_DIS4_PU4"),
1844
+
PINCTRL_PIN(TEGRA_PIN_GPIO_DIS5_PU5, "GPIO_DIS5_PU5"),
1845
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN0_PV0, "GPIO_SEN0_PV0"),
1846
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN1_PV1, "GPIO_SEN1_PV1"),
1847
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN2_PV2, "GPIO_SEN2_PV2"),
1848
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN3_PV3, "GPIO_SEN3_PV3"),
1849
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN4_PV4, "GPIO_SEN4_PV4"),
1850
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN5_PV5, "GPIO_SEN5_PV5"),
1851
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN6_PV6, "GPIO_SEN6_PV6"),
1852
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN7_PV7, "GPIO_SEN7_PV7"),
1853
+
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PW0, "GEN8_I2C_SCL_PW0"),
1854
+
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PW1, "GEN8_I2C_SDA_PW1"),
1855
+
PINCTRL_PIN(TEGRA_PIN_UART3_TX_PW2, "UART3_TX_PW2"),
1856
+
PINCTRL_PIN(TEGRA_PIN_UART3_RX_PW3, "UART3_RX_PW3"),
1857
+
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PW4, "UART3_RTS_PW4"),
1858
+
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PW5, "UART3_CTS_PW5"),
1859
+
PINCTRL_PIN(TEGRA_PIN_UART7_TX_PW6, "UART7_TX_PW6"),
1860
+
PINCTRL_PIN(TEGRA_PIN_UART7_RX_PW7, "UART7_RX_PW7"),
1861
+
PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PZ0, "CAN1_DOUT_PZ0"),
1862
+
PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PZ1, "CAN1_DIN_PZ1"),
1863
+
PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PZ2, "CAN0_DOUT_PZ2"),
1864
+
PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PZ3, "CAN0_DIN_PZ3"),
1865
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO0_PAA0, "CAN_GPIO0_PAA0"),
1866
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO1_PAA1, "CAN_GPIO1_PAA1"),
1867
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO2_PAA2, "CAN_GPIO2_PAA2"),
1868
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO3_PAA3, "CAN_GPIO3_PAA3"),
1869
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO4_PAA4, "CAN_GPIO4_PAA4"),
1870
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO5_PAA5, "CAN_GPIO5_PAA5"),
1871
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO6_PAA6, "CAN_GPIO6_PAA6"),
1872
+
PINCTRL_PIN(TEGRA_PIN_CAN_GPIO7_PAA7, "CAN_GPIO7_PAA7"),
1873
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN8_PEE0, "GPIO_SEN8_PEE0"),
1874
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SEN9_PEE1, "GPIO_SEN9_PEE1"),
1875
+
PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PEE2, "TOUCH_CLK_PEE2"),
1876
+
PINCTRL_PIN(TEGRA_PIN_POWER_ON_PFF0, "POWER_ON_PFF0"),
1877
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SW1_PFF1, "GPIO_SW1_PFF1"),
1878
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SW2_PFF2, "GPIO_SW2_PFF2"),
1879
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SW3_PFF3, "GPIO_SW3_PFF3"),
1880
+
PINCTRL_PIN(TEGRA_PIN_GPIO_SW4_PFF4, "GPIO_SW4_PFF4"),
1881
+
PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
1882
+
PINCTRL_PIN(TEGRA_PIN_PMU_INT, "PMU_INT"),
1883
+
PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
1884
+
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
1885
+
};
1886
+
1887
+
static const struct tegra_pingroup tegra186_aon_groups[] = {
1888
+
PINGROUP(touch_clk_pee2, TOUCH, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1889
+
PINGROUP(uart3_cts_pw5, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1890
+
PINGROUP(uart3_rts_pw4, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1891
+
PINGROUP(uart3_rx_pw3, UARTC, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1892
+
PINGROUP(uart3_tx_pw2, UARTC, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1893
+
PINGROUP(gen8_i2c_sda_pw1, I2C8, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1894
+
PINGROUP(gen8_i2c_scl_pw0, I2C8, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1895
+
PINGROUP(uart7_rx_pw7, UARTG, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1896
+
PINGROUP(uart7_tx_pw6, UARTG, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1897
+
PINGROUP(gpio_sen0_pv0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1898
+
PINGROUP(gpio_sen1_pv1, SPI2, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1899
+
PINGROUP(gpio_sen2_pv2, SPI2, RSVD1, RSVD2, RSVD3, 0x2058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1900
+
PINGROUP(gpio_sen3_pv3, SPI2, RSVD1, RSVD2, RSVD3, 0x2060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1901
+
PINGROUP(gpio_sen4_pv4, SPI2, RSVD1, RSVD2, RSVD3, 0x2068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1902
+
PINGROUP(gpio_sen5_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x2070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1903
+
PINGROUP(gpio_sen6_pv6, RSVD0, GP, RSVD2, RSVD3, 0x2078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1904
+
PINGROUP(gpio_sen7_pv7, RSVD0, WDT, RSVD2, RSVD3, 0x2080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1905
+
PINGROUP(gpio_sen8_pee0, RSVD0, I2C2, RSVD2, RSVD3, 0x2088, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1906
+
PINGROUP(gpio_sen9_pee1, RSVD0, I2C2, RSVD2, RSVD3, 0x2090, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1907
+
PINGROUP(can_gpio7_paa7, RSVD0, WDT, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1908
+
PINGROUP(can1_dout_pz0, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1909
+
PINGROUP(can1_din_pz1, CAN1, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1910
+
PINGROUP(can0_dout_pz2, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1911
+
PINGROUP(can0_din_pz3, CAN0, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1912
+
PINGROUP(can_gpio0_paa0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1913
+
PINGROUP(can_gpio1_paa1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1914
+
PINGROUP(can_gpio2_paa2, GPIO, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1915
+
PINGROUP(can_gpio3_paa3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1916
+
PINGROUP(can_gpio4_paa4, RSVD0, RSVD1, RSVD2, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1917
+
PINGROUP(can_gpio5_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1918
+
PINGROUP(can_gpio6_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1919
+
PINGROUP(gpio_sw1_pff1, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1920
+
PINGROUP(gpio_sw2_pff2, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1921
+
PINGROUP(gpio_sw3_pff3, RSVD0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1922
+
PINGROUP(gpio_sw4_pff4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1923
+
PINGROUP(shutdown, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N),
1924
+
PINGROUP(pmu_int, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N),
1925
+
PINGROUP(safe_state_ps3, SCE, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1926
+
PINGROUP(vcomp_alert_ps4, SOC, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1927
+
PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N),
1928
+
PINGROUP(batt_oc_ps2, SOC, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1929
+
PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1050, 0, Y, -1, -1, 6, 8, -1, -1, -1, -1, N, -1, -1, N),
1930
+
PINGROUP(power_on_pff0, RSVD0, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1931
+
PINGROUP(pwr_i2c_scl_ps0, I2C5, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1932
+
PINGROUP(pwr_i2c_sda_ps1, I2C5, RSVD1, RSVD2, RSVD3, 0x1068, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1933
+
PINGROUP(gpio_dis0_pu0, RSVD0, GP, DCB, DCC, 0x1080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1934
+
PINGROUP(gpio_dis1_pu1, RSVD0, RSVD1, DISPLAYA, RSVD3, 0x1088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1935
+
PINGROUP(gpio_dis2_pu2, RSVD0, GP, DCA, RSVD3, 0x1090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1936
+
PINGROUP(gpio_dis3_pu3, RSVD0, RSVD1, DISPLAYB, DCC, 0x1098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1937
+
PINGROUP(gpio_dis4_pu4, RSVD0, SOC, DCA, RSVD3, 0x10a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1938
+
PINGROUP(gpio_dis5_pu5, RSVD0, GP, DCC, DCB, 0x10a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1939
+
};
1940
+
1941
+
static const struct tegra_pinctrl_soc_data tegra186_pinctrl_aon = {
1942
+
.pins = tegra186_aon_pins,
1943
+
.npins = ARRAY_SIZE(tegra186_aon_pins),
1944
+
.functions = tegra186_functions,
1945
+
.nfunctions = ARRAY_SIZE(tegra186_functions),
1946
+
.groups = tegra186_aon_groups,
1947
+
.ngroups = ARRAY_SIZE(tegra186_aon_groups),
1948
+
.hsm_in_mux = false,
1949
+
.schmitt_in_mux = true,
1950
+
.drvtype_in_mux = true,
1951
+
.sfsel_in_mux = true,
1952
+
};
1953
+
1954
+
static int tegra186_pinctrl_probe(struct platform_device *pdev)
1955
+
{
1956
+
const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);
1957
+
1958
+
return tegra_pinctrl_probe(pdev, soc);
1959
+
}
1960
+
1961
+
static const struct of_device_id tegra186_pinctrl_of_match[] = {
1962
+
{ .compatible = "nvidia,tegra186-pinmux", .data = &tegra186_pinctrl },
1963
+
{ .compatible = "nvidia,tegra186-pinmux-aon", .data = &tegra186_pinctrl_aon },
1964
+
{ },
1965
+
};
1966
+
1967
+
static struct platform_driver tegra186_pinctrl_driver = {
1968
+
.driver = {
1969
+
.name = "tegra186-pinctrl",
1970
+
.of_match_table = tegra186_pinctrl_of_match,
1971
+
},
1972
+
.probe = tegra186_pinctrl_probe,
1973
+
};
1974
+
1975
+
static int __init tegra186_pinctrl_init(void)
1976
+
{
1977
+
return platform_driver_register(&tegra186_pinctrl_driver);
1978
+
}
1979
+
arch_initcall(tegra186_pinctrl_init);
+1
drivers/soc/tegra/Kconfig
+1
drivers/soc/tegra/Kconfig
+1
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+1
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+1
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+1
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+22
include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
+22
include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* This header provides constants for Renesas RZ/T2H family pinctrl bindings.
4
+
*
5
+
* Copyright (C) 2025 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
9
+
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
10
+
11
+
#define RZT2H_PINS_PER_PORT 8
12
+
13
+
/*
14
+
* Create the pin index from its bank and position numbers and store in
15
+
* the upper 16 bits the alternate function identifier
16
+
*/
17
+
#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
18
+
19
+
/* Convert a port and pin label to its global pin index */
20
+
#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin))
21
+
22
+
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */
+2
include/linux/device/devres.h
+2
include/linux/device/devres.h
···
80
80
81
81
void * __realloc_size(3)
82
82
devm_kmemdup(struct device *dev, const void *src, size_t len, gfp_t gfp);
83
+
const void *
84
+
devm_kmemdup_const(struct device *dev, const void *src, size_t len, gfp_t gfp);
83
85
static inline void *devm_kmemdup_array(struct device *dev, const void *src,
84
86
size_t n, size_t size, gfp_t flags)
85
87
{
+8
-4
include/linux/pinctrl/pinconf-generic.h
+8
-4
include/linux/pinctrl/pinconf-generic.h
···
88
88
* passed in the argument on a custom form, else just use argument 1
89
89
* to indicate low power mode, argument 0 turns low power mode off.
90
90
* @PIN_CONFIG_MODE_PWM: this will configure the pin for PWM
91
-
* @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
92
-
* value on the line. Use argument 1 to indicate high level, argument 0 to
93
-
* indicate low level. (Please see Documentation/driver-api/pin-control.rst,
91
+
* @PIN_CONFIG_LEVEL: setting this will configure the pin as an output and
92
+
* drive a value on the line. Use argument 1 to indicate high level,
93
+
* argument 0 to indicate low level. Conversely the value of the line
94
+
* can be read using this parameter, if and only if that value can be
95
+
* represented as a binary 0 or 1 where 0 indicate a low voltage level
96
+
* and 1 indicate a high voltage level.
97
+
* (Please see Documentation/driver-api/pin-control.rst,
94
98
* section "GPIO mode pitfalls" for a discussion around this parameter.)
95
99
* @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
96
100
* without driving a value there. For most platforms this reduces to
···
141
137
PIN_CONFIG_INPUT_SCHMITT_UV,
142
138
PIN_CONFIG_MODE_LOW_POWER,
143
139
PIN_CONFIG_MODE_PWM,
144
-
PIN_CONFIG_OUTPUT,
140
+
PIN_CONFIG_LEVEL,
145
141
PIN_CONFIG_OUTPUT_ENABLE,
146
142
PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS,
147
143
PIN_CONFIG_PERSIST_STATE,
+14
include/linux/pinctrl/pinctrl.h
+14
include/linux/pinctrl/pinctrl.h
···
11
11
#ifndef __LINUX_PINCTRL_PINCTRL_H
12
12
#define __LINUX_PINCTRL_PINCTRL_H
13
13
14
+
#include <linux/bits.h>
14
15
#include <linux/types.h>
15
16
16
17
struct device;
···
207
206
const char *pin_group, const unsigned int **pins,
208
207
unsigned int *num_pins);
209
208
209
+
#define PINFUNCTION_FLAG_GPIO BIT(0)
210
+
210
211
/**
211
212
* struct pinfunction - Description about a function
212
213
* @name: Name of the function
213
214
* @groups: An array of groups for this function
214
215
* @ngroups: Number of groups in @groups
216
+
* @flags: Additional pin function flags
215
217
*/
216
218
struct pinfunction {
217
219
const char *name;
218
220
const char * const *groups;
219
221
size_t ngroups;
222
+
unsigned long flags;
220
223
};
221
224
222
225
/* Convenience macro to define a single named pinfunction */
···
229
224
.name = (_name), \
230
225
.groups = (_groups), \
231
226
.ngroups = (_ngroups), \
227
+
}
228
+
229
+
/* Same as PINCTRL_PINFUNCTION() but for the GPIO category of functions */
230
+
#define PINCTRL_GPIO_PINFUNCTION(_name, _groups, _ngroups) \
231
+
(struct pinfunction) { \
232
+
.name = (_name), \
233
+
.groups = (_groups), \
234
+
.ngroups = (_ngroups), \
235
+
.flags = PINFUNCTION_FLAG_GPIO, \
232
236
}
233
237
234
238
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PINCTRL)
+2
include/linux/pinctrl/pinmux.h
+2
include/linux/pinctrl/pinmux.h
···
66
66
unsigned int selector,
67
67
const char * const **groups,
68
68
unsigned int *num_groups);
69
+
bool (*function_is_gpio) (struct pinctrl_dev *pctldev,
70
+
unsigned int selector);
69
71
int (*set_mux) (struct pinctrl_dev *pctldev, unsigned int func_selector,
70
72
unsigned int group_selector);
71
73
int (*gpio_request_enable) (struct pinctrl_dev *pctldev,