Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'parisc-4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc fixes from Helge Deller:
- a patch to change the ordering of cache and TLB flushes to hopefully
fix the random segfaults we very rarely face (by Dave Anglin).
- a patch to hide the virtual kernel memory layout due to security
reasons.
- two small patches to make the kernel run more smoothly under qemu.
* 'parisc-4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Reduce irq overhead when run in qemu
parisc: Use cr16 interval timers unconditionally on qemu
parisc: Check if secondary CPUs want own PDC calls
parisc: Hide virtual kernel memory layout
parisc: Fix ordering of cache and TLB flushes
+86
-39
+1
arch/parisc/include/asm/cacheflush.h
+1
arch/parisc/include/asm/cacheflush.h
···
26
26
void flush_kernel_icache_range_asm(unsigned long, unsigned long);
27
27
void flush_user_dcache_range_asm(unsigned long, unsigned long);
28
28
void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
29
+
void purge_kernel_dcache_range_asm(unsigned long, unsigned long);
29
30
void flush_kernel_dcache_page_asm(void *);
30
31
void flush_kernel_icache_page(void *);
31
32
+2
arch/parisc/include/asm/processor.h
+2
arch/parisc/include/asm/processor.h
+31
-26
arch/parisc/kernel/cache.c
+31
-26
arch/parisc/kernel/cache.c
···
465
465
int __flush_tlb_range(unsigned long sid, unsigned long start,
466
466
unsigned long end)
467
467
{
468
-
unsigned long flags, size;
468
+
unsigned long flags;
469
469
470
-
size = (end - start);
471
-
if (size >= parisc_tlb_flush_threshold) {
470
+
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
471
+
end - start >= parisc_tlb_flush_threshold) {
472
472
flush_tlb_all();
473
473
return 1;
474
474
}
···
539
539
struct vm_area_struct *vma;
540
540
pgd_t *pgd;
541
541
542
-
/* Flush the TLB to avoid speculation if coherency is required. */
543
-
if (parisc_requires_coherency())
544
-
flush_tlb_all();
545
-
546
542
/* Flushing the whole cache on each cpu takes forever on
547
543
rp3440, etc. So, avoid it if the mm isn't too big. */
548
-
if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
544
+
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
545
+
mm_total_size(mm) >= parisc_cache_flush_threshold) {
546
+
flush_tlb_all();
549
547
flush_cache_all();
550
548
return;
551
549
}
···
551
553
if (mm->context == mfsp(3)) {
552
554
for (vma = mm->mmap; vma; vma = vma->vm_next) {
553
555
flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
554
-
if ((vma->vm_flags & VM_EXEC) == 0)
555
-
continue;
556
-
flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
556
+
if (vma->vm_flags & VM_EXEC)
557
+
flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
558
+
flush_tlb_range(vma, vma->vm_start, vma->vm_end);
557
559
}
558
560
return;
559
561
}
···
579
581
void flush_cache_range(struct vm_area_struct *vma,
580
582
unsigned long start, unsigned long end)
581
583
{
582
-
BUG_ON(!vma->vm_mm->context);
583
-
584
-
/* Flush the TLB to avoid speculation if coherency is required. */
585
-
if (parisc_requires_coherency())
584
+
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
585
+
end - start >= parisc_cache_flush_threshold) {
586
586
flush_tlb_range(vma, start, end);
587
-
588
-
if ((end - start) >= parisc_cache_flush_threshold
589
-
|| vma->vm_mm->context != mfsp(3)) {
590
587
flush_cache_all();
591
588
return;
592
589
}
···
589
596
flush_user_dcache_range_asm(start, end);
590
597
if (vma->vm_flags & VM_EXEC)
591
598
flush_user_icache_range_asm(start, end);
599
+
flush_tlb_range(vma, start, end);
592
600
}
593
601
594
602
void
···
598
604
BUG_ON(!vma->vm_mm->context);
599
605
600
606
if (pfn_valid(pfn)) {
601
-
if (parisc_requires_coherency())
602
-
flush_tlb_page(vma, vmaddr);
607
+
flush_tlb_page(vma, vmaddr);
603
608
__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
604
609
}
605
610
}
···
606
613
void flush_kernel_vmap_range(void *vaddr, int size)
607
614
{
608
615
unsigned long start = (unsigned long)vaddr;
616
+
unsigned long end = start + size;
609
617
610
-
if ((unsigned long)size > parisc_cache_flush_threshold)
618
+
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
619
+
(unsigned long)size >= parisc_cache_flush_threshold) {
620
+
flush_tlb_kernel_range(start, end);
611
621
flush_data_cache();
612
-
else
613
-
flush_kernel_dcache_range_asm(start, start + size);
622
+
return;
623
+
}
624
+
625
+
flush_kernel_dcache_range_asm(start, end);
626
+
flush_tlb_kernel_range(start, end);
614
627
}
615
628
EXPORT_SYMBOL(flush_kernel_vmap_range);
616
629
617
630
void invalidate_kernel_vmap_range(void *vaddr, int size)
618
631
{
619
632
unsigned long start = (unsigned long)vaddr;
633
+
unsigned long end = start + size;
620
634
621
-
if ((unsigned long)size > parisc_cache_flush_threshold)
635
+
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
636
+
(unsigned long)size >= parisc_cache_flush_threshold) {
637
+
flush_tlb_kernel_range(start, end);
622
638
flush_data_cache();
623
-
else
624
-
flush_kernel_dcache_range_asm(start, start + size);
639
+
return;
640
+
}
641
+
642
+
purge_kernel_dcache_range_asm(start, end);
643
+
flush_tlb_kernel_range(start, end);
625
644
}
626
645
EXPORT_SYMBOL(invalidate_kernel_vmap_range);
+12
-6
arch/parisc/kernel/head.S
+12
-6
arch/parisc/kernel/head.S
···
138
138
std %dp,0x18(%r10)
139
139
#endif
140
140
141
+
#ifdef CONFIG_64BIT
142
+
/* Get PDCE_PROC for monarch CPU. */
143
+
#define MEM_PDC_LO 0x388
144
+
#define MEM_PDC_HI 0x35C
145
+
ldw MEM_PDC_LO(%r0),%r3
146
+
ldw MEM_PDC_HI(%r0),%r10
147
+
depd %r10, 31, 32, %r3 /* move to upper word */
148
+
#endif
149
+
150
+
141
151
#ifdef CONFIG_SMP
142
152
/* Set the smp rendezvous address into page zero.
143
153
** It would be safer to do this in init_smp_config() but
···
206
196
** Someday, palo might not do this for the Monarch either.
207
197
*/
208
198
2:
209
-
#define MEM_PDC_LO 0x388
210
-
#define MEM_PDC_HI 0x35C
211
-
ldw MEM_PDC_LO(%r0),%r3
212
-
ldw MEM_PDC_HI(%r0),%r6
213
-
depd %r6, 31, 32, %r3 /* move to upper word */
214
-
215
199
mfctl %cr30,%r6 /* PCX-W2 firmware bug */
216
200
217
201
ldo PDC_PSW(%r0),%arg0 /* 21 */
···
271
267
.align 128
272
268
aligned_rfi:
273
269
pcxt_ssm_bug
270
+
271
+
copy %r3, %arg0 /* PDCE_PROC for smp_callin() */
274
272
275
273
rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */
276
274
/* Don't need NOPs, have 8 compliant insn before rfi */
+22
arch/parisc/kernel/pacache.S
+22
arch/parisc/kernel/pacache.S
···
1110
1110
.procend
1111
1111
ENDPROC_CFI(flush_kernel_dcache_range_asm)
1112
1112
1113
+
ENTRY_CFI(purge_kernel_dcache_range_asm)
1114
+
.proc
1115
+
.callinfo NO_CALLS
1116
+
.entry
1117
+
1118
+
ldil L%dcache_stride, %r1
1119
+
ldw R%dcache_stride(%r1), %r23
1120
+
ldo -1(%r23), %r21
1121
+
ANDCM %r26, %r21, %r26
1122
+
1123
+
1: cmpb,COND(<<),n %r26, %r25,1b
1124
+
pdc,m %r23(%r26)
1125
+
1126
+
sync
1127
+
syncdma
1128
+
bv %r0(%r2)
1129
+
nop
1130
+
.exit
1131
+
1132
+
.procend
1133
+
ENDPROC_CFI(purge_kernel_dcache_range_asm)
1134
+
1113
1135
ENTRY_CFI(flush_user_icache_range_asm)
1114
1136
.proc
1115
1137
.callinfo NO_CALLS
+6
-1
arch/parisc/kernel/smp.c
+6
-1
arch/parisc/kernel/smp.c
···
292
292
* Slaves start using C here. Indirectly called from smp_slave_stext.
293
293
* Do what start_kernel() and main() do for boot strap processor (aka monarch)
294
294
*/
295
-
void __init smp_callin(void)
295
+
void __init smp_callin(unsigned long pdce_proc)
296
296
{
297
297
int slave_id = cpu_now_booting;
298
+
299
+
#ifdef CONFIG_64BIT
300
+
WARN_ON(((unsigned long)(PAGE0->mem_pdc_hi) << 32
301
+
| PAGE0->mem_pdc) != pdce_proc);
302
+
#endif
298
303
299
304
smp_cpu_init(slave_id);
300
305
preempt_disable();
+6
-5
arch/parisc/kernel/time.c
+6
-5
arch/parisc/kernel/time.c
···
76
76
next_tick = cpuinfo->it_value;
77
77
78
78
/* Calculate how many ticks have elapsed. */
79
+
now = mfctl(16);
79
80
do {
80
81
++ticks_elapsed;
81
82
next_tick += cpt;
82
-
now = mfctl(16);
83
83
} while (next_tick - now > cpt);
84
84
85
85
/* Store (in CR16 cycles) up to when we are accounting right now. */
···
103
103
* if one or the other wrapped. If "now" is "bigger" we'll end up
104
104
* with a very large unsigned number.
105
105
*/
106
-
while (next_tick - mfctl(16) > cpt)
106
+
now = mfctl(16);
107
+
while (next_tick - now > cpt)
107
108
next_tick += cpt;
108
109
109
110
/* Program the IT when to deliver the next interrupt.
110
111
* Only bottom 32-bits of next_tick are writable in CR16!
111
112
* Timer interrupt will be delivered at least a few hundred cycles
112
-
* after the IT fires, so if we are too close (<= 500 cycles) to the
113
+
* after the IT fires, so if we are too close (<= 8000 cycles) to the
113
114
* next cycle, simply skip it.
114
115
*/
115
-
if (next_tick - mfctl(16) <= 500)
116
+
if (next_tick - now <= 8000)
116
117
next_tick += cpt;
117
118
mtctl(next_tick, 16);
118
119
···
249
248
* different sockets, so mark them unstable and lower rating on
250
249
* multi-socket SMP systems.
251
250
*/
252
-
if (num_online_cpus() > 1) {
251
+
if (num_online_cpus() > 1 && !running_on_qemu) {
253
252
int cpu;
254
253
unsigned long cpu0_loc;
255
254
cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
+6
-1
arch/parisc/mm/init.c
+6
-1
arch/parisc/mm/init.c
···
629
629
#endif
630
630
631
631
mem_init_print_info(NULL);
632
-
#ifdef CONFIG_DEBUG_KERNEL /* double-sanity-check paranoia */
632
+
633
+
#if 0
634
+
/*
635
+
* Do not expose the virtual kernel memory layout to userspace.
636
+
* But keep code for debugging purposes.
637
+
*/
633
638
printk("virtual kernel memory layout:\n"
634
639
" vmalloc : 0x%px - 0x%px (%4ld MB)\n"
635
640
" memory : 0x%px - 0x%px (%4ld MB)\n"