tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-for-4.8-rc6' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Two sets of i915 fixes, one set of vc4 crasher fixes, and a couple of
atmel fixes.

Nothing too out there at this stage, though I think some people are
holidaying so it's been quiet enough"

* tag 'drm-fixes-for-4.8-rc6' of git://people.freedesktop.org/~airlied/linux:
drm/i915: Ignore OpRegion panel type except on select machines
Revert "drm/i915/psr: Make idle_frames sensible again"
drm/i915: Restore lost "Initialized i915" welcome message
drm/vc4: mark vc4_bo_cache_purge() static
drm/i915: Add GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE to SNB
drm/i915: disable 48bit full PPGTT when vGPU is active
drm/i915: enable vGPU detection for all
drm/atmel-hlcdc: Make ->reset() implementation static
drm: atmel-hlcdc: Fix vertical scaling
drm/vc4: Allow some more signals to be packed with uniform resets.
drm/i915/dvo: Remove dangling call to drm_encoder_cleanup()

Linus Torvalds 5fbf3e32 095f5cfa

+61 -23
+1 -1
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
··· 387 387 atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c)); 388 388 } 389 389 390 - void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) 390 + static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) 391 391 { 392 392 struct atmel_hlcdc_crtc_state *state; 393 393
+5 -5
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
··· 320 320 u32 *coeff_tab = heo_upscaling_ycoef; 321 321 u32 max_memsize; 322 322 323 - if (state->crtc_w < state->src_w) 323 + if (state->crtc_h < state->src_h) 324 324 coeff_tab = heo_downscaling_ycoef; 325 325 for (i = 0; i < ARRAY_SIZE(heo_upscaling_ycoef); i++) 326 326 atmel_hlcdc_layer_update_cfg(&plane->layer, 327 327 33 + i, 328 328 0xffffffff, 329 329 coeff_tab[i]); 330 - factor = ((8 * 256 * state->src_w) - (256 * 4)) / 331 - state->crtc_w; 330 + factor = ((8 * 256 * state->src_h) - (256 * 4)) / 331 + state->crtc_h; 332 332 factor++; 333 - max_memsize = ((factor * state->crtc_w) + (256 * 4)) / 333 + max_memsize = ((factor * state->crtc_h) + (256 * 4)) / 334 334 2048; 335 - if (max_memsize > state->src_w) 335 + if (max_memsize > state->src_h) 336 336 factor--; 337 337 factor_reg |= (factor << 16) | 0x80000000; 338 338 }
+5
drivers/gpu/drm/i915/i915_drv.c
··· 1281 1281 1282 1282 intel_runtime_pm_enable(dev_priv); 1283 1283 1284 + /* Everything is in place, we can now relax! */ 1285 + DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", 1286 + driver.name, driver.major, driver.minor, driver.patchlevel, 1287 + driver.date, pci_name(pdev), dev_priv->drm.primary->index); 1288 + 1284 1289 intel_runtime_pm_put(dev_priv); 1285 1290 1286 1291 return 0;
+6 -3
drivers/gpu/drm/i915/i915_gem_gtt.c
··· 122 122 has_full_48bit_ppgtt = 123 123 IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9; 124 124 125 - if (intel_vgpu_active(dev_priv)) 126 - has_full_ppgtt = false; /* emulation is too hard */ 125 + if (intel_vgpu_active(dev_priv)) { 126 + /* emulation is too hard */ 127 + has_full_ppgtt = false; 128 + has_full_48bit_ppgtt = false; 129 + } 127 130 128 131 if (!has_aliasing_ppgtt) 129 132 return 0; ··· 161 158 return 0; 162 159 } 163 160 164 - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) 161 + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) 165 162 return has_full_48bit_ppgtt ? 3 : 2; 166 163 else 167 164 return has_aliasing_ppgtt ? 1 : 0;
-3
drivers/gpu/drm/i915/i915_vgpu.c
··· 65 65 66 66 BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE); 67 67 68 - if (!IS_HASWELL(dev_priv)) 69 - return; 70 - 71 68 magic = __raw_i915_read64(dev_priv, vgtif_reg(magic)); 72 69 if (magic != VGT_MAGIC) 73 70 return;
-1
drivers/gpu/drm/i915/intel_dvo.c
··· 554 554 return; 555 555 } 556 556 557 - drm_encoder_cleanup(&intel_encoder->base); 558 557 kfree(intel_dvo); 559 558 kfree(intel_connector); 560 559 }
+27
drivers/gpu/drm/i915/intel_opregion.c
··· 1047 1047 return err; 1048 1048 } 1049 1049 1050 + static int intel_use_opregion_panel_type_callback(const struct dmi_system_id *id) 1051 + { 1052 + DRM_INFO("Using panel type from OpRegion on %s\n", id->ident); 1053 + return 1; 1054 + } 1055 + 1056 + static const struct dmi_system_id intel_use_opregion_panel_type[] = { 1057 + { 1058 + .callback = intel_use_opregion_panel_type_callback, 1059 + .ident = "Conrac GmbH IX45GM2", 1060 + .matches = {DMI_MATCH(DMI_SYS_VENDOR, "Conrac GmbH"), 1061 + DMI_MATCH(DMI_PRODUCT_NAME, "IX45GM2"), 1062 + }, 1063 + }, 1064 + { } 1065 + }; 1066 + 1050 1067 int 1051 1068 intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) 1052 1069 { ··· 1086 1069 /* fall back to VBT panel type? */ 1087 1070 if (ret == 0x0) { 1088 1071 DRM_DEBUG_KMS("No panel type in OpRegion\n"); 1072 + return -ENODEV; 1073 + } 1074 + 1075 + /* 1076 + * So far we know that some machined must use it, others must not use it. 1077 + * There doesn't seem to be any way to determine which way to go, except 1078 + * via a quirk list :( 1079 + */ 1080 + if (!dmi_check_system(intel_use_opregion_panel_type)) { 1081 + DRM_DEBUG_KMS("Ignoring OpRegion panel type (%d)\n", ret - 1); 1089 1082 return -ENODEV; 1090 1083 } 1091 1084
+1
drivers/gpu/drm/i915/intel_pm.c
··· 7859 7859 case GEN6_PCODE_ILLEGAL_CMD: 7860 7860 return -ENXIO; 7861 7861 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: 7862 + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: 7862 7863 return -EOVERFLOW; 7863 7864 case GEN6_PCODE_TIMEOUT: 7864 7865 return -ETIMEDOUT;
+7 -7
drivers/gpu/drm/i915/intel_psr.c
··· 255 255 struct drm_i915_private *dev_priv = to_i915(dev); 256 256 257 257 uint32_t max_sleep_time = 0x1f; 258 - /* Lately it was identified that depending on panel idle frame count 259 - * calculated at HW can be off by 1. So let's use what came 260 - * from VBT + 1. 261 - * There are also other cases where panel demands at least 4 262 - * but VBT is not being set. To cover these 2 cases lets use 263 - * at least 5 when VBT isn't set to be on the safest side. 258 + /* 259 + * Let's respect VBT in case VBT asks a higher idle_frame value. 260 + * Let's use 6 as the minimum to cover all known cases including 261 + * the off-by-one issue that HW has in some cases. Also there are 262 + * cases where sink should be able to train 263 + * with the 5 or 6 idle patterns. 264 264 */ 265 - uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1; 265 + uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 266 266 uint32_t val = EDP_PSR_ENABLE; 267 267 268 268 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+1 -1
drivers/gpu/drm/vc4/vc4_bo.c
··· 144 144 return &vc4->bo_cache.size_list[page_index]; 145 145 } 146 146 147 - void vc4_bo_cache_purge(struct drm_device *dev) 147 + static void vc4_bo_cache_purge(struct drm_device *dev) 148 148 { 149 149 struct vc4_dev *vc4 = to_vc4_dev(dev); 150 150
+8 -2
drivers/gpu/drm/vc4/vc4_validate_shaders.c
··· 309 309 * of uniforms on each side. However, this scheme is easy to 310 310 * validate so it's all we allow for now. 311 311 */ 312 - 313 - if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_NONE) { 312 + switch (QPU_GET_FIELD(inst, QPU_SIG)) { 313 + case QPU_SIG_NONE: 314 + case QPU_SIG_SCOREBOARD_UNLOCK: 315 + case QPU_SIG_COLOR_LOAD: 316 + case QPU_SIG_LOAD_TMU0: 317 + case QPU_SIG_LOAD_TMU1: 318 + break; 319 + default: 314 320 DRM_ERROR("uniforms address change must be " 315 321 "normal math\n"); 316 322 return false;