Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-19-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
5fc21d1b
87d71378
+105
-86
+43
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
+43
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
7
+
#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_
8
+
9
+
/* Only for QMP V4_20 PHY - TX registers */
10
+
#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11
+
#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12
+
#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13
+
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14
+
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
15
+
16
+
/* Only for QMP V4_20 PHY - RX registers */
17
+
#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18
+
#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19
+
#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20
+
#define QSERDES_V4_20_RX_DFE_3 0x110
21
+
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
22
+
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
23
+
#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
24
+
#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
25
+
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
26
+
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
27
+
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
28
+
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
29
+
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
30
+
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
31
+
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
32
+
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
33
+
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
34
+
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
35
+
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
36
+
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
37
+
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
38
+
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
39
+
#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
40
+
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
41
+
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
42
+
43
+
#endif
+60
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
+60
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
7
+
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_
8
+
9
+
/* Only for QMP V5_20 PHY - TX registers */
10
+
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11
+
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12
+
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13
+
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14
+
15
+
/* Only for QMP V5_20 PHY - RX registers */
16
+
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
17
+
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
18
+
#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
19
+
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
20
+
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
21
+
#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
22
+
#define QSERDES_V5_20_RX_DFE_3 0x090
23
+
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
24
+
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
25
+
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
26
+
#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
27
+
#define QSERDES_V5_20_RX_GM_CAL 0x0ec
28
+
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
29
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
30
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
31
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
32
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
33
+
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
34
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
35
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
36
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
37
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
38
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
39
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
40
+
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
41
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
42
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
43
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
44
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
45
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
46
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
47
+
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
48
+
#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
49
+
#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
50
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
51
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
52
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
53
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
54
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
55
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
56
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
57
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
58
+
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
59
+
60
+
#endif
+2
-86
drivers/phy/qualcomm/phy-qcom-qmp.h
+2
-86
drivers/phy/qualcomm/phy-qcom-qmp.h
···
14
14
15
15
#include "phy-qcom-qmp-qserdes-com-v4.h"
16
16
#include "phy-qcom-qmp-qserdes-txrx-v4.h"
17
+
#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
17
18
18
19
#include "phy-qcom-qmp-qserdes-com-v5.h"
19
20
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
21
+
#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
20
22
21
23
#include "phy-qcom-qmp-qserdes-pll.h"
22
24
···
110
108
111
109
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
112
110
113
-
114
-
/* Only for QMP V4_20 PHY - TX registers */
115
-
#define QSERDES_V4_20_TX_LANE_MODE_1 0x88
116
-
#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
117
-
#define QSERDES_V4_20_TX_LANE_MODE_3 0x90
118
-
#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
119
-
#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
120
-
121
111
/* Only for QMP V4 PHY - DP PHY registers */
122
112
#define QSERDES_V4_DP_PHY_CFG_1 0x014
123
113
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
···
120
126
#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
121
127
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
122
128
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
123
-
124
-
/* Only for QMP V4_20 PHY - RX registers */
125
-
#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
126
-
#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
127
-
#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
128
-
#define QSERDES_V4_20_RX_DFE_3 0x110
129
-
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
130
-
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138
131
-
#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150
132
-
#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178
133
-
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8
134
-
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc
135
-
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0
136
-
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4
137
-
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8
138
-
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc
139
-
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0
140
-
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4
141
-
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8
142
-
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec
143
-
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0
144
-
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4
145
-
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8
146
-
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc
147
-
#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200
148
-
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c
149
-
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c
150
129
151
130
/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
152
131
#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188
···
142
175
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
143
176
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
144
177
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
145
-
146
-
/* Only for QMP V5_20 PHY - TX registers */
147
-
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
148
-
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
149
-
#define QSERDES_V5_20_TX_LANE_MODE_1 0x78
150
-
#define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
151
-
152
-
/* Only for QMP V5_20 PHY - RX registers */
153
-
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
154
-
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
155
-
#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020
156
-
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c
157
-
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030
158
-
#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c
159
-
#define QSERDES_V5_20_RX_DFE_3 0x090
160
-
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4
161
-
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4
162
-
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8
163
-
#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc
164
-
#define QSERDES_V5_20_RX_GM_CAL 0x0ec
165
-
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108
166
-
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164
167
-
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168
168
-
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c
169
-
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174
170
-
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178
171
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c
172
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180
173
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184
174
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188
175
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c
176
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190
177
-
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194
178
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198
179
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c
180
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0
181
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4
182
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8
183
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac
184
-
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0
185
-
#define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4
186
-
#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0
187
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
188
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8
189
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
190
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200
191
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
192
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208
193
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210
194
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218
195
-
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220
196
178
197
179
/* Only for QMP V5_20 PHY - PCIe PCS registers */
198
180
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c