Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://github.com/davem330/sparc
* git://github.com/davem330/sparc:
sparc64: Force the execute bit in OpenFirmware's translation entries.
sparc: Make '-p' boot option meaningful again.
sparc, exec: remove redundant addr_limit assignment
sparc64: Future proof Niagara cpu detection.
+61
-15
+2
arch/sparc/include/asm/spitfire.h
+2
arch/sparc/include/asm/spitfire.h
+3
-1
arch/sparc/include/asm/xor_64.h
+3
-1
arch/sparc/include/asm/xor_64.h
···
66
66
((tlb_type == hypervisor && \
67
67
(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
68
68
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
69
-
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
69
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
70
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
71
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
70
72
&xor_block_niagara : \
71
73
&xor_block_VIS)
+12
arch/sparc/kernel/cpu.c
+12
arch/sparc/kernel/cpu.c
···
481
481
sparc_pmu_type = "niagara3";
482
482
break;
483
483
484
+
case SUN4V_CHIP_NIAGARA4:
485
+
sparc_cpu_type = "UltraSparc T4 (Niagara4)";
486
+
sparc_fpu_type = "UltraSparc T4 integrated FPU";
487
+
sparc_pmu_type = "niagara4";
488
+
break;
489
+
490
+
case SUN4V_CHIP_NIAGARA5:
491
+
sparc_cpu_type = "UltraSparc T5 (Niagara5)";
492
+
sparc_fpu_type = "UltraSparc T5 integrated FPU";
493
+
sparc_pmu_type = "niagara5";
494
+
break;
495
+
484
496
default:
485
497
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
486
498
prom_cpu_compatible);
+2
arch/sparc/kernel/cpumap.c
+2
arch/sparc/kernel/cpumap.c
+22
-3
arch/sparc/kernel/head_64.S
+22
-3
arch/sparc/kernel/head_64.S
···
133
133
prom_niagara_prefix:
134
134
.asciz "SUNW,UltraSPARC-T"
135
135
prom_sparc_prefix:
136
-
.asciz "SPARC-T"
136
+
.asciz "SPARC-"
137
137
.align 4
138
138
prom_root_compatible:
139
139
.skip 64
···
396
396
or %g1, %lo(prom_cpu_compatible), %g1
397
397
sethi %hi(prom_sparc_prefix), %g7
398
398
or %g7, %lo(prom_sparc_prefix), %g7
399
-
mov 7, %g3
399
+
mov 6, %g3
400
400
90: ldub [%g7], %g2
401
401
ldub [%g1], %g4
402
402
cmp %g2, %g4
···
408
408
409
409
sethi %hi(prom_cpu_compatible), %g1
410
410
or %g1, %lo(prom_cpu_compatible), %g1
411
-
ldub [%g1 + 7], %g2
411
+
ldub [%g1 + 6], %g2
412
+
cmp %g2, 'T'
413
+
be,pt %xcc, 70f
414
+
cmp %g2, 'M'
415
+
bne,pn %xcc, 4f
416
+
nop
417
+
418
+
70: ldub [%g1 + 7], %g2
412
419
cmp %g2, '3'
413
420
be,pt %xcc, 5f
414
421
mov SUN4V_CHIP_NIAGARA3, %g4
422
+
cmp %g2, '4'
423
+
be,pt %xcc, 5f
424
+
mov SUN4V_CHIP_NIAGARA4, %g4
425
+
cmp %g2, '5'
426
+
be,pt %xcc, 5f
427
+
mov SUN4V_CHIP_NIAGARA5, %g4
415
428
ba,pt %xcc, 4f
416
429
nop
417
430
···
556
543
be,pt %xcc, niagara2_patch
557
544
nop
558
545
cmp %g1, SUN4V_CHIP_NIAGARA3
546
+
be,pt %xcc, niagara2_patch
547
+
nop
548
+
cmp %g1, SUN4V_CHIP_NIAGARA4
549
+
be,pt %xcc, niagara2_patch
550
+
nop
551
+
cmp %g1, SUN4V_CHIP_NIAGARA5
559
552
be,pt %xcc, niagara2_patch
560
553
nop
561
554
+1
-2
arch/sparc/kernel/process_32.c
+1
-2
arch/sparc/kernel/process_32.c
···
380
380
#endif
381
381
}
382
382
383
-
/* Now, this task is no longer a kernel thread. */
384
-
current->thread.current_ds = USER_DS;
383
+
/* This task is no longer a kernel thread. */
385
384
if (current->thread.flags & SPARC_FLAG_KTHREAD) {
386
385
current->thread.flags &= ~SPARC_FLAG_KTHREAD;
387
386
-3
arch/sparc/kernel/process_64.c
-3
arch/sparc/kernel/process_64.c
+1
-1
arch/sparc/kernel/setup_32.c
+1
-1
arch/sparc/kernel/setup_32.c
+13
-5
arch/sparc/kernel/setup_64.c
+13
-5
arch/sparc/kernel/setup_64.c
···
106
106
prom_halt();
107
107
break;
108
108
case 'p':
109
-
/* Just ignore, this behavior is now the default. */
109
+
prom_early_console.flags &= ~CON_BOOT;
110
110
break;
111
111
case 'P':
112
112
/* Force UltraSPARC-III P-Cache on. */
···
425
425
else if (tlb_type == hypervisor) {
426
426
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
427
427
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
428
-
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
428
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
429
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
430
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
429
431
cap |= HWCAP_SPARC_BLKINIT;
430
432
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
431
-
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
433
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
434
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
435
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
432
436
cap |= HWCAP_SPARC_N2;
433
437
}
434
438
···
456
452
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
457
453
cap |= AV_SPARC_ASI_BLK_INIT;
458
454
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
459
-
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
455
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
456
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
457
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
460
458
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
461
459
AV_SPARC_ASI_BLK_INIT |
462
460
AV_SPARC_POPC);
463
-
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
461
+
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
462
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
463
+
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
464
464
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
465
465
AV_SPARC_FMAF);
466
466
}
+5
arch/sparc/mm/init_64.c
+5
arch/sparc/mm/init_64.c
···
511
511
for (i = 0; i < prom_trans_ents; i++)
512
512
prom_trans[i].data &= ~0x0003fe0000000000UL;
513
513
}
514
+
515
+
/* Force execute bit on. */
516
+
for (i = 0; i < prom_trans_ents; i++)
517
+
prom_trans[i].data |= (tlb_type == hypervisor ?
518
+
_PAGE_EXEC_4V : _PAGE_EXEC_4U);
514
519
}
515
520
516
521
static void __init hypervisor_tlb_lock(unsigned long vaddr,