Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.9-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Seems to be quietening down nicely, a few mediatek, one exynos and one
hdlcd fix, along with two amd fixes"
* tag 'drm-fixes-for-v4.9-rc7' of git://people.freedesktop.org/~airlied/linux:
gpu/drm/exynos/exynos_hdmi - Unmap region obtained by of_iomap
drm/mediatek: fix null pointer dereference
drm/mediatek: fixed the calc method of data rate per lane
drm/mediatek: fix a typo of DISP_OD_CFG to OD_RELAYMODE
drm/radeon: fix power state when port pm is unavailable (v2)
drm/amdgpu: fix power state when port pm is unavailable
drm/arm: hdlcd: fix plane base address update
drm/amd/powerplay: avoid out of bounds access on array ps.
+87
-37
+8
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+8
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
···
34
34
35
35
static struct amdgpu_atpx_priv {
36
36
bool atpx_detected;
37
+
bool bridge_pm_usable;
37
38
/* handle for device - and atpx */
38
39
acpi_handle dhandle;
39
40
acpi_handle other_handle;
···
206
205
atpx->is_hybrid = false;
207
206
if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
208
207
printk("ATPX Hybrid Graphics\n");
209
-
atpx->functions.power_cntl = false;
208
+
/*
209
+
* Disable legacy PM methods only when pcie port PM is usable,
210
+
* otherwise the device might fail to power off or power on.
211
+
*/
212
+
atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
210
213
atpx->is_hybrid = true;
211
214
}
212
215
···
485
480
*/
486
481
static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
487
482
{
483
+
struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
488
484
acpi_handle dhandle, atpx_handle;
489
485
acpi_status status;
490
486
···
500
494
}
501
495
amdgpu_atpx_priv.dhandle = dhandle;
502
496
amdgpu_atpx_priv.atpx.handle = atpx_handle;
497
+
amdgpu_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
503
498
return true;
504
499
}
505
500
+6
-6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+6
-6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
2984
2984
if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
2985
2985
data->highest_mclk = memory_clock;
2986
2986
2987
-
performance_level = &(ps->performance_levels
2988
-
[ps->performance_level_count++]);
2989
-
2990
2987
PP_ASSERT_WITH_CODE(
2991
2988
(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
2992
2989
"Performance levels exceeds SMC limit!",
2993
2990
return -EINVAL);
2994
2991
2995
2992
PP_ASSERT_WITH_CODE(
2996
-
(ps->performance_level_count <=
2993
+
(ps->performance_level_count <
2997
2994
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
2998
-
"Performance levels exceeds Driver limit!",
2999
-
return -EINVAL);
2995
+
"Performance levels exceeds Driver limit, Skip!",
2996
+
return 0);
2997
+
2998
+
performance_level = &(ps->performance_levels
2999
+
[ps->performance_level_count++]);
3000
3000
3001
3001
/* Performance levels are arranged from low to high. */
3002
3002
performance_level->memory_clock = memory_clock;
+2
-3
drivers/gpu/drm/arm/hdlcd_crtc.c
+2
-3
drivers/gpu/drm/arm/hdlcd_crtc.c
···
150
150
clk_prepare_enable(hdlcd->clk);
151
151
hdlcd_crtc_mode_set_nofb(crtc);
152
152
hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
153
+
drm_crtc_vblank_on(crtc);
153
154
}
154
155
155
156
static void hdlcd_crtc_disable(struct drm_crtc *crtc)
156
157
{
157
158
struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
158
159
159
-
if (!crtc->state->active)
160
-
return;
161
-
160
+
drm_crtc_vblank_off(crtc);
162
161
hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
163
162
clk_disable_unprepare(hdlcd->clk);
164
163
}
+5
drivers/gpu/drm/exynos/exynos_hdmi.c
+5
drivers/gpu/drm/exynos/exynos_hdmi.c
···
1907
1907
err_hdmiphy:
1908
1908
if (hdata->hdmiphy_port)
1909
1909
put_device(&hdata->hdmiphy_port->dev);
1910
+
if (hdata->regs_hdmiphy)
1911
+
iounmap(hdata->regs_hdmiphy);
1910
1912
err_ddc:
1911
1913
put_device(&hdata->ddc_adpt->dev);
1912
1914
···
1930
1928
1931
1929
if (hdata->hdmiphy_port)
1932
1930
put_device(&hdata->hdmiphy_port->dev);
1931
+
1932
+
if (hdata->regs_hdmiphy)
1933
+
iounmap(hdata->regs_hdmiphy);
1933
1934
1934
1935
put_device(&hdata->ddc_adpt->dev);
1935
1936
+7
-7
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+7
-7
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
···
251
251
if (irq < 0)
252
252
return irq;
253
253
254
-
ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
255
-
IRQF_TRIGGER_NONE, dev_name(dev), priv);
256
-
if (ret < 0) {
257
-
dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
258
-
return ret;
259
-
}
260
-
261
254
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
262
255
if (comp_id < 0) {
263
256
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
···
265
272
}
266
273
267
274
platform_set_drvdata(pdev, priv);
275
+
276
+
ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
277
+
IRQF_TRIGGER_NONE, dev_name(dev), priv);
278
+
if (ret < 0) {
279
+
dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
280
+
return ret;
281
+
}
268
282
269
283
ret = component_add(dev, &mtk_disp_ovl_component_ops);
270
284
if (ret)
+1
-1
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+1
-1
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+50
-18
drivers/gpu/drm/mediatek/mtk_dsi.c
+50
-18
drivers/gpu/drm/mediatek/mtk_dsi.c
···
86
86
87
87
#define DSI_PHY_TIMECON0 0x110
88
88
#define LPX (0xff << 0)
89
-
#define HS_PRPR (0xff << 8)
89
+
#define HS_PREP (0xff << 8)
90
90
#define HS_ZERO (0xff << 16)
91
91
#define HS_TRAIL (0xff << 24)
92
92
···
102
102
#define CLK_TRAIL (0xff << 24)
103
103
104
104
#define DSI_PHY_TIMECON3 0x11c
105
-
#define CLK_HS_PRPR (0xff << 0)
105
+
#define CLK_HS_PREP (0xff << 0)
106
106
#define CLK_HS_POST (0xff << 8)
107
107
#define CLK_HS_EXIT (0xff << 16)
108
+
109
+
#define T_LPX 5
110
+
#define T_HS_PREP 6
111
+
#define T_HS_TRAIL 8
112
+
#define T_HS_EXIT 7
113
+
#define T_HS_ZERO 10
108
114
109
115
#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
110
116
···
167
161
static void dsi_phy_timconfig(struct mtk_dsi *dsi)
168
162
{
169
163
u32 timcon0, timcon1, timcon2, timcon3;
170
-
unsigned int ui, cycle_time;
171
-
unsigned int lpx;
164
+
u32 ui, cycle_time;
172
165
173
166
ui = 1000 / dsi->data_rate + 0x01;
174
167
cycle_time = 8000 / dsi->data_rate + 0x01;
175
-
lpx = 5;
176
168
177
-
timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
178
-
timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
179
-
(4 * lpx);
169
+
timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
170
+
timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
171
+
T_HS_EXIT << 24;
180
172
timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
181
173
(NS_TO_CYCLE(0x150, cycle_time) << 16);
182
-
timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
183
-
NS_TO_CYCLE(0x40, cycle_time);
174
+
timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
175
+
NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
184
176
185
177
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
186
178
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
···
206
202
{
207
203
struct device *dev = dsi->dev;
208
204
int ret;
205
+
u64 pixel_clock, total_bits;
206
+
u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
209
207
210
208
if (++dsi->refcount != 1)
211
209
return 0;
212
210
213
-
/**
214
-
* data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
215
-
* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
216
-
* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
217
-
* we set mipi_ratio is 1.05.
218
-
*/
219
-
dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10);
211
+
switch (dsi->format) {
212
+
case MIPI_DSI_FMT_RGB565:
213
+
bit_per_pixel = 16;
214
+
break;
215
+
case MIPI_DSI_FMT_RGB666_PACKED:
216
+
bit_per_pixel = 18;
217
+
break;
218
+
case MIPI_DSI_FMT_RGB666:
219
+
case MIPI_DSI_FMT_RGB888:
220
+
default:
221
+
bit_per_pixel = 24;
222
+
break;
223
+
}
220
224
221
-
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000);
225
+
/**
226
+
* vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
227
+
* htotal_time = htotal * byte_per_pixel / num_lanes
228
+
* overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
229
+
* mipi_ratio = (htotal_time + overhead_time) / htotal_time
230
+
* data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
231
+
*/
232
+
pixel_clock = dsi->vm.pixelclock * 1000;
233
+
htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
234
+
dsi->vm.hsync_len;
235
+
htotal_bits = htotal * bit_per_pixel;
236
+
237
+
overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
238
+
T_HS_EXIT;
239
+
overhead_bits = overhead_cycles * dsi->lanes * 8;
240
+
total_bits = htotal_bits + overhead_bits;
241
+
242
+
dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
243
+
htotal * dsi->lanes);
244
+
245
+
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
222
246
if (ret < 0) {
223
247
dev_err(dev, "Failed to set data rate: %d\n", ret);
224
248
goto err_refcount;
+8
-1
drivers/gpu/drm/radeon/radeon_atpx_handler.c
+8
-1
drivers/gpu/drm/radeon/radeon_atpx_handler.c
···
34
34
35
35
static struct radeon_atpx_priv {
36
36
bool atpx_detected;
37
+
bool bridge_pm_usable;
37
38
/* handle for device - and atpx */
38
39
acpi_handle dhandle;
39
40
struct radeon_atpx atpx;
···
204
203
atpx->is_hybrid = false;
205
204
if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
206
205
printk("ATPX Hybrid Graphics\n");
207
-
atpx->functions.power_cntl = false;
206
+
/*
207
+
* Disable legacy PM methods only when pcie port PM is usable,
208
+
* otherwise the device might fail to power off or power on.
209
+
*/
210
+
atpx->functions.power_cntl = !radeon_atpx_priv.bridge_pm_usable;
208
211
atpx->is_hybrid = true;
209
212
}
210
213
···
479
474
*/
480
475
static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
481
476
{
477
+
struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
482
478
acpi_handle dhandle, atpx_handle;
483
479
acpi_status status;
484
480
···
493
487
494
488
radeon_atpx_priv.dhandle = dhandle;
495
489
radeon_atpx_priv.atpx.handle = atpx_handle;
490
+
radeon_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
496
491
return true;
497
492
}
498
493