Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'icc-cleanup' into icc-next
* icc-cleanup
interconnect: qcom: sm8550: Remove bogus per-RSC BCMs and nodes
dt-bindings: interconnect: Remove bogus interconnect nodes
interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes
interconnect: qcom: sa8775p: constify pointer to qcom_icc_node
interconnect: qcom: sm8250: constify pointer to qcom_icc_node
interconnect: qcom: sm6115: constify pointer to qcom_icc_node
interconnect: qcom: sa8775p: constify pointer to qcom_icc_bcm
interconnect: qcom: x1e80100: constify pointer to qcom_icc_bcm
dt-bindings: interconnect: qcom,rpmh: Fix bouncing @codeaurora address
interconnect: constify of_phandle_args in xlate
Signed-off-by: Georgi Djakov <djakov@kernel.org>
+189
-1138
+1
-1
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+1
-1
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+2
-2
drivers/interconnect/core.c
+2
-2
drivers/interconnect/core.c
···
343
343
* an array of icc nodes specified in the icc_onecell_data struct when
344
344
* registering the provider.
345
345
*/
346
-
struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
346
+
struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
347
347
void *data)
348
348
{
349
349
struct icc_onecell_data *icc_data = data;
···
368
368
* Returns a valid pointer to struct icc_node_data on success or ERR_PTR()
369
369
* on failure.
370
370
*/
371
-
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
371
+
struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
372
372
{
373
373
struct icc_node *node = ERR_PTR(-EPROBE_DEFER);
374
374
struct icc_node_data *data = NULL;
+2
-1
drivers/interconnect/qcom/icc-common.c
+2
-1
drivers/interconnect/qcom/icc-common.c
···
9
9
10
10
#include "icc-common.h"
11
11
12
-
struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data)
12
+
struct icc_node_data *qcom_icc_xlate_extended(const struct of_phandle_args *spec,
13
+
void *data)
13
14
{
14
15
struct icc_node_data *ndata;
15
16
struct icc_node *node;
+2
-1
drivers/interconnect/qcom/icc-common.h
+2
-1
drivers/interconnect/qcom/icc-common.h
+28
-28
drivers/interconnect/qcom/sa8775p.c
+28
-28
drivers/interconnect/qcom/sa8775p.c
···
2092
2092
.nodes = { &xs_qdss_stm },
2093
2093
};
2094
2094
2095
-
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
2095
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
2096
2096
&bcm_sn3,
2097
2097
};
2098
2098
2099
-
static struct qcom_icc_node *aggre1_noc_nodes[] = {
2099
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
2100
2100
[MASTER_QUP_3] = &qxm_qup3,
2101
2101
[MASTER_EMAC] = &xm_emac_0,
2102
2102
[MASTER_EMAC_1] = &xm_emac_1,
···
2115
2115
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
2116
2116
};
2117
2117
2118
-
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
2118
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
2119
2119
&bcm_ce0,
2120
2120
&bcm_sn4,
2121
2121
};
2122
2122
2123
-
static struct qcom_icc_node *aggre2_noc_nodes[] = {
2123
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
2124
2124
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
2125
2125
[MASTER_QUP_0] = &qhm_qup0,
2126
2126
[MASTER_QUP_1] = &qhm_qup1,
···
2142
2142
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
2143
2143
};
2144
2144
2145
-
static struct qcom_icc_bcm *clk_virt_bcms[] = {
2145
+
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
2146
2146
&bcm_qup0,
2147
2147
&bcm_qup1,
2148
2148
&bcm_qup2,
2149
2149
};
2150
2150
2151
-
static struct qcom_icc_node *clk_virt_nodes[] = {
2151
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
2152
2152
[MASTER_QUP_CORE_0] = &qup0_core_master,
2153
2153
[MASTER_QUP_CORE_1] = &qup1_core_master,
2154
2154
[MASTER_QUP_CORE_2] = &qup2_core_master,
···
2166
2166
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
2167
2167
};
2168
2168
2169
-
static struct qcom_icc_bcm *config_noc_bcms[] = {
2169
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
2170
2170
&bcm_cn0,
2171
2171
&bcm_cn1,
2172
2172
&bcm_cn2,
···
2175
2175
&bcm_sn10,
2176
2176
};
2177
2177
2178
-
static struct qcom_icc_node *config_noc_nodes[] = {
2178
+
static struct qcom_icc_node * const config_noc_nodes[] = {
2179
2179
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
2180
2180
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
2181
2181
[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
···
2271
2271
.num_bcms = ARRAY_SIZE(config_noc_bcms),
2272
2272
};
2273
2273
2274
-
static struct qcom_icc_bcm *dc_noc_bcms[] = {
2274
+
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
2275
2275
};
2276
2276
2277
-
static struct qcom_icc_node *dc_noc_nodes[] = {
2277
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
2278
2278
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2279
2279
[SLAVE_LLCC_CFG] = &qhs_llcc,
2280
2280
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
···
2287
2287
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
2288
2288
};
2289
2289
2290
-
static struct qcom_icc_bcm *gem_noc_bcms[] = {
2290
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
2291
2291
&bcm_sh0,
2292
2292
&bcm_sh2,
2293
2293
};
2294
2294
2295
-
static struct qcom_icc_node *gem_noc_nodes[] = {
2295
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
2296
2296
[MASTER_GPU_TCU] = &alm_gpu_tcu,
2297
2297
[MASTER_PCIE_TCU] = &alm_pcie_tcu,
2298
2298
[MASTER_SYS_TCU] = &alm_sys_tcu,
···
2323
2323
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
2324
2324
};
2325
2325
2326
-
static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
2326
+
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
2327
2327
&bcm_gna0,
2328
2328
&bcm_gnb0,
2329
2329
};
2330
2330
2331
-
static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
2331
+
static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
2332
2332
[MASTER_DSP0] = &qxm_dsp0,
2333
2333
[MASTER_DSP1] = &qxm_dsp1,
2334
2334
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
···
2341
2341
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2342
2342
};
2343
2343
2344
-
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
2344
+
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
2345
2345
&bcm_sn9,
2346
2346
};
2347
2347
2348
-
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
2348
+
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2349
2349
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2350
2350
[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2351
2351
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
···
2364
2364
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2365
2365
};
2366
2366
2367
-
static struct qcom_icc_bcm *mc_virt_bcms[] = {
2367
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2368
2368
&bcm_acv,
2369
2369
&bcm_mc0,
2370
2370
};
2371
2371
2372
-
static struct qcom_icc_node *mc_virt_nodes[] = {
2372
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
2373
2373
[MASTER_LLCC] = &llcc_mc,
2374
2374
[SLAVE_EBI1] = &ebi,
2375
2375
};
···
2381
2381
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
2382
2382
};
2383
2383
2384
-
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
2384
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2385
2385
&bcm_mm0,
2386
2386
&bcm_mm1,
2387
2387
};
2388
2388
2389
-
static struct qcom_icc_node *mmss_noc_nodes[] = {
2389
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
2390
2390
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2391
2391
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2392
2392
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
···
2413
2413
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2414
2414
};
2415
2415
2416
-
static struct qcom_icc_bcm *nspa_noc_bcms[] = {
2416
+
static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
2417
2417
&bcm_nsa0,
2418
2418
&bcm_nsa1,
2419
2419
};
2420
2420
2421
-
static struct qcom_icc_node *nspa_noc_nodes[] = {
2421
+
static struct qcom_icc_node * const nspa_noc_nodes[] = {
2422
2422
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2423
2423
[MASTER_CDSP_PROC] = &qxm_nsp,
2424
2424
[SLAVE_HCP_A] = &qns_hcp,
···
2433
2433
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2434
2434
};
2435
2435
2436
-
static struct qcom_icc_bcm *nspb_noc_bcms[] = {
2436
+
static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
2437
2437
&bcm_nsb0,
2438
2438
&bcm_nsb1,
2439
2439
};
2440
2440
2441
-
static struct qcom_icc_node *nspb_noc_nodes[] = {
2441
+
static struct qcom_icc_node * const nspb_noc_nodes[] = {
2442
2442
[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2443
2443
[MASTER_CDSP_PROC_B] = &qxm_nspb,
2444
2444
[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
···
2453
2453
.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2454
2454
};
2455
2455
2456
-
static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
2456
+
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2457
2457
&bcm_pci0,
2458
2458
};
2459
2459
2460
-
static struct qcom_icc_node *pcie_anoc_nodes[] = {
2460
+
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2461
2461
[MASTER_PCIE_0] = &xm_pcie3_0,
2462
2462
[MASTER_PCIE_1] = &xm_pcie3_1,
2463
2463
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
···
2470
2470
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2471
2471
};
2472
2472
2473
-
static struct qcom_icc_bcm *system_noc_bcms[] = {
2473
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
2474
2474
&bcm_sn0,
2475
2475
&bcm_sn1,
2476
2476
&bcm_sn3,
···
2478
2478
&bcm_sn9,
2479
2479
};
2480
2480
2481
-
static struct qcom_icc_node *system_noc_nodes[] = {
2481
+
static struct qcom_icc_node * const system_noc_nodes[] = {
2482
2482
[MASTER_GIC_AHB] = &qhm_gic,
2483
2483
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2484
2484
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
+6
-6
drivers/interconnect/qcom/sm6115.c
+6
-6
drivers/interconnect/qcom/sm6115.c
···
1193
1193
.links = slv_anoc_snoc_links,
1194
1194
};
1195
1195
1196
-
static struct qcom_icc_node *bimc_nodes[] = {
1196
+
static struct qcom_icc_node * const bimc_nodes[] = {
1197
1197
[MASTER_AMPSS_M0] = &apps_proc,
1198
1198
[MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt,
1199
1199
[MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt,
···
1223
1223
.ab_coeff = 153,
1224
1224
};
1225
1225
1226
-
static struct qcom_icc_node *config_noc_nodes[] = {
1226
+
static struct qcom_icc_node * const config_noc_nodes[] = {
1227
1227
[SNOC_CNOC_MAS] = &mas_snoc_cnoc,
1228
1228
[MASTER_QDSS_DAP] = &xm_dap,
1229
1229
[SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb,
···
1294
1294
.keep_alive = true,
1295
1295
};
1296
1296
1297
-
static struct qcom_icc_node *sys_noc_nodes[] = {
1297
+
static struct qcom_icc_node * const sys_noc_nodes[] = {
1298
1298
[MASTER_CRYPTO_CORE0] = &crypto_c0,
1299
1299
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1300
1300
[MASTER_TIC] = &qhm_tic,
···
1339
1339
.keep_alive = true,
1340
1340
};
1341
1341
1342
-
static struct qcom_icc_node *clk_virt_nodes[] = {
1342
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
1343
1343
[MASTER_QUP_CORE_0] = &qup0_core_master,
1344
1344
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1345
1345
};
···
1353
1353
.keep_alive = true,
1354
1354
};
1355
1355
1356
-
static struct qcom_icc_node *mmnrt_virt_nodes[] = {
1356
+
static struct qcom_icc_node * const mmnrt_virt_nodes[] = {
1357
1357
[MASTER_CAMNOC_SF] = &qnm_camera_nrt,
1358
1358
[MASTER_VIDEO_P0] = &qxm_venus0,
1359
1359
[MASTER_VIDEO_PROC] = &qxm_venus_cpu,
···
1370
1370
.ab_coeff = 142,
1371
1371
};
1372
1372
1373
-
static struct qcom_icc_node *mmrt_virt_nodes[] = {
1373
+
static struct qcom_icc_node * const mmrt_virt_nodes[] = {
1374
1374
[MASTER_CAMNOC_HF] = &qnm_camera_rt,
1375
1375
[MASTER_MDP_PORT0] = &qxm_mdp0,
1376
1376
[SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt,
+1
-1
drivers/interconnect/qcom/sm8250.c
+1
-1
drivers/interconnect/qcom/sm8250.c
···
1673
1673
&bcm_qup0,
1674
1674
};
1675
1675
1676
-
static struct qcom_icc_node *qup_virt_nodes[] = {
1676
+
static struct qcom_icc_node * const qup_virt_nodes[] = {
1677
1677
[MASTER_QUP_CORE_0] = &qup0_core_master,
1678
1678
[MASTER_QUP_CORE_1] = &qup1_core_master,
1679
1679
[MASTER_QUP_CORE_2] = &qup2_core_master,
-574
drivers/interconnect/qcom/sm8550.c
-574
drivers/interconnect/qcom/sm8550.c
···
524
524
.links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
525
525
};
526
526
527
-
static struct qcom_icc_node qnm_mnoc_hf_disp = {
528
-
.name = "qnm_mnoc_hf_disp",
529
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_DISP,
530
-
.channels = 2,
531
-
.buswidth = 32,
532
-
.num_links = 1,
533
-
.links = { SM8550_SLAVE_LLCC_DISP },
534
-
};
535
-
536
-
static struct qcom_icc_node qnm_pcie_disp = {
537
-
.name = "qnm_pcie_disp",
538
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP,
539
-
.channels = 1,
540
-
.buswidth = 16,
541
-
.num_links = 1,
542
-
.links = { SM8550_SLAVE_LLCC_DISP },
543
-
};
544
-
545
-
static struct qcom_icc_node llcc_mc_disp = {
546
-
.name = "llcc_mc_disp",
547
-
.id = SM8550_MASTER_LLCC_DISP,
548
-
.channels = 4,
549
-
.buswidth = 4,
550
-
.num_links = 1,
551
-
.links = { SM8550_SLAVE_EBI1_DISP },
552
-
};
553
-
554
-
static struct qcom_icc_node qnm_mdp_disp = {
555
-
.name = "qnm_mdp_disp",
556
-
.id = SM8550_MASTER_MDP_DISP,
557
-
.channels = 2,
558
-
.buswidth = 32,
559
-
.num_links = 1,
560
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP },
561
-
};
562
-
563
-
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = {
564
-
.name = "qnm_mnoc_hf_cam_ife_0",
565
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0,
566
-
.channels = 2,
567
-
.buswidth = 32,
568
-
.num_links = 1,
569
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
570
-
};
571
-
572
-
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = {
573
-
.name = "qnm_mnoc_sf_cam_ife_0",
574
-
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0,
575
-
.channels = 2,
576
-
.buswidth = 32,
577
-
.num_links = 1,
578
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
579
-
};
580
-
581
-
static struct qcom_icc_node qnm_pcie_cam_ife_0 = {
582
-
.name = "qnm_pcie_cam_ife_0",
583
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0,
584
-
.channels = 1,
585
-
.buswidth = 16,
586
-
.num_links = 1,
587
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
588
-
};
589
-
590
-
static struct qcom_icc_node llcc_mc_cam_ife_0 = {
591
-
.name = "llcc_mc_cam_ife_0",
592
-
.id = SM8550_MASTER_LLCC_CAM_IFE_0,
593
-
.channels = 4,
594
-
.buswidth = 4,
595
-
.num_links = 1,
596
-
.links = { SM8550_SLAVE_EBI1_CAM_IFE_0 },
597
-
};
598
-
599
-
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = {
600
-
.name = "qnm_camnoc_hf_cam_ife_0",
601
-
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_0,
602
-
.channels = 2,
603
-
.buswidth = 32,
604
-
.num_links = 1,
605
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 },
606
-
};
607
-
608
-
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = {
609
-
.name = "qnm_camnoc_icp_cam_ife_0",
610
-
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0,
611
-
.channels = 1,
612
-
.buswidth = 8,
613
-
.num_links = 1,
614
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
615
-
};
616
-
617
-
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = {
618
-
.name = "qnm_camnoc_sf_cam_ife_0",
619
-
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_0,
620
-
.channels = 2,
621
-
.buswidth = 32,
622
-
.num_links = 1,
623
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
624
-
};
625
-
626
-
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = {
627
-
.name = "qnm_mnoc_hf_cam_ife_1",
628
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1,
629
-
.channels = 2,
630
-
.buswidth = 32,
631
-
.num_links = 1,
632
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
633
-
};
634
-
635
-
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = {
636
-
.name = "qnm_mnoc_sf_cam_ife_1",
637
-
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1,
638
-
.channels = 2,
639
-
.buswidth = 32,
640
-
.num_links = 1,
641
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
642
-
};
643
-
644
-
static struct qcom_icc_node qnm_pcie_cam_ife_1 = {
645
-
.name = "qnm_pcie_cam_ife_1",
646
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1,
647
-
.channels = 1,
648
-
.buswidth = 16,
649
-
.num_links = 1,
650
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
651
-
};
652
-
653
-
static struct qcom_icc_node llcc_mc_cam_ife_1 = {
654
-
.name = "llcc_mc_cam_ife_1",
655
-
.id = SM8550_MASTER_LLCC_CAM_IFE_1,
656
-
.channels = 4,
657
-
.buswidth = 4,
658
-
.num_links = 1,
659
-
.links = { SM8550_SLAVE_EBI1_CAM_IFE_1 },
660
-
};
661
-
662
-
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = {
663
-
.name = "qnm_camnoc_hf_cam_ife_1",
664
-
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_1,
665
-
.channels = 2,
666
-
.buswidth = 32,
667
-
.num_links = 1,
668
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 },
669
-
};
670
-
671
-
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = {
672
-
.name = "qnm_camnoc_icp_cam_ife_1",
673
-
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1,
674
-
.channels = 1,
675
-
.buswidth = 8,
676
-
.num_links = 1,
677
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
678
-
};
679
-
680
-
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = {
681
-
.name = "qnm_camnoc_sf_cam_ife_1",
682
-
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_1,
683
-
.channels = 2,
684
-
.buswidth = 32,
685
-
.num_links = 1,
686
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
687
-
};
688
-
689
-
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = {
690
-
.name = "qnm_mnoc_hf_cam_ife_2",
691
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2,
692
-
.channels = 2,
693
-
.buswidth = 32,
694
-
.num_links = 1,
695
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
696
-
};
697
-
698
-
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = {
699
-
.name = "qnm_mnoc_sf_cam_ife_2",
700
-
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2,
701
-
.channels = 2,
702
-
.buswidth = 32,
703
-
.num_links = 1,
704
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
705
-
};
706
-
707
-
static struct qcom_icc_node qnm_pcie_cam_ife_2 = {
708
-
.name = "qnm_pcie_cam_ife_2",
709
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2,
710
-
.channels = 1,
711
-
.buswidth = 16,
712
-
.num_links = 1,
713
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
714
-
};
715
-
716
-
static struct qcom_icc_node llcc_mc_cam_ife_2 = {
717
-
.name = "llcc_mc_cam_ife_2",
718
-
.id = SM8550_MASTER_LLCC_CAM_IFE_2,
719
-
.channels = 4,
720
-
.buswidth = 4,
721
-
.num_links = 1,
722
-
.links = { SM8550_SLAVE_EBI1_CAM_IFE_2 },
723
-
};
724
-
725
-
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = {
726
-
.name = "qnm_camnoc_hf_cam_ife_2",
727
-
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_2,
728
-
.channels = 2,
729
-
.buswidth = 32,
730
-
.num_links = 1,
731
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 },
732
-
};
733
-
734
-
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = {
735
-
.name = "qnm_camnoc_icp_cam_ife_2",
736
-
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2,
737
-
.channels = 1,
738
-
.buswidth = 8,
739
-
.num_links = 1,
740
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
741
-
};
742
-
743
-
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = {
744
-
.name = "qnm_camnoc_sf_cam_ife_2",
745
-
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_2,
746
-
.channels = 2,
747
-
.buswidth = 32,
748
-
.num_links = 1,
749
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
750
-
};
751
-
752
527
static struct qcom_icc_node qns_a1noc_snoc = {
753
528
.name = "qns_a1noc_snoc",
754
529
.id = SM8550_SLAVE_A1NOC_SNOC,
···
1117
1342
.links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
1118
1343
};
1119
1344
1120
-
static struct qcom_icc_node qns_llcc_disp = {
1121
-
.name = "qns_llcc_disp",
1122
-
.id = SM8550_SLAVE_LLCC_DISP,
1123
-
.channels = 4,
1124
-
.buswidth = 16,
1125
-
.num_links = 1,
1126
-
.links = { SM8550_MASTER_LLCC_DISP },
1127
-
};
1128
-
1129
-
static struct qcom_icc_node ebi_disp = {
1130
-
.name = "ebi_disp",
1131
-
.id = SM8550_SLAVE_EBI1_DISP,
1132
-
.channels = 4,
1133
-
.buswidth = 4,
1134
-
.num_links = 0,
1135
-
};
1136
-
1137
-
static struct qcom_icc_node qns_mem_noc_hf_disp = {
1138
-
.name = "qns_mem_noc_hf_disp",
1139
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP,
1140
-
.channels = 2,
1141
-
.buswidth = 32,
1142
-
.num_links = 1,
1143
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_DISP },
1144
-
};
1145
-
1146
-
static struct qcom_icc_node qns_llcc_cam_ife_0 = {
1147
-
.name = "qns_llcc_cam_ife_0",
1148
-
.id = SM8550_SLAVE_LLCC_CAM_IFE_0,
1149
-
.channels = 4,
1150
-
.buswidth = 16,
1151
-
.num_links = 1,
1152
-
.links = { SM8550_MASTER_LLCC_CAM_IFE_0 },
1153
-
};
1154
-
1155
-
static struct qcom_icc_node ebi_cam_ife_0 = {
1156
-
.name = "ebi_cam_ife_0",
1157
-
.id = SM8550_SLAVE_EBI1_CAM_IFE_0,
1158
-
.channels = 4,
1159
-
.buswidth = 4,
1160
-
.num_links = 0,
1161
-
};
1162
-
1163
-
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = {
1164
-
.name = "qns_mem_noc_hf_cam_ife_0",
1165
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0,
1166
-
.channels = 2,
1167
-
.buswidth = 32,
1168
-
.num_links = 1,
1169
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 },
1170
-
};
1171
-
1172
-
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = {
1173
-
.name = "qns_mem_noc_sf_cam_ife_0",
1174
-
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0,
1175
-
.channels = 2,
1176
-
.buswidth = 32,
1177
-
.num_links = 1,
1178
-
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 },
1179
-
};
1180
-
1181
-
static struct qcom_icc_node qns_llcc_cam_ife_1 = {
1182
-
.name = "qns_llcc_cam_ife_1",
1183
-
.id = SM8550_SLAVE_LLCC_CAM_IFE_1,
1184
-
.channels = 4,
1185
-
.buswidth = 16,
1186
-
.num_links = 1,
1187
-
.links = { SM8550_MASTER_LLCC_CAM_IFE_1 },
1188
-
};
1189
-
1190
-
static struct qcom_icc_node ebi_cam_ife_1 = {
1191
-
.name = "ebi_cam_ife_1",
1192
-
.id = SM8550_SLAVE_EBI1_CAM_IFE_1,
1193
-
.channels = 4,
1194
-
.buswidth = 4,
1195
-
.num_links = 0,
1196
-
};
1197
-
1198
-
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = {
1199
-
.name = "qns_mem_noc_hf_cam_ife_1",
1200
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1,
1201
-
.channels = 2,
1202
-
.buswidth = 32,
1203
-
.num_links = 1,
1204
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 },
1205
-
};
1206
-
1207
-
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = {
1208
-
.name = "qns_mem_noc_sf_cam_ife_1",
1209
-
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1,
1210
-
.channels = 2,
1211
-
.buswidth = 32,
1212
-
.num_links = 1,
1213
-
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 },
1214
-
};
1215
-
1216
-
static struct qcom_icc_node qns_llcc_cam_ife_2 = {
1217
-
.name = "qns_llcc_cam_ife_2",
1218
-
.id = SM8550_SLAVE_LLCC_CAM_IFE_2,
1219
-
.channels = 4,
1220
-
.buswidth = 16,
1221
-
.num_links = 1,
1222
-
.links = { SM8550_MASTER_LLCC_CAM_IFE_2 },
1223
-
};
1224
-
1225
-
static struct qcom_icc_node ebi_cam_ife_2 = {
1226
-
.name = "ebi_cam_ife_2",
1227
-
.id = SM8550_SLAVE_EBI1_CAM_IFE_2,
1228
-
.channels = 4,
1229
-
.buswidth = 4,
1230
-
.num_links = 0,
1231
-
};
1232
-
1233
-
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = {
1234
-
.name = "qns_mem_noc_hf_cam_ife_2",
1235
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2,
1236
-
.channels = 2,
1237
-
.buswidth = 32,
1238
-
.num_links = 1,
1239
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 },
1240
-
};
1241
-
1242
-
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
1243
-
.name = "qns_mem_noc_sf_cam_ife_2",
1244
-
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2,
1245
-
.channels = 2,
1246
-
.buswidth = 32,
1247
-
.num_links = 1,
1248
-
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 },
1249
-
};
1250
-
1251
1345
static struct qcom_icc_bcm bcm_acv = {
1252
1346
.name = "ACV",
1253
1347
.enable_mask = 0x8,
···
1283
1639
.nodes = { &qns_pcie_mem_noc },
1284
1640
};
1285
1641
1286
-
static struct qcom_icc_bcm bcm_acv_disp = {
1287
-
.name = "ACV",
1288
-
.enable_mask = 0x1,
1289
-
.num_nodes = 1,
1290
-
.nodes = { &ebi_disp },
1291
-
};
1292
-
1293
-
static struct qcom_icc_bcm bcm_mc0_disp = {
1294
-
.name = "MC0",
1295
-
.num_nodes = 1,
1296
-
.nodes = { &ebi_disp },
1297
-
};
1298
-
1299
-
static struct qcom_icc_bcm bcm_mm0_disp = {
1300
-
.name = "MM0",
1301
-
.num_nodes = 1,
1302
-
.nodes = { &qns_mem_noc_hf_disp },
1303
-
};
1304
-
1305
-
static struct qcom_icc_bcm bcm_sh0_disp = {
1306
-
.name = "SH0",
1307
-
.num_nodes = 1,
1308
-
.nodes = { &qns_llcc_disp },
1309
-
};
1310
-
1311
-
static struct qcom_icc_bcm bcm_sh1_disp = {
1312
-
.name = "SH1",
1313
-
.enable_mask = 0x1,
1314
-
.num_nodes = 2,
1315
-
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
1316
-
};
1317
-
1318
-
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
1319
-
.name = "ACV",
1320
-
.enable_mask = 0x0,
1321
-
.num_nodes = 1,
1322
-
.nodes = { &ebi_cam_ife_0 },
1323
-
};
1324
-
1325
-
static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = {
1326
-
.name = "MC0",
1327
-
.num_nodes = 1,
1328
-
.nodes = { &ebi_cam_ife_0 },
1329
-
};
1330
-
1331
-
static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
1332
-
.name = "MM0",
1333
-
.num_nodes = 1,
1334
-
.nodes = { &qns_mem_noc_hf_cam_ife_0 },
1335
-
};
1336
-
1337
-
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
1338
-
.name = "MM1",
1339
-
.enable_mask = 0x1,
1340
-
.num_nodes = 4,
1341
-
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
1342
-
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
1343
-
};
1344
-
1345
-
static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
1346
-
.name = "SH0",
1347
-
.num_nodes = 1,
1348
-
.nodes = { &qns_llcc_cam_ife_0 },
1349
-
};
1350
-
1351
-
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
1352
-
.name = "SH1",
1353
-
.enable_mask = 0x1,
1354
-
.num_nodes = 3,
1355
-
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
1356
-
&qnm_pcie_cam_ife_0 },
1357
-
};
1358
-
1359
-
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
1360
-
.name = "ACV",
1361
-
.enable_mask = 0x0,
1362
-
.num_nodes = 1,
1363
-
.nodes = { &ebi_cam_ife_1 },
1364
-
};
1365
-
1366
-
static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = {
1367
-
.name = "MC0",
1368
-
.num_nodes = 1,
1369
-
.nodes = { &ebi_cam_ife_1 },
1370
-
};
1371
-
1372
-
static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
1373
-
.name = "MM0",
1374
-
.num_nodes = 1,
1375
-
.nodes = { &qns_mem_noc_hf_cam_ife_1 },
1376
-
};
1377
-
1378
-
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
1379
-
.name = "MM1",
1380
-
.enable_mask = 0x1,
1381
-
.num_nodes = 4,
1382
-
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
1383
-
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
1384
-
};
1385
-
1386
-
static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
1387
-
.name = "SH0",
1388
-
.num_nodes = 1,
1389
-
.nodes = { &qns_llcc_cam_ife_1 },
1390
-
};
1391
-
1392
-
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
1393
-
.name = "SH1",
1394
-
.enable_mask = 0x1,
1395
-
.num_nodes = 3,
1396
-
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
1397
-
&qnm_pcie_cam_ife_1 },
1398
-
};
1399
-
1400
-
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
1401
-
.name = "ACV",
1402
-
.enable_mask = 0x0,
1403
-
.num_nodes = 1,
1404
-
.nodes = { &ebi_cam_ife_2 },
1405
-
};
1406
-
1407
-
static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = {
1408
-
.name = "MC0",
1409
-
.num_nodes = 1,
1410
-
.nodes = { &ebi_cam_ife_2 },
1411
-
};
1412
-
1413
-
static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
1414
-
.name = "MM0",
1415
-
.num_nodes = 1,
1416
-
.nodes = { &qns_mem_noc_hf_cam_ife_2 },
1417
-
};
1418
-
1419
-
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
1420
-
.name = "MM1",
1421
-
.enable_mask = 0x1,
1422
-
.num_nodes = 4,
1423
-
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
1424
-
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
1425
-
};
1426
-
1427
-
static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
1428
-
.name = "SH0",
1429
-
.num_nodes = 1,
1430
-
.nodes = { &qns_llcc_cam_ife_2 },
1431
-
};
1432
-
1433
-
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
1434
-
.name = "SH1",
1435
-
.enable_mask = 0x1,
1436
-
.num_nodes = 3,
1437
-
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
1438
-
&qnm_pcie_cam_ife_2 },
1439
-
};
1440
-
1441
1642
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1442
1643
};
1443
1644
···
1434
1945
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1435
1946
&bcm_sh0,
1436
1947
&bcm_sh1,
1437
-
&bcm_sh0_disp,
1438
-
&bcm_sh1_disp,
1439
-
&bcm_sh0_cam_ife_0,
1440
-
&bcm_sh1_cam_ife_0,
1441
-
&bcm_sh0_cam_ife_1,
1442
-
&bcm_sh1_cam_ife_1,
1443
-
&bcm_sh0_cam_ife_2,
1444
-
&bcm_sh1_cam_ife_2,
1445
1948
};
1446
1949
1447
1950
static struct qcom_icc_node * const gem_noc_nodes[] = {
···
1452
1971
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1453
1972
[SLAVE_LLCC] = &qns_llcc,
1454
1973
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1455
-
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1456
-
[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1457
-
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1458
-
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0,
1459
-
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0,
1460
-
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0,
1461
-
[SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0,
1462
-
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1,
1463
-
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1,
1464
-
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1,
1465
-
[SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1,
1466
-
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2,
1467
-
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2,
1468
-
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2,
1469
-
[SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2,
1470
1974
};
1471
1975
1472
1976
static const struct qcom_icc_desc sm8550_gem_noc = {
···
1510
2044
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1511
2045
&bcm_acv,
1512
2046
&bcm_mc0,
1513
-
&bcm_acv_disp,
1514
-
&bcm_mc0_disp,
1515
-
&bcm_acv_cam_ife_0,
1516
-
&bcm_mc0_cam_ife_0,
1517
-
&bcm_acv_cam_ife_1,
1518
-
&bcm_mc0_cam_ife_1,
1519
-
&bcm_acv_cam_ife_2,
1520
-
&bcm_mc0_cam_ife_2,
1521
2047
};
1522
2048
1523
2049
static struct qcom_icc_node * const mc_virt_nodes[] = {
1524
2050
[MASTER_LLCC] = &llcc_mc,
1525
2051
[SLAVE_EBI1] = &ebi,
1526
-
[MASTER_LLCC_DISP] = &llcc_mc_disp,
1527
-
[SLAVE_EBI1_DISP] = &ebi_disp,
1528
-
[MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0,
1529
-
[SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0,
1530
-
[MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1,
1531
-
[SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1,
1532
-
[MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2,
1533
-
[SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2,
1534
2052
};
1535
2053
1536
2054
static const struct qcom_icc_desc sm8550_mc_virt = {
···
1527
2077
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1528
2078
&bcm_mm0,
1529
2079
&bcm_mm1,
1530
-
&bcm_mm0_disp,
1531
-
&bcm_mm0_cam_ife_0,
1532
-
&bcm_mm1_cam_ife_0,
1533
-
&bcm_mm0_cam_ife_1,
1534
-
&bcm_mm1_cam_ife_1,
1535
-
&bcm_mm0_cam_ife_2,
1536
-
&bcm_mm1_cam_ife_2,
1537
2080
};
1538
2081
1539
2082
static struct qcom_icc_node * const mmss_noc_nodes[] = {
···
1543
2100
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1544
2101
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1545
2102
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1546
-
[MASTER_MDP_DISP] = &qnm_mdp_disp,
1547
-
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1548
-
[MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0,
1549
-
[MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0,
1550
-
[MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0,
1551
-
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0,
1552
-
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0,
1553
-
[MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1,
1554
-
[MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1,
1555
-
[MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1,
1556
-
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1,
1557
-
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1,
1558
-
[MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2,
1559
-
[MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2,
1560
-
[MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2,
1561
-
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2,
1562
-
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2,
1563
2103
};
1564
2104
1565
2105
static const struct qcom_icc_desc sm8550_mmss_noc = {
+122
-162
drivers/interconnect/qcom/sm8550.h
+122
-162
drivers/interconnect/qcom/sm8550.h
···
12
12
#define SM8550_MASTER_A1NOC_SNOC 0
13
13
#define SM8550_MASTER_A2NOC_SNOC 1
14
14
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
15
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3
16
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4
17
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5
18
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP 6
19
-
#define SM8550_MASTER_APPSS_PROC 7
20
-
#define SM8550_MASTER_CAMNOC_HF 8
21
-
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0 9
22
-
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1 10
23
-
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2 11
24
-
#define SM8550_MASTER_CAMNOC_ICP 12
25
-
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0 13
26
-
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1 14
27
-
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2 15
28
-
#define SM8550_MASTER_CAMNOC_SF 16
29
-
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0 17
30
-
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1 18
31
-
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2 19
32
-
#define SM8550_MASTER_CDSP_HCP 20
33
-
#define SM8550_MASTER_CDSP_PROC 21
34
-
#define SM8550_MASTER_CNOC_CFG 22
35
-
#define SM8550_MASTER_CNOC_MNOC_CFG 23
36
-
#define SM8550_MASTER_COMPUTE_NOC 24
37
-
#define SM8550_MASTER_CRYPTO 25
38
-
#define SM8550_MASTER_GEM_NOC_CNOC 26
39
-
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 27
40
-
#define SM8550_MASTER_GFX3D 28
41
-
#define SM8550_MASTER_GIC 29
42
-
#define SM8550_MASTER_GIC_AHB 30
43
-
#define SM8550_MASTER_GPU_TCU 31
44
-
#define SM8550_MASTER_IPA 32
45
-
#define SM8550_MASTER_LLCC 33
46
-
#define SM8550_MASTER_LLCC_CAM_IFE_0 34
47
-
#define SM8550_MASTER_LLCC_CAM_IFE_1 35
48
-
#define SM8550_MASTER_LLCC_CAM_IFE_2 36
49
-
#define SM8550_MASTER_LLCC_DISP 37
50
-
#define SM8550_MASTER_LPASS_GEM_NOC 38
51
-
#define SM8550_MASTER_LPASS_LPINOC 39
52
-
#define SM8550_MASTER_LPASS_PROC 40
53
-
#define SM8550_MASTER_LPIAON_NOC 41
54
-
#define SM8550_MASTER_MDP 42
55
-
#define SM8550_MASTER_MDP_DISP 43
56
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC 44
57
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 45
58
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 46
59
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 47
60
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP 48
61
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC 49
62
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 50
63
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 51
64
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 52
65
-
#define SM8550_MASTER_MSS_PROC 53
66
-
#define SM8550_MASTER_PCIE_0 54
67
-
#define SM8550_MASTER_PCIE_1 55
68
-
#define SM8550_MASTER_PCIE_ANOC_CFG 56
69
-
#define SM8550_MASTER_QDSS_BAM 57
70
-
#define SM8550_MASTER_QDSS_ETR 58
71
-
#define SM8550_MASTER_QDSS_ETR_1 59
72
-
#define SM8550_MASTER_QSPI_0 60
73
-
#define SM8550_MASTER_QUP_1 61
74
-
#define SM8550_MASTER_QUP_2 62
75
-
#define SM8550_MASTER_QUP_CORE_0 63
76
-
#define SM8550_MASTER_QUP_CORE_1 64
77
-
#define SM8550_MASTER_QUP_CORE_2 65
78
-
#define SM8550_MASTER_SDCC_2 66
79
-
#define SM8550_MASTER_SDCC_4 67
80
-
#define SM8550_MASTER_SNOC_GC_MEM_NOC 68
81
-
#define SM8550_MASTER_SNOC_SF_MEM_NOC 69
82
-
#define SM8550_MASTER_SP 70
83
-
#define SM8550_MASTER_SYS_TCU 71
84
-
#define SM8550_MASTER_UFS_MEM 72
85
-
#define SM8550_MASTER_USB3_0 73
86
-
#define SM8550_MASTER_VIDEO 74
87
-
#define SM8550_MASTER_VIDEO_CV_PROC 75
88
-
#define SM8550_MASTER_VIDEO_PROC 76
89
-
#define SM8550_MASTER_VIDEO_V_PROC 77
90
-
#define SM8550_SLAVE_A1NOC_SNOC 78
91
-
#define SM8550_SLAVE_A2NOC_SNOC 79
92
-
#define SM8550_SLAVE_AHB2PHY_NORTH 80
93
-
#define SM8550_SLAVE_AHB2PHY_SOUTH 81
94
-
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 82
95
-
#define SM8550_SLAVE_AOSS 83
96
-
#define SM8550_SLAVE_APPSS 84
97
-
#define SM8550_SLAVE_BOOT_IMEM 85
98
-
#define SM8550_SLAVE_CAMERA_CFG 86
99
-
#define SM8550_SLAVE_CDSP_MEM_NOC 87
100
-
#define SM8550_SLAVE_CLK_CTL 88
101
-
#define SM8550_SLAVE_CNOC_CFG 89
102
-
#define SM8550_SLAVE_CNOC_MNOC_CFG 90
103
-
#define SM8550_SLAVE_CNOC_MSS 91
104
-
#define SM8550_SLAVE_CPR_NSPCX 92
105
-
#define SM8550_SLAVE_CRYPTO_0_CFG 93
106
-
#define SM8550_SLAVE_CX_RDPM 94
107
-
#define SM8550_SLAVE_DDRSS_CFG 95
108
-
#define SM8550_SLAVE_DISPLAY_CFG 96
109
-
#define SM8550_SLAVE_EBI1 97
110
-
#define SM8550_SLAVE_EBI1_CAM_IFE_0 98
111
-
#define SM8550_SLAVE_EBI1_CAM_IFE_1 99
112
-
#define SM8550_SLAVE_EBI1_CAM_IFE_2 100
113
-
#define SM8550_SLAVE_EBI1_DISP 101
114
-
#define SM8550_SLAVE_GEM_NOC_CNOC 102
115
-
#define SM8550_SLAVE_GFX3D_CFG 103
116
-
#define SM8550_SLAVE_I2C 104
117
-
#define SM8550_SLAVE_IMEM 105
118
-
#define SM8550_SLAVE_IMEM_CFG 106
119
-
#define SM8550_SLAVE_IPA_CFG 107
120
-
#define SM8550_SLAVE_IPC_ROUTER_CFG 108
121
-
#define SM8550_SLAVE_LLCC 109
122
-
#define SM8550_SLAVE_LLCC_CAM_IFE_0 110
123
-
#define SM8550_SLAVE_LLCC_CAM_IFE_1 111
124
-
#define SM8550_SLAVE_LLCC_CAM_IFE_2 112
125
-
#define SM8550_SLAVE_LLCC_DISP 113
126
-
#define SM8550_SLAVE_LPASS_GEM_NOC 114
127
-
#define SM8550_SLAVE_LPASS_QTB_CFG 115
128
-
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 116
129
-
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 117
130
-
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 118
131
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 119
132
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 120
133
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 121
134
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 122
135
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP 123
136
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 124
137
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 125
138
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 126
139
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 127
140
-
#define SM8550_SLAVE_MX_RDPM 128
141
-
#define SM8550_SLAVE_NSP_QTB_CFG 129
142
-
#define SM8550_SLAVE_PCIE_0 130
143
-
#define SM8550_SLAVE_PCIE_0_CFG 131
144
-
#define SM8550_SLAVE_PCIE_1 132
145
-
#define SM8550_SLAVE_PCIE_1_CFG 133
146
-
#define SM8550_SLAVE_PCIE_ANOC_CFG 134
147
-
#define SM8550_SLAVE_PDM 135
148
-
#define SM8550_SLAVE_PIMEM_CFG 136
149
-
#define SM8550_SLAVE_PRNG 137
150
-
#define SM8550_SLAVE_QDSS_CFG 138
151
-
#define SM8550_SLAVE_QDSS_STM 139
152
-
#define SM8550_SLAVE_QSPI_0 140
153
-
#define SM8550_SLAVE_QUP_1 141
154
-
#define SM8550_SLAVE_QUP_2 142
155
-
#define SM8550_SLAVE_QUP_CORE_0 143
156
-
#define SM8550_SLAVE_QUP_CORE_1 144
157
-
#define SM8550_SLAVE_QUP_CORE_2 145
158
-
#define SM8550_SLAVE_RBCPR_CX_CFG 146
159
-
#define SM8550_SLAVE_RBCPR_MMCX_CFG 147
160
-
#define SM8550_SLAVE_RBCPR_MXA_CFG 148
161
-
#define SM8550_SLAVE_RBCPR_MXC_CFG 149
162
-
#define SM8550_SLAVE_SDCC_2 150
163
-
#define SM8550_SLAVE_SDCC_4 151
164
-
#define SM8550_SLAVE_SERVICE_MNOC 152
165
-
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 153
166
-
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 154
167
-
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 155
168
-
#define SM8550_SLAVE_SPSS_CFG 156
169
-
#define SM8550_SLAVE_TCSR 157
170
-
#define SM8550_SLAVE_TCU 158
171
-
#define SM8550_SLAVE_TLMM 159
172
-
#define SM8550_SLAVE_TME_CFG 160
173
-
#define SM8550_SLAVE_UFS_MEM_CFG 161
174
-
#define SM8550_SLAVE_USB3_0 162
175
-
#define SM8550_SLAVE_VENUS_CFG 163
176
-
#define SM8550_SLAVE_VSENSE_CTRL_CFG 164
15
+
#define SM8550_MASTER_APPSS_PROC 3
16
+
#define SM8550_MASTER_CAMNOC_HF 4
17
+
#define SM8550_MASTER_CAMNOC_ICP 5
18
+
#define SM8550_MASTER_CAMNOC_SF 6
19
+
#define SM8550_MASTER_CDSP_HCP 7
20
+
#define SM8550_MASTER_CDSP_PROC 8
21
+
#define SM8550_MASTER_CNOC_CFG 9
22
+
#define SM8550_MASTER_CNOC_MNOC_CFG 10
23
+
#define SM8550_MASTER_COMPUTE_NOC 11
24
+
#define SM8550_MASTER_CRYPTO 12
25
+
#define SM8550_MASTER_GEM_NOC_CNOC 13
26
+
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
27
+
#define SM8550_MASTER_GFX3D 15
28
+
#define SM8550_MASTER_GIC 16
29
+
#define SM8550_MASTER_GIC_AHB 17
30
+
#define SM8550_MASTER_GPU_TCU 18
31
+
#define SM8550_MASTER_IPA 19
32
+
#define SM8550_MASTER_LLCC 20
33
+
#define SM8550_MASTER_LPASS_GEM_NOC 21
34
+
#define SM8550_MASTER_LPASS_LPINOC 22
35
+
#define SM8550_MASTER_LPASS_PROC 23
36
+
#define SM8550_MASTER_LPIAON_NOC 24
37
+
#define SM8550_MASTER_MDP 25
38
+
#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
39
+
#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
40
+
#define SM8550_MASTER_MSS_PROC 28
41
+
#define SM8550_MASTER_PCIE_0 29
42
+
#define SM8550_MASTER_PCIE_1 30
43
+
#define SM8550_MASTER_PCIE_ANOC_CFG 31
44
+
#define SM8550_MASTER_QDSS_BAM 32
45
+
#define SM8550_MASTER_QDSS_ETR 33
46
+
#define SM8550_MASTER_QDSS_ETR_1 34
47
+
#define SM8550_MASTER_QSPI_0 35
48
+
#define SM8550_MASTER_QUP_1 36
49
+
#define SM8550_MASTER_QUP_2 37
50
+
#define SM8550_MASTER_QUP_CORE_0 38
51
+
#define SM8550_MASTER_QUP_CORE_1 39
52
+
#define SM8550_MASTER_QUP_CORE_2 40
53
+
#define SM8550_MASTER_SDCC_2 41
54
+
#define SM8550_MASTER_SDCC_4 42
55
+
#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
56
+
#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
57
+
#define SM8550_MASTER_SP 45
58
+
#define SM8550_MASTER_SYS_TCU 46
59
+
#define SM8550_MASTER_UFS_MEM 47
60
+
#define SM8550_MASTER_USB3_0 48
61
+
#define SM8550_MASTER_VIDEO 49
62
+
#define SM8550_MASTER_VIDEO_CV_PROC 50
63
+
#define SM8550_MASTER_VIDEO_PROC 51
64
+
#define SM8550_MASTER_VIDEO_V_PROC 52
65
+
#define SM8550_SLAVE_A1NOC_SNOC 53
66
+
#define SM8550_SLAVE_A2NOC_SNOC 54
67
+
#define SM8550_SLAVE_AHB2PHY_NORTH 55
68
+
#define SM8550_SLAVE_AHB2PHY_SOUTH 56
69
+
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
70
+
#define SM8550_SLAVE_AOSS 58
71
+
#define SM8550_SLAVE_APPSS 59
72
+
#define SM8550_SLAVE_BOOT_IMEM 60
73
+
#define SM8550_SLAVE_CAMERA_CFG 61
74
+
#define SM8550_SLAVE_CDSP_MEM_NOC 62
75
+
#define SM8550_SLAVE_CLK_CTL 63
76
+
#define SM8550_SLAVE_CNOC_CFG 64
77
+
#define SM8550_SLAVE_CNOC_MNOC_CFG 65
78
+
#define SM8550_SLAVE_CNOC_MSS 66
79
+
#define SM8550_SLAVE_CPR_NSPCX 67
80
+
#define SM8550_SLAVE_CRYPTO_0_CFG 68
81
+
#define SM8550_SLAVE_CX_RDPM 69
82
+
#define SM8550_SLAVE_DDRSS_CFG 70
83
+
#define SM8550_SLAVE_DISPLAY_CFG 71
84
+
#define SM8550_SLAVE_EBI1 72
85
+
#define SM8550_SLAVE_GEM_NOC_CNOC 73
86
+
#define SM8550_SLAVE_GFX3D_CFG 74
87
+
#define SM8550_SLAVE_I2C 75
88
+
#define SM8550_SLAVE_IMEM 76
89
+
#define SM8550_SLAVE_IMEM_CFG 77
90
+
#define SM8550_SLAVE_IPA_CFG 78
91
+
#define SM8550_SLAVE_IPC_ROUTER_CFG 79
92
+
#define SM8550_SLAVE_LLCC 80
93
+
#define SM8550_SLAVE_LPASS_GEM_NOC 81
94
+
#define SM8550_SLAVE_LPASS_QTB_CFG 82
95
+
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
96
+
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
97
+
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
98
+
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
99
+
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
100
+
#define SM8550_SLAVE_MX_RDPM 88
101
+
#define SM8550_SLAVE_NSP_QTB_CFG 89
102
+
#define SM8550_SLAVE_PCIE_0 90
103
+
#define SM8550_SLAVE_PCIE_0_CFG 91
104
+
#define SM8550_SLAVE_PCIE_1 92
105
+
#define SM8550_SLAVE_PCIE_1_CFG 93
106
+
#define SM8550_SLAVE_PCIE_ANOC_CFG 94
107
+
#define SM8550_SLAVE_PDM 95
108
+
#define SM8550_SLAVE_PIMEM_CFG 96
109
+
#define SM8550_SLAVE_PRNG 97
110
+
#define SM8550_SLAVE_QDSS_CFG 98
111
+
#define SM8550_SLAVE_QDSS_STM 99
112
+
#define SM8550_SLAVE_QSPI_0 100
113
+
#define SM8550_SLAVE_QUP_1 101
114
+
#define SM8550_SLAVE_QUP_2 102
115
+
#define SM8550_SLAVE_QUP_CORE_0 103
116
+
#define SM8550_SLAVE_QUP_CORE_1 104
117
+
#define SM8550_SLAVE_QUP_CORE_2 105
118
+
#define SM8550_SLAVE_RBCPR_CX_CFG 106
119
+
#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
120
+
#define SM8550_SLAVE_RBCPR_MXA_CFG 108
121
+
#define SM8550_SLAVE_RBCPR_MXC_CFG 109
122
+
#define SM8550_SLAVE_SDCC_2 110
123
+
#define SM8550_SLAVE_SDCC_4 111
124
+
#define SM8550_SLAVE_SERVICE_MNOC 112
125
+
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
126
+
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
127
+
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
128
+
#define SM8550_SLAVE_SPSS_CFG 116
129
+
#define SM8550_SLAVE_TCSR 117
130
+
#define SM8550_SLAVE_TCU 118
131
+
#define SM8550_SLAVE_TLMM 119
132
+
#define SM8550_SLAVE_TME_CFG 120
133
+
#define SM8550_SLAVE_UFS_MEM_CFG 121
134
+
#define SM8550_SLAVE_USB3_0 122
135
+
#define SM8550_SLAVE_VENUS_CFG 123
136
+
#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
177
137
178
138
#endif
+6
-321
drivers/interconnect/qcom/x1e80100.c
+6
-321
drivers/interconnect/qcom/x1e80100.c
···
670
670
.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
671
671
};
672
672
673
-
static struct qcom_icc_node qnm_mnoc_hf_disp = {
674
-
.name = "qnm_mnoc_hf_disp",
675
-
.id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,
676
-
.channels = 2,
677
-
.buswidth = 32,
678
-
.num_links = 1,
679
-
.links = { X1E80100_SLAVE_LLCC_DISP },
680
-
};
681
-
682
-
static struct qcom_icc_node qnm_pcie_disp = {
683
-
.name = "qnm_pcie_disp",
684
-
.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,
685
-
.channels = 1,
686
-
.buswidth = 64,
687
-
.num_links = 1,
688
-
.links = { X1E80100_SLAVE_LLCC_DISP },
689
-
};
690
-
691
-
static struct qcom_icc_node llcc_mc_disp = {
692
-
.name = "llcc_mc_disp",
693
-
.id = X1E80100_MASTER_LLCC_DISP,
694
-
.channels = 8,
695
-
.buswidth = 4,
696
-
.num_links = 1,
697
-
.links = { X1E80100_SLAVE_EBI1_DISP },
698
-
};
699
-
700
-
static struct qcom_icc_node qnm_mdp_disp = {
701
-
.name = "qnm_mdp_disp",
702
-
.id = X1E80100_MASTER_MDP_DISP,
703
-
.channels = 2,
704
-
.buswidth = 32,
705
-
.num_links = 1,
706
-
.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },
707
-
};
708
-
709
-
static struct qcom_icc_node qnm_pcie_pcie = {
710
-
.name = "qnm_pcie_pcie",
711
-
.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,
712
-
.channels = 1,
713
-
.buswidth = 64,
714
-
.num_links = 1,
715
-
.links = { X1E80100_SLAVE_LLCC_PCIE },
716
-
};
717
-
718
-
static struct qcom_icc_node llcc_mc_pcie = {
719
-
.name = "llcc_mc_pcie",
720
-
.id = X1E80100_MASTER_LLCC_PCIE,
721
-
.channels = 8,
722
-
.buswidth = 4,
723
-
.num_links = 1,
724
-
.links = { X1E80100_SLAVE_EBI1_PCIE },
725
-
};
726
-
727
-
static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {
728
-
.name = "qnm_pcie_north_gem_noc_pcie",
729
-
.id = X1E80100_MASTER_PCIE_NORTH_PCIE,
730
-
.channels = 1,
731
-
.buswidth = 64,
732
-
.num_links = 1,
733
-
.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
734
-
};
735
-
736
-
static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {
737
-
.name = "qnm_pcie_south_gem_noc_pcie",
738
-
.id = X1E80100_MASTER_PCIE_SOUTH_PCIE,
739
-
.channels = 1,
740
-
.buswidth = 64,
741
-
.num_links = 1,
742
-
.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
743
-
};
744
-
745
-
static struct qcom_icc_node xm_pcie_3_pcie = {
746
-
.name = "xm_pcie_3_pcie",
747
-
.id = X1E80100_MASTER_PCIE_3_PCIE,
748
-
.channels = 1,
749
-
.buswidth = 64,
750
-
.num_links = 1,
751
-
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
752
-
};
753
-
754
-
static struct qcom_icc_node xm_pcie_4_pcie = {
755
-
.name = "xm_pcie_4_pcie",
756
-
.id = X1E80100_MASTER_PCIE_4_PCIE,
757
-
.channels = 1,
758
-
.buswidth = 8,
759
-
.num_links = 1,
760
-
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
761
-
};
762
-
763
-
static struct qcom_icc_node xm_pcie_5_pcie = {
764
-
.name = "xm_pcie_5_pcie",
765
-
.id = X1E80100_MASTER_PCIE_5_PCIE,
766
-
.channels = 1,
767
-
.buswidth = 8,
768
-
.num_links = 1,
769
-
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
770
-
};
771
-
772
-
static struct qcom_icc_node xm_pcie_0_pcie = {
773
-
.name = "xm_pcie_0_pcie",
774
-
.id = X1E80100_MASTER_PCIE_0_PCIE,
775
-
.channels = 1,
776
-
.buswidth = 16,
777
-
.num_links = 1,
778
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
779
-
};
780
-
781
-
static struct qcom_icc_node xm_pcie_1_pcie = {
782
-
.name = "xm_pcie_1_pcie",
783
-
.id = X1E80100_MASTER_PCIE_1_PCIE,
784
-
.channels = 1,
785
-
.buswidth = 16,
786
-
.num_links = 1,
787
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
788
-
};
789
-
790
-
static struct qcom_icc_node xm_pcie_2_pcie = {
791
-
.name = "xm_pcie_2_pcie",
792
-
.id = X1E80100_MASTER_PCIE_2_PCIE,
793
-
.channels = 1,
794
-
.buswidth = 16,
795
-
.num_links = 1,
796
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
797
-
};
798
-
799
-
static struct qcom_icc_node xm_pcie_6a_pcie = {
800
-
.name = "xm_pcie_6a_pcie",
801
-
.id = X1E80100_MASTER_PCIE_6A_PCIE,
802
-
.channels = 1,
803
-
.buswidth = 32,
804
-
.num_links = 1,
805
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
806
-
};
807
-
808
-
static struct qcom_icc_node xm_pcie_6b_pcie = {
809
-
.name = "xm_pcie_6b_pcie",
810
-
.id = X1E80100_MASTER_PCIE_6B_PCIE,
811
-
.channels = 1,
812
-
.buswidth = 16,
813
-
.num_links = 1,
814
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
815
-
};
816
-
817
673
static struct qcom_icc_node qns_a1noc_snoc = {
818
674
.name = "qns_a1noc_snoc",
819
675
.id = X1E80100_SLAVE_A1NOC_SNOC,
···
1370
1514
.links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
1371
1515
};
1372
1516
1373
-
static struct qcom_icc_node qns_llcc_disp = {
1374
-
.name = "qns_llcc_disp",
1375
-
.id = X1E80100_SLAVE_LLCC_DISP,
1376
-
.channels = 8,
1377
-
.buswidth = 16,
1378
-
.num_links = 1,
1379
-
.links = { X1E80100_MASTER_LLCC_DISP },
1380
-
};
1381
-
1382
-
static struct qcom_icc_node ebi_disp = {
1383
-
.name = "ebi_disp",
1384
-
.id = X1E80100_SLAVE_EBI1_DISP,
1385
-
.channels = 8,
1386
-
.buswidth = 4,
1387
-
.num_links = 0,
1388
-
};
1389
-
1390
-
static struct qcom_icc_node qns_mem_noc_hf_disp = {
1391
-
.name = "qns_mem_noc_hf_disp",
1392
-
.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,
1393
-
.channels = 2,
1394
-
.buswidth = 32,
1395
-
.num_links = 1,
1396
-
.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },
1397
-
};
1398
-
1399
-
static struct qcom_icc_node qns_llcc_pcie = {
1400
-
.name = "qns_llcc_pcie",
1401
-
.id = X1E80100_SLAVE_LLCC_PCIE,
1402
-
.channels = 8,
1403
-
.buswidth = 16,
1404
-
.num_links = 1,
1405
-
.links = { X1E80100_MASTER_LLCC_PCIE },
1406
-
};
1407
-
1408
-
static struct qcom_icc_node ebi_pcie = {
1409
-
.name = "ebi_pcie",
1410
-
.id = X1E80100_SLAVE_EBI1_PCIE,
1411
-
.channels = 8,
1412
-
.buswidth = 4,
1413
-
.num_links = 0,
1414
-
};
1415
-
1416
-
static struct qcom_icc_node qns_pcie_mem_noc_pcie = {
1417
-
.name = "qns_pcie_mem_noc_pcie",
1418
-
.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,
1419
-
.channels = 1,
1420
-
.buswidth = 64,
1421
-
.num_links = 1,
1422
-
.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },
1423
-
};
1424
-
1425
-
static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {
1426
-
.name = "qns_pcie_north_gem_noc_pcie",
1427
-
.id = X1E80100_SLAVE_PCIE_NORTH_PCIE,
1428
-
.channels = 1,
1429
-
.buswidth = 64,
1430
-
.num_links = 1,
1431
-
.links = { X1E80100_MASTER_PCIE_NORTH_PCIE },
1432
-
};
1433
-
1434
-
static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {
1435
-
.name = "qns_pcie_south_gem_noc_pcie",
1436
-
.id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,
1437
-
.channels = 1,
1438
-
.buswidth = 64,
1439
-
.num_links = 1,
1440
-
.links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },
1441
-
};
1442
-
1443
1517
static struct qcom_icc_bcm bcm_acv = {
1444
1518
.name = "ACV",
1445
1519
.num_nodes = 1,
···
1541
1755
.nodes = { &qnm_usb_anoc },
1542
1756
};
1543
1757
1544
-
static struct qcom_icc_bcm bcm_acv_disp = {
1545
-
.name = "ACV",
1546
-
.num_nodes = 1,
1547
-
.nodes = { &ebi_disp },
1548
-
};
1549
-
1550
-
static struct qcom_icc_bcm bcm_mc0_disp = {
1551
-
.name = "MC0",
1552
-
.num_nodes = 1,
1553
-
.nodes = { &ebi_disp },
1554
-
};
1555
-
1556
-
static struct qcom_icc_bcm bcm_mm0_disp = {
1557
-
.name = "MM0",
1558
-
.num_nodes = 1,
1559
-
.nodes = { &qns_mem_noc_hf_disp },
1560
-
};
1561
-
1562
-
static struct qcom_icc_bcm bcm_mm1_disp = {
1563
-
.name = "MM1",
1564
-
.num_nodes = 1,
1565
-
.nodes = { &qnm_mdp_disp },
1566
-
};
1567
-
1568
-
static struct qcom_icc_bcm bcm_sh0_disp = {
1569
-
.name = "SH0",
1570
-
.num_nodes = 1,
1571
-
.nodes = { &qns_llcc_disp },
1572
-
};
1573
-
1574
-
static struct qcom_icc_bcm bcm_sh1_disp = {
1575
-
.name = "SH1",
1576
-
.num_nodes = 2,
1577
-
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
1578
-
};
1579
-
1580
-
static struct qcom_icc_bcm bcm_acv_pcie = {
1581
-
.name = "ACV",
1582
-
.num_nodes = 1,
1583
-
.nodes = { &ebi_pcie },
1584
-
};
1585
-
1586
-
static struct qcom_icc_bcm bcm_mc0_pcie = {
1587
-
.name = "MC0",
1588
-
.num_nodes = 1,
1589
-
.nodes = { &ebi_pcie },
1590
-
};
1591
-
1592
-
static struct qcom_icc_bcm bcm_pc0_pcie = {
1593
-
.name = "PC0",
1594
-
.num_nodes = 1,
1595
-
.nodes = { &qns_pcie_mem_noc_pcie },
1596
-
};
1597
-
1598
-
static struct qcom_icc_bcm bcm_sh0_pcie = {
1599
-
.name = "SH0",
1600
-
.num_nodes = 1,
1601
-
.nodes = { &qns_llcc_pcie },
1602
-
};
1603
-
1604
-
static struct qcom_icc_bcm bcm_sh1_pcie = {
1605
-
.name = "SH1",
1606
-
.num_nodes = 1,
1607
-
.nodes = { &qnm_pcie_pcie },
1608
-
};
1609
-
1610
-
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
1758
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1611
1759
};
1612
1760
1613
1761
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
···
1702
1982
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1703
1983
&bcm_sh0,
1704
1984
&bcm_sh1,
1705
-
&bcm_sh0_disp,
1706
-
&bcm_sh1_disp,
1707
-
&bcm_sh0_pcie,
1708
-
&bcm_sh1_pcie,
1709
1985
};
1710
1986
1711
1987
static struct qcom_icc_node * const gem_noc_nodes[] = {
···
1720
2004
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1721
2005
[SLAVE_LLCC] = &qns_llcc,
1722
2006
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1723
-
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1724
-
[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1725
-
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1726
-
[MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie,
1727
-
[SLAVE_LLCC_PCIE] = &qns_llcc_pcie,
1728
2007
};
1729
2008
1730
2009
static const struct qcom_icc_desc x1e80100_gem_noc = {
···
1729
2018
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1730
2019
};
1731
2020
1732
-
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
2021
+
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1733
2022
};
1734
2023
1735
2024
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
···
1778
2067
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1779
2068
&bcm_acv,
1780
2069
&bcm_mc0,
1781
-
&bcm_acv_disp,
1782
-
&bcm_mc0_disp,
1783
-
&bcm_acv_pcie,
1784
-
&bcm_mc0_pcie,
1785
2070
};
1786
2071
1787
2072
static struct qcom_icc_node * const mc_virt_nodes[] = {
1788
2073
[MASTER_LLCC] = &llcc_mc,
1789
2074
[SLAVE_EBI1] = &ebi,
1790
-
[MASTER_LLCC_DISP] = &llcc_mc_disp,
1791
-
[SLAVE_EBI1_DISP] = &ebi_disp,
1792
-
[MASTER_LLCC_PCIE] = &llcc_mc_pcie,
1793
-
[SLAVE_EBI1_PCIE] = &ebi_pcie,
1794
2075
};
1795
2076
1796
2077
static const struct qcom_icc_desc x1e80100_mc_virt = {
···
1795
2092
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1796
2093
&bcm_mm0,
1797
2094
&bcm_mm1,
1798
-
&bcm_mm0_disp,
1799
-
&bcm_mm1_disp,
1800
2095
};
1801
2096
1802
2097
static struct qcom_icc_node * const mmss_noc_nodes[] = {
···
1811
2110
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1812
2111
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1813
2112
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1814
-
[MASTER_MDP_DISP] = &qnm_mdp_disp,
1815
-
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1816
2113
};
1817
2114
1818
2115
static const struct qcom_icc_desc x1e80100_mmss_noc = {
···
1838
2139
1839
2140
static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
1840
2141
&bcm_pc0,
1841
-
&bcm_pc0_pcie,
1842
2142
};
1843
2143
1844
2144
static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
1845
2145
[MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
1846
2146
[MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
1847
2147
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1848
-
[MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie,
1849
-
[MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie,
1850
-
[SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie,
1851
2148
};
1852
2149
1853
2150
static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
···
1861
2166
[MASTER_PCIE_4] = &xm_pcie_4,
1862
2167
[MASTER_PCIE_5] = &xm_pcie_5,
1863
2168
[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
1864
-
[MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie,
1865
-
[MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie,
1866
-
[MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie,
1867
-
[SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie,
1868
2169
};
1869
2170
1870
2171
static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
···
1870
2179
.num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),
1871
2180
};
1872
2181
1873
-
static struct qcom_icc_bcm *pcie_south_anoc_bcms[] = {
2182
+
static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = {
1874
2183
};
1875
2184
1876
2185
static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
···
1880
2189
[MASTER_PCIE_6A] = &xm_pcie_6a,
1881
2190
[MASTER_PCIE_6B] = &xm_pcie_6b,
1882
2191
[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
1883
-
[MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie,
1884
-
[MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie,
1885
-
[MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie,
1886
-
[MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie,
1887
-
[MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie,
1888
-
[SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie,
1889
2192
};
1890
2193
1891
2194
static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
···
1889
2204
.num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),
1890
2205
};
1891
2206
1892
-
static struct qcom_icc_bcm *system_noc_bcms[] = {
2207
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
1893
2208
&bcm_sn0,
1894
2209
&bcm_sn2,
1895
2210
&bcm_sn3,
···
1927
2242
.num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),
1928
2243
};
1929
2244
1930
-
static struct qcom_icc_bcm *usb_north_anoc_bcms[] = {
2245
+
static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = {
1931
2246
};
1932
2247
1933
2248
static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
···
1943
2258
.num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
1944
2259
};
1945
2260
1946
-
static struct qcom_icc_bcm *usb_south_anoc_bcms[] = {
2261
+
static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
1947
2262
};
1948
2263
1949
2264
static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
+1
-1
drivers/interconnect/samsung/exynos.c
+1
-1
drivers/interconnect/samsung/exynos.c
+1
-1
drivers/memory/tegra/mc.c
+1
-1
drivers/memory/tegra/mc.c
···
755
755
[6] = "SMMU translation error",
756
756
};
757
757
758
-
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data)
758
+
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec, void *data)
759
759
{
760
760
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
761
761
struct icc_node *node;
+1
-1
drivers/memory/tegra/tegra124-emc.c
+1
-1
drivers/memory/tegra/tegra124-emc.c
···
1285
1285
}
1286
1286
1287
1287
static struct icc_node_data *
1288
-
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1288
+
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1289
1289
{
1290
1290
struct icc_provider *provider = data;
1291
1291
struct icc_node_data *ndata;
+1
-1
drivers/memory/tegra/tegra124.c
+1
-1
drivers/memory/tegra/tegra124.c
···
1170
1170
}
1171
1171
1172
1172
static struct icc_node_data *
1173
-
tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1173
+
tegra124_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1174
1174
{
1175
1175
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1176
1176
const struct tegra_mc_client *client;
+1
-1
drivers/memory/tegra/tegra186-emc.c
+1
-1
drivers/memory/tegra/tegra186-emc.c
+1
-1
drivers/memory/tegra/tegra20-emc.c
+1
-1
drivers/memory/tegra/tegra20-emc.c
···
950
950
}
951
951
952
952
static struct icc_node_data *
953
-
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
953
+
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
954
954
{
955
955
struct icc_provider *provider = data;
956
956
struct icc_node_data *ndata;
+1
-1
drivers/memory/tegra/tegra20.c
+1
-1
drivers/memory/tegra/tegra20.c
···
390
390
}
391
391
392
392
static struct icc_node_data *
393
-
tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
393
+
tegra20_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
394
394
{
395
395
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
396
396
unsigned int i, idx = spec->args[0];
+1
-1
drivers/memory/tegra/tegra30-emc.c
+1
-1
drivers/memory/tegra/tegra30-emc.c
···
1468
1468
}
1469
1469
1470
1470
static struct icc_node_data *
1471
-
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1471
+
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1472
1472
{
1473
1473
struct icc_provider *provider = data;
1474
1474
struct icc_node_data *ndata;
+1
-1
drivers/memory/tegra/tegra30.c
+1
-1
drivers/memory/tegra/tegra30.c
···
1332
1332
}
1333
1333
1334
1334
static struct icc_node_data *
1335
-
tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1335
+
tegra30_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1336
1336
{
1337
1337
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1338
1338
const struct tegra_mc_client *client;
-24
include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
-24
include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
···
112
112
#define SLAVE_GEM_NOC_CNOC 12
113
113
#define SLAVE_LLCC 13
114
114
#define SLAVE_MEM_NOC_PCIE_SNOC 14
115
-
#define MASTER_MNOC_HF_MEM_NOC_DISP 15
116
-
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
117
-
#define SLAVE_LLCC_DISP 17
118
-
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18
119
-
#define SLAVE_LLCC_PCIE 19
120
115
121
116
#define MASTER_LPIAON_NOC 0
122
117
#define SLAVE_LPASS_GEM_NOC 1
···
124
129
125
130
#define MASTER_LLCC 0
126
131
#define SLAVE_EBI1 1
127
-
#define MASTER_LLCC_DISP 2
128
-
#define SLAVE_EBI1_DISP 3
129
-
#define MASTER_LLCC_PCIE 4
130
-
#define SLAVE_EBI1_PCIE 5
131
132
132
133
#define MASTER_AV1_ENC 0
133
134
#define MASTER_CAMNOC_HF 1
···
138
147
#define SLAVE_MNOC_HF_MEM_NOC 10
139
148
#define SLAVE_MNOC_SF_MEM_NOC 11
140
149
#define SLAVE_SERVICE_MNOC 12
141
-
#define MASTER_MDP_DISP 13
142
-
#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
143
150
144
151
#define MASTER_CDSP_PROC 0
145
152
#define SLAVE_CDSP_MEM_NOC 1
···
145
156
#define MASTER_PCIE_NORTH 0
146
157
#define MASTER_PCIE_SOUTH 1
147
158
#define SLAVE_ANOC_PCIE_GEM_NOC 2
148
-
#define MASTER_PCIE_NORTH_PCIE 3
149
-
#define MASTER_PCIE_SOUTH_PCIE 4
150
-
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5
151
159
152
160
#define MASTER_PCIE_3 0
153
161
#define MASTER_PCIE_4 1
154
162
#define MASTER_PCIE_5 2
155
163
#define SLAVE_PCIE_NORTH 3
156
-
#define MASTER_PCIE_3_PCIE 4
157
-
#define MASTER_PCIE_4_PCIE 5
158
-
#define MASTER_PCIE_5_PCIE 6
159
-
#define SLAVE_PCIE_NORTH_PCIE 7
160
164
161
165
#define MASTER_PCIE_0 0
162
166
#define MASTER_PCIE_1 1
···
157
175
#define MASTER_PCIE_6A 3
158
176
#define MASTER_PCIE_6B 4
159
177
#define SLAVE_PCIE_SOUTH 5
160
-
#define MASTER_PCIE_0_PCIE 6
161
-
#define MASTER_PCIE_1_PCIE 7
162
-
#define MASTER_PCIE_2_PCIE 8
163
-
#define MASTER_PCIE_6A_PCIE 9
164
-
#define MASTER_PCIE_6B_PCIE 10
165
-
#define SLAVE_PCIE_SOUTH_PCIE 11
166
178
167
179
#define MASTER_A1NOC_SNOC 0
168
180
#define MASTER_A2NOC_SNOC 1
+6
-5
include/linux/interconnect-provider.h
+6
-5
include/linux/interconnect-provider.h
···
36
36
struct icc_node *nodes[] __counted_by(num_nodes);
37
37
};
38
38
39
-
struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
39
+
struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
40
40
void *data);
41
41
42
42
/**
···
65
65
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
66
66
void (*pre_aggregate)(struct icc_node *node);
67
67
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
68
-
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
69
-
struct icc_node_data* (*xlate_extended)(struct of_phandle_args *spec, void *data);
68
+
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
69
+
struct icc_node_data* (*xlate_extended)(const struct of_phandle_args *spec,
70
+
void *data);
70
71
struct device *dev;
71
72
int users;
72
73
bool inter_set;
···
125
124
void icc_provider_init(struct icc_provider *provider);
126
125
int icc_provider_register(struct icc_provider *provider);
127
126
void icc_provider_deregister(struct icc_provider *provider);
128
-
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec);
127
+
struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec);
129
128
void icc_sync_state(struct device *dev);
130
129
131
130
#else
···
172
171
173
172
static inline void icc_provider_deregister(struct icc_provider *provider) { }
174
173
175
-
static inline struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
174
+
static inline struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
176
175
{
177
176
return ERR_PTR(-ENOTSUPP);
178
177
}
+4
-3
include/soc/tegra/mc.h
+4
-3
include/soc/tegra/mc.h
···
146
146
int (*set)(struct icc_node *src, struct icc_node *dst);
147
147
int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
148
148
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
149
-
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
150
-
struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
149
+
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
150
+
struct icc_node_data *(*xlate_extended)(const struct of_phandle_args *spec,
151
151
void *data);
152
152
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
153
153
};
154
154
155
-
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data);
155
+
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec,
156
+
void *data);
156
157
extern const struct tegra_mc_icc_ops tegra_mc_icc_ops;
157
158
158
159
struct tegra_mc_ops {