Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6524/1: GIC irq desciptor bug fix
ARM: 6523/1: iop: ensure sched_clock() is notrace
ARM: 6456/1: Fix for building DEBUG with sa11xx_base.c as a module.
ARM: 6519/1: kuser: Fix incorrect cmpxchg syscall in kuser helpers
ARM: 6505/1: kprobes: Don't HAVE_KPROBES when CONFIG_THUMB2_KERNEL is selected
ARM: 6508/1: vexpress: Correct data alignment in headsmp.S for CONFIG_THUMB2_KERNEL
ARM: 6507/1: RealView: Correct data alignment in headsmp.S for CONFIG_THUMB2_KERNEL
ARM: 6504/1: Thumb-2: Fix long-distance conditional branches in head.S for Thumb-2.
ARM: 6503/1: Thumb-2: Restore sensible zImage header layout for CONFIG_THUMB2_KERNEL
ARM: 6502/1: Thumb-2: Fix CONFIG_THUMB2_KERNEL breakage in compressed/head.S
ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in mm/proc-v7.S
ARM: 6500/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in kernel/head.S
ARM: 6499/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in bootp/init.S
ARM: 6498/1: vfp: Correct data alignment for CONFIG_THUMB2_KERNEL
ARM: 6497/1: kexec: Correct data alignment for CONFIG_THUMB2_KERNEL
ARM: 6496/1: GIC: Do not try to register more then NR_IRQS interrupts
ARM: cns3xxx: Fix build with CONFIG_PCI=y
+56
-30
+1
-1
arch/arm/Kconfig
+1
-1
arch/arm/Kconfig
···
9
9
select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
10
10
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
11
11
select HAVE_ARCH_KGDB
12
-
select HAVE_KPROBES if (!XIP_KERNEL)
12
+
select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
13
13
select HAVE_KRETPROBES if (HAVE_KPROBES)
14
14
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
15
15
select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
-5
arch/arm/boot/Makefile
-5
arch/arm/boot/Makefile
···
70
70
$(obj)/uImage: LOADADDR=$(ZRELADDR)
71
71
endif
72
72
73
-
ifeq ($(CONFIG_THUMB2_KERNEL),y)
74
-
# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
75
-
$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
76
-
else
77
73
$(obj)/uImage: STARTADDR=$(LOADADDR)
78
-
endif
79
74
80
75
$(obj)/uImage: $(obj)/zImage FORCE
81
76
$(call if_changed,uimage)
+2
arch/arm/boot/bootp/init.S
+2
arch/arm/boot/bootp/init.S
+10
-3
arch/arm/boot/compressed/head.S
+10
-3
arch/arm/boot/compressed/head.S
···
125
125
* sort out different calling conventions
126
126
*/
127
127
.align
128
+
.arm @ Always enter in ARM state
128
129
start:
129
130
.type start,#function
130
-
.rept 8
131
+
THUMB( adr r12, BSYM(1f) )
132
+
THUMB( bx r12 )
133
+
THUMB( .rept 6 )
134
+
ARM( .rept 8 )
131
135
mov r0, r0
132
136
.endr
133
137
···
139
135
.word 0x016f2818 @ Magic numbers to help the loader
140
136
.word start @ absolute load/run zImage address
141
137
.word _edata @ zImage end address
138
+
THUMB( .thumb )
142
139
1: mov r7, r1 @ save architecture ID
143
140
mov r8, r2 @ save atags pointer
144
141
···
179
174
ldr sp, [r0, #28]
180
175
#ifdef CONFIG_AUTO_ZRELADDR
181
176
@ determine final kernel image address
182
-
and r4, pc, #0xf8000000
177
+
mov r4, pc
178
+
and r4, r4, #0xf8000000
183
179
add r4, r4, #TEXT_OFFSET
184
180
#else
185
181
ldr r4, =zreladdr
···
451
445
*/
452
446
mov r1, #0x1e
453
447
orr r1, r1, #3 << 10
454
-
mov r2, pc, lsr #20
448
+
mov r2, pc
449
+
mov r2, r2, lsr #20
455
450
orr r1, r1, r2, lsl #20
456
451
add r0, r3, r2, lsl #2
457
452
str r1, [r0], #4
+24
-16
arch/arm/common/gic.c
+24
-16
arch/arm/common/gic.c
···
146
146
unsigned int shift = (irq % 4) * 8;
147
147
unsigned int cpu = cpumask_first(mask_val);
148
148
u32 val;
149
+
struct irq_desc *desc;
149
150
150
151
spin_lock(&irq_controller_lock);
151
-
irq_desc[irq].node = cpu;
152
+
desc = irq_to_desc(irq);
153
+
if (desc == NULL) {
154
+
spin_unlock(&irq_controller_lock);
155
+
return -EINVAL;
156
+
}
157
+
desc->node = cpu;
152
158
val = readl(reg) & ~(0xff << shift);
153
159
val |= 1 << (cpu + shift);
154
160
writel(val, reg);
···
216
210
void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
217
211
unsigned int irq_start)
218
212
{
219
-
unsigned int max_irq, i;
213
+
unsigned int gic_irqs, irq_limit, i;
220
214
u32 cpumask = 1 << smp_processor_id();
221
215
222
216
if (gic_nr >= MAX_GIC_NR)
···
232
226
233
227
/*
234
228
* Find out how many interrupts are supported.
235
-
*/
236
-
max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
237
-
max_irq = (max_irq + 1) * 32;
238
-
239
-
/*
240
229
* The GIC only supports up to 1020 interrupt sources.
241
-
* Limit this to either the architected maximum, or the
242
-
* platform maximum.
243
230
*/
244
-
if (max_irq > max(1020, NR_IRQS))
245
-
max_irq = max(1020, NR_IRQS);
231
+
gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
232
+
gic_irqs = (gic_irqs + 1) * 32;
233
+
if (gic_irqs > 1020)
234
+
gic_irqs = 1020;
246
235
247
236
/*
248
237
* Set all global interrupts to be level triggered, active low.
249
238
*/
250
-
for (i = 32; i < max_irq; i += 16)
239
+
for (i = 32; i < gic_irqs; i += 16)
251
240
writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
252
241
253
242
/*
254
243
* Set all global interrupts to this CPU only.
255
244
*/
256
-
for (i = 32; i < max_irq; i += 4)
245
+
for (i = 32; i < gic_irqs; i += 4)
257
246
writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
258
247
259
248
/*
260
249
* Set priority on all global interrupts.
261
250
*/
262
-
for (i = 32; i < max_irq; i += 4)
251
+
for (i = 32; i < gic_irqs; i += 4)
263
252
writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
264
253
265
254
/*
266
255
* Disable all interrupts. Leave the PPI and SGIs alone
267
256
* as these enables are banked registers.
268
257
*/
269
-
for (i = 32; i < max_irq; i += 32)
258
+
for (i = 32; i < gic_irqs; i += 32)
270
259
writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
260
+
261
+
/*
262
+
* Limit number of interrupts registered to the platform maximum
263
+
*/
264
+
irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
265
+
if (WARN_ON(irq_limit > NR_IRQS))
266
+
irq_limit = NR_IRQS;
271
267
272
268
/*
273
269
* Setup the Linux IRQ subsystem.
274
270
*/
275
-
for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
271
+
for (i = irq_start; i < irq_limit; i++) {
276
272
set_irq_chip(i, &gic_chip);
277
273
set_irq_chip_data(i, &gic_data[gic_nr]);
278
274
set_irq_handler(i, handle_level_irq);
+1
-1
arch/arm/kernel/entry-armv.S
+1
-1
arch/arm/kernel/entry-armv.S
+7
arch/arm/kernel/head.S
+7
arch/arm/kernel/head.S
···
85
85
mrc p15, 0, r9, c0, c0 @ get processor id
86
86
bl __lookup_processor_type @ r5=procinfo r9=cpuid
87
87
movs r10, r5 @ invalid processor (r5=0)?
88
+
THUMB( it eq ) @ force fixup-able long branch encoding
88
89
beq __error_p @ yes, error 'p'
89
90
bl __lookup_machine_type @ r5=machinfo
90
91
movs r8, r5 @ invalid machine (r5=0)?
92
+
THUMB( it eq ) @ force fixup-able long branch encoding
91
93
beq __error_a @ yes, error 'a'
92
94
bl __vet_atags
93
95
#ifdef CONFIG_SMP_ON_UP
···
264
262
mov pc, lr
265
263
ENDPROC(__create_page_tables)
266
264
.ltorg
265
+
.align
267
266
__enable_mmu_loc:
268
267
.long .
269
268
.long __enable_mmu
···
285
282
bl __lookup_processor_type
286
283
movs r10, r5 @ invalid processor?
287
284
moveq r0, #'p' @ yes, error 'p'
285
+
THUMB( it eq ) @ force fixup-able long branch encoding
288
286
beq __error_p
289
287
290
288
/*
···
311
307
mov fp, #0
312
308
b secondary_start_kernel
313
309
ENDPROC(__secondary_switched)
310
+
311
+
.align
314
312
315
313
.type __secondary_data, %object
316
314
__secondary_data:
···
419
413
mov pc, lr
420
414
ENDPROC(__fixup_smp)
421
415
416
+
.align
422
417
1: .word .
423
418
.word __smpalt_begin
424
419
.word __smpalt_end
+2
arch/arm/kernel/relocate_kernel.S
+2
arch/arm/kernel/relocate_kernel.S
+1
-1
arch/arm/mach-cns3xxx/pcie.c
+1
-1
arch/arm/mach-cns3xxx/pcie.c
+1
arch/arm/mach-realview/headsmp.S
+1
arch/arm/mach-realview/headsmp.S
+1
arch/arm/mach-vexpress/headsmp.S
+1
arch/arm/mach-vexpress/headsmp.S
+2
-2
arch/arm/mm/proc-v7.S
+2
-2
arch/arm/mm/proc-v7.S
···
381
381
PMD_SECT_XN | \
382
382
PMD_SECT_AP_WRITE | \
383
383
PMD_SECT_AP_READ
384
-
b __v7_ca9mp_setup
384
+
W(b) __v7_ca9mp_setup
385
385
.long cpu_arch_name
386
386
.long cpu_elf_name
387
387
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
···
413
413
PMD_SECT_XN | \
414
414
PMD_SECT_AP_WRITE | \
415
415
PMD_SECT_AP_READ
416
-
b __v7_setup
416
+
W(b) __v7_setup
417
417
.long cpu_arch_name
418
418
.long cpu_elf_name
419
419
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
+2
-1
arch/arm/plat-iop/time.c
+2
-1
arch/arm/plat-iop/time.c
···
18
18
#include <linux/time.h>
19
19
#include <linux/init.h>
20
20
#include <linux/timex.h>
21
+
#include <linux/sched.h>
21
22
#include <linux/io.h>
22
23
#include <linux/clocksource.h>
23
24
#include <linux/clockchips.h>
···
37
36
/*
38
37
* IOP clocksource (free-running timer 1).
39
38
*/
40
-
static cycle_t iop_clocksource_read(struct clocksource *unused)
39
+
static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
41
40
{
42
41
return 0xffffffffu - read_tcr1();
43
42
}
+1
arch/arm/vfp/vfphw.S
+1
arch/arm/vfp/vfphw.S