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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
This adds the necessary bits to drive the VPU blk-ctrl on the i.MX8MQ, to
avoid putting more of this functionality into the decoder driver.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
authored by
Lucas Stach
and committed by
Shawn Guo
608d7c32
a1415fbc
+66
+66
drivers/soc/imx/imx8m-blk-ctrl.c
+66
drivers/soc/imx/imx8m-blk-ctrl.c
···
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/power/imx8mn-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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#define BLK_SFT_RSTN 0x0
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#define BLK_CLK_EN 0x4
···
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.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
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};
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static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
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power_nb);
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if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
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return NOTIFY_OK;
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/*
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* The ADB in the VPUMIX domain has no separate reset and clock
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* enable bits, but is ungated and reset together with the VPUs. The
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* reset and clock enable inputs to the ADB is a logical OR of the
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* VPU bits. In order to set the G2 fuse bits, the G2 clock must
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* also be enabled.
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*/
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regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
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regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));
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if (action == GENPD_NOTIFY_ON) {
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/*
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* On power up we have no software backchannel to the GPC to
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* wait for the ADB handshake to happen, so we just delay for a
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* bit. On power down the GPC driver waits for the handshake.
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*/
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udelay(5);
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/* set "fuse" bits to enable the VPUs */
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regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
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regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
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regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
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}
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return NOTIFY_OK;
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}
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static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
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[IMX8MQ_VPUBLK_PD_G1] = {
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.name = "vpublk-g1",
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.clk_names = (const char *[]){ "g1", },
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.num_clks = 1,
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.gpc_name = "g1",
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.rst_mask = BIT(1),
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.clk_mask = BIT(1),
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},
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[IMX8MQ_VPUBLK_PD_G2] = {
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.name = "vpublk-g2",
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.clk_names = (const char *[]){ "g2", },
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.num_clks = 1,
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.gpc_name = "g2",
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.rst_mask = BIT(0),
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.clk_mask = BIT(0),
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},
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};
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static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {
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.max_reg = 0x14,
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.power_notifier_fn = imx8mq_vpu_power_notifier,
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.domains = imx8mq_vpu_blk_ctl_domain_data,
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.num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),
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};
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static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
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{
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.compatible = "fsl,imx8mm-vpu-blk-ctrl",
···
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}, {
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.compatible = "fsl,imx8mn-disp-blk-ctrl",
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.data = &imx8mn_disp_blk_ctl_dev_data
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}, {
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.compatible = "fsl,imx8mq-vpu-blk-ctrl",
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.data = &imx8mq_vpu_blk_ctl_dev_data
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}, {
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/* Sentinel */
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}