Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/adreno: Do CX GBIF config before GMU start
GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF
configurations before GMU wakes up. This was not a problem so far, but
A840 GPU is very sensitive to this requirement. Also, move these
registers to the catalog.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689024/
Message-ID: <20251118-kaana-gpu-support-v4-17-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
60a4e18e
0700b9f6
+54
-14
+32
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+32
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
···
672
672
};
673
673
DECLARE_ADRENO_PROTECT(a690_protect, 48);
674
674
675
+
static const struct adreno_reglist a640_gbif[] = {
676
+
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 },
677
+
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 },
678
+
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 },
679
+
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 },
680
+
{ },
681
+
};
682
+
675
683
static const struct adreno_info a6xx_gpus[] = {
676
684
{
677
685
.chip_ids = ADRENO_CHIP_IDS(0x06010000),
···
696
688
.a6xx = &(const struct a6xx_info) {
697
689
.hwcg = a612_hwcg,
698
690
.protect = &a630_protect,
691
+
.gbif_cx = a640_gbif,
699
692
.gmu_cgc_mode = 0x00020202,
700
693
.prim_fifo_threshold = 0x00080000,
701
694
},
···
903
894
.a6xx = &(const struct a6xx_info) {
904
895
.hwcg = a620_hwcg,
905
896
.protect = &a650_protect,
897
+
.gbif_cx = a640_gbif,
906
898
.gmu_cgc_mode = 0x00020200,
907
899
.prim_fifo_threshold = 0x00010000,
908
900
},
···
926
916
.a6xx = &(const struct a6xx_info) {
927
917
.hwcg = a690_hwcg,
928
918
.protect = &a650_protect,
919
+
.gbif_cx = a640_gbif,
929
920
.gmu_cgc_mode = 0x00020200,
930
921
.prim_fifo_threshold = 0x00010000,
931
922
.bcms = (const struct a6xx_bcm[]) {
···
1009
998
.a6xx = &(const struct a6xx_info) {
1010
999
.hwcg = a650_hwcg,
1011
1000
.protect = &a650_protect,
1001
+
.gbif_cx = a640_gbif,
1012
1002
.gmu_cgc_mode = 0x00020202,
1013
1003
.prim_fifo_threshold = 0x00300200,
1014
1004
},
···
1036
1024
.a6xx = &(const struct a6xx_info) {
1037
1025
.hwcg = a660_hwcg,
1038
1026
.protect = &a660_protect,
1027
+
.gbif_cx = a640_gbif,
1039
1028
.gmu_cgc_mode = 0x00020000,
1040
1029
.prim_fifo_threshold = 0x00300200,
1041
1030
},
···
1055
1042
.a6xx = &(const struct a6xx_info) {
1056
1043
.hwcg = a690_hwcg,
1057
1044
.protect = &a660_protect,
1045
+
.gbif_cx = a640_gbif,
1058
1046
.gmu_cgc_mode = 0x00020200,
1059
1047
.prim_fifo_threshold = 0x00300200,
1060
1048
},
···
1080
1066
.a6xx = &(const struct a6xx_info) {
1081
1067
.hwcg = a660_hwcg,
1082
1068
.protect = &a660_protect,
1069
+
.gbif_cx = a640_gbif,
1083
1070
.gmu_cgc_mode = 0x00020202,
1084
1071
.prim_fifo_threshold = 0x00200200,
1085
1072
},
···
1127
1112
.a6xx = &(const struct a6xx_info) {
1128
1113
.hwcg = a690_hwcg,
1129
1114
.protect = &a690_protect,
1115
+
.gbif_cx = a640_gbif,
1130
1116
.gmu_cgc_mode = 0x00020200,
1131
1117
.prim_fifo_threshold = 0x00800200,
1132
1118
},
···
1463
1447
.a6xx = &(const struct a6xx_info) {
1464
1448
.hwcg = a702_hwcg,
1465
1449
.protect = &a650_protect,
1450
+
.gbif_cx = a640_gbif,
1466
1451
.gmu_cgc_mode = 0x00020202,
1467
1452
.prim_fifo_threshold = 0x0000c000,
1468
1453
},
···
1491
1474
.hwcg = a730_hwcg,
1492
1475
.protect = &a730_protect,
1493
1476
.pwrup_reglist = &a7xx_pwrup_reglist,
1477
+
.gbif_cx = a640_gbif,
1494
1478
.gmu_cgc_mode = 0x00020000,
1495
1479
},
1496
1480
.preempt_record_size = 2860 * SZ_1K,
···
1513
1495
.hwcg = a740_hwcg,
1514
1496
.protect = &a730_protect,
1515
1497
.pwrup_reglist = &a7xx_pwrup_reglist,
1498
+
.gbif_cx = a640_gbif,
1516
1499
.gmu_chipid = 0x7020100,
1517
1500
.gmu_cgc_mode = 0x00020202,
1518
1501
.bcms = (const struct a6xx_bcm[]) {
···
1548
1529
.protect = &a730_protect,
1549
1530
.pwrup_reglist = &a7xx_pwrup_reglist,
1550
1531
.ifpc_reglist = &a750_ifpc_reglist,
1532
+
.gbif_cx = a640_gbif,
1551
1533
.gmu_chipid = 0x7050001,
1552
1534
.gmu_cgc_mode = 0x00020202,
1553
1535
.bcms = (const struct a6xx_bcm[]) {
···
1590
1570
.protect = &a730_protect,
1591
1571
.pwrup_reglist = &a7xx_pwrup_reglist,
1592
1572
.ifpc_reglist = &a750_ifpc_reglist,
1573
+
.gbif_cx = a640_gbif,
1593
1574
.gmu_chipid = 0x7090100,
1594
1575
.gmu_cgc_mode = 0x00020202,
1595
1576
.bcms = (const struct a6xx_bcm[]) {
···
1623
1602
.hwcg = a740_hwcg,
1624
1603
.protect = &a730_protect,
1625
1604
.pwrup_reglist = &a7xx_pwrup_reglist,
1605
+
.gbif_cx = a640_gbif,
1626
1606
.gmu_chipid = 0x70f0000,
1627
1607
.gmu_cgc_mode = 0x00020222,
1628
1608
.bcms = (const struct a6xx_bcm[]) {
···
1771
1749
};
1772
1750
DECLARE_ADRENO_PROTECT(a840_protect, 15);
1773
1751
1752
+
static const struct adreno_reglist a840_gbif[] = {
1753
+
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },
1754
+
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
1755
+
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },
1756
+
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },
1757
+
{ REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },
1758
+
{ },
1759
+
};
1760
+
1774
1761
static const struct adreno_info a8xx_gpus[] = {
1775
1762
{
1776
1763
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
···
1797
1766
.a6xx = &(const struct a6xx_info) {
1798
1767
.protect = &a840_protect,
1799
1768
.nonctxt_reglist = a840_nonctxt_regs,
1769
+
.gbif_cx = a840_gbif,
1800
1770
.max_slices = 3,
1801
1771
.gmu_chipid = 0x8020100,
1802
1772
.bcms = (const struct a6xx_bcm[]) {
+11
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+11
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
894
894
{
895
895
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
896
896
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
897
+
struct msm_gpu *gpu = &adreno_gpu->base;
897
898
const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx;
899
+
const struct adreno_reglist *gbif_cx = a6xx_info->gbif_cx;
898
900
u32 fence_range_lower, fence_range_upper;
899
901
u32 chipid = 0;
900
902
int ret;
···
990
988
991
989
gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
992
990
gmu->log.iova | (gmu->log.size / SZ_4K - 1));
991
+
}
992
+
993
+
/* For A7x and newer, do the CX GBIF configurations before GMU wake up */
994
+
for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++)
995
+
gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value);
996
+
997
+
if (adreno_is_a8xx(adreno_gpu)) {
998
+
gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
999
+
gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
993
1000
}
994
1001
995
1002
/* Set up the lowest idle level on the GMU */
+10
-7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+10
-7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
1279
1279
/* enable hardware clockgating */
1280
1280
a6xx_set_hwcg(gpu, true);
1281
1281
1282
-
/* VBIF/GBIF start*/
1283
-
if (adreno_is_a610_family(adreno_gpu) ||
1284
-
adreno_is_a640_family(adreno_gpu) ||
1285
-
adreno_is_a650_family(adreno_gpu) ||
1286
-
adreno_is_a7xx(adreno_gpu)) {
1282
+
/* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */
1283
+
if (adreno_is_a610_family(adreno_gpu)) {
1287
1284
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
1288
1285
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
1289
1286
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
1290
1287
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1291
-
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
1292
-
adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3);
1288
+
}
1289
+
1290
+
if (adreno_is_a610_family(adreno_gpu) ||
1291
+
adreno_is_a640_family(adreno_gpu) ||
1292
+
adreno_is_a650_family(adreno_gpu)) {
1293
+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
1294
+
} else if (adreno_is_a7xx(adreno_gpu)) {
1295
+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212);
1293
1296
} else {
1294
1297
gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
1295
1298
}
+1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
···
46
46
const struct adreno_protect *protect;
47
47
const struct adreno_reglist_list *pwrup_reglist;
48
48
const struct adreno_reglist_list *ifpc_reglist;
49
+
const struct adreno_reglist *gbif_cx;
49
50
const struct adreno_reglist_pipe *nonctxt_reglist;
50
51
u32 max_slices;
51
52
u32 gmu_chipid;
-7
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
-7
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
···
519
519
gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000);
520
520
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
521
521
522
-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
523
-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
524
-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
525
-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
526
-
gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
527
-
gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
528
-
529
522
/* Make all blocks contribute to the GPU BUSY perf counter */
530
523
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
531
524